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CommitLineData
093bc2cd
AK
1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK
14 */
15
d38ea87a 16#include "qemu/osdep.h"
da34e65c 17#include "qapi/error.h"
33c11879 18#include "cpu.h"
022c62cb
PB
19#include "exec/memory.h"
20#include "exec/address-spaces.h"
409ddd01 21#include "qapi/visitor.h"
1de7afc9 22#include "qemu/bitops.h"
8c56c1a5 23#include "qemu/error-report.h"
db725815 24#include "qemu/main-loop.h"
b6b71cb5 25#include "qemu/qemu-print.h"
2c9b15ca 26#include "qom/object.h"
0ab8ed18 27#include "trace-root.h"
093bc2cd 28
022c62cb 29#include "exec/memory-internal.h"
220c3ebd 30#include "exec/ram_addr.h"
8c56c1a5 31#include "sysemu/kvm.h"
54d31236 32#include "sysemu/runstate.h"
14a48c1d 33#include "sysemu/tcg.h"
8072aae3 34#include "sysemu/accel.h"
8072aae3 35#include "hw/boards.h"
b08199c6 36#include "migration/vmstate.h"
67d95c15 37
d197063f
PB
38//#define DEBUG_UNASSIGNED
39
22bde714
JK
40static unsigned memory_region_transaction_depth;
41static bool memory_region_update_pending;
4dc56152 42static bool ioeventfd_update_pending;
ae7a2bca 43bool global_dirty_log;
7664e80c 44
eae3eb3e 45static QTAILQ_HEAD(, MemoryListener) memory_listeners
72e22d2f 46 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 47
0d673e36
AK
48static QTAILQ_HEAD(, AddressSpace) address_spaces
49 = QTAILQ_HEAD_INITIALIZER(address_spaces);
50
967dc9b1
AK
51static GHashTable *flat_views;
52
093bc2cd
AK
53typedef struct AddrRange AddrRange;
54
8417cebf 55/*
c9cdaa3a 56 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK
57 * (large MemoryRegion::alias_offset).
58 */
093bc2cd 59struct AddrRange {
08dafab4
AK
60 Int128 start;
61 Int128 size;
093bc2cd
AK
62};
63
08dafab4 64static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK
65{
66 return (AddrRange) { start, size };
67}
68
69static bool addrrange_equal(AddrRange r1, AddrRange r2)
70{
08dafab4 71 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK
72}
73
08dafab4 74static Int128 addrrange_end(AddrRange r)
093bc2cd 75{
08dafab4 76 return int128_add(r.start, r.size);
093bc2cd
AK
77}
78
08dafab4 79static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 80{
08dafab4 81 int128_addto(&range.start, delta);
093bc2cd
AK
82 return range;
83}
84
08dafab4
AK
85static bool addrrange_contains(AddrRange range, Int128 addr)
86{
87 return int128_ge(addr, range.start)
88 && int128_lt(addr, addrrange_end(range));
89}
90
093bc2cd
AK
91static bool addrrange_intersects(AddrRange r1, AddrRange r2)
92{
08dafab4
AK
93 return addrrange_contains(r1, r2.start)
94 || addrrange_contains(r2, r1.start);
093bc2cd
AK
95}
96
97static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
98{
08dafab4
AK
99 Int128 start = int128_max(r1.start, r2.start);
100 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
101 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK
102}
103
0e0d36b4
AK
104enum ListenerDirection { Forward, Reverse };
105
7376e582 106#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK
107 do { \
108 MemoryListener *_listener; \
109 \
110 switch (_direction) { \
111 case Forward: \
112 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK
113 if (_listener->_callback) { \
114 _listener->_callback(_listener, ##_args); \
115 } \
0e0d36b4
AK
116 } \
117 break; \
118 case Reverse: \
eae3eb3e 119 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
975aefe0
AK
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
0e0d36b4
AK
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
9a54635d 130#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK
131 do { \
132 MemoryListener *_listener; \
133 \
134 switch (_direction) { \
135 case Forward: \
eae3eb3e 136 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
9a54635d 137 if (_listener->_callback) { \
7376e582
AK
138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
eae3eb3e 143 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
9a54635d 144 if (_listener->_callback) { \
7376e582
AK
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
dfde4e6e 154/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 155#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 156 do { \
16620684
AK
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
9a54635d 159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 160 } while(0)
0e0d36b4 161
093bc2cd
AK
162struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165};
166
3e9d69e7
AK
167struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
753d5e14 171 EventNotifier *e;
3e9d69e7
AK
172};
173
73bb753d
TB
174static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
3e9d69e7 176{
73bb753d 177 if (int128_lt(a->addr.start, b->addr.start)) {
3e9d69e7 178 return true;
73bb753d 179 } else if (int128_gt(a->addr.start, b->addr.start)) {
3e9d69e7 180 return false;
73bb753d 181 } else if (int128_lt(a->addr.size, b->addr.size)) {
3e9d69e7 182 return true;
73bb753d 183 } else if (int128_gt(a->addr.size, b->addr.size)) {
3e9d69e7 184 return false;
73bb753d 185 } else if (a->match_data < b->match_data) {
3e9d69e7 186 return true;
73bb753d 187 } else if (a->match_data > b->match_data) {
3e9d69e7 188 return false;
73bb753d
TB
189 } else if (a->match_data) {
190 if (a->data < b->data) {
3e9d69e7 191 return true;
73bb753d 192 } else if (a->data > b->data) {
3e9d69e7
AK
193 return false;
194 }
195 }
73bb753d 196 if (a->e < b->e) {
3e9d69e7 197 return true;
73bb753d 198 } else if (a->e > b->e) {
3e9d69e7
AK
199 return false;
200 }
201 return false;
202}
203
73bb753d
TB
204static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
3e9d69e7
AK
206{
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209}
210
093bc2cd
AK
211/* Range of memory in the global map. Addresses are absolute. */
212struct FlatRange {
213 MemoryRegion *mr;
a8170e5e 214 hwaddr offset_in_region;
093bc2cd 215 AddrRange addr;
5a583347 216 uint8_t dirty_log_mask;
b138e654 217 bool romd_mode;
fb1cd6f9 218 bool readonly;
c26763f8 219 bool nonvolatile;
3ac7d43a 220 int has_coalesced_range;
093bc2cd
AK
221};
222
093bc2cd
AK
223#define FOR_EACH_FLAT_RANGE(var, view) \
224 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
225
9c1f8f44 226static inline MemoryRegionSection
16620684 227section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
228{
229 return (MemoryRegionSection) {
230 .mr = fr->mr,
16620684 231 .fv = fv,
9c1f8f44
PB
232 .offset_within_region = fr->offset_in_region,
233 .size = fr->addr.size,
234 .offset_within_address_space = int128_get64(fr->addr.start),
235 .readonly = fr->readonly,
c26763f8 236 .nonvolatile = fr->nonvolatile,
9c1f8f44
PB
237 };
238}
239
093bc2cd
AK
240static bool flatrange_equal(FlatRange *a, FlatRange *b)
241{
242 return a->mr == b->mr
243 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 244 && a->offset_in_region == b->offset_in_region
b138e654 245 && a->romd_mode == b->romd_mode
c26763f8
MAL
246 && a->readonly == b->readonly
247 && a->nonvolatile == b->nonvolatile;
093bc2cd
AK
248}
249
89c177bb 250static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 251{
cc94cd6d
AK
252 FlatView *view;
253
254 view = g_new0(FlatView, 1);
856d7245 255 view->ref = 1;
89c177bb
AK
256 view->root = mr_root;
257 memory_region_ref(mr_root);
02d9651d 258 trace_flatview_new(view, mr_root);
cc94cd6d
AK
259
260 return view;
093bc2cd
AK
261}
262
263/* Insert a range into a given position. Caller is responsible for maintaining
264 * sorting order.
265 */
266static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
267{
268 if (view->nr == view->nr_allocated) {
269 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 270 view->ranges = g_realloc(view->ranges,
093bc2cd
AK
271 view->nr_allocated * sizeof(*view->ranges));
272 }
273 memmove(view->ranges + pos + 1, view->ranges + pos,
274 (view->nr - pos) * sizeof(FlatRange));
275 view->ranges[pos] = *range;
dfde4e6e 276 memory_region_ref(range->mr);
093bc2cd
AK
277 ++view->nr;
278}
279
280static void flatview_destroy(FlatView *view)
281{
dfde4e6e
PB
282 int i;
283
02d9651d 284 trace_flatview_destroy(view, view->root);
66a6df1d
AK
285 if (view->dispatch) {
286 address_space_dispatch_free(view->dispatch);
287 }
dfde4e6e
PB
288 for (i = 0; i < view->nr; i++) {
289 memory_region_unref(view->ranges[i].mr);
290 }
7267c094 291 g_free(view->ranges);
89c177bb 292 memory_region_unref(view->root);
a9a0c06d 293 g_free(view);
093bc2cd
AK
294}
295
447b0d0b 296static bool flatview_ref(FlatView *view)
856d7245 297{
447b0d0b 298 return atomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
299}
300
48564041 301void flatview_unref(FlatView *view)
856d7245
PB
302{
303 if (atomic_fetch_dec(&view->ref) == 1) {
02d9651d 304 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 305 assert(view->root);
66a6df1d 306 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
307 }
308}
309
3d8e6bf9
AK
310static bool can_merge(FlatRange *r1, FlatRange *r2)
311{
08dafab4 312 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 313 && r1->mr == r2->mr
08dafab4
AK
314 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
315 r1->addr.size),
316 int128_make64(r2->offset_in_region))
d0a9b5bc 317 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 318 && r1->romd_mode == r2->romd_mode
c26763f8
MAL
319 && r1->readonly == r2->readonly
320 && r1->nonvolatile == r2->nonvolatile;
3d8e6bf9
AK
321}
322
8508e024 323/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
324static void flatview_simplify(FlatView *view)
325{
838ec117 326 unsigned i, j, k;
3d8e6bf9
AK
327
328 i = 0;
329 while (i < view->nr) {
330 j = i + 1;
331 while (j < view->nr
332 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 333 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK
334 ++j;
335 }
336 ++i;
838ec117
KW
337 for (k = i; k < j; k++) {
338 memory_region_unref(view->ranges[k].mr);
339 }
3d8e6bf9
AK
340 memmove(&view->ranges[i], &view->ranges[j],
341 (view->nr - j) * sizeof(view->ranges[j]));
342 view->nr -= j - i;
343 }
344}
345
e7342aa3
PB
346static bool memory_region_big_endian(MemoryRegion *mr)
347{
348#ifdef TARGET_WORDS_BIGENDIAN
349 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
350#else
351 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
352#endif
353}
354
e11ef3d1
PB
355static bool memory_region_wrong_endianness(MemoryRegion *mr)
356{
357#ifdef TARGET_WORDS_BIGENDIAN
358 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
359#else
360 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
361#endif
362}
363
364static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
365{
366 if (memory_region_wrong_endianness(mr)) {
367 switch (size) {
368 case 1:
369 break;
370 case 2:
371 *data = bswap16(*data);
372 break;
373 case 4:
374 *data = bswap32(*data);
375 break;
376 case 8:
377 *data = bswap64(*data);
378 break;
379 default:
380 abort();
381 }
382 }
383}
384
3c754a93 385static inline void memory_region_shift_read_access(uint64_t *value,
98f52cdb 386 signed shift,
3c754a93
PMD
387 uint64_t mask,
388 uint64_t tmp)
389{
98f52cdb
PMD
390 if (shift >= 0) {
391 *value |= (tmp & mask) << shift;
392 } else {
393 *value |= (tmp & mask) >> -shift;
394 }
3c754a93
PMD
395}
396
397static inline uint64_t memory_region_shift_write_access(uint64_t *value,
98f52cdb 398 signed shift,
3c754a93
PMD
399 uint64_t mask)
400{
98f52cdb
PMD
401 uint64_t tmp;
402
403 if (shift >= 0) {
404 tmp = (*value >> shift) & mask;
405 } else {
406 tmp = (*value << -shift) & mask;
407 }
408
409 return tmp;
3c754a93
PMD
410}
411
4779dc1d
HB
412static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
413{
414 MemoryRegion *root;
415 hwaddr abs_addr = offset;
416
417 abs_addr += mr->addr;
418 for (root = mr; root->container; ) {
419 root = root->container;
420 abs_addr += root->addr;
421 }
422
423 return abs_addr;
424}
425
5a68be94
HB
426static int get_cpu_index(void)
427{
428 if (current_cpu) {
429 return current_cpu->cpu_index;
430 }
431 return -1;
432}
433
cc05c43a 434static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
435 hwaddr addr,
436 uint64_t *value,
437 unsigned size,
98f52cdb 438 signed shift,
cc05c43a
PM
439 uint64_t mask,
440 MemTxAttrs attrs)
ce5d2f33 441{
ce5d2f33
PB
442 uint64_t tmp;
443
cc05c43a 444 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 445 if (mr->subpage) {
5a68be94 446 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
447 } else if (mr == &io_mem_notdirty) {
448 /* Accesses to code which has previously been translated into a TB show
449 * up in the MMIO path, as accesses to the io_mem_notdirty
450 * MemoryRegion. */
451 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
452 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
453 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 454 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 455 }
3c754a93 456 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 457 return MEMTX_OK;
ce5d2f33
PB
458}
459
cc05c43a
PM
460static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
461 hwaddr addr,
462 uint64_t *value,
463 unsigned size,
98f52cdb 464 signed shift,
cc05c43a
PM
465 uint64_t mask,
466 MemTxAttrs attrs)
164a4dcd 467{
cc05c43a
PM
468 uint64_t tmp = 0;
469 MemTxResult r;
164a4dcd 470
cc05c43a 471 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 472 if (mr->subpage) {
5a68be94 473 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
474 } else if (mr == &io_mem_notdirty) {
475 /* Accesses to code which has previously been translated into a TB show
476 * up in the MMIO path, as accesses to the io_mem_notdirty
477 * MemoryRegion. */
478 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
479 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
480 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 481 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 482 }
3c754a93 483 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 484 return r;
164a4dcd
AK
485}
486
cc05c43a
PM
487static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
488 hwaddr addr,
489 uint64_t *value,
490 unsigned size,
98f52cdb 491 signed shift,
cc05c43a
PM
492 uint64_t mask,
493 MemTxAttrs attrs)
164a4dcd 494{
3c754a93 495 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
164a4dcd 496
23d92d68 497 if (mr->subpage) {
5a68be94 498 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
499 } else if (mr == &io_mem_notdirty) {
500 /* Accesses to code which has previously been translated into a TB show
501 * up in the MMIO path, as accesses to the io_mem_notdirty
502 * MemoryRegion. */
503 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
504 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
505 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 506 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 507 }
164a4dcd 508 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 509 return MEMTX_OK;
164a4dcd
AK
510}
511
cc05c43a
PM
512static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
513 hwaddr addr,
514 uint64_t *value,
515 unsigned size,
98f52cdb 516 signed shift,
cc05c43a
PM
517 uint64_t mask,
518 MemTxAttrs attrs)
519{
3c754a93 520 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
cc05c43a 521
23d92d68 522 if (mr->subpage) {
5a68be94 523 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
f2d08942
HB
524 } else if (mr == &io_mem_notdirty) {
525 /* Accesses to code which has previously been translated into a TB show
526 * up in the MMIO path, as accesses to the io_mem_notdirty
527 * MemoryRegion. */
528 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
4779dc1d
HB
529 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
530 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 531 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 532 }
cc05c43a
PM
533 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
534}
535
536static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
537 uint64_t *value,
538 unsigned size,
539 unsigned access_size_min,
540 unsigned access_size_max,
05e015f7
KF
541 MemTxResult (*access_fn)
542 (MemoryRegion *mr,
543 hwaddr addr,
544 uint64_t *value,
545 unsigned size,
98f52cdb 546 signed shift,
05e015f7
KF
547 uint64_t mask,
548 MemTxAttrs attrs),
cc05c43a
PM
549 MemoryRegion *mr,
550 MemTxAttrs attrs)
164a4dcd
AK
551{
552 uint64_t access_mask;
553 unsigned access_size;
554 unsigned i;
cc05c43a 555 MemTxResult r = MEMTX_OK;
164a4dcd
AK
556
557 if (!access_size_min) {
558 access_size_min = 1;
559 }
560 if (!access_size_max) {
561 access_size_max = 4;
562 }
ce5d2f33
PB
563
564 /* FIXME: support unaligned access? */
164a4dcd 565 access_size = MAX(MIN(size, access_size_max), access_size_min);
36960b4d 566 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
e7342aa3
PB
567 if (memory_region_big_endian(mr)) {
568 for (i = 0; i < size; i += access_size) {
05e015f7 569 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 570 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
571 }
572 } else {
573 for (i = 0; i < size; i += access_size) {
05e015f7 574 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 575 access_mask, attrs);
e7342aa3 576 }
164a4dcd 577 }
cc05c43a 578 return r;
164a4dcd
AK
579}
580
e2177955
AK
581static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
582{
0d673e36
AK
583 AddressSpace *as;
584
feca4ac1
PB
585 while (mr->container) {
586 mr = mr->container;
e2177955 587 }
0d673e36
AK
588 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
589 if (mr == as->root) {
590 return as;
591 }
e2177955 592 }
eed2bacf 593 return NULL;
e2177955
AK
594}
595
093bc2cd
AK
596/* Render a memory region into the global view. Ranges in @view obscure
597 * ranges in @mr.
598 */
599static void render_memory_region(FlatView *view,
600 MemoryRegion *mr,
08dafab4 601 Int128 base,
fb1cd6f9 602 AddrRange clip,
c26763f8
MAL
603 bool readonly,
604 bool nonvolatile)
093bc2cd
AK
605{
606 MemoryRegion *subregion;
607 unsigned i;
a8170e5e 608 hwaddr offset_in_region;
08dafab4
AK
609 Int128 remain;
610 Int128 now;
093bc2cd
AK
611 FlatRange fr;
612 AddrRange tmp;
613
6bba19ba
AK
614 if (!mr->enabled) {
615 return;
616 }
617
08dafab4 618 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 619 readonly |= mr->readonly;
c26763f8 620 nonvolatile |= mr->nonvolatile;
093bc2cd
AK
621
622 tmp = addrrange_make(base, mr->size);
623
624 if (!addrrange_intersects(tmp, clip)) {
625 return;
626 }
627
628 clip = addrrange_intersection(tmp, clip);
629
630 if (mr->alias) {
08dafab4
AK
631 int128_subfrom(&base, int128_make64(mr->alias->addr));
632 int128_subfrom(&base, int128_make64(mr->alias_offset));
c26763f8
MAL
633 render_memory_region(view, mr->alias, base, clip,
634 readonly, nonvolatile);
093bc2cd
AK
635 return;
636 }
637
638 /* Render subregions in priority order. */
639 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
c26763f8
MAL
640 render_memory_region(view, subregion, base, clip,
641 readonly, nonvolatile);
093bc2cd
AK
642 }
643
14a3c10a 644 if (!mr->terminates) {
093bc2cd
AK
645 return;
646 }
647
08dafab4 648 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
649 base = clip.start;
650 remain = clip.size;
651
2eb74e1a 652 fr.mr = mr;
6f6a5ef3 653 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 654 fr.romd_mode = mr->romd_mode;
2eb74e1a 655 fr.readonly = readonly;
c26763f8 656 fr.nonvolatile = nonvolatile;
3ac7d43a 657 fr.has_coalesced_range = 0;
2eb74e1a 658
093bc2cd 659 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
660 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
661 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
662 continue;
663 }
08dafab4
AK
664 if (int128_lt(base, view->ranges[i].addr.start)) {
665 now = int128_min(remain,
666 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
667 fr.offset_in_region = offset_in_region;
668 fr.addr = addrrange_make(base, now);
669 flatview_insert(view, i, &fr);
670 ++i;
08dafab4
AK
671 int128_addto(&base, now);
672 offset_in_region += int128_get64(now);
673 int128_subfrom(&remain, now);
093bc2cd 674 }
d26a8cae
AK
675 now = int128_sub(int128_min(int128_add(base, remain),
676 addrrange_end(view->ranges[i].addr)),
677 base);
678 int128_addto(&base, now);
679 offset_in_region += int128_get64(now);
680 int128_subfrom(&remain, now);
093bc2cd 681 }
08dafab4 682 if (int128_nz(remain)) {
093bc2cd
AK
683 fr.offset_in_region = offset_in_region;
684 fr.addr = addrrange_make(base, remain);
685 flatview_insert(view, i, &fr);
686 }
687}
688
89c177bb
AK
689static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
690{
e673ba9a
PB
691 while (mr->enabled) {
692 if (mr->alias) {
693 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
694 /* The alias is included in its entirety. Use it as
695 * the "real" root, so that we can share more FlatViews.
696 */
697 mr = mr->alias;
698 continue;
699 }
700 } else if (!mr->terminates) {
701 unsigned int found = 0;
702 MemoryRegion *child, *next = NULL;
703 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
704 if (child->enabled) {
705 if (++found > 1) {
706 next = NULL;
707 break;
708 }
709 if (!child->addr && int128_ge(mr->size, child->size)) {
710 /* A child is included in its entirety. If it's the only
711 * enabled one, use it in the hope of finding an alias down the
712 * way. This will also let us share FlatViews.
713 */
714 next = child;
715 }
716 }
717 }
092aa2fc
AK
718 if (found == 0) {
719 return NULL;
720 }
e673ba9a
PB
721 if (next) {
722 mr = next;
723 continue;
724 }
725 }
726
092aa2fc 727 return mr;
89c177bb
AK
728 }
729
092aa2fc 730 return NULL;
89c177bb
AK
731}
732
093bc2cd 733/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 734static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 735{
9bf561e3 736 int i;
a9a0c06d 737 FlatView *view;
093bc2cd 738
89c177bb 739 view = flatview_new(mr);
093bc2cd 740
83f3c251 741 if (mr) {
a9a0c06d 742 render_memory_region(view, mr, int128_zero(),
c26763f8
MAL
743 addrrange_make(int128_zero(), int128_2_64()),
744 false, false);
83f3c251 745 }
a9a0c06d 746 flatview_simplify(view);
093bc2cd 747
9bf561e3
AK
748 view->dispatch = address_space_dispatch_new(view);
749 for (i = 0; i < view->nr; i++) {
750 MemoryRegionSection mrs =
751 section_from_flat_range(&view->ranges[i], view);
752 flatview_add_to_dispatch(view, &mrs);
753 }
754 address_space_dispatch_compact(view->dispatch);
967dc9b1 755 g_hash_table_replace(flat_views, mr, view);
9bf561e3 756
093bc2cd
AK
757 return view;
758}
759
3e9d69e7
AK
760static void address_space_add_del_ioeventfds(AddressSpace *as,
761 MemoryRegionIoeventfd *fds_new,
762 unsigned fds_new_nb,
763 MemoryRegionIoeventfd *fds_old,
764 unsigned fds_old_nb)
765{
766 unsigned iold, inew;
80a1ea37
AK
767 MemoryRegionIoeventfd *fd;
768 MemoryRegionSection section;
3e9d69e7
AK
769
770 /* Generate a symmetric difference of the old and new fd sets, adding
771 * and deleting as necessary.
772 */
773
774 iold = inew = 0;
775 while (iold < fds_old_nb || inew < fds_new_nb) {
776 if (iold < fds_old_nb
777 && (inew == fds_new_nb
73bb753d
TB
778 || memory_region_ioeventfd_before(&fds_old[iold],
779 &fds_new[inew]))) {
80a1ea37
AK
780 fd = &fds_old[iold];
781 section = (MemoryRegionSection) {
16620684 782 .fv = address_space_to_flatview(as),
80a1ea37 783 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 784 .size = fd->addr.size,
80a1ea37 785 };
9a54635d 786 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 787 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
788 ++iold;
789 } else if (inew < fds_new_nb
790 && (iold == fds_old_nb
73bb753d
TB
791 || memory_region_ioeventfd_before(&fds_new[inew],
792 &fds_old[iold]))) {
80a1ea37
AK
793 fd = &fds_new[inew];
794 section = (MemoryRegionSection) {
16620684 795 .fv = address_space_to_flatview(as),
80a1ea37 796 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 797 .size = fd->addr.size,
80a1ea37 798 };
9a54635d 799 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 800 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
801 ++inew;
802 } else {
803 ++iold;
804 ++inew;
805 }
806 }
807}
808
48564041 809FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB
810{
811 FlatView *view;
812
374f2981 813 rcu_read_lock();
447b0d0b 814 do {
16620684 815 view = address_space_to_flatview(as);
447b0d0b
PB
816 /* If somebody has replaced as->current_map concurrently,
817 * flatview_ref returns false.
818 */
819 } while (!flatview_ref(view));
374f2981 820 rcu_read_unlock();
856d7245
PB
821 return view;
822}
823
3e9d69e7
AK
824static void address_space_update_ioeventfds(AddressSpace *as)
825{
99e86347 826 FlatView *view;
3e9d69e7
AK
827 FlatRange *fr;
828 unsigned ioeventfd_nb = 0;
829 MemoryRegionIoeventfd *ioeventfds = NULL;
830 AddrRange tmp;
831 unsigned i;
832
856d7245 833 view = address_space_get_flatview(as);
99e86347 834 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
835 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
836 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
837 int128_sub(fr->addr.start,
838 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
839 if (addrrange_intersects(fr->addr, tmp)) {
840 ++ioeventfd_nb;
7267c094 841 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
842 ioeventfd_nb * sizeof(*ioeventfds));
843 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
844 ioeventfds[ioeventfd_nb-1].addr = tmp;
845 }
846 }
847 }
848
849 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
850 as->ioeventfds, as->ioeventfd_nb);
851
7267c094 852 g_free(as->ioeventfds);
3e9d69e7
AK
853 as->ioeventfds = ioeventfds;
854 as->ioeventfd_nb = ioeventfd_nb;
856d7245 855 flatview_unref(view);
3e9d69e7
AK
856}
857
909bf763
PB
858static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
859{
1f7af804
PB
860 if (!fr->has_coalesced_range) {
861 return;
862 }
863
3ac7d43a
PB
864 if (--fr->has_coalesced_range > 0) {
865 return;
866 }
867
909bf763
PB
868 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
869 int128_get64(fr->addr.start),
870 int128_get64(fr->addr.size));
871}
872
873static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
874{
875 MemoryRegion *mr = fr->mr;
876 CoalescedMemoryRange *cmr;
877 AddrRange tmp;
878
1f7af804
PB
879 if (QTAILQ_EMPTY(&mr->coalesced)) {
880 return;
881 }
882
3ac7d43a
PB
883 if (fr->has_coalesced_range++) {
884 return;
885 }
886
909bf763
PB
887 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
888 tmp = addrrange_shift(cmr->addr,
889 int128_sub(fr->addr.start,
890 int128_make64(fr->offset_in_region)));
891 if (!addrrange_intersects(tmp, fr->addr)) {
892 continue;
893 }
894 tmp = addrrange_intersection(tmp, fr->addr);
895 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
896 int128_get64(tmp.start),
897 int128_get64(tmp.size));
898 }
899}
900
b8af1afb 901static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
902 const FlatView *old_view,
903 const FlatView *new_view,
b8af1afb 904 bool adding)
093bc2cd 905{
093bc2cd
AK
906 unsigned iold, inew;
907 FlatRange *frold, *frnew;
093bc2cd
AK
908
909 /* Generate a symmetric difference of the old and new memory maps.
910 * Kill ranges in the old map, and instantiate ranges in the new map.
911 */
912 iold = inew = 0;
a9a0c06d
PB
913 while (iold < old_view->nr || inew < new_view->nr) {
914 if (iold < old_view->nr) {
915 frold = &old_view->ranges[iold];
093bc2cd
AK
916 } else {
917 frold = NULL;
918 }
a9a0c06d
PB
919 if (inew < new_view->nr) {
920 frnew = &new_view->ranges[inew];
093bc2cd
AK
921 } else {
922 frnew = NULL;
923 }
924
925 if (frold
926 && (!frnew
08dafab4
AK
927 || int128_lt(frold->addr.start, frnew->addr.start)
928 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 929 && !flatrange_equal(frold, frnew)))) {
41a6e477 930 /* In old but not in new, or in both but attributes changed. */
093bc2cd 931
b8af1afb 932 if (!adding) {
3ac7d43a 933 flat_range_coalesced_io_del(frold, as);
72e22d2f 934 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
935 }
936
093bc2cd
AK
937 ++iold;
938 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 939 /* In both and unchanged (except logging may have changed) */
093bc2cd 940
4f826024 941 if (adding) {
50c1e149 942 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
943 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
944 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
945 frold->dirty_log_mask,
946 frnew->dirty_log_mask);
947 }
948 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
949 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
950 frold->dirty_log_mask,
951 frnew->dirty_log_mask);
b8af1afb 952 }
5a583347
AK
953 }
954
093bc2cd
AK
955 ++iold;
956 ++inew;
093bc2cd
AK
957 } else {
958 /* In new */
959
b8af1afb 960 if (adding) {
72e22d2f 961 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
3ac7d43a 962 flat_range_coalesced_io_add(frnew, as);
b8af1afb
AK
963 }
964
093bc2cd
AK
965 ++inew;
966 }
967 }
b8af1afb
AK
968}
969
967dc9b1
AK
970static void flatviews_init(void)
971{
092aa2fc
AK
972 static FlatView *empty_view;
973
967dc9b1
AK
974 if (flat_views) {
975 return;
976 }
977
978 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
979 (GDestroyNotify) flatview_unref);
092aa2fc
AK
980 if (!empty_view) {
981 empty_view = generate_memory_topology(NULL);
982 /* We keep it alive forever in the global variable. */
983 flatview_ref(empty_view);
984 } else {
985 g_hash_table_replace(flat_views, NULL, empty_view);
986 flatview_ref(empty_view);
987 }
967dc9b1
AK
988}
989
990static void flatviews_reset(void)
991{
992 AddressSpace *as;
993
994 if (flat_views) {
995 g_hash_table_unref(flat_views);
996 flat_views = NULL;
997 }
998 flatviews_init();
999
1000 /* Render unique FVs */
1001 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1002 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1003
1004 if (g_hash_table_lookup(flat_views, physmr)) {
1005 continue;
1006 }
1007
1008 generate_memory_topology(physmr);
1009 }
1010}
1011
1012static void address_space_set_flatview(AddressSpace *as)
b8af1afb 1013{
67ace39b 1014 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK
1015 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1016 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1017
1018 assert(new_view);
1019
67ace39b
AK
1020 if (old_view == new_view) {
1021 return;
1022 }
1023
1024 if (old_view) {
1025 flatview_ref(old_view);
1026 }
1027
967dc9b1 1028 flatview_ref(new_view);
9a62e24f
AK
1029
1030 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK
1031 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1032
1033 if (!old_view2) {
1034 old_view2 = &tmpview;
1035 }
1036 address_space_update_topology_pass(as, old_view2, new_view, false);
1037 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1038 }
b8af1afb 1039
374f2981
PB
1040 /* Writes are protected by the BQL. */
1041 atomic_rcu_set(&as->current_map, new_view);
67ace39b
AK
1042 if (old_view) {
1043 flatview_unref(old_view);
1044 }
856d7245
PB
1045
1046 /* Note that all the old MemoryRegions are still alive up to this
1047 * point. This relieves most MemoryListeners from the need to
1048 * ref/unref the MemoryRegions they get---unless they use them
1049 * outside the iothread mutex, in which case precise reference
1050 * counting is necessary.
1051 */
67ace39b
AK
1052 if (old_view) {
1053 flatview_unref(old_view);
1054 }
093bc2cd
AK
1055}
1056
202fc01b
AK
1057static void address_space_update_topology(AddressSpace *as)
1058{
1059 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1060
1061 flatviews_init();
1062 if (!g_hash_table_lookup(flat_views, physmr)) {
1063 generate_memory_topology(physmr);
1064 }
1065 address_space_set_flatview(as);
1066}
1067
4ef4db86
AK
1068void memory_region_transaction_begin(void)
1069{
bb880ded 1070 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
1071 ++memory_region_transaction_depth;
1072}
1073
1074void memory_region_transaction_commit(void)
1075{
0d673e36
AK
1076 AddressSpace *as;
1077
4ef4db86 1078 assert(memory_region_transaction_depth);
8d04fb55
JK
1079 assert(qemu_mutex_iothread_locked());
1080
4ef4db86 1081 --memory_region_transaction_depth;
4dc56152
GA
1082 if (!memory_region_transaction_depth) {
1083 if (memory_region_update_pending) {
967dc9b1
AK
1084 flatviews_reset();
1085
4dc56152 1086 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1087
4dc56152 1088 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1089 address_space_set_flatview(as);
02218487 1090 address_space_update_ioeventfds(as);
4dc56152 1091 }
ade9c1aa 1092 memory_region_update_pending = false;
0b152095 1093 ioeventfd_update_pending = false;
4dc56152
GA
1094 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1095 } else if (ioeventfd_update_pending) {
1096 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1097 address_space_update_ioeventfds(as);
1098 }
ade9c1aa 1099 ioeventfd_update_pending = false;
4dc56152 1100 }
4dc56152 1101 }
4ef4db86
AK
1102}
1103
545e92e0
AK
1104static void memory_region_destructor_none(MemoryRegion *mr)
1105{
1106}
1107
1108static void memory_region_destructor_ram(MemoryRegion *mr)
1109{
f1060c55 1110 qemu_ram_free(mr->ram_block);
545e92e0
AK
1111}
1112
b4fefef9
PC
1113static bool memory_region_need_escape(char c)
1114{
1115 return c == '/' || c == '[' || c == '\\' || c == ']';
1116}
1117
1118static char *memory_region_escape_name(const char *name)
1119{
1120 const char *p;
1121 char *escaped, *q;
1122 uint8_t c;
1123 size_t bytes = 0;
1124
1125 for (p = name; *p; p++) {
1126 bytes += memory_region_need_escape(*p) ? 4 : 1;
1127 }
1128 if (bytes == p - name) {
1129 return g_memdup(name, bytes + 1);
1130 }
1131
1132 escaped = g_malloc(bytes + 1);
1133 for (p = name, q = escaped; *p; p++) {
1134 c = *p;
1135 if (unlikely(memory_region_need_escape(c))) {
1136 *q++ = '\\';
1137 *q++ = 'x';
1138 *q++ = "0123456789abcdef"[c >> 4];
1139 c = "0123456789abcdef"[c & 15];
1140 }
1141 *q++ = c;
1142 }
1143 *q = 0;
1144 return escaped;
1145}
1146
3df9d748
AK
1147static void memory_region_do_init(MemoryRegion *mr,
1148 Object *owner,
1149 const char *name,
1150 uint64_t size)
093bc2cd 1151{
08dafab4
AK
1152 mr->size = int128_make64(size);
1153 if (size == UINT64_MAX) {
1154 mr->size = int128_2_64();
1155 }
302fa283 1156 mr->name = g_strdup(name);
612263cf 1157 mr->owner = owner;
58eaa217 1158 mr->ram_block = NULL;
b4fefef9
PC
1159
1160 if (name) {
843ef73a
PC
1161 char *escaped_name = memory_region_escape_name(name);
1162 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1163
1164 if (!owner) {
1165 owner = container_get(qdev_get_machine(), "/unattached");
1166 }
1167
843ef73a 1168 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
b4fefef9 1169 object_unref(OBJECT(mr));
843ef73a
PC
1170 g_free(name_array);
1171 g_free(escaped_name);
b4fefef9
PC
1172 }
1173}
1174
3df9d748
AK
1175void memory_region_init(MemoryRegion *mr,
1176 Object *owner,
1177 const char *name,
1178 uint64_t size)
1179{
1180 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1181 memory_region_do_init(mr, owner, name, size);
1182}
1183
d7bce999
EB
1184static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1185 void *opaque, Error **errp)
409ddd01
PC
1186{
1187 MemoryRegion *mr = MEMORY_REGION(obj);
1188 uint64_t value = mr->addr;
1189
51e72bc1 1190 visit_type_uint64(v, name, &value, errp);
409ddd01
PC
1191}
1192
d7bce999
EB
1193static void memory_region_get_container(Object *obj, Visitor *v,
1194 const char *name, void *opaque,
1195 Error **errp)
409ddd01
PC
1196{
1197 MemoryRegion *mr = MEMORY_REGION(obj);
1198 gchar *path = (gchar *)"";
1199
1200 if (mr->container) {
1201 path = object_get_canonical_path(OBJECT(mr->container));
1202 }
51e72bc1 1203 visit_type_str(v, name, &path, errp);
409ddd01
PC
1204 if (mr->container) {
1205 g_free(path);
1206 }
1207}
1208
1209static Object *memory_region_resolve_container(Object *obj, void *opaque,
1210 const char *part)
1211{
1212 MemoryRegion *mr = MEMORY_REGION(obj);
1213
1214 return OBJECT(mr->container);
1215}
1216
d7bce999
EB
1217static void memory_region_get_priority(Object *obj, Visitor *v,
1218 const char *name, void *opaque,
1219 Error **errp)
d33382da
PC
1220{
1221 MemoryRegion *mr = MEMORY_REGION(obj);
1222 int32_t value = mr->priority;
1223
51e72bc1 1224 visit_type_int32(v, name, &value, errp);
d33382da
PC
1225}
1226
d7bce999
EB
1227static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1228 void *opaque, Error **errp)
52aef7bb
PC
1229{
1230 MemoryRegion *mr = MEMORY_REGION(obj);
1231 uint64_t value = memory_region_size(mr);
1232
51e72bc1 1233 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1234}
1235
b4fefef9
PC
1236static void memory_region_initfn(Object *obj)
1237{
1238 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1239 ObjectProperty *op;
b4fefef9
PC
1240
1241 mr->ops = &unassigned_mem_ops;
6bba19ba 1242 mr->enabled = true;
5f9a5ea1 1243 mr->romd_mode = true;
196ea131 1244 mr->global_locking = true;
545e92e0 1245 mr->destructor = memory_region_destructor_none;
093bc2cd 1246 QTAILQ_INIT(&mr->subregions);
093bc2cd 1247 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1248
1249 op = object_property_add(OBJECT(mr), "container",
1250 "link<" TYPE_MEMORY_REGION ">",
1251 memory_region_get_container,
1252 NULL, /* memory_region_set_container */
1253 NULL, NULL, &error_abort);
1254 op->resolve = memory_region_resolve_container;
1255
1256 object_property_add(OBJECT(mr), "addr", "uint64",
1257 memory_region_get_addr,
1258 NULL, /* memory_region_set_addr */
1259 NULL, NULL, &error_abort);
d33382da
PC
1260 object_property_add(OBJECT(mr), "priority", "uint32",
1261 memory_region_get_priority,
1262 NULL, /* memory_region_set_priority */
1263 NULL, NULL, &error_abort);
52aef7bb
PC
1264 object_property_add(OBJECT(mr), "size", "uint64",
1265 memory_region_get_size,
1266 NULL, /* memory_region_set_size, */
1267 NULL, NULL, &error_abort);
093bc2cd
AK
1268}
1269
3df9d748
AK
1270static void iommu_memory_region_initfn(Object *obj)
1271{
1272 MemoryRegion *mr = MEMORY_REGION(obj);
1273
1274 mr->is_iommu = true;
1275}
1276
b018ddf6
PB
1277static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1278 unsigned size)
1279{
1280#ifdef DEBUG_UNASSIGNED
1281 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1282#endif
4917cf44 1283 if (current_cpu != NULL) {
dbea78a4
PM
1284 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1285 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
c658b94f 1286 }
68a7439a 1287 return 0;
b018ddf6
PB
1288}
1289
1290static void unassigned_mem_write(void *opaque, hwaddr addr,
1291 uint64_t val, unsigned size)
1292{
1293#ifdef DEBUG_UNASSIGNED
1294 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1295#endif
4917cf44
AF
1296 if (current_cpu != NULL) {
1297 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
c658b94f 1298 }
b018ddf6
PB
1299}
1300
d197063f 1301static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
8372d383
PM
1302 unsigned size, bool is_write,
1303 MemTxAttrs attrs)
d197063f
PB
1304{
1305 return false;
1306}
1307
1308const MemoryRegionOps unassigned_mem_ops = {
1309 .valid.accepts = unassigned_mem_accepts,
1310 .endianness = DEVICE_NATIVE_ENDIAN,
1311};
1312
4a2e242b
AW
1313static uint64_t memory_region_ram_device_read(void *opaque,
1314 hwaddr addr, unsigned size)
1315{
1316 MemoryRegion *mr = opaque;
1317 uint64_t data = (uint64_t)~0;
1318
1319 switch (size) {
1320 case 1:
1321 data = *(uint8_t *)(mr->ram_block->host + addr);
1322 break;
1323 case 2:
1324 data = *(uint16_t *)(mr->ram_block->host + addr);
1325 break;
1326 case 4:
1327 data = *(uint32_t *)(mr->ram_block->host + addr);
1328 break;
1329 case 8:
1330 data = *(uint64_t *)(mr->ram_block->host + addr);
1331 break;
1332 }
1333
1334 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1335
1336 return data;
1337}
1338
1339static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1340 uint64_t data, unsigned size)
1341{
1342 MemoryRegion *mr = opaque;
1343
1344 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1345
1346 switch (size) {
1347 case 1:
1348 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1349 break;
1350 case 2:
1351 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1352 break;
1353 case 4:
1354 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1355 break;
1356 case 8:
1357 *(uint64_t *)(mr->ram_block->host + addr) = data;
1358 break;
1359 }
1360}
1361
1362static const MemoryRegionOps ram_device_mem_ops = {
1363 .read = memory_region_ram_device_read,
1364 .write = memory_region_ram_device_write,
c99a29e7 1365 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1366 .valid = {
1367 .min_access_size = 1,
1368 .max_access_size = 8,
1369 .unaligned = true,
1370 },
1371 .impl = {
1372 .min_access_size = 1,
1373 .max_access_size = 8,
1374 .unaligned = true,
1375 },
1376};
1377
d2702032
PB
1378bool memory_region_access_valid(MemoryRegion *mr,
1379 hwaddr addr,
1380 unsigned size,
6d7b9a6c
PM
1381 bool is_write,
1382 MemTxAttrs attrs)
093bc2cd 1383{
a014ed07
PB
1384 int access_size_min, access_size_max;
1385 int access_size, i;
897fa7cf 1386
093bc2cd
AK
1387 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1388 return false;
1389 }
1390
a014ed07 1391 if (!mr->ops->valid.accepts) {
093bc2cd
AK
1392 return true;
1393 }
1394
a014ed07
PB
1395 access_size_min = mr->ops->valid.min_access_size;
1396 if (!mr->ops->valid.min_access_size) {
1397 access_size_min = 1;
1398 }
1399
1400 access_size_max = mr->ops->valid.max_access_size;
1401 if (!mr->ops->valid.max_access_size) {
1402 access_size_max = 4;
1403 }
1404
1405 access_size = MAX(MIN(size, access_size_max), access_size_min);
1406 for (i = 0; i < size; i += access_size) {
1407 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
8372d383 1408 is_write, attrs)) {
a014ed07
PB
1409 return false;
1410 }
093bc2cd 1411 }
a014ed07 1412
093bc2cd
AK
1413 return true;
1414}
1415
cc05c43a
PM
1416static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1417 hwaddr addr,
1418 uint64_t *pval,
1419 unsigned size,
1420 MemTxAttrs attrs)
093bc2cd 1421{
cc05c43a 1422 *pval = 0;
093bc2cd 1423
ce5d2f33 1424 if (mr->ops->read) {
cc05c43a
PM
1425 return access_with_adjusted_size(addr, pval, size,
1426 mr->ops->impl.min_access_size,
1427 mr->ops->impl.max_access_size,
1428 memory_region_read_accessor,
1429 mr, attrs);
62a0db94 1430 } else {
cc05c43a
PM
1431 return access_with_adjusted_size(addr, pval, size,
1432 mr->ops->impl.min_access_size,
1433 mr->ops->impl.max_access_size,
1434 memory_region_read_with_attrs_accessor,
1435 mr, attrs);
74901c3b 1436 }
093bc2cd
AK
1437}
1438
3b643495
PM
1439MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1440 hwaddr addr,
1441 uint64_t *pval,
1442 unsigned size,
1443 MemTxAttrs attrs)
a621f38d 1444{
cc05c43a
PM
1445 MemTxResult r;
1446
6d7b9a6c 1447 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
791af8c8 1448 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1449 return MEMTX_DECODE_ERROR;
791af8c8 1450 }
a621f38d 1451
cc05c43a 1452 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
791af8c8 1453 adjust_endianness(mr, pval, size);
cc05c43a 1454 return r;
a621f38d 1455}
093bc2cd 1456
8c56c1a5
PF
1457/* Return true if an eventfd was signalled */
1458static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1459 hwaddr addr,
1460 uint64_t data,
1461 unsigned size,
1462 MemTxAttrs attrs)
1463{
1464 MemoryRegionIoeventfd ioeventfd = {
1465 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1466 .data = data,
1467 };
1468 unsigned i;
1469
1470 for (i = 0; i < mr->ioeventfd_nb; i++) {
1471 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1472 ioeventfd.e = mr->ioeventfds[i].e;
1473
73bb753d 1474 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
8c56c1a5
PF
1475 event_notifier_set(ioeventfd.e);
1476 return true;
1477 }
1478 }
1479
1480 return false;
1481}
1482
3b643495
PM
1483MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1484 hwaddr addr,
1485 uint64_t data,
1486 unsigned size,
1487 MemTxAttrs attrs)
a621f38d 1488{
6d7b9a6c 1489 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
b018ddf6 1490 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1491 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1492 }
1493
a621f38d
AK
1494 adjust_endianness(mr, &data, size);
1495
8c56c1a5
PF
1496 if ((!kvm_eventfds_enabled()) &&
1497 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1498 return MEMTX_OK;
1499 }
1500
ce5d2f33 1501 if (mr->ops->write) {
cc05c43a
PM
1502 return access_with_adjusted_size(addr, &data, size,
1503 mr->ops->impl.min_access_size,
1504 mr->ops->impl.max_access_size,
1505 memory_region_write_accessor, mr,
1506 attrs);
62a0db94 1507 } else {
cc05c43a
PM
1508 return
1509 access_with_adjusted_size(addr, &data, size,
1510 mr->ops->impl.min_access_size,
1511 mr->ops->impl.max_access_size,
1512 memory_region_write_with_attrs_accessor,
1513 mr, attrs);
74901c3b 1514 }
093bc2cd
AK
1515}
1516
093bc2cd 1517void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1518 Object *owner,
093bc2cd
AK
1519 const MemoryRegionOps *ops,
1520 void *opaque,
1521 const char *name,
1522 uint64_t size)
1523{
2c9b15ca 1524 memory_region_init(mr, owner, name, size);
6d6d2abf 1525 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1526 mr->opaque = opaque;
14a3c10a 1527 mr->terminates = true;
093bc2cd
AK
1528}
1529
1cfe48c1
PM
1530void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1531 Object *owner,
1532 const char *name,
1533 uint64_t size,
1534 Error **errp)
06329cce
MA
1535{
1536 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1537}
1538
1539void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1540 Object *owner,
1541 const char *name,
1542 uint64_t size,
1543 bool share,
1544 Error **errp)
093bc2cd 1545{
1cd3d492 1546 Error *err = NULL;
2c9b15ca 1547 memory_region_init(mr, owner, name, size);
8ea9252a 1548 mr->ram = true;
14a3c10a 1549 mr->terminates = true;
545e92e0 1550 mr->destructor = memory_region_destructor_ram;
1cd3d492 1551 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
677e7805 1552 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1553 if (err) {
1554 mr->size = int128_zero();
1555 object_unparent(OBJECT(mr));
1556 error_propagate(errp, err);
1557 }
0b183fc8
PB
1558}
1559
60786ef3
MT
1560void memory_region_init_resizeable_ram(MemoryRegion *mr,
1561 Object *owner,
1562 const char *name,
1563 uint64_t size,
1564 uint64_t max_size,
1565 void (*resized)(const char*,
1566 uint64_t length,
1567 void *host),
1568 Error **errp)
1569{
1cd3d492 1570 Error *err = NULL;
60786ef3
MT
1571 memory_region_init(mr, owner, name, size);
1572 mr->ram = true;
1573 mr->terminates = true;
1574 mr->destructor = memory_region_destructor_ram;
8e41fb63 1575 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1cd3d492 1576 mr, &err);
677e7805 1577 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1578 if (err) {
1579 mr->size = int128_zero();
1580 object_unparent(OBJECT(mr));
1581 error_propagate(errp, err);
1582 }
60786ef3
MT
1583}
1584
d5dbde46 1585#ifdef CONFIG_POSIX
0b183fc8
PB
1586void memory_region_init_ram_from_file(MemoryRegion *mr,
1587 struct Object *owner,
1588 const char *name,
1589 uint64_t size,
98376843 1590 uint64_t align,
cbfc0171 1591 uint32_t ram_flags,
7f56e740
PB
1592 const char *path,
1593 Error **errp)
0b183fc8 1594{
1cd3d492 1595 Error *err = NULL;
0b183fc8
PB
1596 memory_region_init(mr, owner, name, size);
1597 mr->ram = true;
1598 mr->terminates = true;
1599 mr->destructor = memory_region_destructor_ram;
98376843 1600 mr->align = align;
1cd3d492 1601 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
677e7805 1602 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1603 if (err) {
1604 mr->size = int128_zero();
1605 object_unparent(OBJECT(mr));
1606 error_propagate(errp, err);
1607 }
093bc2cd 1608}
fea617c5
MAL
1609
1610void memory_region_init_ram_from_fd(MemoryRegion *mr,
1611 struct Object *owner,
1612 const char *name,
1613 uint64_t size,
1614 bool share,
1615 int fd,
1616 Error **errp)
1617{
1cd3d492 1618 Error *err = NULL;
fea617c5
MAL
1619 memory_region_init(mr, owner, name, size);
1620 mr->ram = true;
1621 mr->terminates = true;
1622 mr->destructor = memory_region_destructor_ram;
cbfc0171
JH
1623 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1624 share ? RAM_SHARED : 0,
1cd3d492 1625 fd, &err);
fea617c5 1626 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1627 if (err) {
1628 mr->size = int128_zero();
1629 object_unparent(OBJECT(mr));
1630 error_propagate(errp, err);
1631 }
fea617c5 1632}
0b183fc8 1633#endif
093bc2cd
AK
1634
1635void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1636 Object *owner,
093bc2cd
AK
1637 const char *name,
1638 uint64_t size,
1639 void *ptr)
1640{
2c9b15ca 1641 memory_region_init(mr, owner, name, size);
8ea9252a 1642 mr->ram = true;
14a3c10a 1643 mr->terminates = true;
fc3e7665 1644 mr->destructor = memory_region_destructor_ram;
677e7805 1645 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
ef701d7b
HT
1646
1647 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1648 assert(ptr != NULL);
8e41fb63 1649 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1650}
1651
21e00fa5
AW
1652void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1653 Object *owner,
1654 const char *name,
1655 uint64_t size,
1656 void *ptr)
e4dc3f59 1657{
2ddb89b0
BS
1658 memory_region_init(mr, owner, name, size);
1659 mr->ram = true;
1660 mr->terminates = true;
21e00fa5 1661 mr->ram_device = true;
4a2e242b
AW
1662 mr->ops = &ram_device_mem_ops;
1663 mr->opaque = mr;
2ddb89b0
BS
1664 mr->destructor = memory_region_destructor_ram;
1665 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1666 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1667 assert(ptr != NULL);
1668 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
e4dc3f59
ND
1669}
1670
093bc2cd 1671void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1672 Object *owner,
093bc2cd
AK
1673 const char *name,
1674 MemoryRegion *orig,
a8170e5e 1675 hwaddr offset,
093bc2cd
AK
1676 uint64_t size)
1677{
2c9b15ca 1678 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1679 mr->alias = orig;
1680 mr->alias_offset = offset;
1681}
1682
b59821a9
PM
1683void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1684 struct Object *owner,
1685 const char *name,
1686 uint64_t size,
1687 Error **errp)
a1777f7f 1688{
1cd3d492 1689 Error *err = NULL;
a1777f7f
PM
1690 memory_region_init(mr, owner, name, size);
1691 mr->ram = true;
1692 mr->readonly = true;
1693 mr->terminates = true;
1694 mr->destructor = memory_region_destructor_ram;
1cd3d492 1695 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
a1777f7f 1696 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1cd3d492
IM
1697 if (err) {
1698 mr->size = int128_zero();
1699 object_unparent(OBJECT(mr));
1700 error_propagate(errp, err);
1701 }
a1777f7f
PM
1702}
1703
b59821a9
PM
1704void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1705 Object *owner,
1706 const MemoryRegionOps *ops,
1707 void *opaque,
1708 const char *name,
1709 uint64_t size,
1710 Error **errp)
d0a9b5bc 1711{
1cd3d492 1712 Error *err = NULL;
39e0b03d 1713 assert(ops);
2c9b15ca 1714 memory_region_init(mr, owner, name, size);
7bc2b9cd 1715 mr->ops = ops;
75f5941c 1716 mr->opaque = opaque;
d0a9b5bc 1717 mr->terminates = true;
75c578dc 1718 mr->rom_device = true;
58268c8d 1719 mr->destructor = memory_region_destructor_ram;
1cd3d492
IM
1720 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1721 if (err) {
1722 mr->size = int128_zero();
1723 object_unparent(OBJECT(mr));
1724 error_propagate(errp, err);
1725 }
d0a9b5bc
AK
1726}
1727
1221a474
AK
1728void memory_region_init_iommu(void *_iommu_mr,
1729 size_t instance_size,
1730 const char *mrtypename,
2c9b15ca 1731 Object *owner,
30951157
AK
1732 const char *name,
1733 uint64_t size)
1734{
1221a474 1735 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1736 struct MemoryRegion *mr;
1737
1221a474
AK
1738 object_initialize(_iommu_mr, instance_size, mrtypename);
1739 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1740 memory_region_do_init(mr, owner, name, size);
1741 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1742 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1743 QLIST_INIT(&iommu_mr->iommu_notify);
1744 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1745}
1746
b4fefef9 1747static void memory_region_finalize(Object *obj)
093bc2cd 1748{
b4fefef9
PC
1749 MemoryRegion *mr = MEMORY_REGION(obj);
1750
2e2b8eb7
PB
1751 assert(!mr->container);
1752
1753 /* We know the region is not visible in any address space (it
1754 * does not have a container and cannot be a root either because
1755 * it has no references, so we can blindly clear mr->enabled.
1756 * memory_region_set_enabled instead could trigger a transaction
1757 * and cause an infinite loop.
1758 */
1759 mr->enabled = false;
1760 memory_region_transaction_begin();
1761 while (!QTAILQ_EMPTY(&mr->subregions)) {
1762 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1763 memory_region_del_subregion(mr, subregion);
1764 }
1765 memory_region_transaction_commit();
1766
545e92e0 1767 mr->destructor(mr);
093bc2cd 1768 memory_region_clear_coalescing(mr);
302fa283 1769 g_free((char *)mr->name);
7267c094 1770 g_free(mr->ioeventfds);
093bc2cd
AK
1771}
1772
803c0816
PB
1773Object *memory_region_owner(MemoryRegion *mr)
1774{
22a893e4
PB
1775 Object *obj = OBJECT(mr);
1776 return obj->parent;
803c0816
PB
1777}
1778
46637be2
PB
1779void memory_region_ref(MemoryRegion *mr)
1780{
22a893e4
PB
1781 /* MMIO callbacks most likely will access data that belongs
1782 * to the owner, hence the need to ref/unref the owner whenever
1783 * the memory region is in use.
1784 *
1785 * The memory region is a child of its owner. As long as the
1786 * owner doesn't call unparent itself on the memory region,
1787 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1788 * Memory regions without an owner are supposed to never go away;
1789 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1790 */
612263cf
PB
1791 if (mr && mr->owner) {
1792 object_ref(mr->owner);
46637be2
PB
1793 }
1794}
1795
1796void memory_region_unref(MemoryRegion *mr)
1797{
612263cf
PB
1798 if (mr && mr->owner) {
1799 object_unref(mr->owner);
46637be2
PB
1800 }
1801}
1802
093bc2cd
AK
1803uint64_t memory_region_size(MemoryRegion *mr)
1804{
08dafab4
AK
1805 if (int128_eq(mr->size, int128_2_64())) {
1806 return UINT64_MAX;
1807 }
1808 return int128_get64(mr->size);
093bc2cd
AK
1809}
1810
5d546d4b 1811const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1812{
d1dd32af
PC
1813 if (!mr->name) {
1814 ((MemoryRegion *)mr)->name =
1815 object_get_canonical_path_component(OBJECT(mr));
1816 }
302fa283 1817 return mr->name;
8991c79b
AK
1818}
1819
21e00fa5 1820bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1821{
21e00fa5 1822 return mr->ram_device;
e4dc3f59
ND
1823}
1824
2d1a35be 1825uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1826{
6f6a5ef3 1827 uint8_t mask = mr->dirty_log_mask;
adaad61c 1828 if (global_dirty_log && mr->ram_block) {
6f6a5ef3
PB
1829 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1830 }
1831 return mask;
55043ba3
AK
1832}
1833
2d1a35be
PB
1834bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1835{
1836 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1837}
1838
3df9d748 1839static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
5bf3d319
PX
1840{
1841 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1842 IOMMUNotifier *iommu_notifier;
1221a474 1843 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
5bf3d319 1844
3df9d748 1845 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1846 flags |= iommu_notifier->notifier_flags;
1847 }
1848
1221a474
AK
1849 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1850 imrc->notify_flag_changed(iommu_mr,
1851 iommu_mr->iommu_notify_flags,
1852 flags);
5bf3d319
PX
1853 }
1854
3df9d748 1855 iommu_mr->iommu_notify_flags = flags;
5bf3d319
PX
1856}
1857
cdb30812
PX
1858void memory_region_register_iommu_notifier(MemoryRegion *mr,
1859 IOMMUNotifier *n)
06866575 1860{
3df9d748
AK
1861 IOMMUMemoryRegion *iommu_mr;
1862
efcd38c5
JW
1863 if (mr->alias) {
1864 memory_region_register_iommu_notifier(mr->alias, n);
1865 return;
1866 }
1867
cdb30812 1868 /* We need to register for at least one bitfield */
3df9d748 1869 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1870 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1871 assert(n->start <= n->end);
cb1efcf4
PM
1872 assert(n->iommu_idx >= 0 &&
1873 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1874
3df9d748
AK
1875 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1876 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1877}
1878
3df9d748 1879uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1880{
1221a474
AK
1881 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1882
1883 if (imrc->get_min_page_size) {
1884 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1885 }
1886 return TARGET_PAGE_SIZE;
1887}
1888
3df9d748 1889void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1890{
3df9d748 1891 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1892 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1893 hwaddr addr, granularity;
a788f227
DG
1894 IOMMUTLBEntry iotlb;
1895
faa362e3 1896 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1897 if (imrc->replay) {
1898 imrc->replay(iommu_mr, n);
faa362e3
PX
1899 return;
1900 }
1901
3df9d748 1902 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1903
a788f227 1904 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
2c91bcf2 1905 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
a788f227
DG
1906 if (iotlb.perm != IOMMU_NONE) {
1907 n->notify(n, &iotlb);
1908 }
1909
1910 /* if (2^64 - MR size) < granularity, it's possible to get an
1911 * infinite loop here. This should catch such a wraparound */
1912 if ((addr + granularity) < addr) {
1913 break;
1914 }
1915 }
1916}
1917
3df9d748 1918void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
de472e4a
PX
1919{
1920 IOMMUNotifier *notifier;
1921
3df9d748
AK
1922 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1923 memory_region_iommu_replay(iommu_mr, notifier);
de472e4a
PX
1924 }
1925}
1926
cdb30812
PX
1927void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1928 IOMMUNotifier *n)
06866575 1929{
3df9d748
AK
1930 IOMMUMemoryRegion *iommu_mr;
1931
efcd38c5
JW
1932 if (mr->alias) {
1933 memory_region_unregister_iommu_notifier(mr->alias, n);
1934 return;
1935 }
cdb30812 1936 QLIST_REMOVE(n, node);
3df9d748
AK
1937 iommu_mr = IOMMU_MEMORY_REGION(mr);
1938 memory_region_update_iommu_notify_flags(iommu_mr);
06866575
DG
1939}
1940
bd2bfa4c
PX
1941void memory_region_notify_one(IOMMUNotifier *notifier,
1942 IOMMUTLBEntry *entry)
06866575 1943{
cdb30812 1944 IOMMUNotifierFlag request_flags;
03c7140c 1945 hwaddr entry_end = entry->iova + entry->addr_mask;
cdb30812 1946
bd2bfa4c
PX
1947 /*
1948 * Skip the notification if the notification does not overlap
1949 * with registered range.
1950 */
03c7140c 1951 if (notifier->start > entry_end || notifier->end < entry->iova) {
bd2bfa4c
PX
1952 return;
1953 }
cdb30812 1954
03c7140c
YZ
1955 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1956
bd2bfa4c 1957 if (entry->perm & IOMMU_RW) {
cdb30812
PX
1958 request_flags = IOMMU_NOTIFIER_MAP;
1959 } else {
1960 request_flags = IOMMU_NOTIFIER_UNMAP;
1961 }
1962
bd2bfa4c
PX
1963 if (notifier->notifier_flags & request_flags) {
1964 notifier->notify(notifier, entry);
1965 }
1966}
1967
3df9d748 1968void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
cb1efcf4 1969 int iommu_idx,
bd2bfa4c
PX
1970 IOMMUTLBEntry entry)
1971{
1972 IOMMUNotifier *iommu_notifier;
1973
3df9d748 1974 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1975
3df9d748 1976 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
cb1efcf4
PM
1977 if (iommu_notifier->iommu_idx == iommu_idx) {
1978 memory_region_notify_one(iommu_notifier, &entry);
1979 }
cdb30812 1980 }
06866575
DG
1981}
1982
f1334de6
AK
1983int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1984 enum IOMMUMemoryRegionAttr attr,
1985 void *data)
1986{
1987 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1988
1989 if (!imrc->get_attr) {
1990 return -EINVAL;
1991 }
1992
1993 return imrc->get_attr(iommu_mr, attr, data);
1994}
1995
21f40209
PM
1996int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1997 MemTxAttrs attrs)
1998{
1999 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2000
2001 if (!imrc->attrs_to_index) {
2002 return 0;
2003 }
2004
2005 return imrc->attrs_to_index(iommu_mr, attrs);
2006}
2007
2008int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2009{
2010 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2011
2012 if (!imrc->num_indexes) {
2013 return 1;
2014 }
2015
2016 return imrc->num_indexes(iommu_mr);
2017}
2018
093bc2cd
AK
2019void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2020{
5a583347 2021 uint8_t mask = 1 << client;
deb809ed 2022 uint8_t old_logging;
5a583347 2023
dbddac6d 2024 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
2025 old_logging = mr->vga_logging_count;
2026 mr->vga_logging_count += log ? 1 : -1;
2027 if (!!old_logging == !!mr->vga_logging_count) {
2028 return;
2029 }
2030
59023ef4 2031 memory_region_transaction_begin();
5a583347 2032 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 2033 memory_region_update_pending |= mr->enabled;
59023ef4 2034 memory_region_transaction_commit();
093bc2cd
AK
2035}
2036
a8170e5e
AK
2037void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2038 hwaddr size)
093bc2cd 2039{
8e41fb63
FZ
2040 assert(mr->ram_block);
2041 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2042 size,
58d2707e 2043 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
2044}
2045
0fe1eca7 2046static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 2047{
0a752eee 2048 MemoryListener *listener;
0d673e36 2049 AddressSpace *as;
0a752eee 2050 FlatView *view;
5a583347
AK
2051 FlatRange *fr;
2052
0a752eee
PB
2053 /* If the same address space has multiple log_sync listeners, we
2054 * visit that address space's FlatView multiple times. But because
2055 * log_sync listeners are rare, it's still cheaper than walking each
2056 * address space once.
2057 */
2058 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2059 if (!listener->log_sync) {
2060 continue;
2061 }
2062 as = listener->address_space;
2063 view = address_space_get_flatview(as);
99e86347 2064 FOR_EACH_FLAT_RANGE(fr, view) {
3ebb1817 2065 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
16620684 2066 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 2067 listener->log_sync(listener, &mrs);
0d673e36 2068 }
5a583347 2069 }
856d7245 2070 flatview_unref(view);
5a583347 2071 }
093bc2cd
AK
2072}
2073
077874e0
PX
2074void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2075 hwaddr len)
2076{
2077 MemoryRegionSection mrs;
2078 MemoryListener *listener;
2079 AddressSpace *as;
2080 FlatView *view;
2081 FlatRange *fr;
2082 hwaddr sec_start, sec_end, sec_size;
2083
2084 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2085 if (!listener->log_clear) {
2086 continue;
2087 }
2088 as = listener->address_space;
2089 view = address_space_get_flatview(as);
2090 FOR_EACH_FLAT_RANGE(fr, view) {
2091 if (!fr->dirty_log_mask || fr->mr != mr) {
2092 /*
2093 * Clear dirty bitmap operation only applies to those
2094 * regions whose dirty logging is at least enabled
2095 */
2096 continue;
2097 }
2098
2099 mrs = section_from_flat_range(fr, view);
2100
2101 sec_start = MAX(mrs.offset_within_region, start);
2102 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2103 sec_end = MIN(sec_end, start + len);
2104
2105 if (sec_start >= sec_end) {
2106 /*
2107 * If this memory region section has no intersection
2108 * with the requested range, skip.
2109 */
2110 continue;
2111 }
2112
2113 /* Valid case; shrink the section if needed */
2114 mrs.offset_within_address_space +=
2115 sec_start - mrs.offset_within_region;
2116 mrs.offset_within_region = sec_start;
2117 sec_size = sec_end - sec_start;
2118 mrs.size = int128_make64(sec_size);
2119 listener->log_clear(listener, &mrs);
2120 }
2121 flatview_unref(view);
2122 }
2123}
2124
0fe1eca7
PB
2125DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2126 hwaddr addr,
2127 hwaddr size,
2128 unsigned client)
2129{
9458a9a1 2130 DirtyBitmapSnapshot *snapshot;
0fe1eca7
PB
2131 assert(mr->ram_block);
2132 memory_region_sync_dirty_bitmap(mr);
9458a9a1
PB
2133 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2134 memory_global_after_dirty_log_sync();
2135 return snapshot;
0fe1eca7
PB
2136}
2137
2138bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2139 hwaddr addr, hwaddr size)
2140{
2141 assert(mr->ram_block);
2142 return cpu_physical_memory_snapshot_get_dirty(snap,
2143 memory_region_get_ram_addr(mr) + addr, size);
2144}
2145
093bc2cd
AK
2146void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2147{
fb1cd6f9 2148 if (mr->readonly != readonly) {
59023ef4 2149 memory_region_transaction_begin();
fb1cd6f9 2150 mr->readonly = readonly;
22bde714 2151 memory_region_update_pending |= mr->enabled;
59023ef4 2152 memory_region_transaction_commit();
fb1cd6f9 2153 }
093bc2cd
AK
2154}
2155
c26763f8
MAL
2156void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2157{
2158 if (mr->nonvolatile != nonvolatile) {
2159 memory_region_transaction_begin();
2160 mr->nonvolatile = nonvolatile;
2161 memory_region_update_pending |= mr->enabled;
2162 memory_region_transaction_commit();
2163 }
2164}
2165
5f9a5ea1 2166void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2167{
5f9a5ea1 2168 if (mr->romd_mode != romd_mode) {
59023ef4 2169 memory_region_transaction_begin();
5f9a5ea1 2170 mr->romd_mode = romd_mode;
22bde714 2171 memory_region_update_pending |= mr->enabled;
59023ef4 2172 memory_region_transaction_commit();
d0a9b5bc
AK
2173 }
2174}
2175
a8170e5e
AK
2176void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2177 hwaddr size, unsigned client)
093bc2cd 2178{
8e41fb63
FZ
2179 assert(mr->ram_block);
2180 cpu_physical_memory_test_and_clear_dirty(
2181 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
2182}
2183
a35ba7be
PB
2184int memory_region_get_fd(MemoryRegion *mr)
2185{
4ff87573
PB
2186 int fd;
2187
2188 rcu_read_lock();
2189 while (mr->alias) {
2190 mr = mr->alias;
a35ba7be 2191 }
4ff87573
PB
2192 fd = mr->ram_block->fd;
2193 rcu_read_unlock();
a35ba7be 2194
4ff87573
PB
2195 return fd;
2196}
a35ba7be 2197
093bc2cd
AK
2198void *memory_region_get_ram_ptr(MemoryRegion *mr)
2199{
49b24afc
PB
2200 void *ptr;
2201 uint64_t offset = 0;
093bc2cd 2202
49b24afc
PB
2203 rcu_read_lock();
2204 while (mr->alias) {
2205 offset += mr->alias_offset;
2206 mr = mr->alias;
2207 }
8e41fb63 2208 assert(mr->ram_block);
0878d0e1 2209 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
49b24afc 2210 rcu_read_unlock();
093bc2cd 2211
0878d0e1 2212 return ptr;
093bc2cd
AK
2213}
2214
07bdaa41
PB
2215MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2216{
2217 RAMBlock *block;
2218
2219 block = qemu_ram_block_from_host(ptr, false, offset);
2220 if (!block) {
2221 return NULL;
2222 }
2223
2224 return block->mr;
2225}
2226
7ebb2745
FZ
2227ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2228{
2229 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2230}
2231
37d7c084
PB
2232void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2233{
8e41fb63 2234 assert(mr->ram_block);
37d7c084 2235
fa53a0e5 2236 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
2237}
2238
0d673e36 2239static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd 2240{
99e86347 2241 FlatView *view;
093bc2cd 2242 FlatRange *fr;
093bc2cd 2243
856d7245 2244 view = address_space_get_flatview(as);
99e86347 2245 FOR_EACH_FLAT_RANGE(fr, view) {
093bc2cd 2246 if (fr->mr == mr) {
909bf763
PB
2247 flat_range_coalesced_io_del(fr, as);
2248 flat_range_coalesced_io_add(fr, as);
093bc2cd
AK
2249 }
2250 }
856d7245 2251 flatview_unref(view);
093bc2cd
AK
2252}
2253
0d673e36
AK
2254static void memory_region_update_coalesced_range(MemoryRegion *mr)
2255{
2256 AddressSpace *as;
2257
2258 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2259 memory_region_update_coalesced_range_as(mr, as);
2260 }
2261}
2262
093bc2cd
AK
2263void memory_region_set_coalescing(MemoryRegion *mr)
2264{
2265 memory_region_clear_coalescing(mr);
08dafab4 2266 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2267}
2268
2269void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2270 hwaddr offset,
093bc2cd
AK
2271 uint64_t size)
2272{
7267c094 2273 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2274
08dafab4 2275 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
2276 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2277 memory_region_update_coalesced_range(mr);
d410515e 2278 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2279}
2280
2281void memory_region_clear_coalescing(MemoryRegion *mr)
2282{
2283 CoalescedMemoryRange *cmr;
ab5b3db5 2284 bool updated = false;
093bc2cd 2285
d410515e
JK
2286 qemu_flush_coalesced_mmio_buffer();
2287 mr->flush_coalesced_mmio = false;
2288
093bc2cd
AK
2289 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2290 cmr = QTAILQ_FIRST(&mr->coalesced);
2291 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 2292 g_free(cmr);
ab5b3db5
FZ
2293 updated = true;
2294 }
2295
2296 if (updated) {
2297 memory_region_update_coalesced_range(mr);
093bc2cd 2298 }
093bc2cd
AK
2299}
2300
d410515e
JK
2301void memory_region_set_flush_coalesced(MemoryRegion *mr)
2302{
2303 mr->flush_coalesced_mmio = true;
2304}
2305
2306void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2307{
2308 qemu_flush_coalesced_mmio_buffer();
2309 if (QTAILQ_EMPTY(&mr->coalesced)) {
2310 mr->flush_coalesced_mmio = false;
2311 }
2312}
2313
196ea131
JK
2314void memory_region_clear_global_locking(MemoryRegion *mr)
2315{
2316 mr->global_locking = false;
2317}
2318
8c56c1a5
PF
2319static bool userspace_eventfd_warning;
2320
3e9d69e7 2321void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2322 hwaddr addr,
3e9d69e7
AK
2323 unsigned size,
2324 bool match_data,
2325 uint64_t data,
753d5e14 2326 EventNotifier *e)
3e9d69e7
AK
2327{
2328 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2329 .addr.start = int128_make64(addr),
2330 .addr.size = int128_make64(size),
3e9d69e7
AK
2331 .match_data = match_data,
2332 .data = data,
753d5e14 2333 .e = e,
3e9d69e7
AK
2334 };
2335 unsigned i;
2336
8c56c1a5
PF
2337 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2338 userspace_eventfd_warning))) {
2339 userspace_eventfd_warning = true;
2340 error_report("Using eventfd without MMIO binding in KVM. "
2341 "Suboptimal performance expected");
2342 }
2343
b8aecea2
JW
2344 if (size) {
2345 adjust_endianness(mr, &mrfd.data, size);
2346 }
59023ef4 2347 memory_region_transaction_begin();
3e9d69e7 2348 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2349 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2350 break;
2351 }
2352 }
2353 ++mr->ioeventfd_nb;
7267c094 2354 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2355 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2356 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2357 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2358 mr->ioeventfds[i] = mrfd;
4dc56152 2359 ioeventfd_update_pending |= mr->enabled;
59023ef4 2360 memory_region_transaction_commit();
3e9d69e7
AK
2361}
2362
2363void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2364 hwaddr addr,
3e9d69e7
AK
2365 unsigned size,
2366 bool match_data,
2367 uint64_t data,
753d5e14 2368 EventNotifier *e)
3e9d69e7
AK
2369{
2370 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2371 .addr.start = int128_make64(addr),
2372 .addr.size = int128_make64(size),
3e9d69e7
AK
2373 .match_data = match_data,
2374 .data = data,
753d5e14 2375 .e = e,
3e9d69e7
AK
2376 };
2377 unsigned i;
2378
b8aecea2
JW
2379 if (size) {
2380 adjust_endianness(mr, &mrfd.data, size);
2381 }
59023ef4 2382 memory_region_transaction_begin();
3e9d69e7 2383 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2384 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2385 break;
2386 }
2387 }
2388 assert(i != mr->ioeventfd_nb);
2389 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2390 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2391 --mr->ioeventfd_nb;
7267c094 2392 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2393 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2394 ioeventfd_update_pending |= mr->enabled;
59023ef4 2395 memory_region_transaction_commit();
3e9d69e7
AK
2396}
2397
feca4ac1 2398static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2399{
feca4ac1 2400 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2401 MemoryRegion *other;
2402
59023ef4
JK
2403 memory_region_transaction_begin();
2404
dfde4e6e 2405 memory_region_ref(subregion);
093bc2cd
AK
2406 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2407 if (subregion->priority >= other->priority) {
2408 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2409 goto done;
2410 }
2411 }
2412 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2413done:
22bde714 2414 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2415 memory_region_transaction_commit();
093bc2cd
AK
2416}
2417
0598701a
PC
2418static void memory_region_add_subregion_common(MemoryRegion *mr,
2419 hwaddr offset,
2420 MemoryRegion *subregion)
2421{
feca4ac1
PB
2422 assert(!subregion->container);
2423 subregion->container = mr;
0598701a 2424 subregion->addr = offset;
feca4ac1 2425 memory_region_update_container_subregions(subregion);
0598701a 2426}
093bc2cd
AK
2427
2428void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2429 hwaddr offset,
093bc2cd
AK
2430 MemoryRegion *subregion)
2431{
093bc2cd
AK
2432 subregion->priority = 0;
2433 memory_region_add_subregion_common(mr, offset, subregion);
2434}
2435
2436void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2437 hwaddr offset,
093bc2cd 2438 MemoryRegion *subregion,
a1ff8ae0 2439 int priority)
093bc2cd 2440{
093bc2cd
AK
2441 subregion->priority = priority;
2442 memory_region_add_subregion_common(mr, offset, subregion);
2443}
2444
2445void memory_region_del_subregion(MemoryRegion *mr,
2446 MemoryRegion *subregion)
2447{
59023ef4 2448 memory_region_transaction_begin();
feca4ac1
PB
2449 assert(subregion->container == mr);
2450 subregion->container = NULL;
093bc2cd 2451 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2452 memory_region_unref(subregion);
22bde714 2453 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2454 memory_region_transaction_commit();
6bba19ba
AK
2455}
2456
2457void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2458{
2459 if (enabled == mr->enabled) {
2460 return;
2461 }
59023ef4 2462 memory_region_transaction_begin();
6bba19ba 2463 mr->enabled = enabled;
22bde714 2464 memory_region_update_pending = true;
59023ef4 2465 memory_region_transaction_commit();
093bc2cd 2466}
1c0ffa58 2467
e7af4c67
MT
2468void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2469{
2470 Int128 s = int128_make64(size);
2471
2472 if (size == UINT64_MAX) {
2473 s = int128_2_64();
2474 }
2475 if (int128_eq(s, mr->size)) {
2476 return;
2477 }
2478 memory_region_transaction_begin();
2479 mr->size = s;
2480 memory_region_update_pending = true;
2481 memory_region_transaction_commit();
2482}
2483
67891b8a 2484static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2485{
feca4ac1 2486 MemoryRegion *container = mr->container;
2282e1af 2487
feca4ac1 2488 if (container) {
67891b8a
PC
2489 memory_region_transaction_begin();
2490 memory_region_ref(mr);
feca4ac1
PB
2491 memory_region_del_subregion(container, mr);
2492 mr->container = container;
2493 memory_region_update_container_subregions(mr);
67891b8a
PC
2494 memory_region_unref(mr);
2495 memory_region_transaction_commit();
2282e1af 2496 }
67891b8a 2497}
2282e1af 2498
67891b8a
PC
2499void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2500{
2501 if (addr != mr->addr) {
2502 mr->addr = addr;
2503 memory_region_readd_subregion(mr);
2504 }
2282e1af
AK
2505}
2506
a8170e5e 2507void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2508{
4703359e 2509 assert(mr->alias);
4703359e 2510
59023ef4 2511 if (offset == mr->alias_offset) {
4703359e
AK
2512 return;
2513 }
2514
59023ef4
JK
2515 memory_region_transaction_begin();
2516 mr->alias_offset = offset;
22bde714 2517 memory_region_update_pending |= mr->enabled;
59023ef4 2518 memory_region_transaction_commit();
4703359e
AK
2519}
2520
a2b257d6
IM
2521uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2522{
2523 return mr->align;
2524}
2525
e2177955
AK
2526static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2527{
2528 const AddrRange *addr = addr_;
2529 const FlatRange *fr = fr_;
2530
2531 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2532 return -1;
2533 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2534 return 1;
2535 }
2536 return 0;
2537}
2538
99e86347 2539static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2540{
99e86347 2541 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2542 sizeof(FlatRange), cmp_flatrange_addr);
2543}
2544
eed2bacf
IM
2545bool memory_region_is_mapped(MemoryRegion *mr)
2546{
2547 return mr->container ? true : false;
2548}
2549
c6742b14
PB
2550/* Same as memory_region_find, but it does not add a reference to the
2551 * returned region. It must be called from an RCU critical section.
2552 */
2553static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2554 hwaddr addr, uint64_t size)
e2177955 2555{
052e87b0 2556 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2557 MemoryRegion *root;
2558 AddressSpace *as;
2559 AddrRange range;
99e86347 2560 FlatView *view;
73034e9e
PB
2561 FlatRange *fr;
2562
2563 addr += mr->addr;
feca4ac1
PB
2564 for (root = mr; root->container; ) {
2565 root = root->container;
73034e9e
PB
2566 addr += root->addr;
2567 }
e2177955 2568
73034e9e 2569 as = memory_region_to_address_space(root);
eed2bacf
IM
2570 if (!as) {
2571 return ret;
2572 }
73034e9e 2573 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2574
16620684 2575 view = address_space_to_flatview(as);
99e86347 2576 fr = flatview_lookup(view, range);
e2177955 2577 if (!fr) {
c6742b14 2578 return ret;
e2177955
AK
2579 }
2580
99e86347 2581 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2582 --fr;
2583 }
2584
2585 ret.mr = fr->mr;
16620684 2586 ret.fv = view;
e2177955
AK
2587 range = addrrange_intersection(range, fr->addr);
2588 ret.offset_within_region = fr->offset_in_region;
2589 ret.offset_within_region += int128_get64(int128_sub(range.start,
2590 fr->addr.start));
052e87b0 2591 ret.size = range.size;
e2177955 2592 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2593 ret.readonly = fr->readonly;
c26763f8 2594 ret.nonvolatile = fr->nonvolatile;
c6742b14
PB
2595 return ret;
2596}
2597
2598MemoryRegionSection memory_region_find(MemoryRegion *mr,
2599 hwaddr addr, uint64_t size)
2600{
2601 MemoryRegionSection ret;
2602 rcu_read_lock();
2603 ret = memory_region_find_rcu(mr, addr, size);
2604 if (ret.mr) {
2605 memory_region_ref(ret.mr);
2606 }
2b647668 2607 rcu_read_unlock();
e2177955
AK
2608 return ret;
2609}
2610
c6742b14
PB
2611bool memory_region_present(MemoryRegion *container, hwaddr addr)
2612{
2613 MemoryRegion *mr;
2614
2615 rcu_read_lock();
2616 mr = memory_region_find_rcu(container, addr, 1).mr;
2617 rcu_read_unlock();
2618 return mr && mr != container;
2619}
2620
9c1f8f44 2621void memory_global_dirty_log_sync(void)
86e775c6 2622{
3ebb1817 2623 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK
2624}
2625
9458a9a1
PB
2626void memory_global_after_dirty_log_sync(void)
2627{
2628 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2629}
2630
19310760
JZ
2631static VMChangeStateEntry *vmstate_change;
2632
7664e80c
AK
2633void memory_global_dirty_log_start(void)
2634{
19310760
JZ
2635 if (vmstate_change) {
2636 qemu_del_vm_change_state_handler(vmstate_change);
2637 vmstate_change = NULL;
2638 }
2639
7664e80c 2640 global_dirty_log = true;
6f6a5ef3 2641
7376e582 2642 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3 2643
39adb536 2644 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2645 memory_region_transaction_begin();
2646 memory_region_update_pending = true;
2647 memory_region_transaction_commit();
7664e80c
AK
2648}
2649
19310760 2650static void memory_global_dirty_log_do_stop(void)
7664e80c 2651{
7664e80c 2652 global_dirty_log = false;
6f6a5ef3 2653
39adb536 2654 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2655 memory_region_transaction_begin();
2656 memory_region_update_pending = true;
2657 memory_region_transaction_commit();
2658
7376e582 2659 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2660}
2661
19310760
JZ
2662static void memory_vm_change_state_handler(void *opaque, int running,
2663 RunState state)
2664{
2665 if (running) {
2666 memory_global_dirty_log_do_stop();
2667
2668 if (vmstate_change) {
2669 qemu_del_vm_change_state_handler(vmstate_change);
2670 vmstate_change = NULL;
2671 }
2672 }
2673}
2674
2675void memory_global_dirty_log_stop(void)
2676{
2677 if (!runstate_is_running()) {
2678 if (vmstate_change) {
2679 return;
2680 }
2681 vmstate_change = qemu_add_vm_change_state_handler(
2682 memory_vm_change_state_handler, NULL);
2683 return;
2684 }
2685
2686 memory_global_dirty_log_do_stop();
2687}
2688
7664e80c
AK
2689static void listener_add_address_space(MemoryListener *listener,
2690 AddressSpace *as)
2691{
99e86347 2692 FlatView *view;
7664e80c
AK
2693 FlatRange *fr;
2694
680a4783
PB
2695 if (listener->begin) {
2696 listener->begin(listener);
2697 }
7664e80c 2698 if (global_dirty_log) {
975aefe0
AK
2699 if (listener->log_global_start) {
2700 listener->log_global_start(listener);
2701 }
7664e80c 2702 }
975aefe0 2703
856d7245 2704 view = address_space_get_flatview(as);
99e86347 2705 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH
2706 MemoryRegionSection section = section_from_flat_range(fr, view);
2707
975aefe0
AK
2708 if (listener->region_add) {
2709 listener->region_add(listener, &section);
2710 }
ae990e6c
DH
2711 if (fr->dirty_log_mask && listener->log_start) {
2712 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2713 }
7664e80c 2714 }
680a4783
PB
2715 if (listener->commit) {
2716 listener->commit(listener);
2717 }
856d7245 2718 flatview_unref(view);
7664e80c
AK
2719}
2720
d25836ca
PX
2721static void listener_del_address_space(MemoryListener *listener,
2722 AddressSpace *as)
2723{
2724 FlatView *view;
2725 FlatRange *fr;
2726
2727 if (listener->begin) {
2728 listener->begin(listener);
2729 }
2730 view = address_space_get_flatview(as);
2731 FOR_EACH_FLAT_RANGE(fr, view) {
2732 MemoryRegionSection section = section_from_flat_range(fr, view);
2733
2734 if (fr->dirty_log_mask && listener->log_stop) {
2735 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2736 }
2737 if (listener->region_del) {
2738 listener->region_del(listener, &section);
2739 }
2740 }
2741 if (listener->commit) {
2742 listener->commit(listener);
2743 }
2744 flatview_unref(view);
2745}
2746
d45fa784 2747void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2748{
72e22d2f
AK
2749 MemoryListener *other = NULL;
2750
d45fa784 2751 listener->address_space = as;
72e22d2f 2752 if (QTAILQ_EMPTY(&memory_listeners)
eae3eb3e 2753 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
72e22d2f
AK
2754 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2755 } else {
2756 QTAILQ_FOREACH(other, &memory_listeners, link) {
2757 if (listener->priority < other->priority) {
2758 break;
2759 }
2760 }
2761 QTAILQ_INSERT_BEFORE(other, listener, link);
2762 }
0d673e36 2763
9a54635d 2764 if (QTAILQ_EMPTY(&as->listeners)
eae3eb3e 2765 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
9a54635d
PB
2766 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2767 } else {
2768 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2769 if (listener->priority < other->priority) {
2770 break;
2771 }
2772 }
2773 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2774 }
2775
d45fa784 2776 listener_add_address_space(listener, as);
7664e80c
AK
2777}
2778
2779void memory_listener_unregister(MemoryListener *listener)
2780{
1d8280c1
PB
2781 if (!listener->address_space) {
2782 return;
2783 }
2784
d25836ca 2785 listener_del_address_space(listener, listener->address_space);
72e22d2f 2786 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2787 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2788 listener->address_space = NULL;
86e775c6 2789}
e2177955 2790
a2166410
GK
2791void address_space_remove_listeners(AddressSpace *as)
2792{
2793 while (!QTAILQ_EMPTY(&as->listeners)) {
2794 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2795 }
2796}
2797
7dca8043 2798void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2799{
ac95190e 2800 memory_region_ref(root);
8786db7c 2801 as->root = root;
67ace39b 2802 as->current_map = NULL;
4c19eb72
AK
2803 as->ioeventfd_nb = 0;
2804 as->ioeventfds = NULL;
9a54635d 2805 QTAILQ_INIT(&as->listeners);
0d673e36 2806 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2807 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK
2808 address_space_update_topology(as);
2809 address_space_update_ioeventfds(as);
1c0ffa58 2810}
658b2224 2811
374f2981 2812static void do_address_space_destroy(AddressSpace *as)
83f3c251 2813{
9a54635d 2814 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2815
856d7245 2816 flatview_unref(as->current_map);
7dca8043 2817 g_free(as->name);
4c19eb72 2818 g_free(as->ioeventfds);
ac95190e 2819 memory_region_unref(as->root);
83f3c251
AK
2820}
2821
374f2981
PB
2822void address_space_destroy(AddressSpace *as)
2823{
ac95190e
PB
2824 MemoryRegion *root = as->root;
2825
374f2981
PB
2826 /* Flush out anything from MemoryListeners listening in on this */
2827 memory_region_transaction_begin();
2828 as->root = NULL;
2829 memory_region_transaction_commit();
2830 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2831
2832 /* At this point, as->dispatch and as->current_map are dummy
2833 * entries that the guest should never use. Wait for the old
2834 * values to expire before freeing the data.
2835 */
ac95190e 2836 as->root = root;
374f2981
PB
2837 call_rcu(as, do_address_space_destroy, rcu);
2838}
2839
4e831901
PX
2840static const char *memory_region_type(MemoryRegion *mr)
2841{
2842 if (memory_region_is_ram_device(mr)) {
2843 return "ramd";
2844 } else if (memory_region_is_romd(mr)) {
2845 return "romd";
2846 } else if (memory_region_is_rom(mr)) {
2847 return "rom";
2848 } else if (memory_region_is_ram(mr)) {
2849 return "ram";
2850 } else {
2851 return "i/o";
2852 }
2853}
2854
314e2987
BS
2855typedef struct MemoryRegionList MemoryRegionList;
2856
2857struct MemoryRegionList {
2858 const MemoryRegion *mr;
a16878d2 2859 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2860};
2861
b58deb34 2862typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
314e2987 2863
4e831901
PX
2864#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2865 int128_sub((size), int128_one())) : 0)
2866#define MTREE_INDENT " "
2867
b6b71cb5 2868static void mtree_expand_owner(const char *label, Object *obj)
fc051ae6
AK
2869{
2870 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2871
b6b71cb5 2872 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
fc051ae6 2873 if (dev && dev->id) {
b6b71cb5 2874 qemu_printf(" id=%s", dev->id);
fc051ae6
AK
2875 } else {
2876 gchar *canonical_path = object_get_canonical_path(obj);
2877 if (canonical_path) {
b6b71cb5 2878 qemu_printf(" path=%s", canonical_path);
fc051ae6
AK
2879 g_free(canonical_path);
2880 } else {
b6b71cb5 2881 qemu_printf(" type=%s", object_get_typename(obj));
fc051ae6
AK
2882 }
2883 }
b6b71cb5 2884 qemu_printf("}");
fc051ae6
AK
2885}
2886
b6b71cb5 2887static void mtree_print_mr_owner(const MemoryRegion *mr)
fc051ae6
AK
2888{
2889 Object *owner = mr->owner;
2890 Object *parent = memory_region_owner((MemoryRegion *)mr);
2891
2892 if (!owner && !parent) {
b6b71cb5 2893 qemu_printf(" orphan");
fc051ae6
AK
2894 return;
2895 }
2896 if (owner) {
b6b71cb5 2897 mtree_expand_owner("owner", owner);
fc051ae6
AK
2898 }
2899 if (parent && parent != owner) {
b6b71cb5 2900 mtree_expand_owner("parent", parent);
fc051ae6
AK
2901 }
2902}
2903
b6b71cb5 2904static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
a8170e5e 2905 hwaddr base,
fc051ae6
AK
2906 MemoryRegionListHead *alias_print_queue,
2907 bool owner)
314e2987 2908{
9479c57a
JK
2909 MemoryRegionList *new_ml, *ml, *next_ml;
2910 MemoryRegionListHead submr_print_queue;
314e2987
BS
2911 const MemoryRegion *submr;
2912 unsigned int i;
b31f8412 2913 hwaddr cur_start, cur_end;
314e2987 2914
f8a9f720 2915 if (!mr) {
314e2987
BS
2916 return;
2917 }
2918
2919 for (i = 0; i < level; i++) {
b6b71cb5 2920 qemu_printf(MTREE_INDENT);
314e2987
BS
2921 }
2922
b31f8412
PX
2923 cur_start = base + mr->addr;
2924 cur_end = cur_start + MR_SIZE(mr->size);
2925
2926 /*
2927 * Try to detect overflow of memory region. This should never
2928 * happen normally. When it happens, we dump something to warn the
2929 * user who is observing this.
2930 */
2931 if (cur_start < base || cur_end < cur_start) {
b6b71cb5 2932 qemu_printf("[DETECTED OVERFLOW!] ");
b31f8412
PX
2933 }
2934
314e2987
BS
2935 if (mr->alias) {
2936 MemoryRegionList *ml;
2937 bool found = false;
2938
2939 /* check if the alias is already in the queue */
a16878d2 2940 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2941 if (ml->mr == mr->alias) {
314e2987
BS
2942 found = true;
2943 }
2944 }
2945
2946 if (!found) {
2947 ml = g_new(MemoryRegionList, 1);
2948 ml->mr = mr->alias;
a16878d2 2949 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2950 }
b6b71cb5
MA
2951 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2952 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2953 "-" TARGET_FMT_plx "%s",
2954 cur_start, cur_end,
2955 mr->priority,
2956 mr->nonvolatile ? "nv-" : "",
2957 memory_region_type((MemoryRegion *)mr),
2958 memory_region_name(mr),
2959 memory_region_name(mr->alias),
2960 mr->alias_offset,
2961 mr->alias_offset + MR_SIZE(mr->size),
2962 mr->enabled ? "" : " [disabled]");
fc051ae6 2963 if (owner) {
b6b71cb5 2964 mtree_print_mr_owner(mr);
fc051ae6 2965 }
314e2987 2966 } else {
b6b71cb5
MA
2967 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2968 " (prio %d, %s%s): %s%s",
2969 cur_start, cur_end,
2970 mr->priority,
2971 mr->nonvolatile ? "nv-" : "",
2972 memory_region_type((MemoryRegion *)mr),
2973 memory_region_name(mr),
2974 mr->enabled ? "" : " [disabled]");
fc051ae6 2975 if (owner) {
b6b71cb5 2976 mtree_print_mr_owner(mr);
fc051ae6 2977 }
314e2987 2978 }
b6b71cb5 2979 qemu_printf("\n");
9479c57a
JK
2980
2981 QTAILQ_INIT(&submr_print_queue);
2982
314e2987 2983 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
2984 new_ml = g_new(MemoryRegionList, 1);
2985 new_ml->mr = submr;
a16878d2 2986 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
2987 if (new_ml->mr->addr < ml->mr->addr ||
2988 (new_ml->mr->addr == ml->mr->addr &&
2989 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 2990 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
2991 new_ml = NULL;
2992 break;
2993 }
2994 }
2995 if (new_ml) {
a16878d2 2996 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
2997 }
2998 }
2999
a16878d2 3000 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b6b71cb5 3001 mtree_print_mr(ml->mr, level + 1, cur_start,
fc051ae6 3002 alias_print_queue, owner);
9479c57a
JK
3003 }
3004
a16878d2 3005 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 3006 g_free(ml);
314e2987
BS
3007 }
3008}
3009
5e8fd947 3010struct FlatViewInfo {
5e8fd947
AK
3011 int counter;
3012 bool dispatch_tree;
fc051ae6 3013 bool owner;
8072aae3
AK
3014 AccelClass *ac;
3015 const char *ac_name;
5e8fd947
AK
3016};
3017
3018static void mtree_print_flatview(gpointer key, gpointer value,
3019 gpointer user_data)
57bb40c9 3020{
5e8fd947
AK
3021 FlatView *view = key;
3022 GArray *fv_address_spaces = value;
3023 struct FlatViewInfo *fvi = user_data;
57bb40c9
PX
3024 FlatRange *range = &view->ranges[0];
3025 MemoryRegion *mr;
3026 int n = view->nr;
5e8fd947
AK
3027 int i;
3028 AddressSpace *as;
3029
b6b71cb5 3030 qemu_printf("FlatView #%d\n", fvi->counter);
5e8fd947
AK
3031 ++fvi->counter;
3032
3033 for (i = 0; i < fv_address_spaces->len; ++i) {
3034 as = g_array_index(fv_address_spaces, AddressSpace*, i);
b6b71cb5
MA
3035 qemu_printf(" AS \"%s\", root: %s",
3036 as->name, memory_region_name(as->root));
5e8fd947 3037 if (as->root->alias) {
b6b71cb5 3038 qemu_printf(", alias %s", memory_region_name(as->root->alias));
5e8fd947 3039 }
b6b71cb5 3040 qemu_printf("\n");
5e8fd947
AK
3041 }
3042
b6b71cb5 3043 qemu_printf(" Root memory region: %s\n",
5e8fd947 3044 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX
3045
3046 if (n <= 0) {
b6b71cb5 3047 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX
3048 return;
3049 }
3050
3051 while (n--) {
3052 mr = range->mr;
377a07aa 3053 if (range->offset_in_region) {
b6b71cb5
MA
3054 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3055 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3056 int128_get64(range->addr.start),
3057 int128_get64(range->addr.start)
3058 + MR_SIZE(range->addr.size),
3059 mr->priority,
3060 range->nonvolatile ? "nv-" : "",
3061 range->readonly ? "rom" : memory_region_type(mr),
3062 memory_region_name(mr),
3063 range->offset_in_region);
377a07aa 3064 } else {
b6b71cb5
MA
3065 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3066 " (prio %d, %s%s): %s",
3067 int128_get64(range->addr.start),
3068 int128_get64(range->addr.start)
3069 + MR_SIZE(range->addr.size),
3070 mr->priority,
3071 range->nonvolatile ? "nv-" : "",
3072 range->readonly ? "rom" : memory_region_type(mr),
3073 memory_region_name(mr));
377a07aa 3074 }
fc051ae6 3075 if (fvi->owner) {
b6b71cb5 3076 mtree_print_mr_owner(mr);
fc051ae6 3077 }
8072aae3
AK
3078
3079 if (fvi->ac) {
3080 for (i = 0; i < fv_address_spaces->len; ++i) {
3081 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3082 if (fvi->ac->has_memory(current_machine, as,
3083 int128_get64(range->addr.start),
3084 MR_SIZE(range->addr.size) + 1)) {
3085 qemu_printf(" %s", fvi->ac_name);
3086 }
3087 }
3088 }
b6b71cb5 3089 qemu_printf("\n");
57bb40c9
PX
3090 range++;
3091 }
3092
5e8fd947
AK
3093#if !defined(CONFIG_USER_ONLY)
3094 if (fvi->dispatch_tree && view->root) {
b6b71cb5 3095 mtree_print_dispatch(view->dispatch, view->root);
5e8fd947
AK
3096 }
3097#endif
3098
b6b71cb5 3099 qemu_printf("\n");
5e8fd947
AK
3100}
3101
3102static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3103 gpointer user_data)
3104{
3105 FlatView *view = key;
3106 GArray *fv_address_spaces = value;
3107
3108 g_array_unref(fv_address_spaces);
57bb40c9 3109 flatview_unref(view);
5e8fd947
AK
3110
3111 return true;
57bb40c9
PX
3112}
3113
b6b71cb5 3114void mtree_info(bool flatview, bool dispatch_tree, bool owner)
314e2987
BS
3115{
3116 MemoryRegionListHead ml_head;
3117 MemoryRegionList *ml, *ml2;
0d673e36 3118 AddressSpace *as;
314e2987 3119
57bb40c9 3120 if (flatview) {
5e8fd947
AK
3121 FlatView *view;
3122 struct FlatViewInfo fvi = {
5e8fd947 3123 .counter = 0,
fc051ae6
AK
3124 .dispatch_tree = dispatch_tree,
3125 .owner = owner,
5e8fd947
AK
3126 };
3127 GArray *fv_address_spaces;
3128 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
8072aae3
AK
3129 AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator);
3130
3131 if (ac->has_memory) {
3132 fvi.ac = ac;
3133 fvi.ac_name = current_machine->accel ? current_machine->accel :
3134 object_class_get_name(OBJECT_CLASS(ac));
3135 }
5e8fd947
AK
3136
3137 /* Gather all FVs in one table */
57bb40c9 3138 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK
3139 view = address_space_get_flatview(as);
3140
3141 fv_address_spaces = g_hash_table_lookup(views, view);
3142 if (!fv_address_spaces) {
3143 fv_address_spaces = g_array_new(false, false, sizeof(as));
3144 g_hash_table_insert(views, view, fv_address_spaces);
3145 }
3146
3147 g_array_append_val(fv_address_spaces, as);
57bb40c9 3148 }
5e8fd947
AK
3149
3150 /* Print */
3151 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3152
3153 /* Free */
3154 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3155 g_hash_table_unref(views);
3156
57bb40c9
PX
3157 return;
3158 }
3159
314e2987
BS
3160 QTAILQ_INIT(&ml_head);
3161
0d673e36 3162 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b6b71cb5
MA
3163 qemu_printf("address-space: %s\n", as->name);
3164 mtree_print_mr(as->root, 1, 0, &ml_head, owner);
3165 qemu_printf("\n");
b9f9be88
BS
3166 }
3167
314e2987 3168 /* print aliased regions */
a16878d2 3169 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
b6b71cb5
MA
3170 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3171 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner);
3172 qemu_printf("\n");
314e2987
BS
3173 }
3174
a16878d2 3175 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3176 g_free(ml);
314e2987 3177 }
314e2987 3178}
b4fefef9 3179
b08199c6
PM
3180void memory_region_init_ram(MemoryRegion *mr,
3181 struct Object *owner,
3182 const char *name,
3183 uint64_t size,
3184 Error **errp)
3185{
3186 DeviceState *owner_dev;
3187 Error *err = NULL;
3188
3189 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3190 if (err) {
3191 error_propagate(errp, err);
3192 return;
3193 }
3194 /* This will assert if owner is neither NULL nor a DeviceState.
3195 * We only want the owner here for the purposes of defining a
3196 * unique name for migration. TODO: Ideally we should implement
3197 * a naming scheme for Objects which are not DeviceStates, in
3198 * which case we can relax this restriction.
3199 */
3200 owner_dev = DEVICE(owner);
3201 vmstate_register_ram(mr, owner_dev);
3202}
3203
3204void memory_region_init_rom(MemoryRegion *mr,
3205 struct Object *owner,
3206 const char *name,
3207 uint64_t size,
3208 Error **errp)
3209{
3210 DeviceState *owner_dev;
3211 Error *err = NULL;
3212
3213 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3214 if (err) {
3215 error_propagate(errp, err);
3216 return;
3217 }
3218 /* This will assert if owner is neither NULL nor a DeviceState.
3219 * We only want the owner here for the purposes of defining a
3220 * unique name for migration. TODO: Ideally we should implement
3221 * a naming scheme for Objects which are not DeviceStates, in
3222 * which case we can relax this restriction.
3223 */
3224 owner_dev = DEVICE(owner);
3225 vmstate_register_ram(mr, owner_dev);
3226}
3227
3228void memory_region_init_rom_device(MemoryRegion *mr,
3229 struct Object *owner,
3230 const MemoryRegionOps *ops,
3231 void *opaque,
3232 const char *name,
3233 uint64_t size,
3234 Error **errp)
3235{
3236 DeviceState *owner_dev;
3237 Error *err = NULL;
3238
3239 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3240 name, size, &err);
3241 if (err) {
3242 error_propagate(errp, err);
3243 return;
3244 }
3245 /* This will assert if owner is neither NULL nor a DeviceState.
3246 * We only want the owner here for the purposes of defining a
3247 * unique name for migration. TODO: Ideally we should implement
3248 * a naming scheme for Objects which are not DeviceStates, in
3249 * which case we can relax this restriction.
3250 */
3251 owner_dev = DEVICE(owner);
3252 vmstate_register_ram(mr, owner_dev);
3253}
3254
b4fefef9
PC
3255static const TypeInfo memory_region_info = {
3256 .parent = TYPE_OBJECT,
3257 .name = TYPE_MEMORY_REGION,
1b53ecd9 3258 .class_size = sizeof(MemoryRegionClass),
b4fefef9
PC
3259 .instance_size = sizeof(MemoryRegion),
3260 .instance_init = memory_region_initfn,
3261 .instance_finalize = memory_region_finalize,
3262};
3263
3df9d748
AK
3264static const TypeInfo iommu_memory_region_info = {
3265 .parent = TYPE_MEMORY_REGION,
3266 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3267 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3268 .instance_size = sizeof(IOMMUMemoryRegion),
3269 .instance_init = iommu_memory_region_initfn,
1221a474 3270 .abstract = true,
3df9d748
AK
3271};
3272
b4fefef9
PC
3273static void memory_register_types(void)
3274{
3275 type_register_static(&memory_region_info);
3df9d748 3276 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3277}
3278
3279type_init(memory_register_types)