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target/i386: add TCG support for UMIP
[mirror_qemu.git] / softmmu / memory.c
CommitLineData
093bc2cd
AK		 1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB		 12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK		 14 */
15
d38ea87a 16#include "qemu/osdep.h"
21786c7e 17#include "qemu/log.h"
da34e65c 18#include "qapi/error.h"
022c62cb 19#include "exec/memory.h"
409ddd01 20#include "qapi/visitor.h"
1de7afc9 21#include "qemu/bitops.h"
8c56c1a5 22#include "qemu/error-report.h"
db725815 23#include "qemu/main-loop.h"
b6b71cb5 24#include "qemu/qemu-print.h"
2c9b15ca 25#include "qom/object.h"
8b7a5507 26#include "trace.h"
093bc2cd 27
022c62cb 28#include "exec/memory-internal.h"
220c3ebd 29#include "exec/ram_addr.h"
8c56c1a5 30#include "sysemu/kvm.h"
54d31236 31#include "sysemu/runstate.h"
14a48c1d 32#include "sysemu/tcg.h"
940e43aa 33#include "qemu/accel.h"
8072aae3 34#include "hw/boards.h"
b08199c6 35#include "migration/vmstate.h"
67d95c15 36
d197063f
PB		 37//#define DEBUG_UNASSIGNED
38
22bde714
JK		 39static unsigned memory_region_transaction_depth;
40static bool memory_region_update_pending;
4dc56152 41static bool ioeventfd_update_pending;
63b41db4 42unsigned int global_dirty_tracking;
7664e80c 43
eae3eb3e 44static QTAILQ_HEAD(, MemoryListener) memory_listeners
72e22d2f 45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 46
0d673e36
AK		 47static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
967dc9b1
AK		 50static GHashTable *flat_views;
51
093bc2cd
AK		 52typedef struct AddrRange AddrRange;
53
8417cebf 54/*
c9cdaa3a 55 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK		 56 * (large MemoryRegion::alias_offset).
57 */
093bc2cd 58struct AddrRange {
08dafab4
AK		 59 Int128 start;
60 Int128 size;
093bc2cd
AK		 61};
62
08dafab4 63static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK		 64{
65 return (AddrRange) { start, size };
66}
67
68static bool addrrange_equal(AddrRange r1, AddrRange r2)
69{
08dafab4 70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK		 71}
72
08dafab4 73static Int128 addrrange_end(AddrRange r)
093bc2cd 74{
08dafab4 75 return int128_add(r.start, r.size);
093bc2cd
AK		 76}
77
08dafab4 78static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 79{
08dafab4 80 int128_addto(&range.start, delta);
093bc2cd
AK		 81 return range;
82}
83
08dafab4
AK		 84static bool addrrange_contains(AddrRange range, Int128 addr)
85{
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88}
89
093bc2cd
AK		 90static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91{
08dafab4
AK		 92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
093bc2cd
AK		 94}
95
96static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97{
08dafab4
AK		 98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK		 101}
102
0e0d36b4
AK		 103enum ListenerDirection { Forward, Reverse };
104
7376e582 105#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK		 106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK		 112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
0e0d36b4
AK		 115 } \
116 break; \
117 case Reverse: \
eae3eb3e 118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
975aefe0
AK		 119 if (_listener->_callback) { \
120 _listener->_callback(_listener, ##_args); \
121 } \
0e0d36b4
AK		 122 } \
123 break; \
124 default: \
125 abort(); \
126 } \
127 } while (0)
128
9a54635d 129#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK		 130 do { \
131 MemoryListener *_listener; \
132 \
133 switch (_direction) { \
134 case Forward: \
eae3eb3e 135 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
9a54635d 136 if (_listener->_callback) { \
7376e582
AK		 137 _listener->_callback(_listener, _section, ##_args); \
138 } \
139 } \
140 break; \
141 case Reverse: \
eae3eb3e 142 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
9a54635d 143 if (_listener->_callback) { \
7376e582
AK		 144 _listener->_callback(_listener, _section, ##_args); \
145 } \
146 } \
147 break; \
148 default: \
149 abort(); \
150 } \
151 } while (0)
152
dfde4e6e 153/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 154#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 155 do { \
16620684
AK		 156 MemoryRegionSection mrs = section_from_flat_range(fr, \
157 address_space_to_flatview(as)); \
9a54635d 158 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 159 } while(0)
0e0d36b4 160
093bc2cd
AK		 161struct CoalescedMemoryRange {
162 AddrRange addr;
163 QTAILQ_ENTRY(CoalescedMemoryRange) link;
164};
165
3e9d69e7
AK		 166struct MemoryRegionIoeventfd {
167 AddrRange addr;
168 bool match_data;
169 uint64_t data;
753d5e14 170 EventNotifier *e;
3e9d69e7
AK		 171};
172
73bb753d
TB		 173static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
174 MemoryRegionIoeventfd *b)
3e9d69e7 175{
73bb753d 176 if (int128_lt(a->addr.start, b->addr.start)) {
3e9d69e7 177 return true;
73bb753d 178 } else if (int128_gt(a->addr.start, b->addr.start)) {
3e9d69e7 179 return false;
73bb753d 180 } else if (int128_lt(a->addr.size, b->addr.size)) {
3e9d69e7 181 return true;
73bb753d 182 } else if (int128_gt(a->addr.size, b->addr.size)) {
3e9d69e7 183 return false;
73bb753d 184 } else if (a->match_data < b->match_data) {
3e9d69e7 185 return true;
73bb753d 186 } else if (a->match_data > b->match_data) {
3e9d69e7 187 return false;
73bb753d
TB		 188 } else if (a->match_data) {
189 if (a->data < b->data) {
3e9d69e7 190 return true;
73bb753d 191 } else if (a->data > b->data) {
3e9d69e7
AK		 192 return false;
193 }
194 }
73bb753d 195 if (a->e < b->e) {
3e9d69e7 196 return true;
73bb753d 197 } else if (a->e > b->e) {
3e9d69e7
AK		 198 return false;
199 }
200 return false;
201}
202
73bb753d
TB		 203static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
204 MemoryRegionIoeventfd *b)
3e9d69e7 205{
e6ffd757
EA		 206 if (int128_eq(a->addr.start, b->addr.start) &&
207 (!int128_nz(a->addr.size) || !int128_nz(b->addr.size) ||
208 (int128_eq(a->addr.size, b->addr.size) &&
209 (a->match_data == b->match_data) &&
210 ((a->match_data && (a->data == b->data)) || !a->match_data) &&
211 (a->e == b->e))))
212 return true;
213
214 return false;
3e9d69e7
AK		 215}
216
093bc2cd
AK		 217/* Range of memory in the global map. Addresses are absolute. */
218struct FlatRange {
219 MemoryRegion *mr;
a8170e5e 220 hwaddr offset_in_region;
093bc2cd 221 AddrRange addr;
5a583347 222 uint8_t dirty_log_mask;
b138e654 223 bool romd_mode;
fb1cd6f9 224 bool readonly;
c26763f8 225 bool nonvolatile;
093bc2cd
AK		 226};
227
093bc2cd
AK		 228#define FOR_EACH_FLAT_RANGE(var, view) \
229 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
230
9c1f8f44 231static inline MemoryRegionSection
16620684 232section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB		 233{
234 return (MemoryRegionSection) {
235 .mr = fr->mr,
16620684 236 .fv = fv,
9c1f8f44
PB		 237 .offset_within_region = fr->offset_in_region,
238 .size = fr->addr.size,
239 .offset_within_address_space = int128_get64(fr->addr.start),
240 .readonly = fr->readonly,
c26763f8 241 .nonvolatile = fr->nonvolatile,
9c1f8f44
PB		 242 };
243}
244
093bc2cd
AK		 245static bool flatrange_equal(FlatRange *a, FlatRange *b)
246{
247 return a->mr == b->mr
248 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 249 && a->offset_in_region == b->offset_in_region
b138e654 250 && a->romd_mode == b->romd_mode
c26763f8
MAL		 251 && a->readonly == b->readonly
252 && a->nonvolatile == b->nonvolatile;
093bc2cd
AK		 253}
254
89c177bb 255static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 256{
cc94cd6d
AK		 257 FlatView *view;
258
259 view = g_new0(FlatView, 1);
856d7245 260 view->ref = 1;
89c177bb
AK		 261 view->root = mr_root;
262 memory_region_ref(mr_root);
02d9651d 263 trace_flatview_new(view, mr_root);
cc94cd6d
AK		 264
265 return view;
093bc2cd
AK		 266}
267
268/* Insert a range into a given position. Caller is responsible for maintaining
269 * sorting order.
270 */
271static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
272{
273 if (view->nr == view->nr_allocated) {
274 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 275 view->ranges = g_realloc(view->ranges,
093bc2cd
AK		 276 view->nr_allocated * sizeof(*view->ranges));
277 }
278 memmove(view->ranges + pos + 1, view->ranges + pos,
279 (view->nr - pos) * sizeof(FlatRange));
280 view->ranges[pos] = *range;
dfde4e6e 281 memory_region_ref(range->mr);
093bc2cd
AK		 282 ++view->nr;
283}
284
285static void flatview_destroy(FlatView *view)
286{
dfde4e6e
PB		 287 int i;
288
02d9651d 289 trace_flatview_destroy(view, view->root);
66a6df1d
AK		 290 if (view->dispatch) {
291 address_space_dispatch_free(view->dispatch);
292 }
dfde4e6e
PB		 293 for (i = 0; i < view->nr; i++) {
294 memory_region_unref(view->ranges[i].mr);
295 }
7267c094 296 g_free(view->ranges);
89c177bb 297 memory_region_unref(view->root);
a9a0c06d 298 g_free(view);
093bc2cd
AK		 299}
300
447b0d0b 301static bool flatview_ref(FlatView *view)
856d7245 302{
d73415a3 303 return qatomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB		 304}
305
48564041 306void flatview_unref(FlatView *view)
856d7245 307{
d73415a3 308 if (qatomic_fetch_dec(&view->ref) == 1) {
02d9651d 309 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 310 assert(view->root);
66a6df1d 311 call_rcu(view, flatview_destroy, rcu);
856d7245
PB		 312 }
313}
314
3d8e6bf9
AK		 315static bool can_merge(FlatRange *r1, FlatRange *r2)
316{
08dafab4 317 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 318 && r1->mr == r2->mr
08dafab4
AK		 319 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
320 r1->addr.size),
321 int128_make64(r2->offset_in_region))
d0a9b5bc 322 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 323 && r1->romd_mode == r2->romd_mode
c26763f8
MAL		 324 && r1->readonly == r2->readonly
325 && r1->nonvolatile == r2->nonvolatile;
3d8e6bf9
AK		 326}
327
8508e024 328/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK		 329static void flatview_simplify(FlatView *view)
330{
838ec117 331 unsigned i, j, k;
3d8e6bf9
AK		 332
333 i = 0;
334 while (i < view->nr) {
335 j = i + 1;
336 while (j < view->nr
337 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 338 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK		 339 ++j;
340 }
341 ++i;
838ec117
KW		 342 for (k = i; k < j; k++) {
343 memory_region_unref(view->ranges[k].mr);
344 }
3d8e6bf9
AK		 345 memmove(&view->ranges[i], &view->ranges[j],
346 (view->nr - j) * sizeof(view->ranges[j]));
347 view->nr -= j - i;
348 }
349}
350
e7342aa3
PB		 351static bool memory_region_big_endian(MemoryRegion *mr)
352{
353#ifdef TARGET_WORDS_BIGENDIAN
354 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
355#else
356 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
357#endif
358}
359
9bf825bf 360static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
e11ef3d1 361{
9bf825bf
TN		 362 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
363 switch (op & MO_SIZE) {
364 case MO_8:
e11ef3d1 365 break;
9bf825bf 366 case MO_16:
e11ef3d1
PB		 367 *data = bswap16(*data);
368 break;
9bf825bf 369 case MO_32:
e11ef3d1
PB		 370 *data = bswap32(*data);
371 break;
9bf825bf 372 case MO_64:
e11ef3d1
PB		 373 *data = bswap64(*data);
374 break;
375 default:
9bf825bf 376 g_assert_not_reached();
e11ef3d1
PB		 377 }
378 }
379}
380
3c754a93 381static inline void memory_region_shift_read_access(uint64_t *value,
98f52cdb 382 signed shift,
3c754a93
PMD		 383 uint64_t mask,
384 uint64_t tmp)
385{
98f52cdb
PMD		 386 if (shift >= 0) {
387 *value |= (tmp & mask) << shift;
388 } else {
389 *value |= (tmp & mask) >> -shift;
390 }
3c754a93
PMD		 391}
392
393static inline uint64_t memory_region_shift_write_access(uint64_t *value,
98f52cdb 394 signed shift,
3c754a93
PMD		 395 uint64_t mask)
396{
98f52cdb
PMD		 397 uint64_t tmp;
398
399 if (shift >= 0) {
400 tmp = (*value >> shift) & mask;
401 } else {
402 tmp = (*value << -shift) & mask;
403 }
404
405 return tmp;
3c754a93
PMD		 406}
407
4779dc1d
HB		 408static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
409{
410 MemoryRegion *root;
411 hwaddr abs_addr = offset;
412
413 abs_addr += mr->addr;
414 for (root = mr; root->container; ) {
415 root = root->container;
416 abs_addr += root->addr;
417 }
418
419 return abs_addr;
420}
421
5a68be94
HB		 422static int get_cpu_index(void)
423{
424 if (current_cpu) {
425 return current_cpu->cpu_index;
426 }
427 return -1;
428}
429
cc05c43a 430static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB		 431 hwaddr addr,
432 uint64_t *value,
433 unsigned size,
98f52cdb 434 signed shift,
cc05c43a
PM		 435 uint64_t mask,
436 MemTxAttrs attrs)
ce5d2f33 437{
ce5d2f33
PB		 438 uint64_t tmp;
439
cc05c43a 440 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 441 if (mr->subpage) {
5a68be94 442 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
380ea843 443 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
4779dc1d 444 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
9bb54054
PMD		 445 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size,
446 memory_region_name(mr));
23d92d68 447 }
3c754a93 448 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 449 return MEMTX_OK;
ce5d2f33
PB		 450}
451
cc05c43a
PM		 452static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
453 hwaddr addr,
454 uint64_t *value,
455 unsigned size,
98f52cdb 456 signed shift,
cc05c43a
PM		 457 uint64_t mask,
458 MemTxAttrs attrs)
164a4dcd 459{
cc05c43a
PM		 460 uint64_t tmp = 0;
461 MemTxResult r;
164a4dcd 462
cc05c43a 463 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 464 if (mr->subpage) {
5a68be94 465 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
380ea843 466 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
4779dc1d 467 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
9bb54054
PMD		 468 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size,
469 memory_region_name(mr));
23d92d68 470 }
3c754a93 471 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 472 return r;
164a4dcd
AK		 473}
474
cc05c43a
PM		 475static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
476 hwaddr addr,
477 uint64_t *value,
478 unsigned size,
98f52cdb 479 signed shift,
cc05c43a
PM		 480 uint64_t mask,
481 MemTxAttrs attrs)
164a4dcd 482{
3c754a93 483 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
164a4dcd 484
23d92d68 485 if (mr->subpage) {
5a68be94 486 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
380ea843 487 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
4779dc1d 488 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
9bb54054
PMD		 489 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size,
490 memory_region_name(mr));
23d92d68 491 }
164a4dcd 492 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 493 return MEMTX_OK;
164a4dcd
AK		 494}
495
cc05c43a
PM		 496static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
497 hwaddr addr,
498 uint64_t *value,
499 unsigned size,
98f52cdb 500 signed shift,
cc05c43a
PM		 501 uint64_t mask,
502 MemTxAttrs attrs)
503{
3c754a93 504 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
cc05c43a 505
23d92d68 506 if (mr->subpage) {
5a68be94 507 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
380ea843 508 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
4779dc1d 509 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
9bb54054
PMD		 510 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size,
511 memory_region_name(mr));
23d92d68 512 }
cc05c43a
PM		 513 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
514}
515
516static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK		 517 uint64_t *value,
518 unsigned size,
519 unsigned access_size_min,
520 unsigned access_size_max,
05e015f7
KF		 521 MemTxResult (*access_fn)
522 (MemoryRegion *mr,
523 hwaddr addr,
524 uint64_t *value,
525 unsigned size,
98f52cdb 526 signed shift,
05e015f7
KF		 527 uint64_t mask,
528 MemTxAttrs attrs),
cc05c43a
PM		 529 MemoryRegion *mr,
530 MemTxAttrs attrs)
164a4dcd
AK		 531{
532 uint64_t access_mask;
533 unsigned access_size;
534 unsigned i;
cc05c43a 535 MemTxResult r = MEMTX_OK;
164a4dcd
AK		 536
537 if (!access_size_min) {
538 access_size_min = 1;
539 }
540 if (!access_size_max) {
541 access_size_max = 4;
542 }
ce5d2f33
PB		 543
544 /* FIXME: support unaligned access? */
164a4dcd 545 access_size = MAX(MIN(size, access_size_max), access_size_min);
36960b4d 546 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
e7342aa3
PB		 547 if (memory_region_big_endian(mr)) {
548 for (i = 0; i < size; i += access_size) {
05e015f7 549 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 550 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB		 551 }
552 } else {
553 for (i = 0; i < size; i += access_size) {
05e015f7 554 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 555 access_mask, attrs);
e7342aa3 556 }
164a4dcd 557 }
cc05c43a 558 return r;
164a4dcd
AK		 559}
560
e2177955
AK		 561static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
562{
0d673e36
AK		 563 AddressSpace *as;
564
feca4ac1
PB		 565 while (mr->container) {
566 mr = mr->container;
e2177955 567 }
0d673e36
AK		 568 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
569 if (mr == as->root) {
570 return as;
571 }
e2177955 572 }
eed2bacf 573 return NULL;
e2177955
AK		 574}
575
093bc2cd
AK		 576/* Render a memory region into the global view. Ranges in @view obscure
577 * ranges in @mr.
578 */
579static void render_memory_region(FlatView *view,
580 MemoryRegion *mr,
08dafab4 581 Int128 base,
fb1cd6f9 582 AddrRange clip,
c26763f8
MAL		 583 bool readonly,
584 bool nonvolatile)
093bc2cd
AK		 585{
586 MemoryRegion *subregion;
587 unsigned i;
a8170e5e 588 hwaddr offset_in_region;
08dafab4
AK		 589 Int128 remain;
590 Int128 now;
093bc2cd
AK		 591 FlatRange fr;
592 AddrRange tmp;
593
6bba19ba
AK		 594 if (!mr->enabled) {
595 return;
596 }
597
08dafab4 598 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 599 readonly |= mr->readonly;
c26763f8 600 nonvolatile |= mr->nonvolatile;
093bc2cd
AK		 601
602 tmp = addrrange_make(base, mr->size);
603
604 if (!addrrange_intersects(tmp, clip)) {
605 return;
606 }
607
608 clip = addrrange_intersection(tmp, clip);
609
610 if (mr->alias) {
08dafab4
AK		 611 int128_subfrom(&base, int128_make64(mr->alias->addr));
612 int128_subfrom(&base, int128_make64(mr->alias_offset));
c26763f8
MAL		 613 render_memory_region(view, mr->alias, base, clip,
614 readonly, nonvolatile);
093bc2cd
AK		 615 return;
616 }
617
618 /* Render subregions in priority order. */
619 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
c26763f8
MAL		 620 render_memory_region(view, subregion, base, clip,
621 readonly, nonvolatile);
093bc2cd
AK		 622 }
623
14a3c10a 624 if (!mr->terminates) {
093bc2cd
AK		 625 return;
626 }
627
08dafab4 628 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK		 629 base = clip.start;
630 remain = clip.size;
631
2eb74e1a 632 fr.mr = mr;
6f6a5ef3 633 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 634 fr.romd_mode = mr->romd_mode;
2eb74e1a 635 fr.readonly = readonly;
c26763f8 636 fr.nonvolatile = nonvolatile;
2eb74e1a 637
093bc2cd 638 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK		 639 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
640 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK		 641 continue;
642 }
08dafab4
AK		 643 if (int128_lt(base, view->ranges[i].addr.start)) {
644 now = int128_min(remain,
645 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK		 646 fr.offset_in_region = offset_in_region;
647 fr.addr = addrrange_make(base, now);
648 flatview_insert(view, i, &fr);
649 ++i;
08dafab4
AK		 650 int128_addto(&base, now);
651 offset_in_region += int128_get64(now);
652 int128_subfrom(&remain, now);
093bc2cd 653 }
d26a8cae
AK		 654 now = int128_sub(int128_min(int128_add(base, remain),
655 addrrange_end(view->ranges[i].addr)),
656 base);
657 int128_addto(&base, now);
658 offset_in_region += int128_get64(now);
659 int128_subfrom(&remain, now);
093bc2cd 660 }
08dafab4 661 if (int128_nz(remain)) {
093bc2cd
AK		 662 fr.offset_in_region = offset_in_region;
663 fr.addr = addrrange_make(base, remain);
664 flatview_insert(view, i, &fr);
665 }
666}
667
fb5ef4ee
AB		 668void flatview_for_each_range(FlatView *fv, flatview_cb cb , void *opaque)
669{
670 FlatRange *fr;
671
672 assert(fv);
673 assert(cb);
674
675 FOR_EACH_FLAT_RANGE(fr, fv) {
b3566001
PM		 676 if (cb(fr->addr.start, fr->addr.size, fr->mr,
677 fr->offset_in_region, opaque)) {
fb5ef4ee 678 break;
b3566001 679 }
fb5ef4ee
AB		 680 }
681}
682
89c177bb
AK		 683static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
684{
e673ba9a
PB		 685 while (mr->enabled) {
686 if (mr->alias) {
687 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
688 /* The alias is included in its entirety. Use it as
689 * the "real" root, so that we can share more FlatViews.
690 */
691 mr = mr->alias;
692 continue;
693 }
694 } else if (!mr->terminates) {
695 unsigned int found = 0;
696 MemoryRegion *child, *next = NULL;
697 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
698 if (child->enabled) {
699 if (++found > 1) {
700 next = NULL;
701 break;
702 }
703 if (!child->addr && int128_ge(mr->size, child->size)) {
704 /* A child is included in its entirety. If it's the only
705 * enabled one, use it in the hope of finding an alias down the
706 * way. This will also let us share FlatViews.
707 */
708 next = child;
709 }
710 }
711 }
092aa2fc
AK		 712 if (found == 0) {
713 return NULL;
714 }
e673ba9a
PB		 715 if (next) {
716 mr = next;
717 continue;
718 }
719 }
720
092aa2fc 721 return mr;
89c177bb
AK		 722 }
723
092aa2fc 724 return NULL;
89c177bb
AK		 725}
726
093bc2cd 727/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 728static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 729{
9bf561e3 730 int i;
a9a0c06d 731 FlatView *view;
093bc2cd 732
89c177bb 733 view = flatview_new(mr);
093bc2cd 734
83f3c251 735 if (mr) {
a9a0c06d 736 render_memory_region(view, mr, int128_zero(),
c26763f8
MAL		 737 addrrange_make(int128_zero(), int128_2_64()),
738 false, false);
83f3c251 739 }
a9a0c06d 740 flatview_simplify(view);
093bc2cd 741
9bf561e3
AK		 742 view->dispatch = address_space_dispatch_new(view);
743 for (i = 0; i < view->nr; i++) {
744 MemoryRegionSection mrs =
745 section_from_flat_range(&view->ranges[i], view);
746 flatview_add_to_dispatch(view, &mrs);
747 }
748 address_space_dispatch_compact(view->dispatch);
967dc9b1 749 g_hash_table_replace(flat_views, mr, view);
9bf561e3 750
093bc2cd
AK		 751 return view;
752}
753
3e9d69e7
AK		 754static void address_space_add_del_ioeventfds(AddressSpace *as,
755 MemoryRegionIoeventfd *fds_new,
756 unsigned fds_new_nb,
757 MemoryRegionIoeventfd *fds_old,
758 unsigned fds_old_nb)
759{
760 unsigned iold, inew;
80a1ea37
AK		 761 MemoryRegionIoeventfd *fd;
762 MemoryRegionSection section;
3e9d69e7
AK		 763
764 /* Generate a symmetric difference of the old and new fd sets, adding
765 * and deleting as necessary.
766 */
767
768 iold = inew = 0;
769 while (iold < fds_old_nb || inew < fds_new_nb) {
770 if (iold < fds_old_nb
771 && (inew == fds_new_nb
73bb753d
TB		 772 || memory_region_ioeventfd_before(&fds_old[iold],
773 &fds_new[inew]))) {
80a1ea37
AK		 774 fd = &fds_old[iold];
775 section = (MemoryRegionSection) {
16620684 776 .fv = address_space_to_flatview(as),
80a1ea37 777 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 778 .size = fd->addr.size,
80a1ea37 779 };
9a54635d 780 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 781 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 782 ++iold;
783 } else if (inew < fds_new_nb
784 && (iold == fds_old_nb
73bb753d
TB		 785 || memory_region_ioeventfd_before(&fds_new[inew],
786 &fds_old[iold]))) {
80a1ea37
AK		 787 fd = &fds_new[inew];
788 section = (MemoryRegionSection) {
16620684 789 .fv = address_space_to_flatview(as),
80a1ea37 790 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 791 .size = fd->addr.size,
80a1ea37 792 };
9a54635d 793 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 794 fd->match_data, fd->data, fd->e);
3e9d69e7
AK		 795 ++inew;
796 } else {
797 ++iold;
798 ++inew;
799 }
800 }
801}
802
48564041 803FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB		 804{
805 FlatView *view;
806
694ea274 807 RCU_READ_LOCK_GUARD();
447b0d0b 808 do {
16620684 809 view = address_space_to_flatview(as);
447b0d0b
PB		 810 /* If somebody has replaced as->current_map concurrently,
811 * flatview_ref returns false.
812 */
813 } while (!flatview_ref(view));
856d7245
PB		 814 return view;
815}
816
3e9d69e7
AK		 817static void address_space_update_ioeventfds(AddressSpace *as)
818{
99e86347 819 FlatView *view;
3e9d69e7
AK		 820 FlatRange *fr;
821 unsigned ioeventfd_nb = 0;
920d557e
SH		 822 unsigned ioeventfd_max;
823 MemoryRegionIoeventfd *ioeventfds;
3e9d69e7
AK		 824 AddrRange tmp;
825 unsigned i;
826
920d557e
SH		 827 /*
828 * It is likely that the number of ioeventfds hasn't changed much, so use
829 * the previous size as the starting value, with some headroom to avoid
830 * gratuitous reallocations.
831 */
832 ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4);
833 ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max);
834
856d7245 835 view = address_space_get_flatview(as);
99e86347 836 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK		 837 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
838 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK		 839 int128_sub(fr->addr.start,
840 int128_make64(fr->offset_in_region)));
3e9d69e7
AK		 841 if (addrrange_intersects(fr->addr, tmp)) {
842 ++ioeventfd_nb;
920d557e
SH		 843 if (ioeventfd_nb > ioeventfd_max) {
844 ioeventfd_max = MAX(ioeventfd_max * 2, 4);
845 ioeventfds = g_realloc(ioeventfds,
846 ioeventfd_max * sizeof(*ioeventfds));
847 }
3e9d69e7
AK		 848 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
849 ioeventfds[ioeventfd_nb-1].addr = tmp;
850 }
851 }
852 }
853
854 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
855 as->ioeventfds, as->ioeventfd_nb);
856
7267c094 857 g_free(as->ioeventfds);
3e9d69e7
AK		 858 as->ioeventfds = ioeventfds;
859 as->ioeventfd_nb = ioeventfd_nb;
856d7245 860 flatview_unref(view);
3e9d69e7
AK		 861}
862
23f1174a
PX		 863/*
864 * Notify the memory listeners about the coalesced IO change events of
865 * range `cmr'. Only the part that has intersection of the specified
866 * FlatRange will be sent.
867 */
868static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
869 CoalescedMemoryRange *cmr, bool add)
870{
871 AddrRange tmp;
872
873 tmp = addrrange_shift(cmr->addr,
874 int128_sub(fr->addr.start,
875 int128_make64(fr->offset_in_region)));
876 if (!addrrange_intersects(tmp, fr->addr)) {
877 return;
878 }
879 tmp = addrrange_intersection(tmp, fr->addr);
880
881 if (add) {
882 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
883 int128_get64(tmp.start),
884 int128_get64(tmp.size));
885 } else {
886 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
887 int128_get64(tmp.start),
888 int128_get64(tmp.size));
889 }
890}
891
909bf763
PB		 892static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
893{
23f1174a
PX		 894 CoalescedMemoryRange *cmr;
895
23f1174a
PX		 896 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
897 flat_range_coalesced_io_notify(fr, as, cmr, false);
898 }
909bf763
PB		 899}
900
901static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
902{
903 MemoryRegion *mr = fr->mr;
904 CoalescedMemoryRange *cmr;
909bf763 905
1f7af804
PB		 906 if (QTAILQ_EMPTY(&mr->coalesced)) {
907 return;
908 }
909
909bf763 910 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
23f1174a 911 flat_range_coalesced_io_notify(fr, as, cmr, true);
909bf763
PB		 912 }
913}
914
b8af1afb 915static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB		 916 const FlatView *old_view,
917 const FlatView *new_view,
b8af1afb 918 bool adding)
093bc2cd 919{
093bc2cd
AK		 920 unsigned iold, inew;
921 FlatRange *frold, *frnew;
093bc2cd
AK		 922
923 /* Generate a symmetric difference of the old and new memory maps.
924 * Kill ranges in the old map, and instantiate ranges in the new map.
925 */
926 iold = inew = 0;
a9a0c06d
PB		 927 while (iold < old_view->nr || inew < new_view->nr) {
928 if (iold < old_view->nr) {
929 frold = &old_view->ranges[iold];
093bc2cd
AK		 930 } else {
931 frold = NULL;
932 }
a9a0c06d
PB		 933 if (inew < new_view->nr) {
934 frnew = &new_view->ranges[inew];
093bc2cd
AK		 935 } else {
936 frnew = NULL;
937 }
938
939 if (frold
940 && (!frnew
08dafab4
AK		 941 || int128_lt(frold->addr.start, frnew->addr.start)
942 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 943 && !flatrange_equal(frold, frnew)))) {
41a6e477 944 /* In old but not in new, or in both but attributes changed. */
093bc2cd 945
b8af1afb 946 if (!adding) {
3ac7d43a 947 flat_range_coalesced_io_del(frold, as);
72e22d2f 948 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK		 949 }
950
093bc2cd
AK		 951 ++iold;
952 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 953 /* In both and unchanged (except logging may have changed) */
093bc2cd 954
4f826024 955 if (adding) {
50c1e149 956 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB		 957 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
958 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
959 frold->dirty_log_mask,
960 frnew->dirty_log_mask);
961 }
962 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
963 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
964 frold->dirty_log_mask,
965 frnew->dirty_log_mask);
b8af1afb 966 }
5a583347
AK		 967 }
968
093bc2cd
AK		 969 ++iold;
970 ++inew;
093bc2cd
AK		 971 } else {
972 /* In new */
973
b8af1afb 974 if (adding) {
72e22d2f 975 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
3ac7d43a 976 flat_range_coalesced_io_add(frnew, as);
b8af1afb
AK		 977 }
978
093bc2cd
AK		 979 ++inew;
980 }
981 }
b8af1afb
AK		 982}
983
967dc9b1
AK		 984static void flatviews_init(void)
985{
092aa2fc
AK		 986 static FlatView *empty_view;
987
967dc9b1
AK		 988 if (flat_views) {
989 return;
990 }
991
992 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
993 (GDestroyNotify) flatview_unref);
092aa2fc
AK		 994 if (!empty_view) {
995 empty_view = generate_memory_topology(NULL);
996 /* We keep it alive forever in the global variable. */
997 flatview_ref(empty_view);
998 } else {
999 g_hash_table_replace(flat_views, NULL, empty_view);
1000 flatview_ref(empty_view);
1001 }
967dc9b1
AK		 1002}
1003
1004static void flatviews_reset(void)
1005{
1006 AddressSpace *as;
1007
1008 if (flat_views) {
1009 g_hash_table_unref(flat_views);
1010 flat_views = NULL;
1011 }
1012 flatviews_init();
1013
1014 /* Render unique FVs */
1015 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1016 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1017
1018 if (g_hash_table_lookup(flat_views, physmr)) {
1019 continue;
1020 }
1021
1022 generate_memory_topology(physmr);
1023 }
1024}
1025
1026static void address_space_set_flatview(AddressSpace *as)
b8af1afb 1027{
67ace39b 1028 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK		 1029 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1030 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1031
1032 assert(new_view);
1033
67ace39b
AK		 1034 if (old_view == new_view) {
1035 return;
1036 }
1037
1038 if (old_view) {
1039 flatview_ref(old_view);
1040 }
1041
967dc9b1 1042 flatview_ref(new_view);
9a62e24f
AK		 1043
1044 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK		 1045 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1046
1047 if (!old_view2) {
1048 old_view2 = &tmpview;
1049 }
1050 address_space_update_topology_pass(as, old_view2, new_view, false);
1051 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1052 }
b8af1afb 1053
374f2981 1054 /* Writes are protected by the BQL. */
d73415a3 1055 qatomic_rcu_set(&as->current_map, new_view);
67ace39b
AK		 1056 if (old_view) {
1057 flatview_unref(old_view);
1058 }
856d7245
PB		 1059
1060 /* Note that all the old MemoryRegions are still alive up to this
1061 * point. This relieves most MemoryListeners from the need to
1062 * ref/unref the MemoryRegions they get---unless they use them
1063 * outside the iothread mutex, in which case precise reference
1064 * counting is necessary.
1065 */
67ace39b
AK		 1066 if (old_view) {
1067 flatview_unref(old_view);
1068 }
093bc2cd
AK		 1069}
1070
202fc01b
AK		 1071static void address_space_update_topology(AddressSpace *as)
1072{
1073 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1074
1075 flatviews_init();
1076 if (!g_hash_table_lookup(flat_views, physmr)) {
1077 generate_memory_topology(physmr);
1078 }
1079 address_space_set_flatview(as);
1080}
1081
4ef4db86
AK		 1082void memory_region_transaction_begin(void)
1083{
bb880ded 1084 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK		 1085 ++memory_region_transaction_depth;
1086}
1087
1088void memory_region_transaction_commit(void)
1089{
0d673e36
AK		 1090 AddressSpace *as;
1091
4ef4db86 1092 assert(memory_region_transaction_depth);
8d04fb55
JK		 1093 assert(qemu_mutex_iothread_locked());
1094
4ef4db86 1095 --memory_region_transaction_depth;
4dc56152
GA		 1096 if (!memory_region_transaction_depth) {
1097 if (memory_region_update_pending) {
967dc9b1
AK		 1098 flatviews_reset();
1099
4dc56152 1100 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1101
4dc56152 1102 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1103 address_space_set_flatview(as);
02218487 1104 address_space_update_ioeventfds(as);
4dc56152 1105 }
ade9c1aa 1106 memory_region_update_pending = false;
0b152095 1107 ioeventfd_update_pending = false;
4dc56152
GA		 1108 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1109 } else if (ioeventfd_update_pending) {
1110 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1111 address_space_update_ioeventfds(as);
1112 }
ade9c1aa 1113 ioeventfd_update_pending = false;
4dc56152 1114 }
4dc56152 1115 }
4ef4db86
AK		 1116}
1117
545e92e0
AK		 1118static void memory_region_destructor_none(MemoryRegion *mr)
1119{
1120}
1121
1122static void memory_region_destructor_ram(MemoryRegion *mr)
1123{
f1060c55 1124 qemu_ram_free(mr->ram_block);
545e92e0
AK		 1125}
1126
b4fefef9
PC		 1127static bool memory_region_need_escape(char c)
1128{
1129 return c == '/' || c == '[' || c == '\\' || c == ']';
1130}
1131
1132static char *memory_region_escape_name(const char *name)
1133{
1134 const char *p;
1135 char *escaped, *q;
1136 uint8_t c;
1137 size_t bytes = 0;
1138
1139 for (p = name; *p; p++) {
1140 bytes += memory_region_need_escape(*p) ? 4 : 1;
1141 }
1142 if (bytes == p - name) {
1143 return g_memdup(name, bytes + 1);
1144 }
1145
1146 escaped = g_malloc(bytes + 1);
1147 for (p = name, q = escaped; *p; p++) {
1148 c = *p;
1149 if (unlikely(memory_region_need_escape(c))) {
1150 *q++ = '\\';
1151 *q++ = 'x';
1152 *q++ = "0123456789abcdef"[c >> 4];
1153 c = "0123456789abcdef"[c & 15];
1154 }
1155 *q++ = c;
1156 }
1157 *q = 0;
1158 return escaped;
1159}
1160
3df9d748
AK		 1161static void memory_region_do_init(MemoryRegion *mr,
1162 Object *owner,
1163 const char *name,
1164 uint64_t size)
093bc2cd 1165{
08dafab4
AK		 1166 mr->size = int128_make64(size);
1167 if (size == UINT64_MAX) {
1168 mr->size = int128_2_64();
1169 }
302fa283 1170 mr->name = g_strdup(name);
612263cf 1171 mr->owner = owner;
58eaa217 1172 mr->ram_block = NULL;
b4fefef9
PC		 1173
1174 if (name) {
843ef73a
PC		 1175 char *escaped_name = memory_region_escape_name(name);
1176 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB		 1177
1178 if (!owner) {
1179 owner = container_get(qdev_get_machine(), "/unattached");
1180 }
1181
d2623129 1182 object_property_add_child(owner, name_array, OBJECT(mr));
b4fefef9 1183 object_unref(OBJECT(mr));
843ef73a
PC		 1184 g_free(name_array);
1185 g_free(escaped_name);
b4fefef9
PC		 1186 }
1187}
1188
3df9d748
AK		 1189void memory_region_init(MemoryRegion *mr,
1190 Object *owner,
1191 const char *name,
1192 uint64_t size)
1193{
1194 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1195 memory_region_do_init(mr, owner, name, size);
1196}
1197
d7bce999
EB		 1198static void memory_region_get_container(Object *obj, Visitor *v,
1199 const char *name, void *opaque,
1200 Error **errp)
409ddd01
PC		 1201{
1202 MemoryRegion *mr = MEMORY_REGION(obj);
ddfb0baa 1203 char *path = (char *)"";
409ddd01
PC		 1204
1205 if (mr->container) {
1206 path = object_get_canonical_path(OBJECT(mr->container));
1207 }
51e72bc1 1208 visit_type_str(v, name, &path, errp);
409ddd01
PC		 1209 if (mr->container) {
1210 g_free(path);
1211 }
1212}
1213
1214static Object *memory_region_resolve_container(Object *obj, void *opaque,
1215 const char *part)
1216{
1217 MemoryRegion *mr = MEMORY_REGION(obj);
1218
1219 return OBJECT(mr->container);
1220}
1221
d7bce999
EB		 1222static void memory_region_get_priority(Object *obj, Visitor *v,
1223 const char *name, void *opaque,
1224 Error **errp)
d33382da
PC		 1225{
1226 MemoryRegion *mr = MEMORY_REGION(obj);
1227 int32_t value = mr->priority;
1228
51e72bc1 1229 visit_type_int32(v, name, &value, errp);
d33382da
PC		 1230}
1231
d7bce999
EB		 1232static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1233 void *opaque, Error **errp)
52aef7bb
PC		 1234{
1235 MemoryRegion *mr = MEMORY_REGION(obj);
1236 uint64_t value = memory_region_size(mr);
1237
51e72bc1 1238 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC		 1239}
1240
b4fefef9
PC		 1241static void memory_region_initfn(Object *obj)
1242{
1243 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1244 ObjectProperty *op;
b4fefef9
PC		 1245
1246 mr->ops = &unassigned_mem_ops;
6bba19ba 1247 mr->enabled = true;
5f9a5ea1 1248 mr->romd_mode = true;
545e92e0 1249 mr->destructor = memory_region_destructor_none;
093bc2cd 1250 QTAILQ_INIT(&mr->subregions);
093bc2cd 1251 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC		 1252
1253 op = object_property_add(OBJECT(mr), "container",
1254 "link<" TYPE_MEMORY_REGION ">",
1255 memory_region_get_container,
1256 NULL, /* memory_region_set_container */
d2623129 1257 NULL, NULL);
409ddd01
PC		 1258 op->resolve = memory_region_resolve_container;
1259
64a7b8de 1260 object_property_add_uint64_ptr(OBJECT(mr), "addr",
d2623129 1261 &mr->addr, OBJ_PROP_FLAG_READ);
d33382da
PC		 1262 object_property_add(OBJECT(mr), "priority", "uint32",
1263 memory_region_get_priority,
1264 NULL, /* memory_region_set_priority */
d2623129 1265 NULL, NULL);
52aef7bb
PC		 1266 object_property_add(OBJECT(mr), "size", "uint64",
1267 memory_region_get_size,
1268 NULL, /* memory_region_set_size, */
d2623129 1269 NULL, NULL);
093bc2cd
AK		 1270}
1271
3df9d748
AK		 1272static void iommu_memory_region_initfn(Object *obj)
1273{
1274 MemoryRegion *mr = MEMORY_REGION(obj);
1275
1276 mr->is_iommu = true;
1277}
1278
b018ddf6
PB		 1279static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1280 unsigned size)
1281{
1282#ifdef DEBUG_UNASSIGNED
1283 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1284#endif
68a7439a 1285 return 0;
b018ddf6
PB		 1286}
1287
1288static void unassigned_mem_write(void *opaque, hwaddr addr,
1289 uint64_t val, unsigned size)
1290{
1291#ifdef DEBUG_UNASSIGNED
1292 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1293#endif
b018ddf6
PB		 1294}
1295
d197063f 1296static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
8372d383
PM		 1297 unsigned size, bool is_write,
1298 MemTxAttrs attrs)
d197063f
PB		 1299{
1300 return false;
1301}
1302
1303const MemoryRegionOps unassigned_mem_ops = {
1304 .valid.accepts = unassigned_mem_accepts,
1305 .endianness = DEVICE_NATIVE_ENDIAN,
1306};
1307
4a2e242b
AW		 1308static uint64_t memory_region_ram_device_read(void *opaque,
1309 hwaddr addr, unsigned size)
1310{
1311 MemoryRegion *mr = opaque;
1312 uint64_t data = (uint64_t)~0;
1313
1314 switch (size) {
1315 case 1:
1316 data = *(uint8_t *)(mr->ram_block->host + addr);
1317 break;
1318 case 2:
1319 data = *(uint16_t *)(mr->ram_block->host + addr);
1320 break;
1321 case 4:
1322 data = *(uint32_t *)(mr->ram_block->host + addr);
1323 break;
1324 case 8:
1325 data = *(uint64_t *)(mr->ram_block->host + addr);
1326 break;
1327 }
1328
1329 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1330
1331 return data;
1332}
1333
1334static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1335 uint64_t data, unsigned size)
1336{
1337 MemoryRegion *mr = opaque;
1338
1339 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1340
1341 switch (size) {
1342 case 1:
1343 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1344 break;
1345 case 2:
1346 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1347 break;
1348 case 4:
1349 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1350 break;
1351 case 8:
1352 *(uint64_t *)(mr->ram_block->host + addr) = data;
1353 break;
1354 }
1355}
1356
1357static const MemoryRegionOps ram_device_mem_ops = {
1358 .read = memory_region_ram_device_read,
1359 .write = memory_region_ram_device_write,
c99a29e7 1360 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW		 1361 .valid = {
1362 .min_access_size = 1,
1363 .max_access_size = 8,
1364 .unaligned = true,
1365 },
1366 .impl = {
1367 .min_access_size = 1,
1368 .max_access_size = 8,
1369 .unaligned = true,
1370 },
1371};
1372
d2702032
PB		 1373bool memory_region_access_valid(MemoryRegion *mr,
1374 hwaddr addr,
1375 unsigned size,
6d7b9a6c
PM		 1376 bool is_write,
1377 MemTxAttrs attrs)
093bc2cd 1378{
5d971f9e
MT		 1379 if (mr->ops->valid.accepts
1380 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write, attrs)) {
7a7142f0
BZ		 1381 qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX
1382 ", size %u, region '%s', reason: rejected\n",
1383 is_write ? "write" : "read",
21786c7e 1384 addr, size, memory_region_name(mr));
093bc2cd
AK		 1385 return false;
1386 }
1387
5d971f9e 1388 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
7a7142f0
BZ		 1389 qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX
1390 ", size %u, region '%s', reason: unaligned\n",
1391 is_write ? "write" : "read",
21786c7e 1392 addr, size, memory_region_name(mr));
5d971f9e 1393 return false;
a014ed07
PB		 1394 }
1395
5d971f9e 1396 /* Treat zero as compatibility all valid */
a014ed07 1397 if (!mr->ops->valid.max_access_size) {
5d971f9e 1398 return true;
a014ed07
PB		 1399 }
1400
5d971f9e
MT		 1401 if (size > mr->ops->valid.max_access_size
1402 || size < mr->ops->valid.min_access_size) {
7a7142f0
BZ		 1403 qemu_log_mask(LOG_GUEST_ERROR, "Invalid %s at addr 0x%" HWADDR_PRIX
1404 ", size %u, region '%s', reason: invalid size "
1405 "(min:%u max:%u)\n",
1406 is_write ? "write" : "read",
21786c7e
PMD		 1407 addr, size, memory_region_name(mr),
1408 mr->ops->valid.min_access_size,
1409 mr->ops->valid.max_access_size);
5d971f9e 1410 return false;
093bc2cd
AK		 1411 }
1412 return true;
1413}
1414
cc05c43a
PM		 1415static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1416 hwaddr addr,
1417 uint64_t *pval,
1418 unsigned size,
1419 MemTxAttrs attrs)
093bc2cd 1420{
cc05c43a 1421 *pval = 0;
093bc2cd 1422
ce5d2f33 1423 if (mr->ops->read) {
cc05c43a
PM		 1424 return access_with_adjusted_size(addr, pval, size,
1425 mr->ops->impl.min_access_size,
1426 mr->ops->impl.max_access_size,
1427 memory_region_read_accessor,
1428 mr, attrs);
62a0db94 1429 } else {
cc05c43a
PM		 1430 return access_with_adjusted_size(addr, pval, size,
1431 mr->ops->impl.min_access_size,
1432 mr->ops->impl.max_access_size,
1433 memory_region_read_with_attrs_accessor,
1434 mr, attrs);
74901c3b 1435 }
093bc2cd
AK		 1436}
1437
3b643495
PM		 1438MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1439 hwaddr addr,
1440 uint64_t *pval,
e67c9046 1441 MemOp op,
3b643495 1442 MemTxAttrs attrs)
a621f38d 1443{
e67c9046 1444 unsigned size = memop_size(op);
cc05c43a
PM		 1445 MemTxResult r;
1446
1a59bdba
PMD		 1447 if (mr->alias) {
1448 return memory_region_dispatch_read(mr->alias,
1449 mr->alias_offset + addr,
1450 pval, op, attrs);
1451 }
6d7b9a6c 1452 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
791af8c8 1453 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1454 return MEMTX_DECODE_ERROR;
791af8c8 1455 }
a621f38d 1456
cc05c43a 1457 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
9bf825bf 1458 adjust_endianness(mr, pval, op);
cc05c43a 1459 return r;
a621f38d 1460}
093bc2cd 1461
8c56c1a5
PF		 1462/* Return true if an eventfd was signalled */
1463static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1464 hwaddr addr,
1465 uint64_t data,
1466 unsigned size,
1467 MemTxAttrs attrs)
1468{
1469 MemoryRegionIoeventfd ioeventfd = {
1470 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1471 .data = data,
1472 };
1473 unsigned i;
1474
1475 for (i = 0; i < mr->ioeventfd_nb; i++) {
1476 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1477 ioeventfd.e = mr->ioeventfds[i].e;
1478
73bb753d 1479 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
8c56c1a5
PF		 1480 event_notifier_set(ioeventfd.e);
1481 return true;
1482 }
1483 }
1484
1485 return false;
1486}
1487
3b643495
PM		 1488MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1489 hwaddr addr,
1490 uint64_t data,
e67c9046 1491 MemOp op,
3b643495 1492 MemTxAttrs attrs)
a621f38d 1493{
e67c9046
TN		 1494 unsigned size = memop_size(op);
1495
1a59bdba
PMD		 1496 if (mr->alias) {
1497 return memory_region_dispatch_write(mr->alias,
1498 mr->alias_offset + addr,
1499 data, op, attrs);
1500 }
6d7b9a6c 1501 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
b018ddf6 1502 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1503 return MEMTX_DECODE_ERROR;
093bc2cd
AK		 1504 }
1505
9bf825bf 1506 adjust_endianness(mr, &data, op);
a621f38d 1507
8c56c1a5
PF		 1508 if ((!kvm_eventfds_enabled()) &&
1509 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1510 return MEMTX_OK;
1511 }
1512
ce5d2f33 1513 if (mr->ops->write) {
cc05c43a
PM		 1514 return access_with_adjusted_size(addr, &data, size,
1515 mr->ops->impl.min_access_size,
1516 mr->ops->impl.max_access_size,
1517 memory_region_write_accessor, mr,
1518 attrs);
62a0db94 1519 } else {
cc05c43a
PM		 1520 return
1521 access_with_adjusted_size(addr, &data, size,
1522 mr->ops->impl.min_access_size,
1523 mr->ops->impl.max_access_size,
1524 memory_region_write_with_attrs_accessor,
1525 mr, attrs);
74901c3b 1526 }
093bc2cd
AK		 1527}
1528
093bc2cd 1529void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1530 Object *owner,
093bc2cd
AK		 1531 const MemoryRegionOps *ops,
1532 void *opaque,
1533 const char *name,
1534 uint64_t size)
1535{
2c9b15ca 1536 memory_region_init(mr, owner, name, size);
6d6d2abf 1537 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1538 mr->opaque = opaque;
14a3c10a 1539 mr->terminates = true;
093bc2cd
AK		 1540}
1541
1cfe48c1
PM		 1542void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1543 Object *owner,
1544 const char *name,
1545 uint64_t size,
1546 Error **errp)
06329cce 1547{
7f863cba 1548 memory_region_init_ram_flags_nomigrate(mr, owner, name, size, 0, errp);
06329cce
MA		 1549}
1550
7f863cba
DH		 1551void memory_region_init_ram_flags_nomigrate(MemoryRegion *mr,
1552 Object *owner,
1553 const char *name,
1554 uint64_t size,
1555 uint32_t ram_flags,
1556 Error **errp)
093bc2cd 1557{
1cd3d492 1558 Error *err = NULL;
2c9b15ca 1559 memory_region_init(mr, owner, name, size);
8ea9252a 1560 mr->ram = true;
14a3c10a 1561 mr->terminates = true;
545e92e0 1562 mr->destructor = memory_region_destructor_ram;
ebef62d0 1563 mr->ram_block = qemu_ram_alloc(size, ram_flags, mr, &err);
1cd3d492
IM		 1564 if (err) {
1565 mr->size = int128_zero();
1566 object_unparent(OBJECT(mr));
1567 error_propagate(errp, err);
1568 }
0b183fc8
PB		 1569}
1570
60786ef3
MT		 1571void memory_region_init_resizeable_ram(MemoryRegion *mr,
1572 Object *owner,
1573 const char *name,
1574 uint64_t size,
1575 uint64_t max_size,
1576 void (*resized)(const char*,
1577 uint64_t length,
1578 void *host),
1579 Error **errp)
1580{
1cd3d492 1581 Error *err = NULL;
60786ef3
MT		 1582 memory_region_init(mr, owner, name, size);
1583 mr->ram = true;
1584 mr->terminates = true;
1585 mr->destructor = memory_region_destructor_ram;
8e41fb63 1586 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1cd3d492 1587 mr, &err);
1cd3d492
IM		 1588 if (err) {
1589 mr->size = int128_zero();
1590 object_unparent(OBJECT(mr));
1591 error_propagate(errp, err);
1592 }
60786ef3
MT		 1593}
1594
d5dbde46 1595#ifdef CONFIG_POSIX
0b183fc8 1596void memory_region_init_ram_from_file(MemoryRegion *mr,
d32335e8 1597 Object *owner,
0b183fc8
PB		 1598 const char *name,
1599 uint64_t size,
98376843 1600 uint64_t align,
cbfc0171 1601 uint32_t ram_flags,
7f56e740 1602 const char *path,
369d6dc4 1603 bool readonly,
7f56e740 1604 Error **errp)
0b183fc8 1605{
1cd3d492 1606 Error *err = NULL;
0b183fc8
PB		 1607 memory_region_init(mr, owner, name, size);
1608 mr->ram = true;
369d6dc4 1609 mr->readonly = readonly;
0b183fc8
PB		 1610 mr->terminates = true;
1611 mr->destructor = memory_region_destructor_ram;
98376843 1612 mr->align = align;
369d6dc4
SH		 1613 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path,
1614 readonly, &err);
1cd3d492
IM		 1615 if (err) {
1616 mr->size = int128_zero();
1617 object_unparent(OBJECT(mr));
1618 error_propagate(errp, err);
1619 }
093bc2cd 1620}
fea617c5
MAL		 1621
1622void memory_region_init_ram_from_fd(MemoryRegion *mr,
d32335e8 1623 Object *owner,
fea617c5
MAL		 1624 const char *name,
1625 uint64_t size,
d5015b80 1626 uint32_t ram_flags,
fea617c5 1627 int fd,
44a4ff31 1628 ram_addr_t offset,
fea617c5
MAL		 1629 Error **errp)
1630{
1cd3d492 1631 Error *err = NULL;
fea617c5
MAL		 1632 memory_region_init(mr, owner, name, size);
1633 mr->ram = true;
1634 mr->terminates = true;
1635 mr->destructor = memory_region_destructor_ram;
d5015b80
DH		 1636 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, offset,
1637 false, &err);
1cd3d492
IM		 1638 if (err) {
1639 mr->size = int128_zero();
1640 object_unparent(OBJECT(mr));
1641 error_propagate(errp, err);
1642 }
fea617c5 1643}
0b183fc8 1644#endif
093bc2cd
AK		 1645
1646void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1647 Object *owner,
093bc2cd
AK		 1648 const char *name,
1649 uint64_t size,
1650 void *ptr)
1651{
2c9b15ca 1652 memory_region_init(mr, owner, name, size);
8ea9252a 1653 mr->ram = true;
14a3c10a 1654 mr->terminates = true;
fc3e7665 1655 mr->destructor = memory_region_destructor_ram;
ef701d7b
HT		 1656
1657 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1658 assert(ptr != NULL);
8e41fb63 1659 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK		 1660}
1661
21e00fa5
AW		 1662void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1663 Object *owner,
1664 const char *name,
1665 uint64_t size,
1666 void *ptr)
e4dc3f59 1667{
2ddb89b0
BS		 1668 memory_region_init(mr, owner, name, size);
1669 mr->ram = true;
1670 mr->terminates = true;
21e00fa5 1671 mr->ram_device = true;
4a2e242b
AW		 1672 mr->ops = &ram_device_mem_ops;
1673 mr->opaque = mr;
2ddb89b0 1674 mr->destructor = memory_region_destructor_ram;
0a2949e0 1675
2ddb89b0
BS		 1676 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1677 assert(ptr != NULL);
1678 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
e4dc3f59
ND		 1679}
1680
093bc2cd 1681void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1682 Object *owner,
093bc2cd
AK		 1683 const char *name,
1684 MemoryRegion *orig,
a8170e5e 1685 hwaddr offset,
093bc2cd
AK		 1686 uint64_t size)
1687{
2c9b15ca 1688 memory_region_init(mr, owner, name, size);
093bc2cd
AK		 1689 mr->alias = orig;
1690 mr->alias_offset = offset;
1691}
1692
b59821a9 1693void memory_region_init_rom_nomigrate(MemoryRegion *mr,
d32335e8 1694 Object *owner,
b59821a9
PM		 1695 const char *name,
1696 uint64_t size,
1697 Error **errp)
a1777f7f 1698{
7f863cba 1699 memory_region_init_ram_flags_nomigrate(mr, owner, name, size, 0, errp);
a1777f7f 1700 mr->readonly = true;
a1777f7f
PM		 1701}
1702
b59821a9
PM		 1703void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1704 Object *owner,
1705 const MemoryRegionOps *ops,
1706 void *opaque,
1707 const char *name,
1708 uint64_t size,
1709 Error **errp)
d0a9b5bc 1710{
1cd3d492 1711 Error *err = NULL;
39e0b03d 1712 assert(ops);
2c9b15ca 1713 memory_region_init(mr, owner, name, size);
7bc2b9cd 1714 mr->ops = ops;
75f5941c 1715 mr->opaque = opaque;
d0a9b5bc 1716 mr->terminates = true;
75c578dc 1717 mr->rom_device = true;
58268c8d 1718 mr->destructor = memory_region_destructor_ram;
ebef62d0 1719 mr->ram_block = qemu_ram_alloc(size, 0, mr, &err);
1cd3d492
IM		 1720 if (err) {
1721 mr->size = int128_zero();
1722 object_unparent(OBJECT(mr));
1723 error_propagate(errp, err);
1724 }
d0a9b5bc
AK		 1725}
1726
1221a474
AK		 1727void memory_region_init_iommu(void *_iommu_mr,
1728 size_t instance_size,
1729 const char *mrtypename,
2c9b15ca 1730 Object *owner,
30951157
AK		 1731 const char *name,
1732 uint64_t size)
1733{
1221a474 1734 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK		 1735 struct MemoryRegion *mr;
1736
1221a474
AK		 1737 object_initialize(_iommu_mr, instance_size, mrtypename);
1738 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK		 1739 memory_region_do_init(mr, owner, name, size);
1740 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1741 mr->terminates = true; /* then re-forwards */
3df9d748
AK		 1742 QLIST_INIT(&iommu_mr->iommu_notify);
1743 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK		 1744}
1745
b4fefef9 1746static void memory_region_finalize(Object *obj)
093bc2cd 1747{
b4fefef9
PC		 1748 MemoryRegion *mr = MEMORY_REGION(obj);
1749
2e2b8eb7
PB		 1750 assert(!mr->container);
1751
1752 /* We know the region is not visible in any address space (it
1753 * does not have a container and cannot be a root either because
1754 * it has no references, so we can blindly clear mr->enabled.
1755 * memory_region_set_enabled instead could trigger a transaction
1756 * and cause an infinite loop.
1757 */
1758 mr->enabled = false;
1759 memory_region_transaction_begin();
1760 while (!QTAILQ_EMPTY(&mr->subregions)) {
1761 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1762 memory_region_del_subregion(mr, subregion);
1763 }
1764 memory_region_transaction_commit();
1765
545e92e0 1766 mr->destructor(mr);
093bc2cd 1767 memory_region_clear_coalescing(mr);
302fa283 1768 g_free((char *)mr->name);
7267c094 1769 g_free(mr->ioeventfds);
093bc2cd
AK		 1770}
1771
803c0816
PB		 1772Object *memory_region_owner(MemoryRegion *mr)
1773{
22a893e4
PB		 1774 Object *obj = OBJECT(mr);
1775 return obj->parent;
803c0816
PB		 1776}
1777
46637be2
PB		 1778void memory_region_ref(MemoryRegion *mr)
1779{
22a893e4
PB		 1780 /* MMIO callbacks most likely will access data that belongs
1781 * to the owner, hence the need to ref/unref the owner whenever
1782 * the memory region is in use.
1783 *
1784 * The memory region is a child of its owner. As long as the
1785 * owner doesn't call unparent itself on the memory region,
1786 * ref-ing the owner will also keep the memory region alive.
612263cf
PB		 1787 * Memory regions without an owner are supposed to never go away;
1788 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1789 */
612263cf
PB		 1790 if (mr && mr->owner) {
1791 object_ref(mr->owner);
46637be2
PB		 1792 }
1793}
1794
1795void memory_region_unref(MemoryRegion *mr)
1796{
612263cf
PB		 1797 if (mr && mr->owner) {
1798 object_unref(mr->owner);
46637be2
PB		 1799 }
1800}
1801
093bc2cd
AK		 1802uint64_t memory_region_size(MemoryRegion *mr)
1803{
08dafab4
AK		 1804 if (int128_eq(mr->size, int128_2_64())) {
1805 return UINT64_MAX;
1806 }
1807 return int128_get64(mr->size);
093bc2cd
AK		 1808}
1809
5d546d4b 1810const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1811{
d1dd32af
PC		 1812 if (!mr->name) {
1813 ((MemoryRegion *)mr)->name =
7a309cc9 1814 g_strdup(object_get_canonical_path_component(OBJECT(mr)));
d1dd32af 1815 }
302fa283 1816 return mr->name;
8991c79b
AK		 1817}
1818
21e00fa5 1819bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1820{
21e00fa5 1821 return mr->ram_device;
e4dc3f59
ND		 1822}
1823
56918a12
SC		 1824bool memory_region_is_protected(MemoryRegion *mr)
1825{
1826 return mr->ram && (mr->ram_block->flags & RAM_PROTECTED);
1827}
1828
2d1a35be 1829uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1830{
6f6a5ef3 1831 uint8_t mask = mr->dirty_log_mask;
1370d61a
ZY		 1832 RAMBlock *rb = mr->ram_block;
1833
63b41db4 1834 if (global_dirty_tracking && ((rb && qemu_ram_is_migratable(rb)) ||
1370d61a 1835 memory_region_is_iommu(mr))) {
6f6a5ef3
PB		 1836 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1837 }
0a2949e0
PB		 1838
1839 if (tcg_enabled() && rb) {
1840 /* TCG only cares about dirty memory logging for RAM, not IOMMU. */
1841 mask |= (1 << DIRTY_MEMORY_CODE);
1842 }
6f6a5ef3 1843 return mask;
55043ba3
AK		 1844}
1845
2d1a35be
PB		 1846bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1847{
1848 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1849}
1850
549d4005
EA		 1851static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1852 Error **errp)
5bf3d319
PX		 1853{
1854 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1855 IOMMUNotifier *iommu_notifier;
1221a474 1856 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
549d4005 1857 int ret = 0;
5bf3d319 1858
3df9d748 1859 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX		 1860 flags |= iommu_notifier->notifier_flags;
1861 }
1862
1221a474 1863 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
549d4005
EA		 1864 ret = imrc->notify_flag_changed(iommu_mr,
1865 iommu_mr->iommu_notify_flags,
1866 flags, errp);
5bf3d319
PX		 1867 }
1868
549d4005
EA		 1869 if (!ret) {
1870 iommu_mr->iommu_notify_flags = flags;
1871 }
1872 return ret;
5bf3d319
PX		 1873}
1874
457f8cbb
BB		 1875int memory_region_iommu_set_page_size_mask(IOMMUMemoryRegion *iommu_mr,
1876 uint64_t page_size_mask,
1877 Error **errp)
1878{
1879 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1880 int ret = 0;
1881
1882 if (imrc->iommu_set_page_size_mask) {
1883 ret = imrc->iommu_set_page_size_mask(iommu_mr, page_size_mask, errp);
1884 }
1885 return ret;
1886}
1887
549d4005
EA		 1888int memory_region_register_iommu_notifier(MemoryRegion *mr,
1889 IOMMUNotifier *n, Error **errp)
06866575 1890{
3df9d748 1891 IOMMUMemoryRegion *iommu_mr;
549d4005 1892 int ret;
3df9d748 1893
efcd38c5 1894 if (mr->alias) {
549d4005 1895 return memory_region_register_iommu_notifier(mr->alias, n, errp);
efcd38c5
JW		 1896 }
1897
cdb30812 1898 /* We need to register for at least one bitfield */
3df9d748 1899 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1900 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1901 assert(n->start <= n->end);
cb1efcf4
PM		 1902 assert(n->iommu_idx >= 0 &&
1903 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1904
3df9d748 1905 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
549d4005
EA		 1906 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1907 if (ret) {
1908 QLIST_REMOVE(n, node);
1909 }
1910 return ret;
06866575
DG		 1911}
1912
3df9d748 1913uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1914{
1221a474
AK		 1915 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1916
1917 if (imrc->get_min_page_size) {
1918 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK		 1919 }
1920 return TARGET_PAGE_SIZE;
1921}
1922
3df9d748 1923void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1924{
3df9d748 1925 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1926 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1927 hwaddr addr, granularity;
a788f227
DG		 1928 IOMMUTLBEntry iotlb;
1929
faa362e3 1930 /* If the IOMMU has its own replay callback, override */
1221a474
AK		 1931 if (imrc->replay) {
1932 imrc->replay(iommu_mr, n);
faa362e3
PX		 1933 return;
1934 }
1935
3df9d748 1936 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1937
a788f227 1938 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
2c91bcf2 1939 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
a788f227
DG		 1940 if (iotlb.perm != IOMMU_NONE) {
1941 n->notify(n, &iotlb);
1942 }
1943
1944 /* if (2^64 - MR size) < granularity, it's possible to get an
1945 * infinite loop here. This should catch such a wraparound */
1946 if ((addr + granularity) < addr) {
1947 break;
1948 }
1949 }
1950}
1951
cdb30812
PX		 1952void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1953 IOMMUNotifier *n)
06866575 1954{
3df9d748
AK		 1955 IOMMUMemoryRegion *iommu_mr;
1956
efcd38c5
JW		 1957 if (mr->alias) {
1958 memory_region_unregister_iommu_notifier(mr->alias, n);
1959 return;
1960 }
cdb30812 1961 QLIST_REMOVE(n, node);
3df9d748 1962 iommu_mr = IOMMU_MEMORY_REGION(mr);
549d4005 1963 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
06866575
DG		 1964}
1965
3b5ebf85 1966void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
5039caf3 1967 IOMMUTLBEvent *event)
06866575 1968{
5039caf3 1969 IOMMUTLBEntry *entry = &event->entry;
03c7140c 1970 hwaddr entry_end = entry->iova + entry->addr_mask;
1804857f 1971 IOMMUTLBEntry tmp = *entry;
cdb30812 1972
5039caf3
EP		 1973 if (event->type == IOMMU_NOTIFIER_UNMAP) {
1974 assert(entry->perm == IOMMU_NONE);
1975 }
1976
bd2bfa4c
PX		 1977 /*
1978 * Skip the notification if the notification does not overlap
1979 * with registered range.
1980 */
03c7140c 1981 if (notifier->start > entry_end || notifier->end < entry->iova) {
bd2bfa4c
PX		 1982 return;
1983 }
cdb30812 1984
1804857f
EP		 1985 if (notifier->notifier_flags & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) {
1986 /* Crop (iova, addr_mask) to range */
1987 tmp.iova = MAX(tmp.iova, notifier->start);
1988 tmp.addr_mask = MIN(entry_end, notifier->end) - tmp.iova;
1989 } else {
1990 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1991 }
03c7140c 1992
5039caf3 1993 if (event->type & notifier->notifier_flags) {
1804857f 1994 notifier->notify(notifier, &tmp);
bd2bfa4c
PX		 1995 }
1996}
1997
3df9d748 1998void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
cb1efcf4 1999 int iommu_idx,
5039caf3 2000 IOMMUTLBEvent event)
bd2bfa4c
PX		 2001{
2002 IOMMUNotifier *iommu_notifier;
2003
3df9d748 2004 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 2005
3df9d748 2006 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
cb1efcf4 2007 if (iommu_notifier->iommu_idx == iommu_idx) {
5039caf3 2008 memory_region_notify_iommu_one(iommu_notifier, &event);
cb1efcf4 2009 }
cdb30812 2010 }
06866575
DG		 2011}
2012
f1334de6
AK		 2013int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
2014 enum IOMMUMemoryRegionAttr attr,
2015 void *data)
2016{
2017 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2018
2019 if (!imrc->get_attr) {
2020 return -EINVAL;
2021 }
2022
2023 return imrc->get_attr(iommu_mr, attr, data);
2024}
2025
21f40209
PM		 2026int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
2027 MemTxAttrs attrs)
2028{
2029 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2030
2031 if (!imrc->attrs_to_index) {
2032 return 0;
2033 }
2034
2035 return imrc->attrs_to_index(iommu_mr, attrs);
2036}
2037
2038int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2039{
2040 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2041
2042 if (!imrc->num_indexes) {
2043 return 1;
2044 }
2045
2046 return imrc->num_indexes(iommu_mr);
2047}
2048
8947d7fc
DH		 2049RamDiscardManager *memory_region_get_ram_discard_manager(MemoryRegion *mr)
2050{
2051 if (!memory_region_is_mapped(mr) || !memory_region_is_ram(mr)) {
2052 return NULL;
2053 }
2054 return mr->rdm;
2055}
2056
2057void memory_region_set_ram_discard_manager(MemoryRegion *mr,
2058 RamDiscardManager *rdm)
2059{
2060 g_assert(memory_region_is_ram(mr) && !memory_region_is_mapped(mr));
2061 g_assert(!rdm || !mr->rdm);
2062 mr->rdm = rdm;
2063}
2064
2065uint64_t ram_discard_manager_get_min_granularity(const RamDiscardManager *rdm,
2066 const MemoryRegion *mr)
2067{
2068 RamDiscardManagerClass *rdmc = RAM_DISCARD_MANAGER_GET_CLASS(rdm);
2069
2070 g_assert(rdmc->get_min_granularity);
2071 return rdmc->get_min_granularity(rdm, mr);
2072}
2073
2074bool ram_discard_manager_is_populated(const RamDiscardManager *rdm,
2075 const MemoryRegionSection *section)
2076{
2077 RamDiscardManagerClass *rdmc = RAM_DISCARD_MANAGER_GET_CLASS(rdm);
2078
2079 g_assert(rdmc->is_populated);
2080 return rdmc->is_populated(rdm, section);
2081}
2082
2083int ram_discard_manager_replay_populated(const RamDiscardManager *rdm,
2084 MemoryRegionSection *section,
2085 ReplayRamPopulate replay_fn,
2086 void *opaque)
2087{
2088 RamDiscardManagerClass *rdmc = RAM_DISCARD_MANAGER_GET_CLASS(rdm);
2089
2090 g_assert(rdmc->replay_populated);
2091 return rdmc->replay_populated(rdm, section, replay_fn, opaque);
2092}
2093
adaf9d92
DH		 2094void ram_discard_manager_replay_discarded(const RamDiscardManager *rdm,
2095 MemoryRegionSection *section,
2096 ReplayRamDiscard replay_fn,
2097 void *opaque)
2098{
2099 RamDiscardManagerClass *rdmc = RAM_DISCARD_MANAGER_GET_CLASS(rdm);
2100
2101 g_assert(rdmc->replay_discarded);
2102 rdmc->replay_discarded(rdm, section, replay_fn, opaque);
2103}
2104
8947d7fc
DH		 2105void ram_discard_manager_register_listener(RamDiscardManager *rdm,
2106 RamDiscardListener *rdl,
2107 MemoryRegionSection *section)
2108{
2109 RamDiscardManagerClass *rdmc = RAM_DISCARD_MANAGER_GET_CLASS(rdm);
2110
2111 g_assert(rdmc->register_listener);
2112 rdmc->register_listener(rdm, rdl, section);
2113}
2114
2115void ram_discard_manager_unregister_listener(RamDiscardManager *rdm,
2116 RamDiscardListener *rdl)
2117{
2118 RamDiscardManagerClass *rdmc = RAM_DISCARD_MANAGER_GET_CLASS(rdm);
2119
2120 g_assert(rdmc->unregister_listener);
2121 rdmc->unregister_listener(rdm, rdl);
2122}
2123
093bc2cd
AK		 2124void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2125{
5a583347 2126 uint8_t mask = 1 << client;
deb809ed 2127 uint8_t old_logging;
5a583347 2128
dbddac6d 2129 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB		 2130 old_logging = mr->vga_logging_count;
2131 mr->vga_logging_count += log ? 1 : -1;
2132 if (!!old_logging == !!mr->vga_logging_count) {
2133 return;
2134 }
2135
59023ef4 2136 memory_region_transaction_begin();
5a583347 2137 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 2138 memory_region_update_pending |= mr->enabled;
59023ef4 2139 memory_region_transaction_commit();
093bc2cd
AK		 2140}
2141
a8170e5e
AK		 2142void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2143 hwaddr size)
093bc2cd 2144{
8e41fb63
FZ		 2145 assert(mr->ram_block);
2146 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2147 size,
58d2707e 2148 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK		 2149}
2150
b87eaa9b
PX		 2151/*
2152 * If memory region `mr' is NULL, do global sync. Otherwise, sync
2153 * dirty bitmap for the specified memory region.
2154 */
0fe1eca7 2155static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 2156{
0a752eee 2157 MemoryListener *listener;
0d673e36 2158 AddressSpace *as;
0a752eee 2159 FlatView *view;
5a583347
AK		 2160 FlatRange *fr;
2161
0a752eee
PB		 2162 /* If the same address space has multiple log_sync listeners, we
2163 * visit that address space's FlatView multiple times. But because
2164 * log_sync listeners are rare, it's still cheaper than walking each
2165 * address space once.
2166 */
2167 QTAILQ_FOREACH(listener, &memory_listeners, link) {
b87eaa9b
PX		 2168 if (listener->log_sync) {
2169 as = listener->address_space;
2170 view = address_space_get_flatview(as);
2171 FOR_EACH_FLAT_RANGE(fr, view) {
2172 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2173 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2174 listener->log_sync(listener, &mrs);
2175 }
0d673e36 2176 }
b87eaa9b 2177 flatview_unref(view);
fcb3ab34 2178 trace_memory_region_sync_dirty(mr ? mr->name : "(all)", listener->name, 0);
b87eaa9b
PX		 2179 } else if (listener->log_sync_global) {
2180 /*
2181 * No matter whether MR is specified, what we can do here
2182 * is to do a global sync, because we are not capable to
2183 * sync in a finer granularity.
2184 */
2185 listener->log_sync_global(listener);
fcb3ab34 2186 trace_memory_region_sync_dirty(mr ? mr->name : "(all)", listener->name, 1);
5a583347
AK		 2187 }
2188 }
093bc2cd
AK		 2189}
2190
077874e0
PX		 2191void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2192 hwaddr len)
2193{
2194 MemoryRegionSection mrs;
2195 MemoryListener *listener;
2196 AddressSpace *as;
2197 FlatView *view;
2198 FlatRange *fr;
2199 hwaddr sec_start, sec_end, sec_size;
2200
2201 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2202 if (!listener->log_clear) {
2203 continue;
2204 }
2205 as = listener->address_space;
2206 view = address_space_get_flatview(as);
2207 FOR_EACH_FLAT_RANGE(fr, view) {
2208 if (!fr->dirty_log_mask || fr->mr != mr) {
2209 /*
2210 * Clear dirty bitmap operation only applies to those
2211 * regions whose dirty logging is at least enabled
2212 */
2213 continue;
2214 }
2215
2216 mrs = section_from_flat_range(fr, view);
2217
2218 sec_start = MAX(mrs.offset_within_region, start);
2219 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2220 sec_end = MIN(sec_end, start + len);
2221
2222 if (sec_start >= sec_end) {
2223 /*
2224 * If this memory region section has no intersection
2225 * with the requested range, skip.
2226 */
2227 continue;
2228 }
2229
2230 /* Valid case; shrink the section if needed */
2231 mrs.offset_within_address_space +=
2232 sec_start - mrs.offset_within_region;
2233 mrs.offset_within_region = sec_start;
2234 sec_size = sec_end - sec_start;
2235 mrs.size = int128_make64(sec_size);
2236 listener->log_clear(listener, &mrs);
2237 }
2238 flatview_unref(view);
2239 }
2240}
2241
0fe1eca7
PB		 2242DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2243 hwaddr addr,
2244 hwaddr size,
2245 unsigned client)
2246{
9458a9a1 2247 DirtyBitmapSnapshot *snapshot;
0fe1eca7
PB		 2248 assert(mr->ram_block);
2249 memory_region_sync_dirty_bitmap(mr);
9458a9a1
PB		 2250 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2251 memory_global_after_dirty_log_sync();
2252 return snapshot;
0fe1eca7
PB		 2253}
2254
2255bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2256 hwaddr addr, hwaddr size)
2257{
2258 assert(mr->ram_block);
2259 return cpu_physical_memory_snapshot_get_dirty(snap,
2260 memory_region_get_ram_addr(mr) + addr, size);
2261}
2262
093bc2cd
AK		 2263void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2264{
fb1cd6f9 2265 if (mr->readonly != readonly) {
59023ef4 2266 memory_region_transaction_begin();
fb1cd6f9 2267 mr->readonly = readonly;
22bde714 2268 memory_region_update_pending |= mr->enabled;
59023ef4 2269 memory_region_transaction_commit();
fb1cd6f9 2270 }
093bc2cd
AK		 2271}
2272
c26763f8
MAL		 2273void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2274{
2275 if (mr->nonvolatile != nonvolatile) {
2276 memory_region_transaction_begin();
2277 mr->nonvolatile = nonvolatile;
2278 memory_region_update_pending |= mr->enabled;
2279 memory_region_transaction_commit();
2280 }
2281}
2282
5f9a5ea1 2283void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2284{
5f9a5ea1 2285 if (mr->romd_mode != romd_mode) {
59023ef4 2286 memory_region_transaction_begin();
5f9a5ea1 2287 mr->romd_mode = romd_mode;
22bde714 2288 memory_region_update_pending |= mr->enabled;
59023ef4 2289 memory_region_transaction_commit();
d0a9b5bc
AK		 2290 }
2291}
2292
a8170e5e
AK		 2293void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2294 hwaddr size, unsigned client)
093bc2cd 2295{
8e41fb63
FZ		 2296 assert(mr->ram_block);
2297 cpu_physical_memory_test_and_clear_dirty(
2298 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK		 2299}
2300
a35ba7be
PB		 2301int memory_region_get_fd(MemoryRegion *mr)
2302{
4ff87573
PB		 2303 int fd;
2304
694ea274 2305 RCU_READ_LOCK_GUARD();
4ff87573
PB		 2306 while (mr->alias) {
2307 mr = mr->alias;
a35ba7be 2308 }
4ff87573 2309 fd = mr->ram_block->fd;
a35ba7be 2310
4ff87573
PB		 2311 return fd;
2312}
a35ba7be 2313
093bc2cd
AK		 2314void *memory_region_get_ram_ptr(MemoryRegion *mr)
2315{
49b24afc
PB		 2316 void *ptr;
2317 uint64_t offset = 0;
093bc2cd 2318
694ea274 2319 RCU_READ_LOCK_GUARD();
49b24afc
PB		 2320 while (mr->alias) {
2321 offset += mr->alias_offset;
2322 mr = mr->alias;
2323 }
8e41fb63 2324 assert(mr->ram_block);
0878d0e1 2325 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
093bc2cd 2326
0878d0e1 2327 return ptr;
093bc2cd
AK		 2328}
2329
07bdaa41
PB		 2330MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2331{
2332 RAMBlock *block;
2333
2334 block = qemu_ram_block_from_host(ptr, false, offset);
2335 if (!block) {
2336 return NULL;
2337 }
2338
2339 return block->mr;
2340}
2341
7ebb2745
FZ		 2342ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2343{
2344 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2345}
2346
37d7c084
PB		 2347void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2348{
8e41fb63 2349 assert(mr->ram_block);
37d7c084 2350
fa53a0e5 2351 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB		 2352}
2353
9ecc996a
PMD		 2354void memory_region_msync(MemoryRegion *mr, hwaddr addr, hwaddr size)
2355{
2356 if (mr->ram_block) {
ab7e41e6 2357 qemu_ram_msync(mr->ram_block, addr, size);
9ecc996a
PMD		 2358 }
2359}
61c490e2 2360
4dfe59d1 2361void memory_region_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size)
61c490e2
BM		 2362{
2363 /*
2364 * Might be extended case needed to cover
2365 * different types of memory regions
2366 */
9ecc996a
PMD		 2367 if (mr->dirty_log_mask) {
2368 memory_region_msync(mr, addr, size);
61c490e2
BM		 2369 }
2370}
2371
b960fc17
PX		 2372/*
2373 * Call proper memory listeners about the change on the newly
2374 * added/removed CoalescedMemoryRange.
2375 */
2376static void memory_region_update_coalesced_range(MemoryRegion *mr,
2377 CoalescedMemoryRange *cmr,
2378 bool add)
093bc2cd 2379{
b960fc17 2380 AddressSpace *as;
99e86347 2381 FlatView *view;
093bc2cd 2382 FlatRange *fr;
093bc2cd 2383
0d673e36 2384 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b960fc17
PX		 2385 view = address_space_get_flatview(as);
2386 FOR_EACH_FLAT_RANGE(fr, view) {
2387 if (fr->mr == mr) {
2388 flat_range_coalesced_io_notify(fr, as, cmr, add);
2389 }
2390 }
2391 flatview_unref(view);
0d673e36
AK		 2392 }
2393}
2394
093bc2cd
AK		 2395void memory_region_set_coalescing(MemoryRegion *mr)
2396{
2397 memory_region_clear_coalescing(mr);
08dafab4 2398 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK		 2399}
2400
2401void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2402 hwaddr offset,
093bc2cd
AK		 2403 uint64_t size)
2404{
7267c094 2405 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2406
08dafab4 2407 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd 2408 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
b960fc17 2409 memory_region_update_coalesced_range(mr, cmr, true);
d410515e 2410 memory_region_set_flush_coalesced(mr);
093bc2cd
AK		 2411}
2412
2413void memory_region_clear_coalescing(MemoryRegion *mr)
2414{
2415 CoalescedMemoryRange *cmr;
9c1aa1c2
PX		 2416
2417 if (QTAILQ_EMPTY(&mr->coalesced)) {
2418 return;
2419 }
093bc2cd 2420
d410515e
JK		 2421 qemu_flush_coalesced_mmio_buffer();
2422 mr->flush_coalesced_mmio = false;
2423
093bc2cd
AK		 2424 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2425 cmr = QTAILQ_FIRST(&mr->coalesced);
2426 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
b960fc17 2427 memory_region_update_coalesced_range(mr, cmr, false);
7267c094 2428 g_free(cmr);
ab5b3db5 2429 }
093bc2cd
AK		 2430}
2431
d410515e
JK		 2432void memory_region_set_flush_coalesced(MemoryRegion *mr)
2433{
2434 mr->flush_coalesced_mmio = true;
2435}
2436
2437void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2438{
2439 qemu_flush_coalesced_mmio_buffer();
2440 if (QTAILQ_EMPTY(&mr->coalesced)) {
2441 mr->flush_coalesced_mmio = false;
2442 }
2443}
2444
8c56c1a5
PF		 2445static bool userspace_eventfd_warning;
2446
3e9d69e7 2447void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2448 hwaddr addr,
3e9d69e7
AK		 2449 unsigned size,
2450 bool match_data,
2451 uint64_t data,
753d5e14 2452 EventNotifier *e)
3e9d69e7
AK		 2453{
2454 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2455 .addr.start = int128_make64(addr),
2456 .addr.size = int128_make64(size),
3e9d69e7
AK		 2457 .match_data = match_data,
2458 .data = data,
753d5e14 2459 .e = e,
3e9d69e7
AK		 2460 };
2461 unsigned i;
2462
8c56c1a5
PF		 2463 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2464 userspace_eventfd_warning))) {
2465 userspace_eventfd_warning = true;
2466 error_report("Using eventfd without MMIO binding in KVM. "
2467 "Suboptimal performance expected");
2468 }
2469
b8aecea2 2470 if (size) {
9bf825bf 2471 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
b8aecea2 2472 }
59023ef4 2473 memory_region_transaction_begin();
3e9d69e7 2474 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2475 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK		 2476 break;
2477 }
2478 }
2479 ++mr->ioeventfd_nb;
7267c094 2480 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK		 2481 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2482 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2483 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2484 mr->ioeventfds[i] = mrfd;
4dc56152 2485 ioeventfd_update_pending |= mr->enabled;
59023ef4 2486 memory_region_transaction_commit();
3e9d69e7
AK		 2487}
2488
2489void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2490 hwaddr addr,
3e9d69e7
AK		 2491 unsigned size,
2492 bool match_data,
2493 uint64_t data,
753d5e14 2494 EventNotifier *e)
3e9d69e7
AK		 2495{
2496 MemoryRegionIoeventfd mrfd = {
08dafab4
AK		 2497 .addr.start = int128_make64(addr),
2498 .addr.size = int128_make64(size),
3e9d69e7
AK		 2499 .match_data = match_data,
2500 .data = data,
753d5e14 2501 .e = e,
3e9d69e7
AK		 2502 };
2503 unsigned i;
2504
b8aecea2 2505 if (size) {
9bf825bf 2506 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
b8aecea2 2507 }
59023ef4 2508 memory_region_transaction_begin();
3e9d69e7 2509 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2510 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK		 2511 break;
2512 }
2513 }
2514 assert(i != mr->ioeventfd_nb);
2515 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2516 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2517 --mr->ioeventfd_nb;
7267c094 2518 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2519 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2520 ioeventfd_update_pending |= mr->enabled;
59023ef4 2521 memory_region_transaction_commit();
3e9d69e7
AK		 2522}
2523
feca4ac1 2524static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2525{
feca4ac1 2526 MemoryRegion *mr = subregion->container;
093bc2cd
AK		 2527 MemoryRegion *other;
2528
59023ef4
JK		 2529 memory_region_transaction_begin();
2530
dfde4e6e 2531 memory_region_ref(subregion);
093bc2cd
AK		 2532 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2533 if (subregion->priority >= other->priority) {
2534 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2535 goto done;
2536 }
2537 }
2538 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2539done:
22bde714 2540 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2541 memory_region_transaction_commit();
093bc2cd
AK		 2542}
2543
0598701a
PC		 2544static void memory_region_add_subregion_common(MemoryRegion *mr,
2545 hwaddr offset,
2546 MemoryRegion *subregion)
2547{
5ead6218
DH		 2548 MemoryRegion *alias;
2549
feca4ac1
PB		 2550 assert(!subregion->container);
2551 subregion->container = mr;
5ead6218
DH		 2552 for (alias = subregion->alias; alias; alias = alias->alias) {
2553 alias->mapped_via_alias++;
2554 }
0598701a 2555 subregion->addr = offset;
feca4ac1 2556 memory_region_update_container_subregions(subregion);
0598701a 2557}
093bc2cd
AK		 2558
2559void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2560 hwaddr offset,
093bc2cd
AK		 2561 MemoryRegion *subregion)
2562{
093bc2cd
AK		 2563 subregion->priority = 0;
2564 memory_region_add_subregion_common(mr, offset, subregion);
2565}
2566
2567void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2568 hwaddr offset,
093bc2cd 2569 MemoryRegion *subregion,
a1ff8ae0 2570 int priority)
093bc2cd 2571{
093bc2cd
AK		 2572 subregion->priority = priority;
2573 memory_region_add_subregion_common(mr, offset, subregion);
2574}
2575
2576void memory_region_del_subregion(MemoryRegion *mr,
2577 MemoryRegion *subregion)
2578{
5ead6218
DH		 2579 MemoryRegion *alias;
2580
59023ef4 2581 memory_region_transaction_begin();
feca4ac1
PB		 2582 assert(subregion->container == mr);
2583 subregion->container = NULL;
5ead6218
DH		 2584 for (alias = subregion->alias; alias; alias = alias->alias) {
2585 alias->mapped_via_alias--;
2586 assert(alias->mapped_via_alias >= 0);
2587 }
093bc2cd 2588 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2589 memory_region_unref(subregion);
22bde714 2590 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2591 memory_region_transaction_commit();
6bba19ba
AK		 2592}
2593
2594void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2595{
2596 if (enabled == mr->enabled) {
2597 return;
2598 }
59023ef4 2599 memory_region_transaction_begin();
6bba19ba 2600 mr->enabled = enabled;
22bde714 2601 memory_region_update_pending = true;
59023ef4 2602 memory_region_transaction_commit();
093bc2cd 2603}
1c0ffa58 2604
e7af4c67
MT		 2605void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2606{
2607 Int128 s = int128_make64(size);
2608
2609 if (size == UINT64_MAX) {
2610 s = int128_2_64();
2611 }
2612 if (int128_eq(s, mr->size)) {
2613 return;
2614 }
2615 memory_region_transaction_begin();
2616 mr->size = s;
2617 memory_region_update_pending = true;
2618 memory_region_transaction_commit();
2619}
2620
67891b8a 2621static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2622{
feca4ac1 2623 MemoryRegion *container = mr->container;
2282e1af 2624
feca4ac1 2625 if (container) {
67891b8a
PC		 2626 memory_region_transaction_begin();
2627 memory_region_ref(mr);
feca4ac1
PB		 2628 memory_region_del_subregion(container, mr);
2629 mr->container = container;
2630 memory_region_update_container_subregions(mr);
67891b8a
PC		 2631 memory_region_unref(mr);
2632 memory_region_transaction_commit();
2282e1af 2633 }
67891b8a 2634}
2282e1af 2635
67891b8a
PC		 2636void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2637{
2638 if (addr != mr->addr) {
2639 mr->addr = addr;
2640 memory_region_readd_subregion(mr);
2641 }
2282e1af
AK		 2642}
2643
a8170e5e 2644void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2645{
4703359e 2646 assert(mr->alias);
4703359e 2647
59023ef4 2648 if (offset == mr->alias_offset) {
4703359e
AK		 2649 return;
2650 }
2651
59023ef4
JK		 2652 memory_region_transaction_begin();
2653 mr->alias_offset = offset;
22bde714 2654 memory_region_update_pending |= mr->enabled;
59023ef4 2655 memory_region_transaction_commit();
4703359e
AK		 2656}
2657
a2b257d6
IM		 2658uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2659{
2660 return mr->align;
2661}
2662
e2177955
AK		 2663static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2664{
2665 const AddrRange *addr = addr_;
2666 const FlatRange *fr = fr_;
2667
2668 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2669 return -1;
2670 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2671 return 1;
2672 }
2673 return 0;
2674}
2675
99e86347 2676static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2677{
99e86347 2678 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK		 2679 sizeof(FlatRange), cmp_flatrange_addr);
2680}
2681
eed2bacf
IM		 2682bool memory_region_is_mapped(MemoryRegion *mr)
2683{
5ead6218 2684 return !!mr->container || mr->mapped_via_alias;
eed2bacf
IM		 2685}
2686
c6742b14
PB		 2687/* Same as memory_region_find, but it does not add a reference to the
2688 * returned region. It must be called from an RCU critical section.
2689 */
2690static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2691 hwaddr addr, uint64_t size)
e2177955 2692{
052e87b0 2693 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB		 2694 MemoryRegion *root;
2695 AddressSpace *as;
2696 AddrRange range;
99e86347 2697 FlatView *view;
73034e9e
PB		 2698 FlatRange *fr;
2699
2700 addr += mr->addr;
feca4ac1
PB		 2701 for (root = mr; root->container; ) {
2702 root = root->container;
73034e9e
PB		 2703 addr += root->addr;
2704 }
e2177955 2705
73034e9e 2706 as = memory_region_to_address_space(root);
eed2bacf
IM		 2707 if (!as) {
2708 return ret;
2709 }
73034e9e 2710 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2711
16620684 2712 view = address_space_to_flatview(as);
99e86347 2713 fr = flatview_lookup(view, range);
e2177955 2714 if (!fr) {
c6742b14 2715 return ret;
e2177955
AK		 2716 }
2717
99e86347 2718 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK		 2719 --fr;
2720 }
2721
2722 ret.mr = fr->mr;
16620684 2723 ret.fv = view;
e2177955
AK		 2724 range = addrrange_intersection(range, fr->addr);
2725 ret.offset_within_region = fr->offset_in_region;
2726 ret.offset_within_region += int128_get64(int128_sub(range.start,
2727 fr->addr.start));
052e87b0 2728 ret.size = range.size;
e2177955 2729 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2730 ret.readonly = fr->readonly;
c26763f8 2731 ret.nonvolatile = fr->nonvolatile;
c6742b14
PB		 2732 return ret;
2733}
2734
2735MemoryRegionSection memory_region_find(MemoryRegion *mr,
2736 hwaddr addr, uint64_t size)
2737{
2738 MemoryRegionSection ret;
694ea274 2739 RCU_READ_LOCK_GUARD();
c6742b14
PB		 2740 ret = memory_region_find_rcu(mr, addr, size);
2741 if (ret.mr) {
2742 memory_region_ref(ret.mr);
2743 }
e2177955
AK		 2744 return ret;
2745}
2746
22843838
DH		 2747MemoryRegionSection *memory_region_section_new_copy(MemoryRegionSection *s)
2748{
2749 MemoryRegionSection *tmp = g_new(MemoryRegionSection, 1);
2750
2751 *tmp = *s;
2752 if (tmp->mr) {
2753 memory_region_ref(tmp->mr);
2754 }
2755 if (tmp->fv) {
2756 bool ret = flatview_ref(tmp->fv);
2757
2758 g_assert(ret);
2759 }
2760 return tmp;
2761}
2762
2763void memory_region_section_free_copy(MemoryRegionSection *s)
2764{
2765 if (s->fv) {
2766 flatview_unref(s->fv);
2767 }
2768 if (s->mr) {
2769 memory_region_unref(s->mr);
2770 }
2771 g_free(s);
2772}
2773
c6742b14
PB		 2774bool memory_region_present(MemoryRegion *container, hwaddr addr)
2775{
2776 MemoryRegion *mr;
2777
694ea274 2778 RCU_READ_LOCK_GUARD();
c6742b14 2779 mr = memory_region_find_rcu(container, addr, 1).mr;
c6742b14
PB		 2780 return mr && mr != container;
2781}
2782
9c1f8f44 2783void memory_global_dirty_log_sync(void)
86e775c6 2784{
3ebb1817 2785 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK		 2786}
2787
9458a9a1
PB		 2788void memory_global_after_dirty_log_sync(void)
2789{
2790 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2791}
2792
19310760
JZ		 2793static VMChangeStateEntry *vmstate_change;
2794
63b41db4 2795void memory_global_dirty_log_start(unsigned int flags)
7664e80c 2796{
7b0538ed
PX		 2797 unsigned int old_flags = global_dirty_tracking;
2798
19310760
JZ		 2799 if (vmstate_change) {
2800 qemu_del_vm_change_state_handler(vmstate_change);
2801 vmstate_change = NULL;
2802 }
2803
63b41db4
HH		 2804 assert(flags && !(flags & (~GLOBAL_DIRTY_MASK)));
2805 assert(!(global_dirty_tracking & flags));
2806 global_dirty_tracking |= flags;
63b41db4 2807 trace_global_dirty_changed(global_dirty_tracking);
6f6a5ef3 2808
7b0538ed
PX		 2809 if (!old_flags) {
2810 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2811 memory_region_transaction_begin();
2812 memory_region_update_pending = true;
2813 memory_region_transaction_commit();
2814 }
7664e80c
AK		 2815}
2816
63b41db4 2817static void memory_global_dirty_log_do_stop(unsigned int flags)
7664e80c 2818{
63b41db4
HH		 2819 assert(flags && !(flags & (~GLOBAL_DIRTY_MASK)));
2820 assert((global_dirty_tracking & flags) == flags);
2821 global_dirty_tracking &= ~flags;
2822
2823 trace_global_dirty_changed(global_dirty_tracking);
6f6a5ef3 2824
7b0538ed
PX		 2825 if (!global_dirty_tracking) {
2826 memory_region_transaction_begin();
2827 memory_region_update_pending = true;
2828 memory_region_transaction_commit();
2829 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2830 }
7664e80c
AK		 2831}
2832
538f0497 2833static void memory_vm_change_state_handler(void *opaque, bool running,
19310760
JZ		 2834 RunState state)
2835{
63b41db4 2836 unsigned int flags = (unsigned int)(uintptr_t)opaque;
19310760 2837 if (running) {
63b41db4 2838 memory_global_dirty_log_do_stop(flags);
19310760
JZ		 2839
2840 if (vmstate_change) {
2841 qemu_del_vm_change_state_handler(vmstate_change);
2842 vmstate_change = NULL;
2843 }
2844 }
2845}
2846
63b41db4 2847void memory_global_dirty_log_stop(unsigned int flags)
19310760
JZ		 2848{
2849 if (!runstate_is_running()) {
2850 if (vmstate_change) {
2851 return;
2852 }
2853 vmstate_change = qemu_add_vm_change_state_handler(
63b41db4
HH		 2854 memory_vm_change_state_handler,
2855 (void *)(uintptr_t)flags);
19310760
JZ		 2856 return;
2857 }
2858
63b41db4 2859 memory_global_dirty_log_do_stop(flags);
19310760
JZ		 2860}
2861
7664e80c
AK		 2862static void listener_add_address_space(MemoryListener *listener,
2863 AddressSpace *as)
2864{
99e86347 2865 FlatView *view;
7664e80c
AK		 2866 FlatRange *fr;
2867
680a4783
PB		 2868 if (listener->begin) {
2869 listener->begin(listener);
2870 }
63b41db4 2871 if (global_dirty_tracking) {
975aefe0
AK		 2872 if (listener->log_global_start) {
2873 listener->log_global_start(listener);
2874 }
7664e80c 2875 }
975aefe0 2876
856d7245 2877 view = address_space_get_flatview(as);
99e86347 2878 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH		 2879 MemoryRegionSection section = section_from_flat_range(fr, view);
2880
975aefe0
AK		 2881 if (listener->region_add) {
2882 listener->region_add(listener, &section);
2883 }
ae990e6c
DH		 2884 if (fr->dirty_log_mask && listener->log_start) {
2885 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2886 }
7664e80c 2887 }
680a4783
PB		 2888 if (listener->commit) {
2889 listener->commit(listener);
2890 }
856d7245 2891 flatview_unref(view);
7664e80c
AK		 2892}
2893
d25836ca
PX		 2894static void listener_del_address_space(MemoryListener *listener,
2895 AddressSpace *as)
2896{
2897 FlatView *view;
2898 FlatRange *fr;
2899
2900 if (listener->begin) {
2901 listener->begin(listener);
2902 }
2903 view = address_space_get_flatview(as);
2904 FOR_EACH_FLAT_RANGE(fr, view) {
2905 MemoryRegionSection section = section_from_flat_range(fr, view);
2906
2907 if (fr->dirty_log_mask && listener->log_stop) {
2908 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2909 }
2910 if (listener->region_del) {
2911 listener->region_del(listener, &section);
2912 }
2913 }
2914 if (listener->commit) {
2915 listener->commit(listener);
2916 }
2917 flatview_unref(view);
2918}
2919
d45fa784 2920void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2921{
72e22d2f
AK		 2922 MemoryListener *other = NULL;
2923
b87eaa9b
PX		 2924 /* Only one of them can be defined for a listener */
2925 assert(!(listener->log_sync && listener->log_sync_global));
2926
d45fa784 2927 listener->address_space = as;
72e22d2f 2928 if (QTAILQ_EMPTY(&memory_listeners)
eae3eb3e 2929 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
72e22d2f
AK		 2930 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2931 } else {
2932 QTAILQ_FOREACH(other, &memory_listeners, link) {
2933 if (listener->priority < other->priority) {
2934 break;
2935 }
2936 }
2937 QTAILQ_INSERT_BEFORE(other, listener, link);
2938 }
0d673e36 2939
9a54635d 2940 if (QTAILQ_EMPTY(&as->listeners)
eae3eb3e 2941 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
9a54635d
PB		 2942 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2943 } else {
2944 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2945 if (listener->priority < other->priority) {
2946 break;
2947 }
2948 }
2949 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2950 }
2951
d45fa784 2952 listener_add_address_space(listener, as);
7664e80c
AK		 2953}
2954
2955void memory_listener_unregister(MemoryListener *listener)
2956{
1d8280c1
PB		 2957 if (!listener->address_space) {
2958 return;
2959 }
2960
d25836ca 2961 listener_del_address_space(listener, listener->address_space);
72e22d2f 2962 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2963 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2964 listener->address_space = NULL;
86e775c6 2965}
e2177955 2966
a2166410
GK		 2967void address_space_remove_listeners(AddressSpace *as)
2968{
2969 while (!QTAILQ_EMPTY(&as->listeners)) {
2970 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2971 }
2972}
2973
7dca8043 2974void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2975{
ac95190e 2976 memory_region_ref(root);
8786db7c 2977 as->root = root;
67ace39b 2978 as->current_map = NULL;
4c19eb72
AK		 2979 as->ioeventfd_nb = 0;
2980 as->ioeventfds = NULL;
9a54635d 2981 QTAILQ_INIT(&as->listeners);
0d673e36 2982 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2983 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK		 2984 address_space_update_topology(as);
2985 address_space_update_ioeventfds(as);
1c0ffa58 2986}
658b2224 2987
374f2981 2988static void do_address_space_destroy(AddressSpace *as)
83f3c251 2989{
9a54635d 2990 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2991
856d7245 2992 flatview_unref(as->current_map);
7dca8043 2993 g_free(as->name);
4c19eb72 2994 g_free(as->ioeventfds);
ac95190e 2995 memory_region_unref(as->root);
83f3c251
AK		 2996}
2997
374f2981
PB		 2998void address_space_destroy(AddressSpace *as)
2999{
ac95190e
PB		 3000 MemoryRegion *root = as->root;
3001
374f2981
PB		 3002 /* Flush out anything from MemoryListeners listening in on this */
3003 memory_region_transaction_begin();
3004 as->root = NULL;
3005 memory_region_transaction_commit();
3006 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
3007
3008 /* At this point, as->dispatch and as->current_map are dummy
3009 * entries that the guest should never use. Wait for the old
3010 * values to expire before freeing the data.
3011 */
ac95190e 3012 as->root = root;
374f2981
PB		 3013 call_rcu(as, do_address_space_destroy, rcu);
3014}
3015
4e831901
PX		 3016static const char *memory_region_type(MemoryRegion *mr)
3017{
39fa93c4
PMD		 3018 if (mr->alias) {
3019 return memory_region_type(mr->alias);
3020 }
4e831901
PX		 3021 if (memory_region_is_ram_device(mr)) {
3022 return "ramd";
3023 } else if (memory_region_is_romd(mr)) {
3024 return "romd";
3025 } else if (memory_region_is_rom(mr)) {
3026 return "rom";
3027 } else if (memory_region_is_ram(mr)) {
3028 return "ram";
3029 } else {
3030 return "i/o";
3031 }
3032}
3033
314e2987
BS		 3034typedef struct MemoryRegionList MemoryRegionList;
3035
3036struct MemoryRegionList {
3037 const MemoryRegion *mr;
a16878d2 3038 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS		 3039};
3040
b58deb34 3041typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
314e2987 3042
4e831901
PX		 3043#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
3044 int128_sub((size), int128_one())) : 0)
3045#define MTREE_INDENT " "
3046
b6b71cb5 3047static void mtree_expand_owner(const char *label, Object *obj)
fc051ae6
AK		 3048{
3049 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
3050
b6b71cb5 3051 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
fc051ae6 3052 if (dev && dev->id) {
b6b71cb5 3053 qemu_printf(" id=%s", dev->id);
fc051ae6 3054 } else {
ddfb0baa 3055 char *canonical_path = object_get_canonical_path(obj);
fc051ae6 3056 if (canonical_path) {
b6b71cb5 3057 qemu_printf(" path=%s", canonical_path);
fc051ae6
AK		 3058 g_free(canonical_path);
3059 } else {
b6b71cb5 3060 qemu_printf(" type=%s", object_get_typename(obj));
fc051ae6
AK		 3061 }
3062 }
b6b71cb5 3063 qemu_printf("}");
fc051ae6
AK		 3064}
3065
b6b71cb5 3066static void mtree_print_mr_owner(const MemoryRegion *mr)
fc051ae6
AK		 3067{
3068 Object *owner = mr->owner;
3069 Object *parent = memory_region_owner((MemoryRegion *)mr);
3070
3071 if (!owner && !parent) {
b6b71cb5 3072 qemu_printf(" orphan");
fc051ae6
AK		 3073 return;
3074 }
3075 if (owner) {
b6b71cb5 3076 mtree_expand_owner("owner", owner);
fc051ae6
AK		 3077 }
3078 if (parent && parent != owner) {
b6b71cb5 3079 mtree_expand_owner("parent", parent);
fc051ae6
AK		 3080 }
3081}
3082
b6b71cb5 3083static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
a8170e5e 3084 hwaddr base,
fc051ae6 3085 MemoryRegionListHead *alias_print_queue,
2261d393 3086 bool owner, bool display_disabled)
314e2987 3087{
9479c57a
JK		 3088 MemoryRegionList *new_ml, *ml, *next_ml;
3089 MemoryRegionListHead submr_print_queue;
314e2987
BS		 3090 const MemoryRegion *submr;
3091 unsigned int i;
b31f8412 3092 hwaddr cur_start, cur_end;
314e2987 3093
f8a9f720 3094 if (!mr) {
314e2987
BS		 3095 return;
3096 }
3097
b31f8412
PX		 3098 cur_start = base + mr->addr;
3099 cur_end = cur_start + MR_SIZE(mr->size);
3100
3101 /*
3102 * Try to detect overflow of memory region. This should never
3103 * happen normally. When it happens, we dump something to warn the
3104 * user who is observing this.
3105 */
3106 if (cur_start < base || cur_end < cur_start) {
b6b71cb5 3107 qemu_printf("[DETECTED OVERFLOW!] ");
b31f8412
PX		 3108 }
3109
314e2987
BS		 3110 if (mr->alias) {
3111 MemoryRegionList *ml;
3112 bool found = false;
3113
3114 /* check if the alias is already in the queue */
a16878d2 3115 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 3116 if (ml->mr == mr->alias) {
314e2987
BS		 3117 found = true;
3118 }
3119 }
3120
3121 if (!found) {
3122 ml = g_new(MemoryRegionList, 1);
3123 ml->mr = mr->alias;
a16878d2 3124 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 3125 }
2261d393
PMD		 3126 if (mr->enabled || display_disabled) {
3127 for (i = 0; i < level; i++) {
3128 qemu_printf(MTREE_INDENT);
3129 }
3130 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
3131 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
3132 "-" TARGET_FMT_plx "%s",
3133 cur_start, cur_end,
3134 mr->priority,
3135 mr->nonvolatile ? "nv-" : "",
3136 memory_region_type((MemoryRegion *)mr),
3137 memory_region_name(mr),
3138 memory_region_name(mr->alias),
3139 mr->alias_offset,
3140 mr->alias_offset + MR_SIZE(mr->size),
3141 mr->enabled ? "" : " [disabled]");
3142 if (owner) {
3143 mtree_print_mr_owner(mr);
3144 }
3145 qemu_printf("\n");
fc051ae6 3146 }
314e2987 3147 } else {
2261d393
PMD		 3148 if (mr->enabled || display_disabled) {
3149 for (i = 0; i < level; i++) {
3150 qemu_printf(MTREE_INDENT);
3151 }
3152 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
3153 " (prio %d, %s%s): %s%s",
3154 cur_start, cur_end,
3155 mr->priority,
3156 mr->nonvolatile ? "nv-" : "",
3157 memory_region_type((MemoryRegion *)mr),
3158 memory_region_name(mr),
3159 mr->enabled ? "" : " [disabled]");
3160 if (owner) {
3161 mtree_print_mr_owner(mr);
3162 }
3163 qemu_printf("\n");
fc051ae6 3164 }
314e2987 3165 }
9479c57a
JK		 3166
3167 QTAILQ_INIT(&submr_print_queue);
3168
314e2987 3169 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK		 3170 new_ml = g_new(MemoryRegionList, 1);
3171 new_ml->mr = submr;
a16878d2 3172 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK		 3173 if (new_ml->mr->addr < ml->mr->addr ||
3174 (new_ml->mr->addr == ml->mr->addr &&
3175 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 3176 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK		 3177 new_ml = NULL;
3178 break;
3179 }
3180 }
3181 if (new_ml) {
a16878d2 3182 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK		 3183 }
3184 }
3185
a16878d2 3186 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b6b71cb5 3187 mtree_print_mr(ml->mr, level + 1, cur_start,
2261d393 3188 alias_print_queue, owner, display_disabled);
9479c57a
JK		 3189 }
3190
a16878d2 3191 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 3192 g_free(ml);
314e2987
BS		 3193 }
3194}
3195
5e8fd947 3196struct FlatViewInfo {
5e8fd947
AK		 3197 int counter;
3198 bool dispatch_tree;
fc051ae6 3199 bool owner;
8072aae3 3200 AccelClass *ac;
5e8fd947
AK		 3201};
3202
3203static void mtree_print_flatview(gpointer key, gpointer value,
3204 gpointer user_data)
57bb40c9 3205{
5e8fd947
AK		 3206 FlatView *view = key;
3207 GArray *fv_address_spaces = value;
3208 struct FlatViewInfo *fvi = user_data;
57bb40c9
PX		 3209 FlatRange *range = &view->ranges[0];
3210 MemoryRegion *mr;
3211 int n = view->nr;
5e8fd947
AK		 3212 int i;
3213 AddressSpace *as;
3214
b6b71cb5 3215 qemu_printf("FlatView #%d\n", fvi->counter);
5e8fd947
AK		 3216 ++fvi->counter;
3217
3218 for (i = 0; i < fv_address_spaces->len; ++i) {
3219 as = g_array_index(fv_address_spaces, AddressSpace*, i);
b6b71cb5
MA		 3220 qemu_printf(" AS \"%s\", root: %s",
3221 as->name, memory_region_name(as->root));
5e8fd947 3222 if (as->root->alias) {
b6b71cb5 3223 qemu_printf(", alias %s", memory_region_name(as->root->alias));
5e8fd947 3224 }
b6b71cb5 3225 qemu_printf("\n");
5e8fd947
AK		 3226 }
3227
b6b71cb5 3228 qemu_printf(" Root memory region: %s\n",
5e8fd947 3229 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX		 3230
3231 if (n <= 0) {
b6b71cb5 3232 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX		 3233 return;
3234 }
3235
3236 while (n--) {
3237 mr = range->mr;
377a07aa 3238 if (range->offset_in_region) {
b6b71cb5
MA		 3239 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3240 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3241 int128_get64(range->addr.start),
3242 int128_get64(range->addr.start)
3243 + MR_SIZE(range->addr.size),
3244 mr->priority,
3245 range->nonvolatile ? "nv-" : "",
3246 range->readonly ? "rom" : memory_region_type(mr),
3247 memory_region_name(mr),
3248 range->offset_in_region);
377a07aa 3249 } else {
b6b71cb5
MA		 3250 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3251 " (prio %d, %s%s): %s",
3252 int128_get64(range->addr.start),
3253 int128_get64(range->addr.start)
3254 + MR_SIZE(range->addr.size),
3255 mr->priority,
3256 range->nonvolatile ? "nv-" : "",
3257 range->readonly ? "rom" : memory_region_type(mr),
3258 memory_region_name(mr));
377a07aa 3259 }
fc051ae6 3260 if (fvi->owner) {
b6b71cb5 3261 mtree_print_mr_owner(mr);
fc051ae6 3262 }
8072aae3
AK		 3263
3264 if (fvi->ac) {
3265 for (i = 0; i < fv_address_spaces->len; ++i) {
3266 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3267 if (fvi->ac->has_memory(current_machine, as,
3268 int128_get64(range->addr.start),
3269 MR_SIZE(range->addr.size) + 1)) {
53b62bec 3270 qemu_printf(" %s", fvi->ac->name);
8072aae3
AK		 3271 }
3272 }
3273 }
b6b71cb5 3274 qemu_printf("\n");
57bb40c9
PX		 3275 range++;
3276 }
3277
5e8fd947
AK		 3278#if !defined(CONFIG_USER_ONLY)
3279 if (fvi->dispatch_tree && view->root) {
b6b71cb5 3280 mtree_print_dispatch(view->dispatch, view->root);
5e8fd947
AK		 3281 }
3282#endif
3283
b6b71cb5 3284 qemu_printf("\n");
5e8fd947
AK		 3285}
3286
3287static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3288 gpointer user_data)
3289{
3290 FlatView *view = key;
3291 GArray *fv_address_spaces = value;
3292
3293 g_array_unref(fv_address_spaces);
57bb40c9 3294 flatview_unref(view);
5e8fd947
AK		 3295
3296 return true;
57bb40c9
PX		 3297}
3298
670c0780 3299static void mtree_info_flatview(bool dispatch_tree, bool owner)
314e2987 3300{
670c0780
PMD		 3301 struct FlatViewInfo fvi = {
3302 .counter = 0,
3303 .dispatch_tree = dispatch_tree,
3304 .owner = owner,
3305 };
0d673e36 3306 AddressSpace *as;
670c0780
PMD		 3307 FlatView *view;
3308 GArray *fv_address_spaces;
3309 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3310 AccelClass *ac = ACCEL_GET_CLASS(current_accel());
314e2987 3311
670c0780
PMD		 3312 if (ac->has_memory) {
3313 fvi.ac = ac;
3314 }
5e8fd947 3315
670c0780
PMD		 3316 /* Gather all FVs in one table */
3317 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3318 view = address_space_get_flatview(as);
5e8fd947 3319
670c0780
PMD		 3320 fv_address_spaces = g_hash_table_lookup(views, view);
3321 if (!fv_address_spaces) {
3322 fv_address_spaces = g_array_new(false, false, sizeof(as));
3323 g_hash_table_insert(views, view, fv_address_spaces);
57bb40c9 3324 }
5e8fd947 3325
670c0780
PMD		 3326 g_array_append_val(fv_address_spaces, as);
3327 }
5e8fd947 3328
670c0780
PMD		 3329 /* Print */
3330 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
5e8fd947 3331
670c0780
PMD		 3332 /* Free */
3333 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3334 g_hash_table_unref(views);
3335}
3336
7bdbf99a
PMD		 3337struct AddressSpaceInfo {
3338 MemoryRegionListHead *ml_head;
3339 bool owner;
3340 bool disabled;
3341};
3342
3343/* Returns negative value if a < b; zero if a = b; positive value if a > b. */
3344static gint address_space_compare_name(gconstpointer a, gconstpointer b)
3345{
3346 const AddressSpace *as_a = a;
3347 const AddressSpace *as_b = b;
3348
3349 return g_strcmp0(as_a->name, as_b->name);
3350}
3351
3352static void mtree_print_as_name(gpointer data, gpointer user_data)
3353{
3354 AddressSpace *as = data;
3355
3356 qemu_printf("address-space: %s\n", as->name);
3357}
3358
3359static void mtree_print_as(gpointer key, gpointer value, gpointer user_data)
3360{
3361 MemoryRegion *mr = key;
3362 GSList *as_same_root_mr_list = value;
3363 struct AddressSpaceInfo *asi = user_data;
3364
3365 g_slist_foreach(as_same_root_mr_list, mtree_print_as_name, NULL);
3366 mtree_print_mr(mr, 1, 0, asi->ml_head, asi->owner, asi->disabled);
3367 qemu_printf("\n");
3368}
3369
3370static gboolean mtree_info_as_free(gpointer key, gpointer value,
3371 gpointer user_data)
3372{
3373 GSList *as_same_root_mr_list = value;
3374
3375 g_slist_free(as_same_root_mr_list);
3376
3377 return true;
3378}
3379
670c0780
PMD		 3380static void mtree_info_as(bool dispatch_tree, bool owner, bool disabled)
3381{
3382 MemoryRegionListHead ml_head;
3383 MemoryRegionList *ml, *ml2;
3384 AddressSpace *as;
7bdbf99a
PMD		 3385 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3386 GSList *as_same_root_mr_list;
3387 struct AddressSpaceInfo asi = {
3388 .ml_head = &ml_head,
3389 .owner = owner,
3390 .disabled = disabled,
3391 };
57bb40c9 3392
314e2987
BS		 3393 QTAILQ_INIT(&ml_head);
3394
0d673e36 3395 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
7bdbf99a
PMD		 3396 /* Create hashtable, key=AS root MR, value = list of AS */
3397 as_same_root_mr_list = g_hash_table_lookup(views, as->root);
3398 as_same_root_mr_list = g_slist_insert_sorted(as_same_root_mr_list, as,
3399 address_space_compare_name);
3400 g_hash_table_insert(views, as->root, as_same_root_mr_list);
b9f9be88
BS		 3401 }
3402
7bdbf99a
PMD		 3403 /* print address spaces */
3404 g_hash_table_foreach(views, mtree_print_as, &asi);
3405 g_hash_table_foreach_remove(views, mtree_info_as_free, 0);
3406 g_hash_table_unref(views);
3407
314e2987 3408 /* print aliased regions */
a16878d2 3409 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
b6b71cb5 3410 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
2261d393 3411 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner, disabled);
b6b71cb5 3412 qemu_printf("\n");
314e2987
BS		 3413 }
3414
a16878d2 3415 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3416 g_free(ml);
314e2987 3417 }
314e2987 3418}
b4fefef9 3419
670c0780
PMD		 3420void mtree_info(bool flatview, bool dispatch_tree, bool owner, bool disabled)
3421{
3422 if (flatview) {
3423 mtree_info_flatview(dispatch_tree, owner);
3424 } else {
3425 mtree_info_as(dispatch_tree, owner, disabled);
3426 }
3427}
3428
b08199c6 3429void memory_region_init_ram(MemoryRegion *mr,
d32335e8 3430 Object *owner,
b08199c6
PM		 3431 const char *name,
3432 uint64_t size,
3433 Error **errp)
3434{
3435 DeviceState *owner_dev;
3436 Error *err = NULL;
3437
3438 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3439 if (err) {
3440 error_propagate(errp, err);
3441 return;
3442 }
3443 /* This will assert if owner is neither NULL nor a DeviceState.
3444 * We only want the owner here for the purposes of defining a
3445 * unique name for migration. TODO: Ideally we should implement
3446 * a naming scheme for Objects which are not DeviceStates, in
3447 * which case we can relax this restriction.
3448 */
3449 owner_dev = DEVICE(owner);
3450 vmstate_register_ram(mr, owner_dev);
3451}
3452
3453void memory_region_init_rom(MemoryRegion *mr,
d32335e8 3454 Object *owner,
b08199c6
PM		 3455 const char *name,
3456 uint64_t size,
3457 Error **errp)
3458{
3459 DeviceState *owner_dev;
3460 Error *err = NULL;
3461
3462 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3463 if (err) {
3464 error_propagate(errp, err);
3465 return;
3466 }
3467 /* This will assert if owner is neither NULL nor a DeviceState.
3468 * We only want the owner here for the purposes of defining a
3469 * unique name for migration. TODO: Ideally we should implement
3470 * a naming scheme for Objects which are not DeviceStates, in
3471 * which case we can relax this restriction.
3472 */
3473 owner_dev = DEVICE(owner);
3474 vmstate_register_ram(mr, owner_dev);
3475}
3476
3477void memory_region_init_rom_device(MemoryRegion *mr,
d32335e8 3478 Object *owner,
b08199c6
PM		 3479 const MemoryRegionOps *ops,
3480 void *opaque,
3481 const char *name,
3482 uint64_t size,
3483 Error **errp)
3484{
3485 DeviceState *owner_dev;
3486 Error *err = NULL;
3487
3488 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3489 name, size, &err);
3490 if (err) {
3491 error_propagate(errp, err);
3492 return;
3493 }
3494 /* This will assert if owner is neither NULL nor a DeviceState.
3495 * We only want the owner here for the purposes of defining a
3496 * unique name for migration. TODO: Ideally we should implement
3497 * a naming scheme for Objects which are not DeviceStates, in
3498 * which case we can relax this restriction.
3499 */
3500 owner_dev = DEVICE(owner);
3501 vmstate_register_ram(mr, owner_dev);
3502}
3503
e7d3222e
AB		 3504/*
3505 * Support softmmu builds with CONFIG_FUZZ using a weak symbol and a stub for
3506 * the fuzz_dma_read_cb callback
3507 */
3508#ifdef CONFIG_FUZZ
3509void __attribute__((weak)) fuzz_dma_read_cb(size_t addr,
3510 size_t len,
fc1c8344 3511 MemoryRegion *mr)
e7d3222e
AB		 3512{
3513}
3514#endif
3515
b4fefef9
PC		 3516static const TypeInfo memory_region_info = {
3517 .parent = TYPE_OBJECT,
3518 .name = TYPE_MEMORY_REGION,
1b53ecd9 3519 .class_size = sizeof(MemoryRegionClass),
b4fefef9
PC		 3520 .instance_size = sizeof(MemoryRegion),
3521 .instance_init = memory_region_initfn,
3522 .instance_finalize = memory_region_finalize,
3523};
3524
3df9d748
AK		 3525static const TypeInfo iommu_memory_region_info = {
3526 .parent = TYPE_MEMORY_REGION,
3527 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3528 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK		 3529 .instance_size = sizeof(IOMMUMemoryRegion),
3530 .instance_init = iommu_memory_region_initfn,
1221a474 3531 .abstract = true,
3df9d748
AK		 3532};
3533
8947d7fc
DH		 3534static const TypeInfo ram_discard_manager_info = {
3535 .parent = TYPE_INTERFACE,
3536 .name = TYPE_RAM_DISCARD_MANAGER,
3537 .class_size = sizeof(RamDiscardManagerClass),
3538};
3539
b4fefef9
PC		 3540static void memory_register_types(void)
3541{
3542 type_register_static(&memory_region_info);
3df9d748 3543 type_register_static(&iommu_memory_region_info);
8947d7fc 3544 type_register_static(&ram_discard_manager_info);
b4fefef9
PC		 3545}
3546
3547type_init(memory_register_types)
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