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fuzz-test: remove unneccessary debugging flags
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CommitLineData
093bc2cd
AK
1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
6b620ca3
PB
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
093bc2cd
AK
14 */
15
d38ea87a 16#include "qemu/osdep.h"
21786c7e 17#include "qemu/log.h"
da34e65c 18#include "qapi/error.h"
33c11879 19#include "cpu.h"
022c62cb
PB
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
409ddd01 22#include "qapi/visitor.h"
1de7afc9 23#include "qemu/bitops.h"
8c56c1a5 24#include "qemu/error-report.h"
db725815 25#include "qemu/main-loop.h"
b6b71cb5 26#include "qemu/qemu-print.h"
2c9b15ca 27#include "qom/object.h"
8b7a5507 28#include "trace.h"
093bc2cd 29
022c62cb 30#include "exec/memory-internal.h"
220c3ebd 31#include "exec/ram_addr.h"
8c56c1a5 32#include "sysemu/kvm.h"
54d31236 33#include "sysemu/runstate.h"
14a48c1d 34#include "sysemu/tcg.h"
940e43aa 35#include "qemu/accel.h"
8072aae3 36#include "hw/boards.h"
b08199c6 37#include "migration/vmstate.h"
67d95c15 38
d197063f
PB
39//#define DEBUG_UNASSIGNED
40
22bde714
JK
41static unsigned memory_region_transaction_depth;
42static bool memory_region_update_pending;
4dc56152 43static bool ioeventfd_update_pending;
ae7a2bca 44bool global_dirty_log;
7664e80c 45
eae3eb3e 46static QTAILQ_HEAD(, MemoryListener) memory_listeners
72e22d2f 47 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 48
0d673e36
AK
49static QTAILQ_HEAD(, AddressSpace) address_spaces
50 = QTAILQ_HEAD_INITIALIZER(address_spaces);
51
967dc9b1
AK
52static GHashTable *flat_views;
53
093bc2cd
AK
54typedef struct AddrRange AddrRange;
55
8417cebf 56/*
c9cdaa3a 57 * Note that signed integers are needed for negative offsetting in aliases
8417cebf
AK
58 * (large MemoryRegion::alias_offset).
59 */
093bc2cd 60struct AddrRange {
08dafab4
AK
61 Int128 start;
62 Int128 size;
093bc2cd
AK
63};
64
08dafab4 65static AddrRange addrrange_make(Int128 start, Int128 size)
093bc2cd
AK
66{
67 return (AddrRange) { start, size };
68}
69
70static bool addrrange_equal(AddrRange r1, AddrRange r2)
71{
08dafab4 72 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
093bc2cd
AK
73}
74
08dafab4 75static Int128 addrrange_end(AddrRange r)
093bc2cd 76{
08dafab4 77 return int128_add(r.start, r.size);
093bc2cd
AK
78}
79
08dafab4 80static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 81{
08dafab4 82 int128_addto(&range.start, delta);
093bc2cd
AK
83 return range;
84}
85
08dafab4
AK
86static bool addrrange_contains(AddrRange range, Int128 addr)
87{
88 return int128_ge(addr, range.start)
89 && int128_lt(addr, addrrange_end(range));
90}
91
093bc2cd
AK
92static bool addrrange_intersects(AddrRange r1, AddrRange r2)
93{
08dafab4
AK
94 return addrrange_contains(r1, r2.start)
95 || addrrange_contains(r2, r1.start);
093bc2cd
AK
96}
97
98static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
99{
08dafab4
AK
100 Int128 start = int128_max(r1.start, r2.start);
101 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
102 return addrrange_make(start, int128_sub(end, start));
093bc2cd
AK
103}
104
0e0d36b4
AK
105enum ListenerDirection { Forward, Reverse };
106
7376e582 107#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
0e0d36b4
AK
108 do { \
109 MemoryListener *_listener; \
110 \
111 switch (_direction) { \
112 case Forward: \
113 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
975aefe0
AK
114 if (_listener->_callback) { \
115 _listener->_callback(_listener, ##_args); \
116 } \
0e0d36b4
AK
117 } \
118 break; \
119 case Reverse: \
eae3eb3e 120 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
975aefe0
AK
121 if (_listener->_callback) { \
122 _listener->_callback(_listener, ##_args); \
123 } \
0e0d36b4
AK
124 } \
125 break; \
126 default: \
127 abort(); \
128 } \
129 } while (0)
130
9a54635d 131#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
7376e582
AK
132 do { \
133 MemoryListener *_listener; \
134 \
135 switch (_direction) { \
136 case Forward: \
eae3eb3e 137 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
9a54635d 138 if (_listener->_callback) { \
7376e582
AK
139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
eae3eb3e 144 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
9a54635d 145 if (_listener->_callback) { \
7376e582
AK
146 _listener->_callback(_listener, _section, ##_args); \
147 } \
148 } \
149 break; \
150 default: \
151 abort(); \
152 } \
153 } while (0)
154
dfde4e6e 155/* No need to ref/unref .mr, the FlatRange keeps it alive. */
b2dfd71c 156#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
9c1f8f44 157 do { \
16620684
AK
158 MemoryRegionSection mrs = section_from_flat_range(fr, \
159 address_space_to_flatview(as)); \
9a54635d 160 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
9c1f8f44 161 } while(0)
0e0d36b4 162
093bc2cd
AK
163struct CoalescedMemoryRange {
164 AddrRange addr;
165 QTAILQ_ENTRY(CoalescedMemoryRange) link;
166};
167
3e9d69e7
AK
168struct MemoryRegionIoeventfd {
169 AddrRange addr;
170 bool match_data;
171 uint64_t data;
753d5e14 172 EventNotifier *e;
3e9d69e7
AK
173};
174
73bb753d
TB
175static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
176 MemoryRegionIoeventfd *b)
3e9d69e7 177{
73bb753d 178 if (int128_lt(a->addr.start, b->addr.start)) {
3e9d69e7 179 return true;
73bb753d 180 } else if (int128_gt(a->addr.start, b->addr.start)) {
3e9d69e7 181 return false;
73bb753d 182 } else if (int128_lt(a->addr.size, b->addr.size)) {
3e9d69e7 183 return true;
73bb753d 184 } else if (int128_gt(a->addr.size, b->addr.size)) {
3e9d69e7 185 return false;
73bb753d 186 } else if (a->match_data < b->match_data) {
3e9d69e7 187 return true;
73bb753d 188 } else if (a->match_data > b->match_data) {
3e9d69e7 189 return false;
73bb753d
TB
190 } else if (a->match_data) {
191 if (a->data < b->data) {
3e9d69e7 192 return true;
73bb753d 193 } else if (a->data > b->data) {
3e9d69e7
AK
194 return false;
195 }
196 }
73bb753d 197 if (a->e < b->e) {
3e9d69e7 198 return true;
73bb753d 199 } else if (a->e > b->e) {
3e9d69e7
AK
200 return false;
201 }
202 return false;
203}
204
73bb753d
TB
205static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
206 MemoryRegionIoeventfd *b)
3e9d69e7 207{
e6ffd757
EA
208 if (int128_eq(a->addr.start, b->addr.start) &&
209 (!int128_nz(a->addr.size) || !int128_nz(b->addr.size) ||
210 (int128_eq(a->addr.size, b->addr.size) &&
211 (a->match_data == b->match_data) &&
212 ((a->match_data && (a->data == b->data)) || !a->match_data) &&
213 (a->e == b->e))))
214 return true;
215
216 return false;
3e9d69e7
AK
217}
218
093bc2cd
AK
219/* Range of memory in the global map. Addresses are absolute. */
220struct FlatRange {
221 MemoryRegion *mr;
a8170e5e 222 hwaddr offset_in_region;
093bc2cd 223 AddrRange addr;
5a583347 224 uint8_t dirty_log_mask;
b138e654 225 bool romd_mode;
fb1cd6f9 226 bool readonly;
c26763f8 227 bool nonvolatile;
093bc2cd
AK
228};
229
093bc2cd
AK
230#define FOR_EACH_FLAT_RANGE(var, view) \
231 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
232
9c1f8f44 233static inline MemoryRegionSection
16620684 234section_from_flat_range(FlatRange *fr, FlatView *fv)
9c1f8f44
PB
235{
236 return (MemoryRegionSection) {
237 .mr = fr->mr,
16620684 238 .fv = fv,
9c1f8f44
PB
239 .offset_within_region = fr->offset_in_region,
240 .size = fr->addr.size,
241 .offset_within_address_space = int128_get64(fr->addr.start),
242 .readonly = fr->readonly,
c26763f8 243 .nonvolatile = fr->nonvolatile,
9c1f8f44
PB
244 };
245}
246
093bc2cd
AK
247static bool flatrange_equal(FlatRange *a, FlatRange *b)
248{
249 return a->mr == b->mr
250 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 251 && a->offset_in_region == b->offset_in_region
b138e654 252 && a->romd_mode == b->romd_mode
c26763f8
MAL
253 && a->readonly == b->readonly
254 && a->nonvolatile == b->nonvolatile;
093bc2cd
AK
255}
256
89c177bb 257static FlatView *flatview_new(MemoryRegion *mr_root)
093bc2cd 258{
cc94cd6d
AK
259 FlatView *view;
260
261 view = g_new0(FlatView, 1);
856d7245 262 view->ref = 1;
89c177bb
AK
263 view->root = mr_root;
264 memory_region_ref(mr_root);
02d9651d 265 trace_flatview_new(view, mr_root);
cc94cd6d
AK
266
267 return view;
093bc2cd
AK
268}
269
270/* Insert a range into a given position. Caller is responsible for maintaining
271 * sorting order.
272 */
273static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
274{
275 if (view->nr == view->nr_allocated) {
276 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 277 view->ranges = g_realloc(view->ranges,
093bc2cd
AK
278 view->nr_allocated * sizeof(*view->ranges));
279 }
280 memmove(view->ranges + pos + 1, view->ranges + pos,
281 (view->nr - pos) * sizeof(FlatRange));
282 view->ranges[pos] = *range;
dfde4e6e 283 memory_region_ref(range->mr);
093bc2cd
AK
284 ++view->nr;
285}
286
287static void flatview_destroy(FlatView *view)
288{
dfde4e6e
PB
289 int i;
290
02d9651d 291 trace_flatview_destroy(view, view->root);
66a6df1d
AK
292 if (view->dispatch) {
293 address_space_dispatch_free(view->dispatch);
294 }
dfde4e6e
PB
295 for (i = 0; i < view->nr; i++) {
296 memory_region_unref(view->ranges[i].mr);
297 }
7267c094 298 g_free(view->ranges);
89c177bb 299 memory_region_unref(view->root);
a9a0c06d 300 g_free(view);
093bc2cd
AK
301}
302
447b0d0b 303static bool flatview_ref(FlatView *view)
856d7245 304{
d73415a3 305 return qatomic_fetch_inc_nonzero(&view->ref) > 0;
856d7245
PB
306}
307
48564041 308void flatview_unref(FlatView *view)
856d7245 309{
d73415a3 310 if (qatomic_fetch_dec(&view->ref) == 1) {
02d9651d 311 trace_flatview_destroy_rcu(view, view->root);
092aa2fc 312 assert(view->root);
66a6df1d 313 call_rcu(view, flatview_destroy, rcu);
856d7245
PB
314 }
315}
316
3d8e6bf9
AK
317static bool can_merge(FlatRange *r1, FlatRange *r2)
318{
08dafab4 319 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 320 && r1->mr == r2->mr
08dafab4
AK
321 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
322 r1->addr.size),
323 int128_make64(r2->offset_in_region))
d0a9b5bc 324 && r1->dirty_log_mask == r2->dirty_log_mask
b138e654 325 && r1->romd_mode == r2->romd_mode
c26763f8
MAL
326 && r1->readonly == r2->readonly
327 && r1->nonvolatile == r2->nonvolatile;
3d8e6bf9
AK
328}
329
8508e024 330/* Attempt to simplify a view by merging adjacent ranges */
3d8e6bf9
AK
331static void flatview_simplify(FlatView *view)
332{
838ec117 333 unsigned i, j, k;
3d8e6bf9
AK
334
335 i = 0;
336 while (i < view->nr) {
337 j = i + 1;
338 while (j < view->nr
339 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 340 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
3d8e6bf9
AK
341 ++j;
342 }
343 ++i;
838ec117
KW
344 for (k = i; k < j; k++) {
345 memory_region_unref(view->ranges[k].mr);
346 }
3d8e6bf9
AK
347 memmove(&view->ranges[i], &view->ranges[j],
348 (view->nr - j) * sizeof(view->ranges[j]));
349 view->nr -= j - i;
350 }
351}
352
e7342aa3
PB
353static bool memory_region_big_endian(MemoryRegion *mr)
354{
355#ifdef TARGET_WORDS_BIGENDIAN
356 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
357#else
358 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
359#endif
360}
361
9bf825bf 362static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
e11ef3d1 363{
9bf825bf
TN
364 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
365 switch (op & MO_SIZE) {
366 case MO_8:
e11ef3d1 367 break;
9bf825bf 368 case MO_16:
e11ef3d1
PB
369 *data = bswap16(*data);
370 break;
9bf825bf 371 case MO_32:
e11ef3d1
PB
372 *data = bswap32(*data);
373 break;
9bf825bf 374 case MO_64:
e11ef3d1
PB
375 *data = bswap64(*data);
376 break;
377 default:
9bf825bf 378 g_assert_not_reached();
e11ef3d1
PB
379 }
380 }
381}
382
3c754a93 383static inline void memory_region_shift_read_access(uint64_t *value,
98f52cdb 384 signed shift,
3c754a93
PMD
385 uint64_t mask,
386 uint64_t tmp)
387{
98f52cdb
PMD
388 if (shift >= 0) {
389 *value |= (tmp & mask) << shift;
390 } else {
391 *value |= (tmp & mask) >> -shift;
392 }
3c754a93
PMD
393}
394
395static inline uint64_t memory_region_shift_write_access(uint64_t *value,
98f52cdb 396 signed shift,
3c754a93
PMD
397 uint64_t mask)
398{
98f52cdb
PMD
399 uint64_t tmp;
400
401 if (shift >= 0) {
402 tmp = (*value >> shift) & mask;
403 } else {
404 tmp = (*value << -shift) & mask;
405 }
406
407 return tmp;
3c754a93
PMD
408}
409
4779dc1d
HB
410static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
411{
412 MemoryRegion *root;
413 hwaddr abs_addr = offset;
414
415 abs_addr += mr->addr;
416 for (root = mr; root->container; ) {
417 root = root->container;
418 abs_addr += root->addr;
419 }
420
421 return abs_addr;
422}
423
5a68be94
HB
424static int get_cpu_index(void)
425{
426 if (current_cpu) {
427 return current_cpu->cpu_index;
428 }
429 return -1;
430}
431
cc05c43a 432static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
ce5d2f33
PB
433 hwaddr addr,
434 uint64_t *value,
435 unsigned size,
98f52cdb 436 signed shift,
cc05c43a
PM
437 uint64_t mask,
438 MemTxAttrs attrs)
ce5d2f33 439{
ce5d2f33
PB
440 uint64_t tmp;
441
cc05c43a 442 tmp = mr->ops->read(mr->opaque, addr, size);
23d92d68 443 if (mr->subpage) {
5a68be94 444 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
380ea843 445 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
4779dc1d 446 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 447 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 448 }
3c754a93 449 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 450 return MEMTX_OK;
ce5d2f33
PB
451}
452
cc05c43a
PM
453static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
454 hwaddr addr,
455 uint64_t *value,
456 unsigned size,
98f52cdb 457 signed shift,
cc05c43a
PM
458 uint64_t mask,
459 MemTxAttrs attrs)
164a4dcd 460{
cc05c43a
PM
461 uint64_t tmp = 0;
462 MemTxResult r;
164a4dcd 463
cc05c43a 464 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
23d92d68 465 if (mr->subpage) {
5a68be94 466 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
380ea843 467 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
4779dc1d 468 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 469 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 470 }
3c754a93 471 memory_region_shift_read_access(value, shift, mask, tmp);
cc05c43a 472 return r;
164a4dcd
AK
473}
474
cc05c43a
PM
475static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
476 hwaddr addr,
477 uint64_t *value,
478 unsigned size,
98f52cdb 479 signed shift,
cc05c43a
PM
480 uint64_t mask,
481 MemTxAttrs attrs)
164a4dcd 482{
3c754a93 483 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
164a4dcd 484
23d92d68 485 if (mr->subpage) {
5a68be94 486 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
380ea843 487 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
4779dc1d 488 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 489 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 490 }
164a4dcd 491 mr->ops->write(mr->opaque, addr, tmp, size);
cc05c43a 492 return MEMTX_OK;
164a4dcd
AK
493}
494
cc05c43a
PM
495static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
496 hwaddr addr,
497 uint64_t *value,
498 unsigned size,
98f52cdb 499 signed shift,
cc05c43a
PM
500 uint64_t mask,
501 MemTxAttrs attrs)
502{
3c754a93 503 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
cc05c43a 504
23d92d68 505 if (mr->subpage) {
5a68be94 506 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
380ea843 507 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
4779dc1d 508 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
5a68be94 509 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
23d92d68 510 }
cc05c43a
PM
511 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
512}
513
514static MemTxResult access_with_adjusted_size(hwaddr addr,
164a4dcd
AK
515 uint64_t *value,
516 unsigned size,
517 unsigned access_size_min,
518 unsigned access_size_max,
05e015f7
KF
519 MemTxResult (*access_fn)
520 (MemoryRegion *mr,
521 hwaddr addr,
522 uint64_t *value,
523 unsigned size,
98f52cdb 524 signed shift,
05e015f7
KF
525 uint64_t mask,
526 MemTxAttrs attrs),
cc05c43a
PM
527 MemoryRegion *mr,
528 MemTxAttrs attrs)
164a4dcd
AK
529{
530 uint64_t access_mask;
531 unsigned access_size;
532 unsigned i;
cc05c43a 533 MemTxResult r = MEMTX_OK;
164a4dcd
AK
534
535 if (!access_size_min) {
536 access_size_min = 1;
537 }
538 if (!access_size_max) {
539 access_size_max = 4;
540 }
ce5d2f33
PB
541
542 /* FIXME: support unaligned access? */
164a4dcd 543 access_size = MAX(MIN(size, access_size_max), access_size_min);
36960b4d 544 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
e7342aa3
PB
545 if (memory_region_big_endian(mr)) {
546 for (i = 0; i < size; i += access_size) {
05e015f7 547 r |= access_fn(mr, addr + i, value, access_size,
cc05c43a 548 (size - access_size - i) * 8, access_mask, attrs);
e7342aa3
PB
549 }
550 } else {
551 for (i = 0; i < size; i += access_size) {
05e015f7 552 r |= access_fn(mr, addr + i, value, access_size, i * 8,
cc05c43a 553 access_mask, attrs);
e7342aa3 554 }
164a4dcd 555 }
cc05c43a 556 return r;
164a4dcd
AK
557}
558
e2177955
AK
559static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
560{
0d673e36
AK
561 AddressSpace *as;
562
feca4ac1
PB
563 while (mr->container) {
564 mr = mr->container;
e2177955 565 }
0d673e36
AK
566 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
567 if (mr == as->root) {
568 return as;
569 }
e2177955 570 }
eed2bacf 571 return NULL;
e2177955
AK
572}
573
093bc2cd
AK
574/* Render a memory region into the global view. Ranges in @view obscure
575 * ranges in @mr.
576 */
577static void render_memory_region(FlatView *view,
578 MemoryRegion *mr,
08dafab4 579 Int128 base,
fb1cd6f9 580 AddrRange clip,
c26763f8
MAL
581 bool readonly,
582 bool nonvolatile)
093bc2cd
AK
583{
584 MemoryRegion *subregion;
585 unsigned i;
a8170e5e 586 hwaddr offset_in_region;
08dafab4
AK
587 Int128 remain;
588 Int128 now;
093bc2cd
AK
589 FlatRange fr;
590 AddrRange tmp;
591
6bba19ba
AK
592 if (!mr->enabled) {
593 return;
594 }
595
08dafab4 596 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 597 readonly |= mr->readonly;
c26763f8 598 nonvolatile |= mr->nonvolatile;
093bc2cd
AK
599
600 tmp = addrrange_make(base, mr->size);
601
602 if (!addrrange_intersects(tmp, clip)) {
603 return;
604 }
605
606 clip = addrrange_intersection(tmp, clip);
607
608 if (mr->alias) {
08dafab4
AK
609 int128_subfrom(&base, int128_make64(mr->alias->addr));
610 int128_subfrom(&base, int128_make64(mr->alias_offset));
c26763f8
MAL
611 render_memory_region(view, mr->alias, base, clip,
612 readonly, nonvolatile);
093bc2cd
AK
613 return;
614 }
615
616 /* Render subregions in priority order. */
617 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
c26763f8
MAL
618 render_memory_region(view, subregion, base, clip,
619 readonly, nonvolatile);
093bc2cd
AK
620 }
621
14a3c10a 622 if (!mr->terminates) {
093bc2cd
AK
623 return;
624 }
625
08dafab4 626 offset_in_region = int128_get64(int128_sub(clip.start, base));
093bc2cd
AK
627 base = clip.start;
628 remain = clip.size;
629
2eb74e1a 630 fr.mr = mr;
6f6a5ef3 631 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
b138e654 632 fr.romd_mode = mr->romd_mode;
2eb74e1a 633 fr.readonly = readonly;
c26763f8 634 fr.nonvolatile = nonvolatile;
2eb74e1a 635
093bc2cd 636 /* Render the region itself into any gaps left by the current view. */
08dafab4
AK
637 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
638 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
093bc2cd
AK
639 continue;
640 }
08dafab4
AK
641 if (int128_lt(base, view->ranges[i].addr.start)) {
642 now = int128_min(remain,
643 int128_sub(view->ranges[i].addr.start, base));
093bc2cd
AK
644 fr.offset_in_region = offset_in_region;
645 fr.addr = addrrange_make(base, now);
646 flatview_insert(view, i, &fr);
647 ++i;
08dafab4
AK
648 int128_addto(&base, now);
649 offset_in_region += int128_get64(now);
650 int128_subfrom(&remain, now);
093bc2cd 651 }
d26a8cae
AK
652 now = int128_sub(int128_min(int128_add(base, remain),
653 addrrange_end(view->ranges[i].addr)),
654 base);
655 int128_addto(&base, now);
656 offset_in_region += int128_get64(now);
657 int128_subfrom(&remain, now);
093bc2cd 658 }
08dafab4 659 if (int128_nz(remain)) {
093bc2cd
AK
660 fr.offset_in_region = offset_in_region;
661 fr.addr = addrrange_make(base, remain);
662 flatview_insert(view, i, &fr);
663 }
664}
665
fb5ef4ee
AB
666void flatview_for_each_range(FlatView *fv, flatview_cb cb , void *opaque)
667{
668 FlatRange *fr;
669
670 assert(fv);
671 assert(cb);
672
673 FOR_EACH_FLAT_RANGE(fr, fv) {
674 if (cb(fr->addr.start, fr->addr.size, fr->mr, opaque))
675 break;
676 }
677}
678
89c177bb
AK
679static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
680{
e673ba9a
PB
681 while (mr->enabled) {
682 if (mr->alias) {
683 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
684 /* The alias is included in its entirety. Use it as
685 * the "real" root, so that we can share more FlatViews.
686 */
687 mr = mr->alias;
688 continue;
689 }
690 } else if (!mr->terminates) {
691 unsigned int found = 0;
692 MemoryRegion *child, *next = NULL;
693 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
694 if (child->enabled) {
695 if (++found > 1) {
696 next = NULL;
697 break;
698 }
699 if (!child->addr && int128_ge(mr->size, child->size)) {
700 /* A child is included in its entirety. If it's the only
701 * enabled one, use it in the hope of finding an alias down the
702 * way. This will also let us share FlatViews.
703 */
704 next = child;
705 }
706 }
707 }
092aa2fc
AK
708 if (found == 0) {
709 return NULL;
710 }
e673ba9a
PB
711 if (next) {
712 mr = next;
713 continue;
714 }
715 }
716
092aa2fc 717 return mr;
89c177bb
AK
718 }
719
092aa2fc 720 return NULL;
89c177bb
AK
721}
722
093bc2cd 723/* Render a memory topology into a list of disjoint absolute ranges. */
a9a0c06d 724static FlatView *generate_memory_topology(MemoryRegion *mr)
093bc2cd 725{
9bf561e3 726 int i;
a9a0c06d 727 FlatView *view;
093bc2cd 728
89c177bb 729 view = flatview_new(mr);
093bc2cd 730
83f3c251 731 if (mr) {
a9a0c06d 732 render_memory_region(view, mr, int128_zero(),
c26763f8
MAL
733 addrrange_make(int128_zero(), int128_2_64()),
734 false, false);
83f3c251 735 }
a9a0c06d 736 flatview_simplify(view);
093bc2cd 737
9bf561e3
AK
738 view->dispatch = address_space_dispatch_new(view);
739 for (i = 0; i < view->nr; i++) {
740 MemoryRegionSection mrs =
741 section_from_flat_range(&view->ranges[i], view);
742 flatview_add_to_dispatch(view, &mrs);
743 }
744 address_space_dispatch_compact(view->dispatch);
967dc9b1 745 g_hash_table_replace(flat_views, mr, view);
9bf561e3 746
093bc2cd
AK
747 return view;
748}
749
3e9d69e7
AK
750static void address_space_add_del_ioeventfds(AddressSpace *as,
751 MemoryRegionIoeventfd *fds_new,
752 unsigned fds_new_nb,
753 MemoryRegionIoeventfd *fds_old,
754 unsigned fds_old_nb)
755{
756 unsigned iold, inew;
80a1ea37
AK
757 MemoryRegionIoeventfd *fd;
758 MemoryRegionSection section;
3e9d69e7
AK
759
760 /* Generate a symmetric difference of the old and new fd sets, adding
761 * and deleting as necessary.
762 */
763
764 iold = inew = 0;
765 while (iold < fds_old_nb || inew < fds_new_nb) {
766 if (iold < fds_old_nb
767 && (inew == fds_new_nb
73bb753d
TB
768 || memory_region_ioeventfd_before(&fds_old[iold],
769 &fds_new[inew]))) {
80a1ea37
AK
770 fd = &fds_old[iold];
771 section = (MemoryRegionSection) {
16620684 772 .fv = address_space_to_flatview(as),
80a1ea37 773 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 774 .size = fd->addr.size,
80a1ea37 775 };
9a54635d 776 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
753d5e14 777 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
778 ++iold;
779 } else if (inew < fds_new_nb
780 && (iold == fds_old_nb
73bb753d
TB
781 || memory_region_ioeventfd_before(&fds_new[inew],
782 &fds_old[iold]))) {
80a1ea37
AK
783 fd = &fds_new[inew];
784 section = (MemoryRegionSection) {
16620684 785 .fv = address_space_to_flatview(as),
80a1ea37 786 .offset_within_address_space = int128_get64(fd->addr.start),
052e87b0 787 .size = fd->addr.size,
80a1ea37 788 };
9a54635d 789 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
753d5e14 790 fd->match_data, fd->data, fd->e);
3e9d69e7
AK
791 ++inew;
792 } else {
793 ++iold;
794 ++inew;
795 }
796 }
797}
798
48564041 799FlatView *address_space_get_flatview(AddressSpace *as)
856d7245
PB
800{
801 FlatView *view;
802
694ea274 803 RCU_READ_LOCK_GUARD();
447b0d0b 804 do {
16620684 805 view = address_space_to_flatview(as);
447b0d0b
PB
806 /* If somebody has replaced as->current_map concurrently,
807 * flatview_ref returns false.
808 */
809 } while (!flatview_ref(view));
856d7245
PB
810 return view;
811}
812
3e9d69e7
AK
813static void address_space_update_ioeventfds(AddressSpace *as)
814{
99e86347 815 FlatView *view;
3e9d69e7
AK
816 FlatRange *fr;
817 unsigned ioeventfd_nb = 0;
920d557e
SH
818 unsigned ioeventfd_max;
819 MemoryRegionIoeventfd *ioeventfds;
3e9d69e7
AK
820 AddrRange tmp;
821 unsigned i;
822
920d557e
SH
823 /*
824 * It is likely that the number of ioeventfds hasn't changed much, so use
825 * the previous size as the starting value, with some headroom to avoid
826 * gratuitous reallocations.
827 */
828 ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4);
829 ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max);
830
856d7245 831 view = address_space_get_flatview(as);
99e86347 832 FOR_EACH_FLAT_RANGE(fr, view) {
3e9d69e7
AK
833 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
834 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
AK
835 int128_sub(fr->addr.start,
836 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
837 if (addrrange_intersects(fr->addr, tmp)) {
838 ++ioeventfd_nb;
920d557e
SH
839 if (ioeventfd_nb > ioeventfd_max) {
840 ioeventfd_max = MAX(ioeventfd_max * 2, 4);
841 ioeventfds = g_realloc(ioeventfds,
842 ioeventfd_max * sizeof(*ioeventfds));
843 }
3e9d69e7
AK
844 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
845 ioeventfds[ioeventfd_nb-1].addr = tmp;
846 }
847 }
848 }
849
850 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
851 as->ioeventfds, as->ioeventfd_nb);
852
7267c094 853 g_free(as->ioeventfds);
3e9d69e7
AK
854 as->ioeventfds = ioeventfds;
855 as->ioeventfd_nb = ioeventfd_nb;
856d7245 856 flatview_unref(view);
3e9d69e7
AK
857}
858
23f1174a
PX
859/*
860 * Notify the memory listeners about the coalesced IO change events of
861 * range `cmr'. Only the part that has intersection of the specified
862 * FlatRange will be sent.
863 */
864static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
865 CoalescedMemoryRange *cmr, bool add)
866{
867 AddrRange tmp;
868
869 tmp = addrrange_shift(cmr->addr,
870 int128_sub(fr->addr.start,
871 int128_make64(fr->offset_in_region)));
872 if (!addrrange_intersects(tmp, fr->addr)) {
873 return;
874 }
875 tmp = addrrange_intersection(tmp, fr->addr);
876
877 if (add) {
878 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
879 int128_get64(tmp.start),
880 int128_get64(tmp.size));
881 } else {
882 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
883 int128_get64(tmp.start),
884 int128_get64(tmp.size));
885 }
886}
887
909bf763
PB
888static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
889{
23f1174a
PX
890 CoalescedMemoryRange *cmr;
891
23f1174a
PX
892 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
893 flat_range_coalesced_io_notify(fr, as, cmr, false);
894 }
909bf763
PB
895}
896
897static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
898{
899 MemoryRegion *mr = fr->mr;
900 CoalescedMemoryRange *cmr;
909bf763 901
1f7af804
PB
902 if (QTAILQ_EMPTY(&mr->coalesced)) {
903 return;
904 }
905
909bf763 906 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
23f1174a 907 flat_range_coalesced_io_notify(fr, as, cmr, true);
909bf763
PB
908 }
909}
910
b8af1afb 911static void address_space_update_topology_pass(AddressSpace *as,
a9a0c06d
PB
912 const FlatView *old_view,
913 const FlatView *new_view,
b8af1afb 914 bool adding)
093bc2cd 915{
093bc2cd
AK
916 unsigned iold, inew;
917 FlatRange *frold, *frnew;
093bc2cd
AK
918
919 /* Generate a symmetric difference of the old and new memory maps.
920 * Kill ranges in the old map, and instantiate ranges in the new map.
921 */
922 iold = inew = 0;
a9a0c06d
PB
923 while (iold < old_view->nr || inew < new_view->nr) {
924 if (iold < old_view->nr) {
925 frold = &old_view->ranges[iold];
093bc2cd
AK
926 } else {
927 frold = NULL;
928 }
a9a0c06d
PB
929 if (inew < new_view->nr) {
930 frnew = &new_view->ranges[inew];
093bc2cd
AK
931 } else {
932 frnew = NULL;
933 }
934
935 if (frold
936 && (!frnew
08dafab4
AK
937 || int128_lt(frold->addr.start, frnew->addr.start)
938 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd 939 && !flatrange_equal(frold, frnew)))) {
41a6e477 940 /* In old but not in new, or in both but attributes changed. */
093bc2cd 941
b8af1afb 942 if (!adding) {
3ac7d43a 943 flat_range_coalesced_io_del(frold, as);
72e22d2f 944 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
945 }
946
093bc2cd
AK
947 ++iold;
948 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
41a6e477 949 /* In both and unchanged (except logging may have changed) */
093bc2cd 950
4f826024 951 if (adding) {
50c1e149 952 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b2dfd71c
PB
953 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
954 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
955 frold->dirty_log_mask,
956 frnew->dirty_log_mask);
957 }
958 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
959 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
960 frold->dirty_log_mask,
961 frnew->dirty_log_mask);
b8af1afb 962 }
5a583347
AK
963 }
964
093bc2cd
AK
965 ++iold;
966 ++inew;
093bc2cd
AK
967 } else {
968 /* In new */
969
b8af1afb 970 if (adding) {
72e22d2f 971 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
3ac7d43a 972 flat_range_coalesced_io_add(frnew, as);
b8af1afb
AK
973 }
974
093bc2cd
AK
975 ++inew;
976 }
977 }
b8af1afb
AK
978}
979
967dc9b1
AK
980static void flatviews_init(void)
981{
092aa2fc
AK
982 static FlatView *empty_view;
983
967dc9b1
AK
984 if (flat_views) {
985 return;
986 }
987
988 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
989 (GDestroyNotify) flatview_unref);
092aa2fc
AK
990 if (!empty_view) {
991 empty_view = generate_memory_topology(NULL);
992 /* We keep it alive forever in the global variable. */
993 flatview_ref(empty_view);
994 } else {
995 g_hash_table_replace(flat_views, NULL, empty_view);
996 flatview_ref(empty_view);
997 }
967dc9b1
AK
998}
999
1000static void flatviews_reset(void)
1001{
1002 AddressSpace *as;
1003
1004 if (flat_views) {
1005 g_hash_table_unref(flat_views);
1006 flat_views = NULL;
1007 }
1008 flatviews_init();
1009
1010 /* Render unique FVs */
1011 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1012 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1013
1014 if (g_hash_table_lookup(flat_views, physmr)) {
1015 continue;
1016 }
1017
1018 generate_memory_topology(physmr);
1019 }
1020}
1021
1022static void address_space_set_flatview(AddressSpace *as)
b8af1afb 1023{
67ace39b 1024 FlatView *old_view = address_space_to_flatview(as);
967dc9b1
AK
1025 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1026 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1027
1028 assert(new_view);
1029
67ace39b
AK
1030 if (old_view == new_view) {
1031 return;
1032 }
1033
1034 if (old_view) {
1035 flatview_ref(old_view);
1036 }
1037
967dc9b1 1038 flatview_ref(new_view);
9a62e24f
AK
1039
1040 if (!QTAILQ_EMPTY(&as->listeners)) {
67ace39b
AK
1041 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1042
1043 if (!old_view2) {
1044 old_view2 = &tmpview;
1045 }
1046 address_space_update_topology_pass(as, old_view2, new_view, false);
1047 address_space_update_topology_pass(as, old_view2, new_view, true);
9a62e24f 1048 }
b8af1afb 1049
374f2981 1050 /* Writes are protected by the BQL. */
d73415a3 1051 qatomic_rcu_set(&as->current_map, new_view);
67ace39b
AK
1052 if (old_view) {
1053 flatview_unref(old_view);
1054 }
856d7245
PB
1055
1056 /* Note that all the old MemoryRegions are still alive up to this
1057 * point. This relieves most MemoryListeners from the need to
1058 * ref/unref the MemoryRegions they get---unless they use them
1059 * outside the iothread mutex, in which case precise reference
1060 * counting is necessary.
1061 */
67ace39b
AK
1062 if (old_view) {
1063 flatview_unref(old_view);
1064 }
093bc2cd
AK
1065}
1066
202fc01b
AK
1067static void address_space_update_topology(AddressSpace *as)
1068{
1069 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1070
1071 flatviews_init();
1072 if (!g_hash_table_lookup(flat_views, physmr)) {
1073 generate_memory_topology(physmr);
1074 }
1075 address_space_set_flatview(as);
1076}
1077
4ef4db86
AK
1078void memory_region_transaction_begin(void)
1079{
bb880ded 1080 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
1081 ++memory_region_transaction_depth;
1082}
1083
1084void memory_region_transaction_commit(void)
1085{
0d673e36
AK
1086 AddressSpace *as;
1087
4ef4db86 1088 assert(memory_region_transaction_depth);
8d04fb55
JK
1089 assert(qemu_mutex_iothread_locked());
1090
4ef4db86 1091 --memory_region_transaction_depth;
4dc56152
GA
1092 if (!memory_region_transaction_depth) {
1093 if (memory_region_update_pending) {
967dc9b1
AK
1094 flatviews_reset();
1095
4dc56152 1096 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
02e2b95f 1097
4dc56152 1098 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
967dc9b1 1099 address_space_set_flatview(as);
02218487 1100 address_space_update_ioeventfds(as);
4dc56152 1101 }
ade9c1aa 1102 memory_region_update_pending = false;
0b152095 1103 ioeventfd_update_pending = false;
4dc56152
GA
1104 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1105 } else if (ioeventfd_update_pending) {
1106 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1107 address_space_update_ioeventfds(as);
1108 }
ade9c1aa 1109 ioeventfd_update_pending = false;
4dc56152 1110 }
4dc56152 1111 }
4ef4db86
AK
1112}
1113
545e92e0
AK
1114static void memory_region_destructor_none(MemoryRegion *mr)
1115{
1116}
1117
1118static void memory_region_destructor_ram(MemoryRegion *mr)
1119{
f1060c55 1120 qemu_ram_free(mr->ram_block);
545e92e0
AK
1121}
1122
b4fefef9
PC
1123static bool memory_region_need_escape(char c)
1124{
1125 return c == '/' || c == '[' || c == '\\' || c == ']';
1126}
1127
1128static char *memory_region_escape_name(const char *name)
1129{
1130 const char *p;
1131 char *escaped, *q;
1132 uint8_t c;
1133 size_t bytes = 0;
1134
1135 for (p = name; *p; p++) {
1136 bytes += memory_region_need_escape(*p) ? 4 : 1;
1137 }
1138 if (bytes == p - name) {
1139 return g_memdup(name, bytes + 1);
1140 }
1141
1142 escaped = g_malloc(bytes + 1);
1143 for (p = name, q = escaped; *p; p++) {
1144 c = *p;
1145 if (unlikely(memory_region_need_escape(c))) {
1146 *q++ = '\\';
1147 *q++ = 'x';
1148 *q++ = "0123456789abcdef"[c >> 4];
1149 c = "0123456789abcdef"[c & 15];
1150 }
1151 *q++ = c;
1152 }
1153 *q = 0;
1154 return escaped;
1155}
1156
3df9d748
AK
1157static void memory_region_do_init(MemoryRegion *mr,
1158 Object *owner,
1159 const char *name,
1160 uint64_t size)
093bc2cd 1161{
08dafab4
AK
1162 mr->size = int128_make64(size);
1163 if (size == UINT64_MAX) {
1164 mr->size = int128_2_64();
1165 }
302fa283 1166 mr->name = g_strdup(name);
612263cf 1167 mr->owner = owner;
58eaa217 1168 mr->ram_block = NULL;
b4fefef9
PC
1169
1170 if (name) {
843ef73a
PC
1171 char *escaped_name = memory_region_escape_name(name);
1172 char *name_array = g_strdup_printf("%s[*]", escaped_name);
612263cf
PB
1173
1174 if (!owner) {
1175 owner = container_get(qdev_get_machine(), "/unattached");
1176 }
1177
d2623129 1178 object_property_add_child(owner, name_array, OBJECT(mr));
b4fefef9 1179 object_unref(OBJECT(mr));
843ef73a
PC
1180 g_free(name_array);
1181 g_free(escaped_name);
b4fefef9
PC
1182 }
1183}
1184
3df9d748
AK
1185void memory_region_init(MemoryRegion *mr,
1186 Object *owner,
1187 const char *name,
1188 uint64_t size)
1189{
1190 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1191 memory_region_do_init(mr, owner, name, size);
1192}
1193
d7bce999
EB
1194static void memory_region_get_container(Object *obj, Visitor *v,
1195 const char *name, void *opaque,
1196 Error **errp)
409ddd01
PC
1197{
1198 MemoryRegion *mr = MEMORY_REGION(obj);
ddfb0baa 1199 char *path = (char *)"";
409ddd01
PC
1200
1201 if (mr->container) {
1202 path = object_get_canonical_path(OBJECT(mr->container));
1203 }
51e72bc1 1204 visit_type_str(v, name, &path, errp);
409ddd01
PC
1205 if (mr->container) {
1206 g_free(path);
1207 }
1208}
1209
1210static Object *memory_region_resolve_container(Object *obj, void *opaque,
1211 const char *part)
1212{
1213 MemoryRegion *mr = MEMORY_REGION(obj);
1214
1215 return OBJECT(mr->container);
1216}
1217
d7bce999
EB
1218static void memory_region_get_priority(Object *obj, Visitor *v,
1219 const char *name, void *opaque,
1220 Error **errp)
d33382da
PC
1221{
1222 MemoryRegion *mr = MEMORY_REGION(obj);
1223 int32_t value = mr->priority;
1224
51e72bc1 1225 visit_type_int32(v, name, &value, errp);
d33382da
PC
1226}
1227
d7bce999
EB
1228static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1229 void *opaque, Error **errp)
52aef7bb
PC
1230{
1231 MemoryRegion *mr = MEMORY_REGION(obj);
1232 uint64_t value = memory_region_size(mr);
1233
51e72bc1 1234 visit_type_uint64(v, name, &value, errp);
52aef7bb
PC
1235}
1236
b4fefef9
PC
1237static void memory_region_initfn(Object *obj)
1238{
1239 MemoryRegion *mr = MEMORY_REGION(obj);
409ddd01 1240 ObjectProperty *op;
b4fefef9
PC
1241
1242 mr->ops = &unassigned_mem_ops;
6bba19ba 1243 mr->enabled = true;
5f9a5ea1 1244 mr->romd_mode = true;
545e92e0 1245 mr->destructor = memory_region_destructor_none;
093bc2cd 1246 QTAILQ_INIT(&mr->subregions);
093bc2cd 1247 QTAILQ_INIT(&mr->coalesced);
409ddd01
PC
1248
1249 op = object_property_add(OBJECT(mr), "container",
1250 "link<" TYPE_MEMORY_REGION ">",
1251 memory_region_get_container,
1252 NULL, /* memory_region_set_container */
d2623129 1253 NULL, NULL);
409ddd01
PC
1254 op->resolve = memory_region_resolve_container;
1255
64a7b8de 1256 object_property_add_uint64_ptr(OBJECT(mr), "addr",
d2623129 1257 &mr->addr, OBJ_PROP_FLAG_READ);
d33382da
PC
1258 object_property_add(OBJECT(mr), "priority", "uint32",
1259 memory_region_get_priority,
1260 NULL, /* memory_region_set_priority */
d2623129 1261 NULL, NULL);
52aef7bb
PC
1262 object_property_add(OBJECT(mr), "size", "uint64",
1263 memory_region_get_size,
1264 NULL, /* memory_region_set_size, */
d2623129 1265 NULL, NULL);
093bc2cd
AK
1266}
1267
3df9d748
AK
1268static void iommu_memory_region_initfn(Object *obj)
1269{
1270 MemoryRegion *mr = MEMORY_REGION(obj);
1271
1272 mr->is_iommu = true;
1273}
1274
b018ddf6
PB
1275static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1276 unsigned size)
1277{
1278#ifdef DEBUG_UNASSIGNED
1279 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1280#endif
68a7439a 1281 return 0;
b018ddf6
PB
1282}
1283
1284static void unassigned_mem_write(void *opaque, hwaddr addr,
1285 uint64_t val, unsigned size)
1286{
1287#ifdef DEBUG_UNASSIGNED
1288 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1289#endif
b018ddf6
PB
1290}
1291
d197063f 1292static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
8372d383
PM
1293 unsigned size, bool is_write,
1294 MemTxAttrs attrs)
d197063f
PB
1295{
1296 return false;
1297}
1298
1299const MemoryRegionOps unassigned_mem_ops = {
1300 .valid.accepts = unassigned_mem_accepts,
1301 .endianness = DEVICE_NATIVE_ENDIAN,
1302};
1303
4a2e242b
AW
1304static uint64_t memory_region_ram_device_read(void *opaque,
1305 hwaddr addr, unsigned size)
1306{
1307 MemoryRegion *mr = opaque;
1308 uint64_t data = (uint64_t)~0;
1309
1310 switch (size) {
1311 case 1:
1312 data = *(uint8_t *)(mr->ram_block->host + addr);
1313 break;
1314 case 2:
1315 data = *(uint16_t *)(mr->ram_block->host + addr);
1316 break;
1317 case 4:
1318 data = *(uint32_t *)(mr->ram_block->host + addr);
1319 break;
1320 case 8:
1321 data = *(uint64_t *)(mr->ram_block->host + addr);
1322 break;
1323 }
1324
1325 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1326
1327 return data;
1328}
1329
1330static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1331 uint64_t data, unsigned size)
1332{
1333 MemoryRegion *mr = opaque;
1334
1335 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1336
1337 switch (size) {
1338 case 1:
1339 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1340 break;
1341 case 2:
1342 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1343 break;
1344 case 4:
1345 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1346 break;
1347 case 8:
1348 *(uint64_t *)(mr->ram_block->host + addr) = data;
1349 break;
1350 }
1351}
1352
1353static const MemoryRegionOps ram_device_mem_ops = {
1354 .read = memory_region_ram_device_read,
1355 .write = memory_region_ram_device_write,
c99a29e7 1356 .endianness = DEVICE_HOST_ENDIAN,
4a2e242b
AW
1357 .valid = {
1358 .min_access_size = 1,
1359 .max_access_size = 8,
1360 .unaligned = true,
1361 },
1362 .impl = {
1363 .min_access_size = 1,
1364 .max_access_size = 8,
1365 .unaligned = true,
1366 },
1367};
1368
d2702032
PB
1369bool memory_region_access_valid(MemoryRegion *mr,
1370 hwaddr addr,
1371 unsigned size,
6d7b9a6c
PM
1372 bool is_write,
1373 MemTxAttrs attrs)
093bc2cd 1374{
5d971f9e
MT
1375 if (mr->ops->valid.accepts
1376 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write, attrs)) {
21786c7e
PMD
1377 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1378 "0x%" HWADDR_PRIX ", size %u, "
1379 "region '%s', reason: rejected\n",
1380 addr, size, memory_region_name(mr));
093bc2cd
AK
1381 return false;
1382 }
1383
5d971f9e 1384 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
21786c7e
PMD
1385 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1386 "0x%" HWADDR_PRIX ", size %u, "
1387 "region '%s', reason: unaligned\n",
1388 addr, size, memory_region_name(mr));
5d971f9e 1389 return false;
a014ed07
PB
1390 }
1391
5d971f9e 1392 /* Treat zero as compatibility all valid */
a014ed07 1393 if (!mr->ops->valid.max_access_size) {
5d971f9e 1394 return true;
a014ed07
PB
1395 }
1396
5d971f9e
MT
1397 if (size > mr->ops->valid.max_access_size
1398 || size < mr->ops->valid.min_access_size) {
21786c7e
PMD
1399 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1400 "0x%" HWADDR_PRIX ", size %u, "
1401 "region '%s', reason: invalid size "
1402 "(min:%u max:%u)\n",
1403 addr, size, memory_region_name(mr),
1404 mr->ops->valid.min_access_size,
1405 mr->ops->valid.max_access_size);
5d971f9e 1406 return false;
093bc2cd
AK
1407 }
1408 return true;
1409}
1410
cc05c43a
PM
1411static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1412 hwaddr addr,
1413 uint64_t *pval,
1414 unsigned size,
1415 MemTxAttrs attrs)
093bc2cd 1416{
cc05c43a 1417 *pval = 0;
093bc2cd 1418
ce5d2f33 1419 if (mr->ops->read) {
cc05c43a
PM
1420 return access_with_adjusted_size(addr, pval, size,
1421 mr->ops->impl.min_access_size,
1422 mr->ops->impl.max_access_size,
1423 memory_region_read_accessor,
1424 mr, attrs);
62a0db94 1425 } else {
cc05c43a
PM
1426 return access_with_adjusted_size(addr, pval, size,
1427 mr->ops->impl.min_access_size,
1428 mr->ops->impl.max_access_size,
1429 memory_region_read_with_attrs_accessor,
1430 mr, attrs);
74901c3b 1431 }
093bc2cd
AK
1432}
1433
3b643495
PM
1434MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1435 hwaddr addr,
1436 uint64_t *pval,
e67c9046 1437 MemOp op,
3b643495 1438 MemTxAttrs attrs)
a621f38d 1439{
e67c9046 1440 unsigned size = memop_size(op);
cc05c43a
PM
1441 MemTxResult r;
1442
fc1c8344 1443 fuzz_dma_read_cb(addr, size, mr);
6d7b9a6c 1444 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
791af8c8 1445 *pval = unassigned_mem_read(mr, addr, size);
cc05c43a 1446 return MEMTX_DECODE_ERROR;
791af8c8 1447 }
a621f38d 1448
cc05c43a 1449 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
9bf825bf 1450 adjust_endianness(mr, pval, op);
cc05c43a 1451 return r;
a621f38d 1452}
093bc2cd 1453
8c56c1a5
PF
1454/* Return true if an eventfd was signalled */
1455static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1456 hwaddr addr,
1457 uint64_t data,
1458 unsigned size,
1459 MemTxAttrs attrs)
1460{
1461 MemoryRegionIoeventfd ioeventfd = {
1462 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1463 .data = data,
1464 };
1465 unsigned i;
1466
1467 for (i = 0; i < mr->ioeventfd_nb; i++) {
1468 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1469 ioeventfd.e = mr->ioeventfds[i].e;
1470
73bb753d 1471 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
8c56c1a5
PF
1472 event_notifier_set(ioeventfd.e);
1473 return true;
1474 }
1475 }
1476
1477 return false;
1478}
1479
3b643495
PM
1480MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1481 hwaddr addr,
1482 uint64_t data,
e67c9046 1483 MemOp op,
3b643495 1484 MemTxAttrs attrs)
a621f38d 1485{
e67c9046
TN
1486 unsigned size = memop_size(op);
1487
6d7b9a6c 1488 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
b018ddf6 1489 unassigned_mem_write(mr, addr, data, size);
cc05c43a 1490 return MEMTX_DECODE_ERROR;
093bc2cd
AK
1491 }
1492
9bf825bf 1493 adjust_endianness(mr, &data, op);
a621f38d 1494
8c56c1a5
PF
1495 if ((!kvm_eventfds_enabled()) &&
1496 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1497 return MEMTX_OK;
1498 }
1499
ce5d2f33 1500 if (mr->ops->write) {
cc05c43a
PM
1501 return access_with_adjusted_size(addr, &data, size,
1502 mr->ops->impl.min_access_size,
1503 mr->ops->impl.max_access_size,
1504 memory_region_write_accessor, mr,
1505 attrs);
62a0db94 1506 } else {
cc05c43a
PM
1507 return
1508 access_with_adjusted_size(addr, &data, size,
1509 mr->ops->impl.min_access_size,
1510 mr->ops->impl.max_access_size,
1511 memory_region_write_with_attrs_accessor,
1512 mr, attrs);
74901c3b 1513 }
093bc2cd
AK
1514}
1515
093bc2cd 1516void memory_region_init_io(MemoryRegion *mr,
2c9b15ca 1517 Object *owner,
093bc2cd
AK
1518 const MemoryRegionOps *ops,
1519 void *opaque,
1520 const char *name,
1521 uint64_t size)
1522{
2c9b15ca 1523 memory_region_init(mr, owner, name, size);
6d6d2abf 1524 mr->ops = ops ? ops : &unassigned_mem_ops;
093bc2cd 1525 mr->opaque = opaque;
14a3c10a 1526 mr->terminates = true;
093bc2cd
AK
1527}
1528
1cfe48c1
PM
1529void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1530 Object *owner,
1531 const char *name,
1532 uint64_t size,
1533 Error **errp)
06329cce
MA
1534{
1535 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1536}
1537
1538void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1539 Object *owner,
1540 const char *name,
1541 uint64_t size,
1542 bool share,
1543 Error **errp)
093bc2cd 1544{
1cd3d492 1545 Error *err = NULL;
2c9b15ca 1546 memory_region_init(mr, owner, name, size);
8ea9252a 1547 mr->ram = true;
14a3c10a 1548 mr->terminates = true;
545e92e0 1549 mr->destructor = memory_region_destructor_ram;
1cd3d492 1550 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1cd3d492
IM
1551 if (err) {
1552 mr->size = int128_zero();
1553 object_unparent(OBJECT(mr));
1554 error_propagate(errp, err);
1555 }
0b183fc8
PB
1556}
1557
60786ef3
MT
1558void memory_region_init_resizeable_ram(MemoryRegion *mr,
1559 Object *owner,
1560 const char *name,
1561 uint64_t size,
1562 uint64_t max_size,
1563 void (*resized)(const char*,
1564 uint64_t length,
1565 void *host),
1566 Error **errp)
1567{
1cd3d492 1568 Error *err = NULL;
60786ef3
MT
1569 memory_region_init(mr, owner, name, size);
1570 mr->ram = true;
1571 mr->terminates = true;
1572 mr->destructor = memory_region_destructor_ram;
8e41fb63 1573 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1cd3d492 1574 mr, &err);
1cd3d492
IM
1575 if (err) {
1576 mr->size = int128_zero();
1577 object_unparent(OBJECT(mr));
1578 error_propagate(errp, err);
1579 }
60786ef3
MT
1580}
1581
d5dbde46 1582#ifdef CONFIG_POSIX
0b183fc8
PB
1583void memory_region_init_ram_from_file(MemoryRegion *mr,
1584 struct Object *owner,
1585 const char *name,
1586 uint64_t size,
98376843 1587 uint64_t align,
cbfc0171 1588 uint32_t ram_flags,
7f56e740 1589 const char *path,
369d6dc4 1590 bool readonly,
7f56e740 1591 Error **errp)
0b183fc8 1592{
1cd3d492 1593 Error *err = NULL;
0b183fc8
PB
1594 memory_region_init(mr, owner, name, size);
1595 mr->ram = true;
369d6dc4 1596 mr->readonly = readonly;
0b183fc8
PB
1597 mr->terminates = true;
1598 mr->destructor = memory_region_destructor_ram;
98376843 1599 mr->align = align;
369d6dc4
SH
1600 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path,
1601 readonly, &err);
1cd3d492
IM
1602 if (err) {
1603 mr->size = int128_zero();
1604 object_unparent(OBJECT(mr));
1605 error_propagate(errp, err);
1606 }
093bc2cd 1607}
fea617c5
MAL
1608
1609void memory_region_init_ram_from_fd(MemoryRegion *mr,
1610 struct Object *owner,
1611 const char *name,
1612 uint64_t size,
1613 bool share,
1614 int fd,
44a4ff31 1615 ram_addr_t offset,
fea617c5
MAL
1616 Error **errp)
1617{
1cd3d492 1618 Error *err = NULL;
fea617c5
MAL
1619 memory_region_init(mr, owner, name, size);
1620 mr->ram = true;
1621 mr->terminates = true;
1622 mr->destructor = memory_region_destructor_ram;
cbfc0171
JH
1623 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1624 share ? RAM_SHARED : 0,
44a4ff31 1625 fd, offset, false, &err);
1cd3d492
IM
1626 if (err) {
1627 mr->size = int128_zero();
1628 object_unparent(OBJECT(mr));
1629 error_propagate(errp, err);
1630 }
fea617c5 1631}
0b183fc8 1632#endif
093bc2cd
AK
1633
1634void memory_region_init_ram_ptr(MemoryRegion *mr,
2c9b15ca 1635 Object *owner,
093bc2cd
AK
1636 const char *name,
1637 uint64_t size,
1638 void *ptr)
1639{
2c9b15ca 1640 memory_region_init(mr, owner, name, size);
8ea9252a 1641 mr->ram = true;
14a3c10a 1642 mr->terminates = true;
fc3e7665 1643 mr->destructor = memory_region_destructor_ram;
ef701d7b
HT
1644
1645 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1646 assert(ptr != NULL);
8e41fb63 1647 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
093bc2cd
AK
1648}
1649
21e00fa5
AW
1650void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1651 Object *owner,
1652 const char *name,
1653 uint64_t size,
1654 void *ptr)
e4dc3f59 1655{
2ddb89b0
BS
1656 memory_region_init(mr, owner, name, size);
1657 mr->ram = true;
1658 mr->terminates = true;
21e00fa5 1659 mr->ram_device = true;
4a2e242b
AW
1660 mr->ops = &ram_device_mem_ops;
1661 mr->opaque = mr;
2ddb89b0 1662 mr->destructor = memory_region_destructor_ram;
0a2949e0 1663
2ddb89b0
BS
1664 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1665 assert(ptr != NULL);
1666 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
e4dc3f59
ND
1667}
1668
093bc2cd 1669void memory_region_init_alias(MemoryRegion *mr,
2c9b15ca 1670 Object *owner,
093bc2cd
AK
1671 const char *name,
1672 MemoryRegion *orig,
a8170e5e 1673 hwaddr offset,
093bc2cd
AK
1674 uint64_t size)
1675{
2c9b15ca 1676 memory_region_init(mr, owner, name, size);
093bc2cd
AK
1677 mr->alias = orig;
1678 mr->alias_offset = offset;
1679}
1680
b59821a9
PM
1681void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1682 struct Object *owner,
1683 const char *name,
1684 uint64_t size,
1685 Error **errp)
a1777f7f 1686{
83696c8f 1687 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
a1777f7f 1688 mr->readonly = true;
a1777f7f
PM
1689}
1690
b59821a9
PM
1691void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1692 Object *owner,
1693 const MemoryRegionOps *ops,
1694 void *opaque,
1695 const char *name,
1696 uint64_t size,
1697 Error **errp)
d0a9b5bc 1698{
1cd3d492 1699 Error *err = NULL;
39e0b03d 1700 assert(ops);
2c9b15ca 1701 memory_region_init(mr, owner, name, size);
7bc2b9cd 1702 mr->ops = ops;
75f5941c 1703 mr->opaque = opaque;
d0a9b5bc 1704 mr->terminates = true;
75c578dc 1705 mr->rom_device = true;
58268c8d 1706 mr->destructor = memory_region_destructor_ram;
1cd3d492
IM
1707 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1708 if (err) {
1709 mr->size = int128_zero();
1710 object_unparent(OBJECT(mr));
1711 error_propagate(errp, err);
1712 }
d0a9b5bc
AK
1713}
1714
1221a474
AK
1715void memory_region_init_iommu(void *_iommu_mr,
1716 size_t instance_size,
1717 const char *mrtypename,
2c9b15ca 1718 Object *owner,
30951157
AK
1719 const char *name,
1720 uint64_t size)
1721{
1221a474 1722 struct IOMMUMemoryRegion *iommu_mr;
3df9d748
AK
1723 struct MemoryRegion *mr;
1724
1221a474
AK
1725 object_initialize(_iommu_mr, instance_size, mrtypename);
1726 mr = MEMORY_REGION(_iommu_mr);
3df9d748
AK
1727 memory_region_do_init(mr, owner, name, size);
1728 iommu_mr = IOMMU_MEMORY_REGION(mr);
30951157 1729 mr->terminates = true; /* then re-forwards */
3df9d748
AK
1730 QLIST_INIT(&iommu_mr->iommu_notify);
1731 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
30951157
AK
1732}
1733
b4fefef9 1734static void memory_region_finalize(Object *obj)
093bc2cd 1735{
b4fefef9
PC
1736 MemoryRegion *mr = MEMORY_REGION(obj);
1737
2e2b8eb7
PB
1738 assert(!mr->container);
1739
1740 /* We know the region is not visible in any address space (it
1741 * does not have a container and cannot be a root either because
1742 * it has no references, so we can blindly clear mr->enabled.
1743 * memory_region_set_enabled instead could trigger a transaction
1744 * and cause an infinite loop.
1745 */
1746 mr->enabled = false;
1747 memory_region_transaction_begin();
1748 while (!QTAILQ_EMPTY(&mr->subregions)) {
1749 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1750 memory_region_del_subregion(mr, subregion);
1751 }
1752 memory_region_transaction_commit();
1753
545e92e0 1754 mr->destructor(mr);
093bc2cd 1755 memory_region_clear_coalescing(mr);
302fa283 1756 g_free((char *)mr->name);
7267c094 1757 g_free(mr->ioeventfds);
093bc2cd
AK
1758}
1759
803c0816
PB
1760Object *memory_region_owner(MemoryRegion *mr)
1761{
22a893e4
PB
1762 Object *obj = OBJECT(mr);
1763 return obj->parent;
803c0816
PB
1764}
1765
46637be2
PB
1766void memory_region_ref(MemoryRegion *mr)
1767{
22a893e4
PB
1768 /* MMIO callbacks most likely will access data that belongs
1769 * to the owner, hence the need to ref/unref the owner whenever
1770 * the memory region is in use.
1771 *
1772 * The memory region is a child of its owner. As long as the
1773 * owner doesn't call unparent itself on the memory region,
1774 * ref-ing the owner will also keep the memory region alive.
612263cf
PB
1775 * Memory regions without an owner are supposed to never go away;
1776 * we do not ref/unref them because it slows down DMA sensibly.
22a893e4 1777 */
612263cf
PB
1778 if (mr && mr->owner) {
1779 object_ref(mr->owner);
46637be2
PB
1780 }
1781}
1782
1783void memory_region_unref(MemoryRegion *mr)
1784{
612263cf
PB
1785 if (mr && mr->owner) {
1786 object_unref(mr->owner);
46637be2
PB
1787 }
1788}
1789
093bc2cd
AK
1790uint64_t memory_region_size(MemoryRegion *mr)
1791{
08dafab4
AK
1792 if (int128_eq(mr->size, int128_2_64())) {
1793 return UINT64_MAX;
1794 }
1795 return int128_get64(mr->size);
093bc2cd
AK
1796}
1797
5d546d4b 1798const char *memory_region_name(const MemoryRegion *mr)
8991c79b 1799{
d1dd32af
PC
1800 if (!mr->name) {
1801 ((MemoryRegion *)mr)->name =
7a309cc9 1802 g_strdup(object_get_canonical_path_component(OBJECT(mr)));
d1dd32af 1803 }
302fa283 1804 return mr->name;
8991c79b
AK
1805}
1806
21e00fa5 1807bool memory_region_is_ram_device(MemoryRegion *mr)
e4dc3f59 1808{
21e00fa5 1809 return mr->ram_device;
e4dc3f59
ND
1810}
1811
2d1a35be 1812uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
55043ba3 1813{
6f6a5ef3 1814 uint8_t mask = mr->dirty_log_mask;
1370d61a
ZY
1815 RAMBlock *rb = mr->ram_block;
1816
1817 if (global_dirty_log && ((rb && qemu_ram_is_migratable(rb)) ||
1818 memory_region_is_iommu(mr))) {
6f6a5ef3
PB
1819 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1820 }
0a2949e0
PB
1821
1822 if (tcg_enabled() && rb) {
1823 /* TCG only cares about dirty memory logging for RAM, not IOMMU. */
1824 mask |= (1 << DIRTY_MEMORY_CODE);
1825 }
6f6a5ef3 1826 return mask;
55043ba3
AK
1827}
1828
2d1a35be
PB
1829bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1830{
1831 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1832}
1833
549d4005
EA
1834static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1835 Error **errp)
5bf3d319
PX
1836{
1837 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1838 IOMMUNotifier *iommu_notifier;
1221a474 1839 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
549d4005 1840 int ret = 0;
5bf3d319 1841
3df9d748 1842 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
5bf3d319
PX
1843 flags |= iommu_notifier->notifier_flags;
1844 }
1845
1221a474 1846 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
549d4005
EA
1847 ret = imrc->notify_flag_changed(iommu_mr,
1848 iommu_mr->iommu_notify_flags,
1849 flags, errp);
5bf3d319
PX
1850 }
1851
549d4005
EA
1852 if (!ret) {
1853 iommu_mr->iommu_notify_flags = flags;
1854 }
1855 return ret;
5bf3d319
PX
1856}
1857
457f8cbb
BB
1858int memory_region_iommu_set_page_size_mask(IOMMUMemoryRegion *iommu_mr,
1859 uint64_t page_size_mask,
1860 Error **errp)
1861{
1862 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1863 int ret = 0;
1864
1865 if (imrc->iommu_set_page_size_mask) {
1866 ret = imrc->iommu_set_page_size_mask(iommu_mr, page_size_mask, errp);
1867 }
1868 return ret;
1869}
1870
549d4005
EA
1871int memory_region_register_iommu_notifier(MemoryRegion *mr,
1872 IOMMUNotifier *n, Error **errp)
06866575 1873{
3df9d748 1874 IOMMUMemoryRegion *iommu_mr;
549d4005 1875 int ret;
3df9d748 1876
efcd38c5 1877 if (mr->alias) {
549d4005 1878 return memory_region_register_iommu_notifier(mr->alias, n, errp);
efcd38c5
JW
1879 }
1880
cdb30812 1881 /* We need to register for at least one bitfield */
3df9d748 1882 iommu_mr = IOMMU_MEMORY_REGION(mr);
cdb30812 1883 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
698feb5e 1884 assert(n->start <= n->end);
cb1efcf4
PM
1885 assert(n->iommu_idx >= 0 &&
1886 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1887
3df9d748 1888 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
549d4005
EA
1889 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1890 if (ret) {
1891 QLIST_REMOVE(n, node);
1892 }
1893 return ret;
06866575
DG
1894}
1895
3df9d748 1896uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
a788f227 1897{
1221a474
AK
1898 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1899
1900 if (imrc->get_min_page_size) {
1901 return imrc->get_min_page_size(iommu_mr);
f682e9c2
AK
1902 }
1903 return TARGET_PAGE_SIZE;
1904}
1905
3df9d748 1906void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f682e9c2 1907{
3df9d748 1908 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1221a474 1909 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
f682e9c2 1910 hwaddr addr, granularity;
a788f227
DG
1911 IOMMUTLBEntry iotlb;
1912
faa362e3 1913 /* If the IOMMU has its own replay callback, override */
1221a474
AK
1914 if (imrc->replay) {
1915 imrc->replay(iommu_mr, n);
faa362e3
PX
1916 return;
1917 }
1918
3df9d748 1919 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
f682e9c2 1920
a788f227 1921 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
2c91bcf2 1922 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
a788f227
DG
1923 if (iotlb.perm != IOMMU_NONE) {
1924 n->notify(n, &iotlb);
1925 }
1926
1927 /* if (2^64 - MR size) < granularity, it's possible to get an
1928 * infinite loop here. This should catch such a wraparound */
1929 if ((addr + granularity) < addr) {
1930 break;
1931 }
1932 }
1933}
1934
cdb30812
PX
1935void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1936 IOMMUNotifier *n)
06866575 1937{
3df9d748
AK
1938 IOMMUMemoryRegion *iommu_mr;
1939
efcd38c5
JW
1940 if (mr->alias) {
1941 memory_region_unregister_iommu_notifier(mr->alias, n);
1942 return;
1943 }
cdb30812 1944 QLIST_REMOVE(n, node);
3df9d748 1945 iommu_mr = IOMMU_MEMORY_REGION(mr);
549d4005 1946 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
06866575
DG
1947}
1948
3b5ebf85 1949void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
5039caf3 1950 IOMMUTLBEvent *event)
06866575 1951{
5039caf3 1952 IOMMUTLBEntry *entry = &event->entry;
03c7140c 1953 hwaddr entry_end = entry->iova + entry->addr_mask;
1804857f 1954 IOMMUTLBEntry tmp = *entry;
cdb30812 1955
5039caf3
EP
1956 if (event->type == IOMMU_NOTIFIER_UNMAP) {
1957 assert(entry->perm == IOMMU_NONE);
1958 }
1959
bd2bfa4c
PX
1960 /*
1961 * Skip the notification if the notification does not overlap
1962 * with registered range.
1963 */
03c7140c 1964 if (notifier->start > entry_end || notifier->end < entry->iova) {
bd2bfa4c
PX
1965 return;
1966 }
cdb30812 1967
1804857f
EP
1968 if (notifier->notifier_flags & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) {
1969 /* Crop (iova, addr_mask) to range */
1970 tmp.iova = MAX(tmp.iova, notifier->start);
1971 tmp.addr_mask = MIN(entry_end, notifier->end) - tmp.iova;
1972 } else {
1973 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1974 }
03c7140c 1975
5039caf3 1976 if (event->type & notifier->notifier_flags) {
1804857f 1977 notifier->notify(notifier, &tmp);
bd2bfa4c
PX
1978 }
1979}
1980
3df9d748 1981void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
cb1efcf4 1982 int iommu_idx,
5039caf3 1983 IOMMUTLBEvent event)
bd2bfa4c
PX
1984{
1985 IOMMUNotifier *iommu_notifier;
1986
3df9d748 1987 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
bd2bfa4c 1988
3df9d748 1989 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
cb1efcf4 1990 if (iommu_notifier->iommu_idx == iommu_idx) {
5039caf3 1991 memory_region_notify_iommu_one(iommu_notifier, &event);
cb1efcf4 1992 }
cdb30812 1993 }
06866575
DG
1994}
1995
f1334de6
AK
1996int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1997 enum IOMMUMemoryRegionAttr attr,
1998 void *data)
1999{
2000 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2001
2002 if (!imrc->get_attr) {
2003 return -EINVAL;
2004 }
2005
2006 return imrc->get_attr(iommu_mr, attr, data);
2007}
2008
21f40209
PM
2009int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
2010 MemTxAttrs attrs)
2011{
2012 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2013
2014 if (!imrc->attrs_to_index) {
2015 return 0;
2016 }
2017
2018 return imrc->attrs_to_index(iommu_mr, attrs);
2019}
2020
2021int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2022{
2023 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2024
2025 if (!imrc->num_indexes) {
2026 return 1;
2027 }
2028
2029 return imrc->num_indexes(iommu_mr);
2030}
2031
093bc2cd
AK
2032void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2033{
5a583347 2034 uint8_t mask = 1 << client;
deb809ed 2035 uint8_t old_logging;
5a583347 2036
dbddac6d 2037 assert(client == DIRTY_MEMORY_VGA);
deb809ed
PB
2038 old_logging = mr->vga_logging_count;
2039 mr->vga_logging_count += log ? 1 : -1;
2040 if (!!old_logging == !!mr->vga_logging_count) {
2041 return;
2042 }
2043
59023ef4 2044 memory_region_transaction_begin();
5a583347 2045 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 2046 memory_region_update_pending |= mr->enabled;
59023ef4 2047 memory_region_transaction_commit();
093bc2cd
AK
2048}
2049
a8170e5e
AK
2050void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2051 hwaddr size)
093bc2cd 2052{
8e41fb63
FZ
2053 assert(mr->ram_block);
2054 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2055 size,
58d2707e 2056 memory_region_get_dirty_log_mask(mr));
093bc2cd
AK
2057}
2058
0fe1eca7 2059static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
093bc2cd 2060{
0a752eee 2061 MemoryListener *listener;
0d673e36 2062 AddressSpace *as;
0a752eee 2063 FlatView *view;
5a583347
AK
2064 FlatRange *fr;
2065
0a752eee
PB
2066 /* If the same address space has multiple log_sync listeners, we
2067 * visit that address space's FlatView multiple times. But because
2068 * log_sync listeners are rare, it's still cheaper than walking each
2069 * address space once.
2070 */
2071 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2072 if (!listener->log_sync) {
2073 continue;
2074 }
2075 as = listener->address_space;
2076 view = address_space_get_flatview(as);
99e86347 2077 FOR_EACH_FLAT_RANGE(fr, view) {
3ebb1817 2078 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
16620684 2079 MemoryRegionSection mrs = section_from_flat_range(fr, view);
0a752eee 2080 listener->log_sync(listener, &mrs);
0d673e36 2081 }
5a583347 2082 }
856d7245 2083 flatview_unref(view);
5a583347 2084 }
093bc2cd
AK
2085}
2086
077874e0
PX
2087void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2088 hwaddr len)
2089{
2090 MemoryRegionSection mrs;
2091 MemoryListener *listener;
2092 AddressSpace *as;
2093 FlatView *view;
2094 FlatRange *fr;
2095 hwaddr sec_start, sec_end, sec_size;
2096
2097 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2098 if (!listener->log_clear) {
2099 continue;
2100 }
2101 as = listener->address_space;
2102 view = address_space_get_flatview(as);
2103 FOR_EACH_FLAT_RANGE(fr, view) {
2104 if (!fr->dirty_log_mask || fr->mr != mr) {
2105 /*
2106 * Clear dirty bitmap operation only applies to those
2107 * regions whose dirty logging is at least enabled
2108 */
2109 continue;
2110 }
2111
2112 mrs = section_from_flat_range(fr, view);
2113
2114 sec_start = MAX(mrs.offset_within_region, start);
2115 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2116 sec_end = MIN(sec_end, start + len);
2117
2118 if (sec_start >= sec_end) {
2119 /*
2120 * If this memory region section has no intersection
2121 * with the requested range, skip.
2122 */
2123 continue;
2124 }
2125
2126 /* Valid case; shrink the section if needed */
2127 mrs.offset_within_address_space +=
2128 sec_start - mrs.offset_within_region;
2129 mrs.offset_within_region = sec_start;
2130 sec_size = sec_end - sec_start;
2131 mrs.size = int128_make64(sec_size);
2132 listener->log_clear(listener, &mrs);
2133 }
2134 flatview_unref(view);
2135 }
2136}
2137
0fe1eca7
PB
2138DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2139 hwaddr addr,
2140 hwaddr size,
2141 unsigned client)
2142{
9458a9a1 2143 DirtyBitmapSnapshot *snapshot;
0fe1eca7
PB
2144 assert(mr->ram_block);
2145 memory_region_sync_dirty_bitmap(mr);
9458a9a1
PB
2146 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2147 memory_global_after_dirty_log_sync();
2148 return snapshot;
0fe1eca7
PB
2149}
2150
2151bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2152 hwaddr addr, hwaddr size)
2153{
2154 assert(mr->ram_block);
2155 return cpu_physical_memory_snapshot_get_dirty(snap,
2156 memory_region_get_ram_addr(mr) + addr, size);
2157}
2158
093bc2cd
AK
2159void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2160{
fb1cd6f9 2161 if (mr->readonly != readonly) {
59023ef4 2162 memory_region_transaction_begin();
fb1cd6f9 2163 mr->readonly = readonly;
22bde714 2164 memory_region_update_pending |= mr->enabled;
59023ef4 2165 memory_region_transaction_commit();
fb1cd6f9 2166 }
093bc2cd
AK
2167}
2168
c26763f8
MAL
2169void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2170{
2171 if (mr->nonvolatile != nonvolatile) {
2172 memory_region_transaction_begin();
2173 mr->nonvolatile = nonvolatile;
2174 memory_region_update_pending |= mr->enabled;
2175 memory_region_transaction_commit();
2176 }
2177}
2178
5f9a5ea1 2179void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 2180{
5f9a5ea1 2181 if (mr->romd_mode != romd_mode) {
59023ef4 2182 memory_region_transaction_begin();
5f9a5ea1 2183 mr->romd_mode = romd_mode;
22bde714 2184 memory_region_update_pending |= mr->enabled;
59023ef4 2185 memory_region_transaction_commit();
d0a9b5bc
AK
2186 }
2187}
2188
a8170e5e
AK
2189void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2190 hwaddr size, unsigned client)
093bc2cd 2191{
8e41fb63
FZ
2192 assert(mr->ram_block);
2193 cpu_physical_memory_test_and_clear_dirty(
2194 memory_region_get_ram_addr(mr) + addr, size, client);
093bc2cd
AK
2195}
2196
a35ba7be
PB
2197int memory_region_get_fd(MemoryRegion *mr)
2198{
4ff87573
PB
2199 int fd;
2200
694ea274 2201 RCU_READ_LOCK_GUARD();
4ff87573
PB
2202 while (mr->alias) {
2203 mr = mr->alias;
a35ba7be 2204 }
4ff87573 2205 fd = mr->ram_block->fd;
a35ba7be 2206
4ff87573
PB
2207 return fd;
2208}
a35ba7be 2209
093bc2cd
AK
2210void *memory_region_get_ram_ptr(MemoryRegion *mr)
2211{
49b24afc
PB
2212 void *ptr;
2213 uint64_t offset = 0;
093bc2cd 2214
694ea274 2215 RCU_READ_LOCK_GUARD();
49b24afc
PB
2216 while (mr->alias) {
2217 offset += mr->alias_offset;
2218 mr = mr->alias;
2219 }
8e41fb63 2220 assert(mr->ram_block);
0878d0e1 2221 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
093bc2cd 2222
0878d0e1 2223 return ptr;
093bc2cd
AK
2224}
2225
07bdaa41
PB
2226MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2227{
2228 RAMBlock *block;
2229
2230 block = qemu_ram_block_from_host(ptr, false, offset);
2231 if (!block) {
2232 return NULL;
2233 }
2234
2235 return block->mr;
2236}
2237
7ebb2745
FZ
2238ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2239{
2240 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2241}
2242
37d7c084
PB
2243void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2244{
8e41fb63 2245 assert(mr->ram_block);
37d7c084 2246
fa53a0e5 2247 qemu_ram_resize(mr->ram_block, newsize, errp);
37d7c084
PB
2248}
2249
9ecc996a
PMD
2250void memory_region_msync(MemoryRegion *mr, hwaddr addr, hwaddr size)
2251{
2252 if (mr->ram_block) {
ab7e41e6 2253 qemu_ram_msync(mr->ram_block, addr, size);
9ecc996a
PMD
2254 }
2255}
61c490e2 2256
4dfe59d1 2257void memory_region_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size)
61c490e2
BM
2258{
2259 /*
2260 * Might be extended case needed to cover
2261 * different types of memory regions
2262 */
9ecc996a
PMD
2263 if (mr->dirty_log_mask) {
2264 memory_region_msync(mr, addr, size);
61c490e2
BM
2265 }
2266}
2267
b960fc17
PX
2268/*
2269 * Call proper memory listeners about the change on the newly
2270 * added/removed CoalescedMemoryRange.
2271 */
2272static void memory_region_update_coalesced_range(MemoryRegion *mr,
2273 CoalescedMemoryRange *cmr,
2274 bool add)
093bc2cd 2275{
b960fc17 2276 AddressSpace *as;
99e86347 2277 FlatView *view;
093bc2cd 2278 FlatRange *fr;
093bc2cd 2279
0d673e36 2280 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b960fc17
PX
2281 view = address_space_get_flatview(as);
2282 FOR_EACH_FLAT_RANGE(fr, view) {
2283 if (fr->mr == mr) {
2284 flat_range_coalesced_io_notify(fr, as, cmr, add);
2285 }
2286 }
2287 flatview_unref(view);
0d673e36
AK
2288 }
2289}
2290
093bc2cd
AK
2291void memory_region_set_coalescing(MemoryRegion *mr)
2292{
2293 memory_region_clear_coalescing(mr);
08dafab4 2294 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
2295}
2296
2297void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 2298 hwaddr offset,
093bc2cd
AK
2299 uint64_t size)
2300{
7267c094 2301 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 2302
08dafab4 2303 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd 2304 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
b960fc17 2305 memory_region_update_coalesced_range(mr, cmr, true);
d410515e 2306 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
2307}
2308
2309void memory_region_clear_coalescing(MemoryRegion *mr)
2310{
2311 CoalescedMemoryRange *cmr;
9c1aa1c2
PX
2312
2313 if (QTAILQ_EMPTY(&mr->coalesced)) {
2314 return;
2315 }
093bc2cd 2316
d410515e
JK
2317 qemu_flush_coalesced_mmio_buffer();
2318 mr->flush_coalesced_mmio = false;
2319
093bc2cd
AK
2320 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2321 cmr = QTAILQ_FIRST(&mr->coalesced);
2322 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
b960fc17 2323 memory_region_update_coalesced_range(mr, cmr, false);
7267c094 2324 g_free(cmr);
ab5b3db5 2325 }
093bc2cd
AK
2326}
2327
d410515e
JK
2328void memory_region_set_flush_coalesced(MemoryRegion *mr)
2329{
2330 mr->flush_coalesced_mmio = true;
2331}
2332
2333void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2334{
2335 qemu_flush_coalesced_mmio_buffer();
2336 if (QTAILQ_EMPTY(&mr->coalesced)) {
2337 mr->flush_coalesced_mmio = false;
2338 }
2339}
2340
8c56c1a5
PF
2341static bool userspace_eventfd_warning;
2342
3e9d69e7 2343void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 2344 hwaddr addr,
3e9d69e7
AK
2345 unsigned size,
2346 bool match_data,
2347 uint64_t data,
753d5e14 2348 EventNotifier *e)
3e9d69e7
AK
2349{
2350 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2351 .addr.start = int128_make64(addr),
2352 .addr.size = int128_make64(size),
3e9d69e7
AK
2353 .match_data = match_data,
2354 .data = data,
753d5e14 2355 .e = e,
3e9d69e7
AK
2356 };
2357 unsigned i;
2358
8c56c1a5
PF
2359 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2360 userspace_eventfd_warning))) {
2361 userspace_eventfd_warning = true;
2362 error_report("Using eventfd without MMIO binding in KVM. "
2363 "Suboptimal performance expected");
2364 }
2365
b8aecea2 2366 if (size) {
9bf825bf 2367 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
b8aecea2 2368 }
59023ef4 2369 memory_region_transaction_begin();
3e9d69e7 2370 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2371 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2372 break;
2373 }
2374 }
2375 ++mr->ioeventfd_nb;
7267c094 2376 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
2377 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2378 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2379 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2380 mr->ioeventfds[i] = mrfd;
4dc56152 2381 ioeventfd_update_pending |= mr->enabled;
59023ef4 2382 memory_region_transaction_commit();
3e9d69e7
AK
2383}
2384
2385void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 2386 hwaddr addr,
3e9d69e7
AK
2387 unsigned size,
2388 bool match_data,
2389 uint64_t data,
753d5e14 2390 EventNotifier *e)
3e9d69e7
AK
2391{
2392 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
2393 .addr.start = int128_make64(addr),
2394 .addr.size = int128_make64(size),
3e9d69e7
AK
2395 .match_data = match_data,
2396 .data = data,
753d5e14 2397 .e = e,
3e9d69e7
AK
2398 };
2399 unsigned i;
2400
b8aecea2 2401 if (size) {
9bf825bf 2402 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
b8aecea2 2403 }
59023ef4 2404 memory_region_transaction_begin();
3e9d69e7 2405 for (i = 0; i < mr->ioeventfd_nb; ++i) {
73bb753d 2406 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
3e9d69e7
AK
2407 break;
2408 }
2409 }
2410 assert(i != mr->ioeventfd_nb);
2411 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2412 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2413 --mr->ioeventfd_nb;
7267c094 2414 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 2415 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
4dc56152 2416 ioeventfd_update_pending |= mr->enabled;
59023ef4 2417 memory_region_transaction_commit();
3e9d69e7
AK
2418}
2419
feca4ac1 2420static void memory_region_update_container_subregions(MemoryRegion *subregion)
093bc2cd 2421{
feca4ac1 2422 MemoryRegion *mr = subregion->container;
093bc2cd
AK
2423 MemoryRegion *other;
2424
59023ef4
JK
2425 memory_region_transaction_begin();
2426
dfde4e6e 2427 memory_region_ref(subregion);
093bc2cd
AK
2428 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2429 if (subregion->priority >= other->priority) {
2430 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2431 goto done;
2432 }
2433 }
2434 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2435done:
22bde714 2436 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2437 memory_region_transaction_commit();
093bc2cd
AK
2438}
2439
0598701a
PC
2440static void memory_region_add_subregion_common(MemoryRegion *mr,
2441 hwaddr offset,
2442 MemoryRegion *subregion)
2443{
feca4ac1
PB
2444 assert(!subregion->container);
2445 subregion->container = mr;
0598701a 2446 subregion->addr = offset;
feca4ac1 2447 memory_region_update_container_subregions(subregion);
0598701a 2448}
093bc2cd
AK
2449
2450void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 2451 hwaddr offset,
093bc2cd
AK
2452 MemoryRegion *subregion)
2453{
093bc2cd
AK
2454 subregion->priority = 0;
2455 memory_region_add_subregion_common(mr, offset, subregion);
2456}
2457
2458void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 2459 hwaddr offset,
093bc2cd 2460 MemoryRegion *subregion,
a1ff8ae0 2461 int priority)
093bc2cd 2462{
093bc2cd
AK
2463 subregion->priority = priority;
2464 memory_region_add_subregion_common(mr, offset, subregion);
2465}
2466
2467void memory_region_del_subregion(MemoryRegion *mr,
2468 MemoryRegion *subregion)
2469{
59023ef4 2470 memory_region_transaction_begin();
feca4ac1
PB
2471 assert(subregion->container == mr);
2472 subregion->container = NULL;
093bc2cd 2473 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
dfde4e6e 2474 memory_region_unref(subregion);
22bde714 2475 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 2476 memory_region_transaction_commit();
6bba19ba
AK
2477}
2478
2479void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2480{
2481 if (enabled == mr->enabled) {
2482 return;
2483 }
59023ef4 2484 memory_region_transaction_begin();
6bba19ba 2485 mr->enabled = enabled;
22bde714 2486 memory_region_update_pending = true;
59023ef4 2487 memory_region_transaction_commit();
093bc2cd 2488}
1c0ffa58 2489
e7af4c67
MT
2490void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2491{
2492 Int128 s = int128_make64(size);
2493
2494 if (size == UINT64_MAX) {
2495 s = int128_2_64();
2496 }
2497 if (int128_eq(s, mr->size)) {
2498 return;
2499 }
2500 memory_region_transaction_begin();
2501 mr->size = s;
2502 memory_region_update_pending = true;
2503 memory_region_transaction_commit();
2504}
2505
67891b8a 2506static void memory_region_readd_subregion(MemoryRegion *mr)
2282e1af 2507{
feca4ac1 2508 MemoryRegion *container = mr->container;
2282e1af 2509
feca4ac1 2510 if (container) {
67891b8a
PC
2511 memory_region_transaction_begin();
2512 memory_region_ref(mr);
feca4ac1
PB
2513 memory_region_del_subregion(container, mr);
2514 mr->container = container;
2515 memory_region_update_container_subregions(mr);
67891b8a
PC
2516 memory_region_unref(mr);
2517 memory_region_transaction_commit();
2282e1af 2518 }
67891b8a 2519}
2282e1af 2520
67891b8a
PC
2521void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2522{
2523 if (addr != mr->addr) {
2524 mr->addr = addr;
2525 memory_region_readd_subregion(mr);
2526 }
2282e1af
AK
2527}
2528
a8170e5e 2529void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 2530{
4703359e 2531 assert(mr->alias);
4703359e 2532
59023ef4 2533 if (offset == mr->alias_offset) {
4703359e
AK
2534 return;
2535 }
2536
59023ef4
JK
2537 memory_region_transaction_begin();
2538 mr->alias_offset = offset;
22bde714 2539 memory_region_update_pending |= mr->enabled;
59023ef4 2540 memory_region_transaction_commit();
4703359e
AK
2541}
2542
a2b257d6
IM
2543uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2544{
2545 return mr->align;
2546}
2547
e2177955
AK
2548static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2549{
2550 const AddrRange *addr = addr_;
2551 const FlatRange *fr = fr_;
2552
2553 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2554 return -1;
2555 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2556 return 1;
2557 }
2558 return 0;
2559}
2560
99e86347 2561static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
e2177955 2562{
99e86347 2563 return bsearch(&addr, view->ranges, view->nr,
e2177955
AK
2564 sizeof(FlatRange), cmp_flatrange_addr);
2565}
2566
eed2bacf
IM
2567bool memory_region_is_mapped(MemoryRegion *mr)
2568{
2569 return mr->container ? true : false;
2570}
2571
c6742b14
PB
2572/* Same as memory_region_find, but it does not add a reference to the
2573 * returned region. It must be called from an RCU critical section.
2574 */
2575static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2576 hwaddr addr, uint64_t size)
e2177955 2577{
052e87b0 2578 MemoryRegionSection ret = { .mr = NULL };
73034e9e
PB
2579 MemoryRegion *root;
2580 AddressSpace *as;
2581 AddrRange range;
99e86347 2582 FlatView *view;
73034e9e
PB
2583 FlatRange *fr;
2584
2585 addr += mr->addr;
feca4ac1
PB
2586 for (root = mr; root->container; ) {
2587 root = root->container;
73034e9e
PB
2588 addr += root->addr;
2589 }
e2177955 2590
73034e9e 2591 as = memory_region_to_address_space(root);
eed2bacf
IM
2592 if (!as) {
2593 return ret;
2594 }
73034e9e 2595 range = addrrange_make(int128_make64(addr), int128_make64(size));
99e86347 2596
16620684 2597 view = address_space_to_flatview(as);
99e86347 2598 fr = flatview_lookup(view, range);
e2177955 2599 if (!fr) {
c6742b14 2600 return ret;
e2177955
AK
2601 }
2602
99e86347 2603 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
e2177955
AK
2604 --fr;
2605 }
2606
2607 ret.mr = fr->mr;
16620684 2608 ret.fv = view;
e2177955
AK
2609 range = addrrange_intersection(range, fr->addr);
2610 ret.offset_within_region = fr->offset_in_region;
2611 ret.offset_within_region += int128_get64(int128_sub(range.start,
2612 fr->addr.start));
052e87b0 2613 ret.size = range.size;
e2177955 2614 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 2615 ret.readonly = fr->readonly;
c26763f8 2616 ret.nonvolatile = fr->nonvolatile;
c6742b14
PB
2617 return ret;
2618}
2619
2620MemoryRegionSection memory_region_find(MemoryRegion *mr,
2621 hwaddr addr, uint64_t size)
2622{
2623 MemoryRegionSection ret;
694ea274 2624 RCU_READ_LOCK_GUARD();
c6742b14
PB
2625 ret = memory_region_find_rcu(mr, addr, size);
2626 if (ret.mr) {
2627 memory_region_ref(ret.mr);
2628 }
e2177955
AK
2629 return ret;
2630}
2631
c6742b14
PB
2632bool memory_region_present(MemoryRegion *container, hwaddr addr)
2633{
2634 MemoryRegion *mr;
2635
694ea274 2636 RCU_READ_LOCK_GUARD();
c6742b14 2637 mr = memory_region_find_rcu(container, addr, 1).mr;
c6742b14
PB
2638 return mr && mr != container;
2639}
2640
9c1f8f44 2641void memory_global_dirty_log_sync(void)
86e775c6 2642{
3ebb1817 2643 memory_region_sync_dirty_bitmap(NULL);
7664e80c
AK
2644}
2645
9458a9a1
PB
2646void memory_global_after_dirty_log_sync(void)
2647{
2648 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2649}
2650
19310760
JZ
2651static VMChangeStateEntry *vmstate_change;
2652
7664e80c
AK
2653void memory_global_dirty_log_start(void)
2654{
19310760
JZ
2655 if (vmstate_change) {
2656 qemu_del_vm_change_state_handler(vmstate_change);
2657 vmstate_change = NULL;
2658 }
2659
7664e80c 2660 global_dirty_log = true;
6f6a5ef3 2661
7376e582 2662 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
6f6a5ef3 2663
39adb536 2664 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2665 memory_region_transaction_begin();
2666 memory_region_update_pending = true;
2667 memory_region_transaction_commit();
7664e80c
AK
2668}
2669
19310760 2670static void memory_global_dirty_log_do_stop(void)
7664e80c 2671{
7664e80c 2672 global_dirty_log = false;
6f6a5ef3 2673
39adb536 2674 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
6f6a5ef3
PB
2675 memory_region_transaction_begin();
2676 memory_region_update_pending = true;
2677 memory_region_transaction_commit();
2678
7376e582 2679 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
2680}
2681
19310760
JZ
2682static void memory_vm_change_state_handler(void *opaque, int running,
2683 RunState state)
2684{
2685 if (running) {
2686 memory_global_dirty_log_do_stop();
2687
2688 if (vmstate_change) {
2689 qemu_del_vm_change_state_handler(vmstate_change);
2690 vmstate_change = NULL;
2691 }
2692 }
2693}
2694
2695void memory_global_dirty_log_stop(void)
2696{
2697 if (!runstate_is_running()) {
2698 if (vmstate_change) {
2699 return;
2700 }
2701 vmstate_change = qemu_add_vm_change_state_handler(
2702 memory_vm_change_state_handler, NULL);
2703 return;
2704 }
2705
2706 memory_global_dirty_log_do_stop();
2707}
2708
7664e80c
AK
2709static void listener_add_address_space(MemoryListener *listener,
2710 AddressSpace *as)
2711{
99e86347 2712 FlatView *view;
7664e80c
AK
2713 FlatRange *fr;
2714
680a4783
PB
2715 if (listener->begin) {
2716 listener->begin(listener);
2717 }
7664e80c 2718 if (global_dirty_log) {
975aefe0
AK
2719 if (listener->log_global_start) {
2720 listener->log_global_start(listener);
2721 }
7664e80c 2722 }
975aefe0 2723
856d7245 2724 view = address_space_get_flatview(as);
99e86347 2725 FOR_EACH_FLAT_RANGE(fr, view) {
279836f8
DH
2726 MemoryRegionSection section = section_from_flat_range(fr, view);
2727
975aefe0
AK
2728 if (listener->region_add) {
2729 listener->region_add(listener, &section);
2730 }
ae990e6c
DH
2731 if (fr->dirty_log_mask && listener->log_start) {
2732 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2733 }
7664e80c 2734 }
680a4783
PB
2735 if (listener->commit) {
2736 listener->commit(listener);
2737 }
856d7245 2738 flatview_unref(view);
7664e80c
AK
2739}
2740
d25836ca
PX
2741static void listener_del_address_space(MemoryListener *listener,
2742 AddressSpace *as)
2743{
2744 FlatView *view;
2745 FlatRange *fr;
2746
2747 if (listener->begin) {
2748 listener->begin(listener);
2749 }
2750 view = address_space_get_flatview(as);
2751 FOR_EACH_FLAT_RANGE(fr, view) {
2752 MemoryRegionSection section = section_from_flat_range(fr, view);
2753
2754 if (fr->dirty_log_mask && listener->log_stop) {
2755 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2756 }
2757 if (listener->region_del) {
2758 listener->region_del(listener, &section);
2759 }
2760 }
2761 if (listener->commit) {
2762 listener->commit(listener);
2763 }
2764 flatview_unref(view);
2765}
2766
d45fa784 2767void memory_listener_register(MemoryListener *listener, AddressSpace *as)
7664e80c 2768{
72e22d2f
AK
2769 MemoryListener *other = NULL;
2770
d45fa784 2771 listener->address_space = as;
72e22d2f 2772 if (QTAILQ_EMPTY(&memory_listeners)
eae3eb3e 2773 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
72e22d2f
AK
2774 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2775 } else {
2776 QTAILQ_FOREACH(other, &memory_listeners, link) {
2777 if (listener->priority < other->priority) {
2778 break;
2779 }
2780 }
2781 QTAILQ_INSERT_BEFORE(other, listener, link);
2782 }
0d673e36 2783
9a54635d 2784 if (QTAILQ_EMPTY(&as->listeners)
eae3eb3e 2785 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
9a54635d
PB
2786 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2787 } else {
2788 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2789 if (listener->priority < other->priority) {
2790 break;
2791 }
2792 }
2793 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2794 }
2795
d45fa784 2796 listener_add_address_space(listener, as);
7664e80c
AK
2797}
2798
2799void memory_listener_unregister(MemoryListener *listener)
2800{
1d8280c1
PB
2801 if (!listener->address_space) {
2802 return;
2803 }
2804
d25836ca 2805 listener_del_address_space(listener, listener->address_space);
72e22d2f 2806 QTAILQ_REMOVE(&memory_listeners, listener, link);
9a54635d 2807 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
1d8280c1 2808 listener->address_space = NULL;
86e775c6 2809}
e2177955 2810
a2166410
GK
2811void address_space_remove_listeners(AddressSpace *as)
2812{
2813 while (!QTAILQ_EMPTY(&as->listeners)) {
2814 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2815 }
2816}
2817
7dca8043 2818void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1c0ffa58 2819{
ac95190e 2820 memory_region_ref(root);
8786db7c 2821 as->root = root;
67ace39b 2822 as->current_map = NULL;
4c19eb72
AK
2823 as->ioeventfd_nb = 0;
2824 as->ioeventfds = NULL;
9a54635d 2825 QTAILQ_INIT(&as->listeners);
0d673e36 2826 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
7dca8043 2827 as->name = g_strdup(name ? name : "anonymous");
202fc01b
AK
2828 address_space_update_topology(as);
2829 address_space_update_ioeventfds(as);
1c0ffa58 2830}
658b2224 2831
374f2981 2832static void do_address_space_destroy(AddressSpace *as)
83f3c251 2833{
9a54635d 2834 assert(QTAILQ_EMPTY(&as->listeners));
078c44f4 2835
856d7245 2836 flatview_unref(as->current_map);
7dca8043 2837 g_free(as->name);
4c19eb72 2838 g_free(as->ioeventfds);
ac95190e 2839 memory_region_unref(as->root);
83f3c251
AK
2840}
2841
374f2981
PB
2842void address_space_destroy(AddressSpace *as)
2843{
ac95190e
PB
2844 MemoryRegion *root = as->root;
2845
374f2981
PB
2846 /* Flush out anything from MemoryListeners listening in on this */
2847 memory_region_transaction_begin();
2848 as->root = NULL;
2849 memory_region_transaction_commit();
2850 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2851
2852 /* At this point, as->dispatch and as->current_map are dummy
2853 * entries that the guest should never use. Wait for the old
2854 * values to expire before freeing the data.
2855 */
ac95190e 2856 as->root = root;
374f2981
PB
2857 call_rcu(as, do_address_space_destroy, rcu);
2858}
2859
4e831901
PX
2860static const char *memory_region_type(MemoryRegion *mr)
2861{
39fa93c4
PMD
2862 if (mr->alias) {
2863 return memory_region_type(mr->alias);
2864 }
4e831901
PX
2865 if (memory_region_is_ram_device(mr)) {
2866 return "ramd";
2867 } else if (memory_region_is_romd(mr)) {
2868 return "romd";
2869 } else if (memory_region_is_rom(mr)) {
2870 return "rom";
2871 } else if (memory_region_is_ram(mr)) {
2872 return "ram";
2873 } else {
2874 return "i/o";
2875 }
2876}
2877
314e2987
BS
2878typedef struct MemoryRegionList MemoryRegionList;
2879
2880struct MemoryRegionList {
2881 const MemoryRegion *mr;
a16878d2 2882 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
314e2987
BS
2883};
2884
b58deb34 2885typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
314e2987 2886
4e831901
PX
2887#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2888 int128_sub((size), int128_one())) : 0)
2889#define MTREE_INDENT " "
2890
b6b71cb5 2891static void mtree_expand_owner(const char *label, Object *obj)
fc051ae6
AK
2892{
2893 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2894
b6b71cb5 2895 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
fc051ae6 2896 if (dev && dev->id) {
b6b71cb5 2897 qemu_printf(" id=%s", dev->id);
fc051ae6 2898 } else {
ddfb0baa 2899 char *canonical_path = object_get_canonical_path(obj);
fc051ae6 2900 if (canonical_path) {
b6b71cb5 2901 qemu_printf(" path=%s", canonical_path);
fc051ae6
AK
2902 g_free(canonical_path);
2903 } else {
b6b71cb5 2904 qemu_printf(" type=%s", object_get_typename(obj));
fc051ae6
AK
2905 }
2906 }
b6b71cb5 2907 qemu_printf("}");
fc051ae6
AK
2908}
2909
b6b71cb5 2910static void mtree_print_mr_owner(const MemoryRegion *mr)
fc051ae6
AK
2911{
2912 Object *owner = mr->owner;
2913 Object *parent = memory_region_owner((MemoryRegion *)mr);
2914
2915 if (!owner && !parent) {
b6b71cb5 2916 qemu_printf(" orphan");
fc051ae6
AK
2917 return;
2918 }
2919 if (owner) {
b6b71cb5 2920 mtree_expand_owner("owner", owner);
fc051ae6
AK
2921 }
2922 if (parent && parent != owner) {
b6b71cb5 2923 mtree_expand_owner("parent", parent);
fc051ae6
AK
2924 }
2925}
2926
b6b71cb5 2927static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
a8170e5e 2928 hwaddr base,
fc051ae6 2929 MemoryRegionListHead *alias_print_queue,
2261d393 2930 bool owner, bool display_disabled)
314e2987 2931{
9479c57a
JK
2932 MemoryRegionList *new_ml, *ml, *next_ml;
2933 MemoryRegionListHead submr_print_queue;
314e2987
BS
2934 const MemoryRegion *submr;
2935 unsigned int i;
b31f8412 2936 hwaddr cur_start, cur_end;
314e2987 2937
f8a9f720 2938 if (!mr) {
314e2987
BS
2939 return;
2940 }
2941
b31f8412
PX
2942 cur_start = base + mr->addr;
2943 cur_end = cur_start + MR_SIZE(mr->size);
2944
2945 /*
2946 * Try to detect overflow of memory region. This should never
2947 * happen normally. When it happens, we dump something to warn the
2948 * user who is observing this.
2949 */
2950 if (cur_start < base || cur_end < cur_start) {
b6b71cb5 2951 qemu_printf("[DETECTED OVERFLOW!] ");
b31f8412
PX
2952 }
2953
314e2987
BS
2954 if (mr->alias) {
2955 MemoryRegionList *ml;
2956 bool found = false;
2957
2958 /* check if the alias is already in the queue */
a16878d2 2959 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
f54bb15f 2960 if (ml->mr == mr->alias) {
314e2987
BS
2961 found = true;
2962 }
2963 }
2964
2965 if (!found) {
2966 ml = g_new(MemoryRegionList, 1);
2967 ml->mr = mr->alias;
a16878d2 2968 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
314e2987 2969 }
2261d393
PMD
2970 if (mr->enabled || display_disabled) {
2971 for (i = 0; i < level; i++) {
2972 qemu_printf(MTREE_INDENT);
2973 }
2974 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2975 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2976 "-" TARGET_FMT_plx "%s",
2977 cur_start, cur_end,
2978 mr->priority,
2979 mr->nonvolatile ? "nv-" : "",
2980 memory_region_type((MemoryRegion *)mr),
2981 memory_region_name(mr),
2982 memory_region_name(mr->alias),
2983 mr->alias_offset,
2984 mr->alias_offset + MR_SIZE(mr->size),
2985 mr->enabled ? "" : " [disabled]");
2986 if (owner) {
2987 mtree_print_mr_owner(mr);
2988 }
2989 qemu_printf("\n");
fc051ae6 2990 }
314e2987 2991 } else {
2261d393
PMD
2992 if (mr->enabled || display_disabled) {
2993 for (i = 0; i < level; i++) {
2994 qemu_printf(MTREE_INDENT);
2995 }
2996 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2997 " (prio %d, %s%s): %s%s",
2998 cur_start, cur_end,
2999 mr->priority,
3000 mr->nonvolatile ? "nv-" : "",
3001 memory_region_type((MemoryRegion *)mr),
3002 memory_region_name(mr),
3003 mr->enabled ? "" : " [disabled]");
3004 if (owner) {
3005 mtree_print_mr_owner(mr);
3006 }
3007 qemu_printf("\n");
fc051ae6 3008 }
314e2987 3009 }
9479c57a
JK
3010
3011 QTAILQ_INIT(&submr_print_queue);
3012
314e2987 3013 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
3014 new_ml = g_new(MemoryRegionList, 1);
3015 new_ml->mr = submr;
a16878d2 3016 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
9479c57a
JK
3017 if (new_ml->mr->addr < ml->mr->addr ||
3018 (new_ml->mr->addr == ml->mr->addr &&
3019 new_ml->mr->priority > ml->mr->priority)) {
a16878d2 3020 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
9479c57a
JK
3021 new_ml = NULL;
3022 break;
3023 }
3024 }
3025 if (new_ml) {
a16878d2 3026 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
9479c57a
JK
3027 }
3028 }
3029
a16878d2 3030 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
b6b71cb5 3031 mtree_print_mr(ml->mr, level + 1, cur_start,
2261d393 3032 alias_print_queue, owner, display_disabled);
9479c57a
JK
3033 }
3034
a16878d2 3035 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
9479c57a 3036 g_free(ml);
314e2987
BS
3037 }
3038}
3039
5e8fd947 3040struct FlatViewInfo {
5e8fd947
AK
3041 int counter;
3042 bool dispatch_tree;
fc051ae6 3043 bool owner;
8072aae3 3044 AccelClass *ac;
5e8fd947
AK
3045};
3046
3047static void mtree_print_flatview(gpointer key, gpointer value,
3048 gpointer user_data)
57bb40c9 3049{
5e8fd947
AK
3050 FlatView *view = key;
3051 GArray *fv_address_spaces = value;
3052 struct FlatViewInfo *fvi = user_data;
57bb40c9
PX
3053 FlatRange *range = &view->ranges[0];
3054 MemoryRegion *mr;
3055 int n = view->nr;
5e8fd947
AK
3056 int i;
3057 AddressSpace *as;
3058
b6b71cb5 3059 qemu_printf("FlatView #%d\n", fvi->counter);
5e8fd947
AK
3060 ++fvi->counter;
3061
3062 for (i = 0; i < fv_address_spaces->len; ++i) {
3063 as = g_array_index(fv_address_spaces, AddressSpace*, i);
b6b71cb5
MA
3064 qemu_printf(" AS \"%s\", root: %s",
3065 as->name, memory_region_name(as->root));
5e8fd947 3066 if (as->root->alias) {
b6b71cb5 3067 qemu_printf(", alias %s", memory_region_name(as->root->alias));
5e8fd947 3068 }
b6b71cb5 3069 qemu_printf("\n");
5e8fd947
AK
3070 }
3071
b6b71cb5 3072 qemu_printf(" Root memory region: %s\n",
5e8fd947 3073 view->root ? memory_region_name(view->root) : "(none)");
57bb40c9
PX
3074
3075 if (n <= 0) {
b6b71cb5 3076 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
57bb40c9
PX
3077 return;
3078 }
3079
3080 while (n--) {
3081 mr = range->mr;
377a07aa 3082 if (range->offset_in_region) {
b6b71cb5
MA
3083 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3084 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3085 int128_get64(range->addr.start),
3086 int128_get64(range->addr.start)
3087 + MR_SIZE(range->addr.size),
3088 mr->priority,
3089 range->nonvolatile ? "nv-" : "",
3090 range->readonly ? "rom" : memory_region_type(mr),
3091 memory_region_name(mr),
3092 range->offset_in_region);
377a07aa 3093 } else {
b6b71cb5
MA
3094 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3095 " (prio %d, %s%s): %s",
3096 int128_get64(range->addr.start),
3097 int128_get64(range->addr.start)
3098 + MR_SIZE(range->addr.size),
3099 mr->priority,
3100 range->nonvolatile ? "nv-" : "",
3101 range->readonly ? "rom" : memory_region_type(mr),
3102 memory_region_name(mr));
377a07aa 3103 }
fc051ae6 3104 if (fvi->owner) {
b6b71cb5 3105 mtree_print_mr_owner(mr);
fc051ae6 3106 }
8072aae3
AK
3107
3108 if (fvi->ac) {
3109 for (i = 0; i < fv_address_spaces->len; ++i) {
3110 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3111 if (fvi->ac->has_memory(current_machine, as,
3112 int128_get64(range->addr.start),
3113 MR_SIZE(range->addr.size) + 1)) {
53b62bec 3114 qemu_printf(" %s", fvi->ac->name);
8072aae3
AK
3115 }
3116 }
3117 }
b6b71cb5 3118 qemu_printf("\n");
57bb40c9
PX
3119 range++;
3120 }
3121
5e8fd947
AK
3122#if !defined(CONFIG_USER_ONLY)
3123 if (fvi->dispatch_tree && view->root) {
b6b71cb5 3124 mtree_print_dispatch(view->dispatch, view->root);
5e8fd947
AK
3125 }
3126#endif
3127
b6b71cb5 3128 qemu_printf("\n");
5e8fd947
AK
3129}
3130
3131static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3132 gpointer user_data)
3133{
3134 FlatView *view = key;
3135 GArray *fv_address_spaces = value;
3136
3137 g_array_unref(fv_address_spaces);
57bb40c9 3138 flatview_unref(view);
5e8fd947
AK
3139
3140 return true;
57bb40c9
PX
3141}
3142
2261d393 3143void mtree_info(bool flatview, bool dispatch_tree, bool owner, bool disabled)
314e2987
BS
3144{
3145 MemoryRegionListHead ml_head;
3146 MemoryRegionList *ml, *ml2;
0d673e36 3147 AddressSpace *as;
314e2987 3148
57bb40c9 3149 if (flatview) {
5e8fd947
AK
3150 FlatView *view;
3151 struct FlatViewInfo fvi = {
5e8fd947 3152 .counter = 0,
fc051ae6
AK
3153 .dispatch_tree = dispatch_tree,
3154 .owner = owner,
5e8fd947
AK
3155 };
3156 GArray *fv_address_spaces;
3157 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
4f7f5893 3158 AccelClass *ac = ACCEL_GET_CLASS(current_accel());
8072aae3
AK
3159
3160 if (ac->has_memory) {
3161 fvi.ac = ac;
8072aae3 3162 }
5e8fd947
AK
3163
3164 /* Gather all FVs in one table */
57bb40c9 3165 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
5e8fd947
AK
3166 view = address_space_get_flatview(as);
3167
3168 fv_address_spaces = g_hash_table_lookup(views, view);
3169 if (!fv_address_spaces) {
3170 fv_address_spaces = g_array_new(false, false, sizeof(as));
3171 g_hash_table_insert(views, view, fv_address_spaces);
3172 }
3173
3174 g_array_append_val(fv_address_spaces, as);
57bb40c9 3175 }
5e8fd947
AK
3176
3177 /* Print */
3178 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3179
3180 /* Free */
3181 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3182 g_hash_table_unref(views);
3183
57bb40c9
PX
3184 return;
3185 }
3186
314e2987
BS
3187 QTAILQ_INIT(&ml_head);
3188
0d673e36 3189 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
b6b71cb5 3190 qemu_printf("address-space: %s\n", as->name);
2261d393 3191 mtree_print_mr(as->root, 1, 0, &ml_head, owner, disabled);
b6b71cb5 3192 qemu_printf("\n");
b9f9be88
BS
3193 }
3194
314e2987 3195 /* print aliased regions */
a16878d2 3196 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
b6b71cb5 3197 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
2261d393 3198 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner, disabled);
b6b71cb5 3199 qemu_printf("\n");
314e2987
BS
3200 }
3201
a16878d2 3202 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
88365e47 3203 g_free(ml);
314e2987 3204 }
314e2987 3205}
b4fefef9 3206
b08199c6
PM
3207void memory_region_init_ram(MemoryRegion *mr,
3208 struct Object *owner,
3209 const char *name,
3210 uint64_t size,
3211 Error **errp)
3212{
3213 DeviceState *owner_dev;
3214 Error *err = NULL;
3215
3216 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3217 if (err) {
3218 error_propagate(errp, err);
3219 return;
3220 }
3221 /* This will assert if owner is neither NULL nor a DeviceState.
3222 * We only want the owner here for the purposes of defining a
3223 * unique name for migration. TODO: Ideally we should implement
3224 * a naming scheme for Objects which are not DeviceStates, in
3225 * which case we can relax this restriction.
3226 */
3227 owner_dev = DEVICE(owner);
3228 vmstate_register_ram(mr, owner_dev);
3229}
3230
3231void memory_region_init_rom(MemoryRegion *mr,
3232 struct Object *owner,
3233 const char *name,
3234 uint64_t size,
3235 Error **errp)
3236{
3237 DeviceState *owner_dev;
3238 Error *err = NULL;
3239
3240 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3241 if (err) {
3242 error_propagate(errp, err);
3243 return;
3244 }
3245 /* This will assert if owner is neither NULL nor a DeviceState.
3246 * We only want the owner here for the purposes of defining a
3247 * unique name for migration. TODO: Ideally we should implement
3248 * a naming scheme for Objects which are not DeviceStates, in
3249 * which case we can relax this restriction.
3250 */
3251 owner_dev = DEVICE(owner);
3252 vmstate_register_ram(mr, owner_dev);
3253}
3254
3255void memory_region_init_rom_device(MemoryRegion *mr,
3256 struct Object *owner,
3257 const MemoryRegionOps *ops,
3258 void *opaque,
3259 const char *name,
3260 uint64_t size,
3261 Error **errp)
3262{
3263 DeviceState *owner_dev;
3264 Error *err = NULL;
3265
3266 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3267 name, size, &err);
3268 if (err) {
3269 error_propagate(errp, err);
3270 return;
3271 }
3272 /* This will assert if owner is neither NULL nor a DeviceState.
3273 * We only want the owner here for the purposes of defining a
3274 * unique name for migration. TODO: Ideally we should implement
3275 * a naming scheme for Objects which are not DeviceStates, in
3276 * which case we can relax this restriction.
3277 */
3278 owner_dev = DEVICE(owner);
3279 vmstate_register_ram(mr, owner_dev);
3280}
3281
e7d3222e
AB
3282/*
3283 * Support softmmu builds with CONFIG_FUZZ using a weak symbol and a stub for
3284 * the fuzz_dma_read_cb callback
3285 */
3286#ifdef CONFIG_FUZZ
3287void __attribute__((weak)) fuzz_dma_read_cb(size_t addr,
3288 size_t len,
fc1c8344 3289 MemoryRegion *mr)
e7d3222e
AB
3290{
3291}
3292#endif
3293
b4fefef9
PC
3294static const TypeInfo memory_region_info = {
3295 .parent = TYPE_OBJECT,
3296 .name = TYPE_MEMORY_REGION,
1b53ecd9 3297 .class_size = sizeof(MemoryRegionClass),
b4fefef9
PC
3298 .instance_size = sizeof(MemoryRegion),
3299 .instance_init = memory_region_initfn,
3300 .instance_finalize = memory_region_finalize,
3301};
3302
3df9d748
AK
3303static const TypeInfo iommu_memory_region_info = {
3304 .parent = TYPE_MEMORY_REGION,
3305 .name = TYPE_IOMMU_MEMORY_REGION,
1221a474 3306 .class_size = sizeof(IOMMUMemoryRegionClass),
3df9d748
AK
3307 .instance_size = sizeof(IOMMUMemoryRegion),
3308 .instance_init = iommu_memory_region_initfn,
1221a474 3309 .abstract = true,
3df9d748
AK
3310};
3311
b4fefef9
PC
3312static void memory_register_types(void)
3313{
3314 type_register_static(&memory_region_info);
3df9d748 3315 type_register_static(&iommu_memory_region_info);
b4fefef9
PC
3316}
3317
3318type_init(memory_register_types)