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target-i386: cpu_x86_register() consolidate freeing resources
[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
c6dc6f63 26
1de7afc9
PB		 27#include "qemu/option.h"
28#include "qemu/config-file.h"
7b1b5d19 29#include "qapi/qmp/qerror.h"
c6dc6f63 30
7b1b5d19 31#include "qapi/visitor.h"
9c17d615 32#include "sysemu/arch_init.h"
71ad61d3 33
28f52cc0
VR		 34#include "hyperv.h"
35
65dee380 36#include "hw/hw.h"
b834b508 37#if defined(CONFIG_KVM)
ef8621b1 38#include <linux/kvm_para.h>
b834b508 39#endif
65dee380 40
9c17d615 41#include "sysemu/sysemu.h"
bdeec802
IM		 42#ifndef CONFIG_USER_ONLY
43#include "hw/xen.h"
44#include "hw/sysbus.h"
449994eb 45#include "hw/apic_internal.h"
bdeec802
IM		 46#endif
47
c6dc6f63
AP		 48/* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61};
62static const char *ext_feature_name[] = {
f370be3c 63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 64 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 65 "tm2", "ssse3", "cid", NULL,
e117f772 66 "fma", "cx16", "xtpr", "pdcm",
434acb81 67 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 69 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 70 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 71};
3b671a40
EH		 72/* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
c6dc6f63 77static const char *ext2_feature_name[] = {
3b671a40
EH		 78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 85 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 86};
87static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 90 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 95 NULL, NULL, NULL, NULL,
96};
97
89e49c8b
EH		 98static const char *ext4_feature_name[] = {
99 NULL, NULL, "xstore", "xstore-en",
100 NULL, NULL, "xcrypt", "xcrypt-en",
101 "ace2", "ace2-en", "phe", "phe-en",
102 "pmm", "pmm-en", NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107};
108
c6dc6f63 109static const char *kvm_feature_name[] = {
c3d39807
DS		 110 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
111 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
112 NULL, NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 118};
119
296acb64
JR		 120static const char *svm_feature_name[] = {
121 "npt", "lbrv", "svm_lock", "nrip_save",
122 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
123 NULL, NULL, "pause_filter", NULL,
124 "pfthreshold", NULL, NULL, NULL,
125 NULL, NULL, NULL, NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129};
130
a9321a4d 131static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 132 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
133 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 134 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 135 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
136};
137
5ef57876
EH		 138typedef struct FeatureWordInfo {
139 const char **feat_names;
bffd67b0
EH		 140 uint32_t cpuid_eax; /* Input EAX for CPUID */
141 int cpuid_reg; /* R_* register constant */
5ef57876
EH		 142} FeatureWordInfo;
143
144static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 145 [FEAT_1_EDX] = {
146 .feat_names = feature_name,
147 .cpuid_eax = 1, .cpuid_reg = R_EDX,
148 },
149 [FEAT_1_ECX] = {
150 .feat_names = ext_feature_name,
151 .cpuid_eax = 1, .cpuid_reg = R_ECX,
152 },
153 [FEAT_8000_0001_EDX] = {
154 .feat_names = ext2_feature_name,
155 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
156 },
157 [FEAT_8000_0001_ECX] = {
158 .feat_names = ext3_feature_name,
159 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
160 },
89e49c8b
EH		 161 [FEAT_C000_0001_EDX] = {
162 .feat_names = ext4_feature_name,
163 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
164 },
bffd67b0
EH		 165 [FEAT_KVM] = {
166 .feat_names = kvm_feature_name,
167 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
168 },
169 [FEAT_SVM] = {
170 .feat_names = svm_feature_name,
171 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
172 },
173 [FEAT_7_0_EBX] = {
174 .feat_names = cpuid_7_0_ebx_feature_name,
175 .cpuid_eax = 7, .cpuid_reg = R_EBX,
176 },
5ef57876
EH		 177};
178
8b4beddc
EH		 179const char *get_register_name_32(unsigned int reg)
180{
181 static const char *reg_names[CPU_NB_REGS32] = {
182 [R_EAX] = "EAX",
183 [R_ECX] = "ECX",
184 [R_EDX] = "EDX",
185 [R_EBX] = "EBX",
186 [R_ESP] = "ESP",
187 [R_EBP] = "EBP",
188 [R_ESI] = "ESI",
189 [R_EDI] = "EDI",
190 };
191
192 if (reg > CPU_NB_REGS32) {
193 return NULL;
194 }
195 return reg_names[reg];
196}
197
c6dc6f63
AP		 198/* collects per-function cpuid data
199 */
200typedef struct model_features_t {
201 uint32_t *guest_feat;
202 uint32_t *host_feat;
bffd67b0 203 FeatureWord feat_word;
8b4beddc 204} model_features_t;
c6dc6f63
AP		 205
206int check_cpuid = 0;
207int enforce_cpuid = 0;
208
dc59944b
MT		 209#if defined(CONFIG_KVM)
210static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
211 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 212 (1 << KVM_FEATURE_CLOCKSOURCE2) |
213 (1 << KVM_FEATURE_ASYNC_PF) |
214 (1 << KVM_FEATURE_STEAL_TIME) |
215 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
216static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
217#else
218static uint32_t kvm_default_features = 0;
219static const uint32_t kvm_pv_eoi_features = 0;
220#endif
221
222void enable_kvm_pv_eoi(void)
223{
224 kvm_default_features |= kvm_pv_eoi_features;
225}
226
bb44e0d1
JK		 227void host_cpuid(uint32_t function, uint32_t count,
228 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 229{
230#if defined(CONFIG_KVM)
a1fd24af
AL		 231 uint32_t vec[4];
232
233#ifdef __x86_64__
234 asm volatile("cpuid"
235 : "=a"(vec[0]), "=b"(vec[1]),
236 "=c"(vec[2]), "=d"(vec[3])
237 : "0"(function), "c"(count) : "cc");
238#else
239 asm volatile("pusha \n\t"
240 "cpuid \n\t"
241 "mov %%eax, 0(%2) \n\t"
242 "mov %%ebx, 4(%2) \n\t"
243 "mov %%ecx, 8(%2) \n\t"
244 "mov %%edx, 12(%2) \n\t"
245 "popa"
246 : : "a"(function), "c"(count), "S"(vec)
247 : "memory", "cc");
248#endif
249
bdde476a 250 if (eax)
a1fd24af 251 *eax = vec[0];
bdde476a 252 if (ebx)
a1fd24af 253 *ebx = vec[1];
bdde476a 254 if (ecx)
a1fd24af 255 *ecx = vec[2];
bdde476a 256 if (edx)
a1fd24af 257 *edx = vec[3];
bdde476a
AP		 258#endif
259}
c6dc6f63
AP		 260
261#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
262
263/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
264 * a substring. ex if !NULL points to the first char after a substring,
265 * otherwise the string is assumed to sized by a terminating nul.
266 * Return lexical ordering of *s1:*s2.
267 */
268static int sstrcmp(const char *s1, const char *e1, const char *s2,
269 const char *e2)
270{
271 for (;;) {
272 if (!*s1 || !*s2 || *s1 != *s2)
273 return (*s1 - *s2);
274 ++s1, ++s2;
275 if (s1 == e1 && s2 == e2)
276 return (0);
277 else if (s1 == e1)
278 return (*s2);
279 else if (s2 == e2)
280 return (*s1);
281 }
282}
283
284/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
285 * '|' delimited (possibly empty) strings in which case search for a match
286 * within the alternatives proceeds left to right. Return 0 for success,
287 * non-zero otherwise.
288 */
289static int altcmp(const char *s, const char *e, const char *altstr)
290{
291 const char *p, *q;
292
293 for (q = p = altstr; ; ) {
294 while (*p && *p != '|')
295 ++p;
296 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
297 return (0);
298 if (!*p)
299 return (1);
300 else
301 q = ++p;
302 }
303}
304
305/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 306 * *pval and return true, otherwise return false
c6dc6f63 307 */
e41e0fc6
JK		 308static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
309 const char **featureset)
c6dc6f63
AP		 310{
311 uint32_t mask;
312 const char **ppc;
e41e0fc6 313 bool found = false;
c6dc6f63 314
e41e0fc6 315 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 316 if (*ppc && !altcmp(s, e, *ppc)) {
317 *pval |= mask;
e41e0fc6 318 found = true;
c6dc6f63 319 }
e41e0fc6
JK		 320 }
321 return found;
c6dc6f63
AP		 322}
323
5ef57876
EH		 324static void add_flagname_to_bitmaps(const char *flagname,
325 FeatureWordArray words)
c6dc6f63 326{
5ef57876
EH		 327 FeatureWord w;
328 for (w = 0; w < FEATURE_WORDS; w++) {
329 FeatureWordInfo *wi = &feature_word_info[w];
330 if (wi->feat_names &&
331 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
332 break;
333 }
334 }
335 if (w == FEATURE_WORDS) {
336 fprintf(stderr, "CPU feature %s not found\n", flagname);
337 }
c6dc6f63
AP		 338}
339
340typedef struct x86_def_t {
341 struct x86_def_t *next;
342 const char *name;
343 uint32_t level;
344 uint32_t vendor1, vendor2, vendor3;
345 int family;
346 int model;
347 int stepping;
b862d1fe 348 int tsc_khz;
296acb64
JR		 349 uint32_t features, ext_features, ext2_features, ext3_features;
350 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 351 uint32_t xlevel;
352 char model_id[48];
353 int vendor_override;
b3baa152 354 /* Store the results of Centaur's CPUID instructions */
355 uint32_t ext4_features;
356 uint32_t xlevel2;
13526728
EH		 357 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
358 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 359} x86_def_t;
360
361#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
362#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
363 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
364#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
365 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
366 CPUID_PSE36 | CPUID_FXSR)
367#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
368#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
369 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
370 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
371 CPUID_PAE | CPUID_SEP | CPUID_APIC)
372
551a2dec
AP		 373#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
374 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
375 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
376 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
377 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 378 /* partly implemented:
379 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
380 CPUID_PSE36 (needed for Solaris) */
381 /* missing:
382 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 383#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
a0a70681 384 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 385 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 386 /* missing:
387 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 388 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
60032ac0 389#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 390 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
391 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 392 /* missing:
393 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 394#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
395 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 396#define TCG_SVM_FEATURES 0
a9321a4d 397#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
551a2dec 398
c6dc6f63
AP		 399/* maintains list of cpu model definitions
400 */
401static x86_def_t *x86_defs = {NULL};
402
403/* built-in cpu model definitions (deprecated)
404 */
405static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 406 {
407 .name = "qemu64",
408 .level = 4,
409 .vendor1 = CPUID_VENDOR_AMD_1,
410 .vendor2 = CPUID_VENDOR_AMD_2,
411 .vendor3 = CPUID_VENDOR_AMD_3,
412 .family = 6,
413 .model = 2,
414 .stepping = 3,
415 .features = PPRO_FEATURES |
c6dc6f63 416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 417 CPUID_PSE36,
418 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
60032ac0 419 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 420 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
421 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
422 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
423 .xlevel = 0x8000000A,
c6dc6f63
AP		 424 },
425 {
426 .name = "phenom",
427 .level = 5,
428 .vendor1 = CPUID_VENDOR_AMD_1,
429 .vendor2 = CPUID_VENDOR_AMD_2,
430 .vendor3 = CPUID_VENDOR_AMD_3,
431 .family = 16,
432 .model = 2,
433 .stepping = 3,
c6dc6f63
AP		 434 .features = PPRO_FEATURES |
435 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 436 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 437 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
438 CPUID_EXT_POPCNT,
60032ac0 439 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 440 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
441 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 442 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 443 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
444 CPUID_EXT3_CR8LEG,
445 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
446 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
447 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
448 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 449 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 450 .xlevel = 0x8000001A,
451 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
452 },
453 {
454 .name = "core2duo",
455 .level = 10,
ebe8b9c6
IM		 456 .vendor1 = CPUID_VENDOR_INTEL_1,
457 .vendor2 = CPUID_VENDOR_INTEL_2,
458 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 459 .family = 6,
460 .model = 15,
461 .stepping = 11,
c6dc6f63
AP		 462 .features = PPRO_FEATURES |
463 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 464 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
465 CPUID_HT | CPUID_TM | CPUID_PBE,
466 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
467 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
468 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 469 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
470 .ext3_features = CPUID_EXT3_LAHF_LM,
471 .xlevel = 0x80000008,
472 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
473 },
474 {
475 .name = "kvm64",
476 .level = 5,
477 .vendor1 = CPUID_VENDOR_INTEL_1,
478 .vendor2 = CPUID_VENDOR_INTEL_2,
479 .vendor3 = CPUID_VENDOR_INTEL_3,
480 .family = 15,
481 .model = 6,
482 .stepping = 1,
483 /* Missing: CPUID_VME, CPUID_HT */
484 .features = PPRO_FEATURES |
485 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
486 CPUID_PSE36,
487 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
488 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
489 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
60032ac0 490 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 491 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
492 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
493 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
494 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
495 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
496 .ext3_features = 0,
497 .xlevel = 0x80000008,
498 .model_id = "Common KVM processor"
499 },
c6dc6f63
AP		 500 {
501 .name = "qemu32",
502 .level = 4,
ebe8b9c6
IM		 503 .vendor1 = CPUID_VENDOR_INTEL_1,
504 .vendor2 = CPUID_VENDOR_INTEL_2,
505 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 506 .family = 6,
507 .model = 3,
508 .stepping = 3,
509 .features = PPRO_FEATURES,
510 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 511 .xlevel = 0x80000004,
c6dc6f63 512 },
eafaf1e5
AP		 513 {
514 .name = "kvm32",
515 .level = 5,
ebe8b9c6
IM		 516 .vendor1 = CPUID_VENDOR_INTEL_1,
517 .vendor2 = CPUID_VENDOR_INTEL_2,
518 .vendor3 = CPUID_VENDOR_INTEL_3,
eafaf1e5
AP		 519 .family = 15,
520 .model = 6,
521 .stepping = 1,
522 .features = PPRO_FEATURES |
523 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
524 .ext_features = CPUID_EXT_SSE3,
60032ac0 525 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
eafaf1e5
AP		 526 .ext3_features = 0,
527 .xlevel = 0x80000008,
528 .model_id = "Common 32-bit KVM processor"
529 },
c6dc6f63
AP		 530 {
531 .name = "coreduo",
532 .level = 10,
ebe8b9c6
IM		 533 .vendor1 = CPUID_VENDOR_INTEL_1,
534 .vendor2 = CPUID_VENDOR_INTEL_2,
535 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 536 .family = 6,
537 .model = 14,
538 .stepping = 8,
c6dc6f63 539 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 540 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
541 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
542 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
543 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 544 .ext2_features = CPUID_EXT2_NX,
545 .xlevel = 0x80000008,
546 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
547 },
548 {
549 .name = "486",
58012d66 550 .level = 1,
ebe8b9c6
IM		 551 .vendor1 = CPUID_VENDOR_INTEL_1,
552 .vendor2 = CPUID_VENDOR_INTEL_2,
553 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 554 .family = 4,
555 .model = 0,
556 .stepping = 0,
557 .features = I486_FEATURES,
558 .xlevel = 0,
559 },
560 {
561 .name = "pentium",
562 .level = 1,
ebe8b9c6
IM		 563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 566 .family = 5,
567 .model = 4,
568 .stepping = 3,
569 .features = PENTIUM_FEATURES,
570 .xlevel = 0,
571 },
572 {
573 .name = "pentium2",
574 .level = 2,
ebe8b9c6
IM		 575 .vendor1 = CPUID_VENDOR_INTEL_1,
576 .vendor2 = CPUID_VENDOR_INTEL_2,
577 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 578 .family = 6,
579 .model = 5,
580 .stepping = 2,
581 .features = PENTIUM2_FEATURES,
582 .xlevel = 0,
583 },
584 {
585 .name = "pentium3",
586 .level = 2,
ebe8b9c6
IM		 587 .vendor1 = CPUID_VENDOR_INTEL_1,
588 .vendor2 = CPUID_VENDOR_INTEL_2,
589 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 590 .family = 6,
591 .model = 7,
592 .stepping = 3,
593 .features = PENTIUM3_FEATURES,
594 .xlevel = 0,
595 },
596 {
597 .name = "athlon",
598 .level = 2,
599 .vendor1 = CPUID_VENDOR_AMD_1,
600 .vendor2 = CPUID_VENDOR_AMD_2,
601 .vendor3 = CPUID_VENDOR_AMD_3,
602 .family = 6,
603 .model = 2,
604 .stepping = 3,
60032ac0
EH		 605 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
606 CPUID_MCA,
607 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
608 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 609 .xlevel = 0x80000008,
c6dc6f63
AP		 610 },
611 {
612 .name = "n270",
613 /* original is on level 10 */
614 .level = 5,
ebe8b9c6
IM		 615 .vendor1 = CPUID_VENDOR_INTEL_1,
616 .vendor2 = CPUID_VENDOR_INTEL_2,
617 .vendor3 = CPUID_VENDOR_INTEL_3,
c6dc6f63
AP		 618 .family = 6,
619 .model = 28,
620 .stepping = 2,
621 .features = PPRO_FEATURES |
8560efed
AJ		 622 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
623 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 624 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 625 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
626 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
60032ac0
EH		 627 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
628 CPUID_EXT2_NX,
8560efed 629 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 630 .xlevel = 0x8000000A,
631 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
632 },
3eca4642
EH		 633 {
634 .name = "Conroe",
635 .level = 2,
636 .vendor1 = CPUID_VENDOR_INTEL_1,
637 .vendor2 = CPUID_VENDOR_INTEL_2,
638 .vendor3 = CPUID_VENDOR_INTEL_3,
639 .family = 6,
640 .model = 2,
641 .stepping = 3,
642 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
643 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
644 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
645 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
646 CPUID_DE | CPUID_FP87,
647 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
648 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
649 .ext3_features = CPUID_EXT3_LAHF_LM,
650 .xlevel = 0x8000000A,
651 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
652 },
653 {
654 .name = "Penryn",
655 .level = 2,
656 .vendor1 = CPUID_VENDOR_INTEL_1,
657 .vendor2 = CPUID_VENDOR_INTEL_2,
658 .vendor3 = CPUID_VENDOR_INTEL_3,
659 .family = 6,
660 .model = 2,
661 .stepping = 3,
662 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
663 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
664 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
665 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
666 CPUID_DE | CPUID_FP87,
667 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
668 CPUID_EXT_SSE3,
669 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
670 .ext3_features = CPUID_EXT3_LAHF_LM,
671 .xlevel = 0x8000000A,
672 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
673 },
674 {
675 .name = "Nehalem",
676 .level = 2,
677 .vendor1 = CPUID_VENDOR_INTEL_1,
678 .vendor2 = CPUID_VENDOR_INTEL_2,
679 .vendor3 = CPUID_VENDOR_INTEL_3,
680 .family = 6,
681 .model = 2,
682 .stepping = 3,
683 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
684 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
685 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
686 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
687 CPUID_DE | CPUID_FP87,
688 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
689 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
690 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
691 .ext3_features = CPUID_EXT3_LAHF_LM,
692 .xlevel = 0x8000000A,
693 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
694 },
695 {
696 .name = "Westmere",
697 .level = 11,
698 .vendor1 = CPUID_VENDOR_INTEL_1,
699 .vendor2 = CPUID_VENDOR_INTEL_2,
700 .vendor3 = CPUID_VENDOR_INTEL_3,
701 .family = 6,
702 .model = 44,
703 .stepping = 1,
704 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
705 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
706 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
707 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
708 CPUID_DE | CPUID_FP87,
709 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
710 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
711 CPUID_EXT_SSE3,
712 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
713 .ext3_features = CPUID_EXT3_LAHF_LM,
714 .xlevel = 0x8000000A,
715 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
716 },
717 {
718 .name = "SandyBridge",
719 .level = 0xd,
720 .vendor1 = CPUID_VENDOR_INTEL_1,
721 .vendor2 = CPUID_VENDOR_INTEL_2,
722 .vendor3 = CPUID_VENDOR_INTEL_3,
723 .family = 6,
724 .model = 42,
725 .stepping = 1,
726 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
727 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
728 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
729 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
730 CPUID_DE | CPUID_FP87,
731 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
732 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
733 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
734 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
735 CPUID_EXT_SSE3,
736 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
737 CPUID_EXT2_SYSCALL,
738 .ext3_features = CPUID_EXT3_LAHF_LM,
739 .xlevel = 0x8000000A,
740 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
741 },
37507094
EH		 742 {
743 .name = "Haswell",
744 .level = 0xd,
745 .vendor1 = CPUID_VENDOR_INTEL_1,
746 .vendor2 = CPUID_VENDOR_INTEL_2,
747 .vendor3 = CPUID_VENDOR_INTEL_3,
748 .family = 6,
749 .model = 60,
750 .stepping = 1,
751 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
752 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 753 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 754 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
755 CPUID_DE | CPUID_FP87,
756 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
757 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
758 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
759 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
760 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
761 CPUID_EXT_PCID,
80ae4160
EH		 762 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
763 CPUID_EXT2_SYSCALL,
37507094
EH		 764 .ext3_features = CPUID_EXT3_LAHF_LM,
765 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
766 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
767 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
768 CPUID_7_0_EBX_RTM,
769 .xlevel = 0x8000000A,
770 .model_id = "Intel Core Processor (Haswell)",
771 },
3eca4642
EH		 772 {
773 .name = "Opteron_G1",
774 .level = 5,
775 .vendor1 = CPUID_VENDOR_AMD_1,
776 .vendor2 = CPUID_VENDOR_AMD_2,
777 .vendor3 = CPUID_VENDOR_AMD_3,
778 .family = 15,
779 .model = 6,
780 .stepping = 1,
781 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
782 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
783 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
784 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
785 CPUID_DE | CPUID_FP87,
786 .ext_features = CPUID_EXT_SSE3,
787 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
788 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
789 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
790 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
791 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
792 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
793 .xlevel = 0x80000008,
794 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
795 },
796 {
797 .name = "Opteron_G2",
798 .level = 5,
799 .vendor1 = CPUID_VENDOR_AMD_1,
800 .vendor2 = CPUID_VENDOR_AMD_2,
801 .vendor3 = CPUID_VENDOR_AMD_3,
802 .family = 15,
803 .model = 6,
804 .stepping = 1,
805 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
809 CPUID_DE | CPUID_FP87,
810 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
811 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
812 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
813 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
814 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
815 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
816 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
817 CPUID_EXT2_DE | CPUID_EXT2_FPU,
818 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
819 .xlevel = 0x80000008,
820 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
821 },
822 {
823 .name = "Opteron_G3",
824 .level = 5,
825 .vendor1 = CPUID_VENDOR_AMD_1,
826 .vendor2 = CPUID_VENDOR_AMD_2,
827 .vendor3 = CPUID_VENDOR_AMD_3,
828 .family = 15,
829 .model = 6,
830 .stepping = 1,
831 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
832 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
833 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
834 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
835 CPUID_DE | CPUID_FP87,
836 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
837 CPUID_EXT_SSE3,
838 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
839 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
840 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
841 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
842 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
843 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
844 CPUID_EXT2_DE | CPUID_EXT2_FPU,
845 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
846 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
847 .xlevel = 0x80000008,
848 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
849 },
850 {
851 .name = "Opteron_G4",
852 .level = 0xd,
853 .vendor1 = CPUID_VENDOR_AMD_1,
854 .vendor2 = CPUID_VENDOR_AMD_2,
855 .vendor3 = CPUID_VENDOR_AMD_3,
856 .family = 21,
857 .model = 1,
858 .stepping = 2,
859 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
860 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
861 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
862 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
863 CPUID_DE | CPUID_FP87,
864 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
865 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
866 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
867 CPUID_EXT_SSE3,
868 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
869 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
870 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
871 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
872 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
873 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
874 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
875 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
876 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
877 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
878 CPUID_EXT3_LAHF_LM,
879 .xlevel = 0x8000001A,
880 .model_id = "AMD Opteron 62xx class CPU",
881 },
021941b9
AP		 882 {
883 .name = "Opteron_G5",
884 .level = 0xd,
885 .vendor1 = CPUID_VENDOR_AMD_1,
886 .vendor2 = CPUID_VENDOR_AMD_2,
887 .vendor3 = CPUID_VENDOR_AMD_3,
888 .family = 21,
889 .model = 2,
890 .stepping = 0,
891 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
892 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
893 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
894 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
895 CPUID_DE | CPUID_FP87,
896 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
897 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
898 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
899 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
900 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
901 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
902 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
903 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
904 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
905 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
906 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
907 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
908 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
909 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
910 CPUID_EXT3_LAHF_LM,
911 .xlevel = 0x8000001A,
912 .model_id = "AMD Opteron 63xx class CPU",
913 },
c6dc6f63
AP		 914};
915
e4ab0d6b 916#ifdef CONFIG_KVM
c6dc6f63
AP		 917static int cpu_x86_fill_model_id(char *str)
918{
919 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
920 int i;
921
922 for (i = 0; i < 3; i++) {
923 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
924 memcpy(str + i * 16 + 0, &eax, 4);
925 memcpy(str + i * 16 + 4, &ebx, 4);
926 memcpy(str + i * 16 + 8, &ecx, 4);
927 memcpy(str + i * 16 + 12, &edx, 4);
928 }
929 return 0;
930}
e4ab0d6b 931#endif
c6dc6f63 932
6e746f30
EH		 933/* Fill a x86_def_t struct with information about the host CPU, and
934 * the CPU features supported by the host hardware + host kernel
935 *
936 * This function may be called only if KVM is enabled.
937 */
938static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
c6dc6f63 939{
e4ab0d6b 940#ifdef CONFIG_KVM
12869995 941 KVMState *s = kvm_state;
c6dc6f63
AP		 942 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
943
6e746f30
EH		 944 assert(kvm_enabled());
945
c6dc6f63
AP		 946 x86_cpu_def->name = "host";
947 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
c6dc6f63
AP		 948 x86_cpu_def->vendor1 = ebx;
949 x86_cpu_def->vendor2 = edx;
950 x86_cpu_def->vendor3 = ecx;
951
952 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
953 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
954 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
955 x86_cpu_def->stepping = eax & 0x0F;
c6dc6f63 956
12869995
EH		 957 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
958 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
959 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
c6dc6f63 960
6e746f30 961 if (x86_cpu_def->level >= 7) {
12869995
EH		 962 x86_cpu_def->cpuid_7_0_ebx_features =
963 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
13526728
EH		 964 } else {
965 x86_cpu_def->cpuid_7_0_ebx_features = 0;
966 }
967
12869995
EH		 968 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
969 x86_cpu_def->ext2_features =
970 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
971 x86_cpu_def->ext3_features =
972 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
c6dc6f63 973
c6dc6f63
AP		 974 cpu_x86_fill_model_id(x86_cpu_def->model_id);
975 x86_cpu_def->vendor_override = 0;
976
b3baa152 977 /* Call Centaur's CPUID instruction. */
978 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
979 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
980 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
981 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
12869995 982 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
b3baa152 983 if (eax >= 0xC0000001) {
984 /* Support VIA max extended level */
985 x86_cpu_def->xlevel2 = eax;
986 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
12869995
EH		 987 x86_cpu_def->ext4_features =
988 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
b3baa152 989 }
990 }
296acb64 991
fcb93c03
EH		 992 /* Other KVM-specific feature fields: */
993 x86_cpu_def->svm_features =
994 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
bd004bef
EH		 995 x86_cpu_def->kvm_features =
996 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
fcb93c03 997
e4ab0d6b 998#endif /* CONFIG_KVM */
c6dc6f63
AP		 999}
1000
bffd67b0 1001static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1002{
1003 int i;
1004
1005 for (i = 0; i < 32; ++i)
1006 if (1 << i & mask) {
bffd67b0 1007 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1008 assert(reg);
1009 fprintf(stderr, "warning: host doesn't support requested feature: "
1010 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1011 f->cpuid_eax, reg,
1012 f->feat_names[i] ? "." : "",
1013 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1014 break;
1015 }
1016 return 0;
1017}
1018
07ca5945
EH		 1019/* Check if all requested cpu flags are making their way to the guest
1020 *
1021 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1022 *
1023 * This function may be called only if KVM is enabled.
c6dc6f63 1024 */
6e746f30 1025static int kvm_check_features_against_host(x86_def_t *guest_def)
c6dc6f63
AP		 1026{
1027 x86_def_t host_def;
1028 uint32_t mask;
1029 int rv, i;
1030 struct model_features_t ft[] = {
1031 {&guest_def->features, &host_def.features,
bffd67b0 1032 FEAT_1_EDX },
c6dc6f63 1033 {&guest_def->ext_features, &host_def.ext_features,
bffd67b0 1034 FEAT_1_ECX },
c6dc6f63 1035 {&guest_def->ext2_features, &host_def.ext2_features,
bffd67b0 1036 FEAT_8000_0001_EDX },
c6dc6f63 1037 {&guest_def->ext3_features, &host_def.ext3_features,
bffd67b0 1038 FEAT_8000_0001_ECX },
07ca5945
EH		 1039 {&guest_def->ext4_features, &host_def.ext4_features,
1040 FEAT_C000_0001_EDX },
1041 {&guest_def->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
1042 FEAT_7_0_EBX },
1043 {&guest_def->svm_features, &host_def.svm_features,
1044 FEAT_SVM },
1045 {&guest_def->kvm_features, &host_def.kvm_features,
1046 FEAT_KVM },
8b4beddc 1047 };
c6dc6f63 1048
6e746f30
EH		 1049 assert(kvm_enabled());
1050
1051 kvm_cpu_fill_host(&host_def);
bffd67b0
EH		 1052 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1053 FeatureWord w = ft[i].feat_word;
1054 FeatureWordInfo *wi = &feature_word_info[w];
1055 for (mask = 1; mask; mask <<= 1) {
e8beac00 1056 if (*ft[i].guest_feat & mask &&
c6dc6f63 1057 !(*ft[i].host_feat & mask)) {
bffd67b0
EH		 1058 unavailable_host_feature(wi, mask);
1059 rv = 1;
1060 }
1061 }
1062 }
c6dc6f63
AP		 1063 return rv;
1064}
1065
95b8519d
AF		 1066static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1067 const char *name, Error **errp)
1068{
1069 X86CPU *cpu = X86_CPU(obj);
1070 CPUX86State *env = &cpu->env;
1071 int64_t value;
1072
1073 value = (env->cpuid_version >> 8) & 0xf;
1074 if (value == 0xf) {
1075 value += (env->cpuid_version >> 20) & 0xff;
1076 }
1077 visit_type_int(v, &value, name, errp);
1078}
1079
71ad61d3
AF		 1080static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1081 const char *name, Error **errp)
ed5e1ec3 1082{
71ad61d3
AF		 1083 X86CPU *cpu = X86_CPU(obj);
1084 CPUX86State *env = &cpu->env;
1085 const int64_t min = 0;
1086 const int64_t max = 0xff + 0xf;
1087 int64_t value;
1088
1089 visit_type_int(v, &value, name, errp);
1090 if (error_is_set(errp)) {
1091 return;
1092 }
1093 if (value < min || value > max) {
1094 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1095 name ? name : "null", value, min, max);
1096 return;
1097 }
1098
ed5e1ec3 1099 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1100 if (value > 0x0f) {
1101 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1102 } else {
71ad61d3 1103 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1104 }
1105}
1106
67e30c83
AF		 1107static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1108 const char *name, Error **errp)
1109{
1110 X86CPU *cpu = X86_CPU(obj);
1111 CPUX86State *env = &cpu->env;
1112 int64_t value;
1113
1114 value = (env->cpuid_version >> 4) & 0xf;
1115 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1116 visit_type_int(v, &value, name, errp);
1117}
1118
c5291a4f
AF		 1119static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1120 const char *name, Error **errp)
b0704cbd 1121{
c5291a4f
AF		 1122 X86CPU *cpu = X86_CPU(obj);
1123 CPUX86State *env = &cpu->env;
1124 const int64_t min = 0;
1125 const int64_t max = 0xff;
1126 int64_t value;
1127
1128 visit_type_int(v, &value, name, errp);
1129 if (error_is_set(errp)) {
1130 return;
1131 }
1132 if (value < min || value > max) {
1133 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1134 name ? name : "null", value, min, max);
1135 return;
1136 }
1137
b0704cbd 1138 env->cpuid_version &= ~0xf00f0;
c5291a4f 1139 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1140}
1141
35112e41
AF		 1142static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1143 void *opaque, const char *name,
1144 Error **errp)
1145{
1146 X86CPU *cpu = X86_CPU(obj);
1147 CPUX86State *env = &cpu->env;
1148 int64_t value;
1149
1150 value = env->cpuid_version & 0xf;
1151 visit_type_int(v, &value, name, errp);
1152}
1153
036e2222
AF		 1154static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1155 void *opaque, const char *name,
1156 Error **errp)
38c3dc46 1157{
036e2222
AF		 1158 X86CPU *cpu = X86_CPU(obj);
1159 CPUX86State *env = &cpu->env;
1160 const int64_t min = 0;
1161 const int64_t max = 0xf;
1162 int64_t value;
1163
1164 visit_type_int(v, &value, name, errp);
1165 if (error_is_set(errp)) {
1166 return;
1167 }
1168 if (value < min || value > max) {
1169 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1170 name ? name : "null", value, min, max);
1171 return;
1172 }
1173
38c3dc46 1174 env->cpuid_version &= ~0xf;
036e2222 1175 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1176}
1177
8e1898bf
AF		 1178static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1179 const char *name, Error **errp)
1180{
1181 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1182
fa029887 1183 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1184}
1185
1186static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1187 const char *name, Error **errp)
1188{
1189 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1190
fa029887 1191 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1192}
1193
16b93aa8
AF		 1194static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1195 const char *name, Error **errp)
1196{
1197 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1198
fa029887 1199 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1200}
1201
1202static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1203 const char *name, Error **errp)
1204{
1205 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1206
fa029887 1207 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1208}
1209
d480e1af
AF		 1210static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1211{
1212 X86CPU *cpu = X86_CPU(obj);
1213 CPUX86State *env = &cpu->env;
1214 char *value;
1215 int i;
1216
9df694ee 1217 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
d480e1af
AF		 1218 for (i = 0; i < 4; i++) {
1219 value[i ] = env->cpuid_vendor1 >> (8 * i);
1220 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1221 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1222 }
9df694ee 1223 value[CPUID_VENDOR_SZ] = '\0';
d480e1af
AF		 1224 return value;
1225}
1226
1227static void x86_cpuid_set_vendor(Object *obj, const char *value,
1228 Error **errp)
1229{
1230 X86CPU *cpu = X86_CPU(obj);
1231 CPUX86State *env = &cpu->env;
1232 int i;
1233
9df694ee 1234 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1235 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1236 "vendor", value);
1237 return;
1238 }
1239
1240 env->cpuid_vendor1 = 0;
1241 env->cpuid_vendor2 = 0;
1242 env->cpuid_vendor3 = 0;
1243 for (i = 0; i < 4; i++) {
1244 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1245 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1246 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1247 }
1248 env->cpuid_vendor_override = 1;
1249}
1250
63e886eb
AF		 1251static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1252{
1253 X86CPU *cpu = X86_CPU(obj);
1254 CPUX86State *env = &cpu->env;
1255 char *value;
1256 int i;
1257
1258 value = g_malloc(48 + 1);
1259 for (i = 0; i < 48; i++) {
1260 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1261 }
1262 value[48] = '\0';
1263 return value;
1264}
1265
938d4c25
AF		 1266static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1267 Error **errp)
dcce6675 1268{
938d4c25
AF		 1269 X86CPU *cpu = X86_CPU(obj);
1270 CPUX86State *env = &cpu->env;
dcce6675
AF		 1271 int c, len, i;
1272
1273 if (model_id == NULL) {
1274 model_id = "";
1275 }
1276 len = strlen(model_id);
d0a6acf4 1277 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1278 for (i = 0; i < 48; i++) {
1279 if (i >= len) {
1280 c = '\0';
1281 } else {
1282 c = (uint8_t)model_id[i];
1283 }
1284 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1285 }
1286}
1287
89e48965
AF		 1288static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1289 const char *name, Error **errp)
1290{
1291 X86CPU *cpu = X86_CPU(obj);
1292 int64_t value;
1293
1294 value = cpu->env.tsc_khz * 1000;
1295 visit_type_int(v, &value, name, errp);
1296}
1297
1298static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1299 const char *name, Error **errp)
1300{
1301 X86CPU *cpu = X86_CPU(obj);
1302 const int64_t min = 0;
2e84849a 1303 const int64_t max = INT64_MAX;
89e48965
AF		 1304 int64_t value;
1305
1306 visit_type_int(v, &value, name, errp);
1307 if (error_is_set(errp)) {
1308 return;
1309 }
1310 if (value < min || value > max) {
1311 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1312 name ? name : "null", value, min, max);
1313 return;
1314 }
1315
1316 cpu->env.tsc_khz = value / 1000;
1317}
1318
8f961357 1319static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
c6dc6f63 1320{
c6dc6f63
AP		 1321 x86_def_t *def;
1322
9f3fb565
EH		 1323 for (def = x86_defs; def; def = def->next) {
1324 if (name && !strcmp(name, def->name)) {
c6dc6f63 1325 break;
9f3fb565
EH		 1326 }
1327 }
04c5b17a 1328 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
6e746f30 1329 kvm_cpu_fill_host(x86_cpu_def);
c6dc6f63 1330 } else if (!def) {
8f961357 1331 return -1;
c6dc6f63
AP		 1332 } else {
1333 memcpy(x86_cpu_def, def, sizeof(*def));
1334 }
1335
8f961357
EH		 1336 return 0;
1337}
1338
1339/* Parse "+feature,-feature,feature=foo" CPU feature string
1340 */
1341static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1342{
1343 unsigned int i;
1344 char *featurestr; /* Single 'key=value" string being parsed */
1345 /* Features to be added */
077c68c3 1346 FeatureWordArray plus_features = { 0 };
8f961357 1347 /* Features to be removed */
5ef57876 1348 FeatureWordArray minus_features = { 0 };
8f961357
EH		 1349 uint32_t numvalue;
1350
8f961357 1351 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1352
1353 while (featurestr) {
1354 char *val;
1355 if (featurestr[0] == '+') {
5ef57876 1356 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1357 } else if (featurestr[0] == '-') {
5ef57876 1358 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1359 } else if ((val = strchr(featurestr, '='))) {
1360 *val = 0; val++;
1361 if (!strcmp(featurestr, "family")) {
1362 char *err;
1363 numvalue = strtoul(val, &err, 0);
a88a677f 1364 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 1365 fprintf(stderr, "bad numerical value %s\n", val);
1366 goto error;
1367 }
1368 x86_cpu_def->family = numvalue;
1369 } else if (!strcmp(featurestr, "model")) {
1370 char *err;
1371 numvalue = strtoul(val, &err, 0);
1372 if (!*val || *err || numvalue > 0xff) {
1373 fprintf(stderr, "bad numerical value %s\n", val);
1374 goto error;
1375 }
1376 x86_cpu_def->model = numvalue;
1377 } else if (!strcmp(featurestr, "stepping")) {
1378 char *err;
1379 numvalue = strtoul(val, &err, 0);
1380 if (!*val || *err || numvalue > 0xf) {
1381 fprintf(stderr, "bad numerical value %s\n", val);
1382 goto error;
1383 }
1384 x86_cpu_def->stepping = numvalue ;
1385 } else if (!strcmp(featurestr, "level")) {
1386 char *err;
1387 numvalue = strtoul(val, &err, 0);
1388 if (!*val || *err) {
1389 fprintf(stderr, "bad numerical value %s\n", val);
1390 goto error;
1391 }
1392 x86_cpu_def->level = numvalue;
1393 } else if (!strcmp(featurestr, "xlevel")) {
1394 char *err;
1395 numvalue = strtoul(val, &err, 0);
1396 if (!*val || *err) {
1397 fprintf(stderr, "bad numerical value %s\n", val);
1398 goto error;
1399 }
1400 if (numvalue < 0x80000000) {
2f7a21c4 1401 numvalue += 0x80000000;
c6dc6f63
AP		 1402 }
1403 x86_cpu_def->xlevel = numvalue;
1404 } else if (!strcmp(featurestr, "vendor")) {
1405 if (strlen(val) != 12) {
1406 fprintf(stderr, "vendor string must be 12 chars long\n");
1407 goto error;
1408 }
1409 x86_cpu_def->vendor1 = 0;
1410 x86_cpu_def->vendor2 = 0;
1411 x86_cpu_def->vendor3 = 0;
1412 for(i = 0; i < 4; i++) {
1413 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1414 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1415 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1416 }
1417 x86_cpu_def->vendor_override = 1;
1418 } else if (!strcmp(featurestr, "model_id")) {
1419 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1420 val);
b862d1fe
JR		 1421 } else if (!strcmp(featurestr, "tsc_freq")) {
1422 int64_t tsc_freq;
1423 char *err;
1424
1425 tsc_freq = strtosz_suffix_unit(val, &err,
1426 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1427 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 1428 fprintf(stderr, "bad numerical value %s\n", val);
1429 goto error;
1430 }
1431 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 1432 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1433 char *err;
1434 numvalue = strtoul(val, &err, 0);
1435 if (!*val || *err) {
1436 fprintf(stderr, "bad numerical value %s\n", val);
1437 goto error;
1438 }
1439 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 1440 } else {
1441 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1442 goto error;
1443 }
1444 } else if (!strcmp(featurestr, "check")) {
1445 check_cpuid = 1;
1446 } else if (!strcmp(featurestr, "enforce")) {
1447 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 1448 } else if (!strcmp(featurestr, "hv_relaxed")) {
1449 hyperv_enable_relaxed_timing(true);
1450 } else if (!strcmp(featurestr, "hv_vapic")) {
1451 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1452 } else {
1453 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1454 goto error;
1455 }
1456 featurestr = strtok(NULL, ",");
1457 }
5ef57876
EH		 1458 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1459 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1460 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1461 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
89e49c8b 1462 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
5ef57876
EH		 1463 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1464 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1465 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1466 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1467 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1468 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1469 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
89e49c8b 1470 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
5ef57876
EH		 1471 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1472 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1473 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
6e746f30
EH		 1474 if (check_cpuid && kvm_enabled()) {
1475 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
c6dc6f63
AP		 1476 goto error;
1477 }
c6dc6f63
AP		 1478 return 0;
1479
1480error:
c6dc6f63
AP		 1481 return -1;
1482}
1483
1484/* generate a composite string into buf of all cpuid names in featureset
1485 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1486 * if flags, suppress names undefined in featureset.
1487 */
1488static void listflags(char *buf, int bufsize, uint32_t fbits,
1489 const char **featureset, uint32_t flags)
1490{
1491 const char **p = &featureset[31];
1492 char *q, *b, bit;
1493 int nc;
1494
1495 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1496 *buf = '\0';
1497 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1498 if (fbits & 1 << bit && (*p || !flags)) {
1499 if (*p)
1500 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1501 else
1502 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1503 if (bufsize <= nc) {
1504 if (b) {
1505 memcpy(b, "...", sizeof("..."));
1506 }
1507 return;
1508 }
1509 q += nc;
1510 bufsize -= nc;
1511 }
1512}
1513
e916cbf8
PM		 1514/* generate CPU information. */
1515void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1516{
c6dc6f63
AP		 1517 x86_def_t *def;
1518 char buf[256];
1519
c6dc6f63 1520 for (def = x86_defs; def; def = def->next) {
c04321b3 1521 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1522 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1523 }
ed2c54d4
AP		 1524 if (kvm_enabled()) {
1525 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1526 }
6cdf8854
PM		 1527 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1528 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
4a19e505 1529 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1530 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
4a19e505 1531 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1532 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
4a19e505 1533 (*cpu_fprintf)(f, " %s\n", buf);
6cdf8854 1534 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
4a19e505 1535 (*cpu_fprintf)(f, " %s\n", buf);
c6dc6f63
AP		 1536}
1537
76b64a7a 1538CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1539{
1540 CpuDefinitionInfoList *cpu_list = NULL;
1541 x86_def_t *def;
1542
1543 for (def = x86_defs; def; def = def->next) {
1544 CpuDefinitionInfoList *entry;
1545 CpuDefinitionInfo *info;
1546
1547 info = g_malloc0(sizeof(*info));
1548 info->name = g_strdup(def->name);
1549
1550 entry = g_malloc0(sizeof(*entry));
1551 entry->value = info;
1552 entry->next = cpu_list;
1553 cpu_list = entry;
1554 }
1555
1556 return cpu_list;
1557}
1558
bc74b7db
EH		 1559#ifdef CONFIG_KVM
1560static void filter_features_for_kvm(X86CPU *cpu)
1561{
1562 CPUX86State *env = &cpu->env;
1563 KVMState *s = kvm_state;
1564
b8091f24
EH		 1565 env->cpuid_features &=
1566 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1567 env->cpuid_ext_features &=
1568 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1569 env->cpuid_ext2_features &=
1570 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1571 env->cpuid_ext3_features &=
1572 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1573 env->cpuid_svm_features &=
1574 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
ffa8c11f
EH		 1575 env->cpuid_7_0_ebx_features &=
1576 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
bc74b7db 1577 env->cpuid_kvm_features &=
b8091f24
EH		 1578 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1579 env->cpuid_ext4_features &=
1580 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
bc74b7db
EH		 1581
1582}
1583#endif
1584
61dcd775 1585int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1586{
61dcd775 1587 CPUX86State *env = &cpu->env;
c6dc6f63 1588 x86_def_t def1, *def = &def1;
71ad61d3 1589 Error *error = NULL;
8f961357
EH		 1590 char *name, *features;
1591 gchar **model_pieces;
c6dc6f63 1592
db0ad1ba
JR		 1593 memset(def, 0, sizeof(*def));
1594
8f961357
EH		 1595 model_pieces = g_strsplit(cpu_model, ",", 2);
1596 if (!model_pieces[0]) {
fa2db3c4
IM		 1597 error_setg(&error, "Invalid/empty CPU model name");
1598 goto out;
8f961357
EH		 1599 }
1600 name = model_pieces[0];
1601 features = model_pieces[1];
1602
1603 if (cpu_x86_find_by_name(def, name) < 0) {
fa2db3c4
IM		 1604 error_setg(&error, "Unable to find CPU definition: %s", name);
1605 goto out;
8f961357
EH		 1606 }
1607
077c68c3
IM		 1608 def->kvm_features |= kvm_default_features;
1609 def->ext_features |= CPUID_EXT_HYPERVISOR;
1610
8f961357 1611 if (cpu_x86_parse_featurestr(def, features) < 0) {
fa2db3c4
IM		 1612 error_setg(&error, "Invalid cpu_model string format: %s", cpu_model);
1613 goto out;
8f961357 1614 }
ebe8b9c6
IM		 1615 assert(def->vendor1);
1616 env->cpuid_vendor1 = def->vendor1;
1617 env->cpuid_vendor2 = def->vendor2;
1618 env->cpuid_vendor3 = def->vendor3;
c6dc6f63 1619 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1620 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1621 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1622 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1623 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1624 env->cpuid_features = def->features;
c6dc6f63
AP		 1625 env->cpuid_ext_features = def->ext_features;
1626 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1627 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1628 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1629 env->cpuid_kvm_features = def->kvm_features;
296acb64 1630 env->cpuid_svm_features = def->svm_features;
b3baa152 1631 env->cpuid_ext4_features = def->ext4_features;
a9321a4d 1632 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
b3baa152 1633 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1634 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1635 "tsc-frequency", &error);
3b671a40 1636
938d4c25 1637 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
fa2db3c4
IM		 1638
1639out:
1640 g_strfreev(model_pieces);
18eb473f
IM		 1641 if (error) {
1642 fprintf(stderr, "%s\n", error_get_pretty(error));
71ad61d3 1643 error_free(error);
fa2db3c4 1644 return -1;
71ad61d3 1645 }
c6dc6f63
AP		 1646 return 0;
1647}
1648
1649#if !defined(CONFIG_USER_ONLY)
c6dc6f63 1650
0e26b7b8
BS		 1651void cpu_clear_apic_feature(CPUX86State *env)
1652{
1653 env->cpuid_features &= ~CPUID_APIC;
1654}
1655
c6dc6f63
AP		 1656#endif /* !CONFIG_USER_ONLY */
1657
c04321b3 1658/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 1659 */
1660void x86_cpudef_setup(void)
1661{
93bfef4c
CV		 1662 int i, j;
1663 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1664
1665 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
bc3e1291
EH		 1666 x86_def_t *def = &builtin_x86_defs[i];
1667 def->next = x86_defs;
93bfef4c
CV		 1668
1669 /* Look for specific "cpudef" models that */
09faecf2 1670 /* have the QEMU version in .model_id */
93bfef4c 1671 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 1672 if (strcmp(model_with_versions[j], def->name) == 0) {
1673 pstrcpy(def->model_id, sizeof(def->model_id),
1674 "QEMU Virtual CPU version ");
1675 pstrcat(def->model_id, sizeof(def->model_id),
1676 qemu_get_version());
93bfef4c
CV		 1677 break;
1678 }
1679 }
1680
bc3e1291 1681 x86_defs = def;
c6dc6f63 1682 }
c6dc6f63
AP		 1683}
1684
c6dc6f63
AP		 1685static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1686 uint32_t *ecx, uint32_t *edx)
1687{
1688 *ebx = env->cpuid_vendor1;
1689 *edx = env->cpuid_vendor2;
1690 *ecx = env->cpuid_vendor3;
1691
1692 /* sysenter isn't supported on compatibility mode on AMD, syscall
1693 * isn't supported in compatibility mode on Intel.
1694 * Normally we advertise the actual cpu vendor, but you can override
1695 * this if you want to use KVM's sysenter/syscall emulation
1696 * in compatibility mode and when doing cross vendor migration
1697 */
89354998 1698 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1699 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1700 }
1701}
1702
1703void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1704 uint32_t *eax, uint32_t *ebx,
1705 uint32_t *ecx, uint32_t *edx)
1706{
a60f24b5
AF		 1707 X86CPU *cpu = x86_env_get_cpu(env);
1708 CPUState *cs = CPU(cpu);
1709
c6dc6f63
AP		 1710 /* test if maximum index reached */
1711 if (index & 0x80000000) {
b3baa152 1712 if (index > env->cpuid_xlevel) {
1713 if (env->cpuid_xlevel2 > 0) {
1714 /* Handle the Centaur's CPUID instruction. */
1715 if (index > env->cpuid_xlevel2) {
1716 index = env->cpuid_xlevel2;
1717 } else if (index < 0xC0000000) {
1718 index = env->cpuid_xlevel;
1719 }
1720 } else {
57f26ae7
EH		 1721 /* Intel documentation states that invalid EAX input will
1722 * return the same information as EAX=cpuid_level
1723 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1724 */
1725 index = env->cpuid_level;
b3baa152 1726 }
1727 }
c6dc6f63
AP		 1728 } else {
1729 if (index > env->cpuid_level)
1730 index = env->cpuid_level;
1731 }
1732
1733 switch(index) {
1734 case 0:
1735 *eax = env->cpuid_level;
1736 get_cpuid_vendor(env, ebx, ecx, edx);
1737 break;
1738 case 1:
1739 *eax = env->cpuid_version;
1740 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1741 *ecx = env->cpuid_ext_features;
1742 *edx = env->cpuid_features;
ce3960eb
AF		 1743 if (cs->nr_cores * cs->nr_threads > 1) {
1744 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 1745 *edx |= 1 << 28; /* HTT bit */
1746 }
1747 break;
1748 case 2:
1749 /* cache info: needed for Pentium Pro compatibility */
1750 *eax = 1;
1751 *ebx = 0;
1752 *ecx = 0;
1753 *edx = 0x2c307d;
1754 break;
1755 case 4:
1756 /* cache info: needed for Core compatibility */
ce3960eb
AF		 1757 if (cs->nr_cores > 1) {
1758 *eax = (cs->nr_cores - 1) << 26;
c6dc6f63 1759 } else {
2f7a21c4 1760 *eax = 0;
c6dc6f63
AP		 1761 }
1762 switch (count) {
1763 case 0: /* L1 dcache info */
1764 *eax |= 0x0000121;
1765 *ebx = 0x1c0003f;
1766 *ecx = 0x000003f;
1767 *edx = 0x0000001;
1768 break;
1769 case 1: /* L1 icache info */
1770 *eax |= 0x0000122;
1771 *ebx = 0x1c0003f;
1772 *ecx = 0x000003f;
1773 *edx = 0x0000001;
1774 break;
1775 case 2: /* L2 cache info */
1776 *eax |= 0x0000143;
ce3960eb
AF		 1777 if (cs->nr_threads > 1) {
1778 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63
AP		 1779 }
1780 *ebx = 0x3c0003f;
1781 *ecx = 0x0000fff;
1782 *edx = 0x0000001;
1783 break;
1784 default: /* end of info */
1785 *eax = 0;
1786 *ebx = 0;
1787 *ecx = 0;
1788 *edx = 0;
1789 break;
1790 }
1791 break;
1792 case 5:
1793 /* mwait info: needed for Core compatibility */
1794 *eax = 0; /* Smallest monitor-line size in bytes */
1795 *ebx = 0; /* Largest monitor-line size in bytes */
1796 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1797 *edx = 0;
1798 break;
1799 case 6:
1800 /* Thermal and Power Leaf */
1801 *eax = 0;
1802 *ebx = 0;
1803 *ecx = 0;
1804 *edx = 0;
1805 break;
f7911686 1806 case 7:
13526728
EH		 1807 /* Structured Extended Feature Flags Enumeration Leaf */
1808 if (count == 0) {
1809 *eax = 0; /* Maximum ECX value for sub-leaves */
a9321a4d 1810 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
13526728
EH		 1811 *ecx = 0; /* Reserved */
1812 *edx = 0; /* Reserved */
f7911686
YW		 1813 } else {
1814 *eax = 0;
1815 *ebx = 0;
1816 *ecx = 0;
1817 *edx = 0;
1818 }
1819 break;
c6dc6f63
AP		 1820 case 9:
1821 /* Direct Cache Access Information Leaf */
1822 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1823 *ebx = 0;
1824 *ecx = 0;
1825 *edx = 0;
1826 break;
1827 case 0xA:
1828 /* Architectural Performance Monitoring Leaf */
a0fa8208 1829 if (kvm_enabled()) {
a60f24b5 1830 KVMState *s = cs->kvm_state;
a0fa8208
GN		 1831
1832 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1833 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1834 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1835 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1836 } else {
1837 *eax = 0;
1838 *ebx = 0;
1839 *ecx = 0;
1840 *edx = 0;
1841 }
c6dc6f63 1842 break;
51e49430
SY		 1843 case 0xD:
1844 /* Processor Extended State */
1845 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1846 *eax = 0;
1847 *ebx = 0;
1848 *ecx = 0;
1849 *edx = 0;
1850 break;
1851 }
1852 if (kvm_enabled()) {
a60f24b5 1853 KVMState *s = cs->kvm_state;
ba9bc59e
JK		 1854
1855 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1856 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1857 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1858 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1859 } else {
1860 *eax = 0;
1861 *ebx = 0;
1862 *ecx = 0;
1863 *edx = 0;
1864 }
1865 break;
c6dc6f63
AP		 1866 case 0x80000000:
1867 *eax = env->cpuid_xlevel;
1868 *ebx = env->cpuid_vendor1;
1869 *edx = env->cpuid_vendor2;
1870 *ecx = env->cpuid_vendor3;
1871 break;
1872 case 0x80000001:
1873 *eax = env->cpuid_version;
1874 *ebx = 0;
1875 *ecx = env->cpuid_ext3_features;
1876 *edx = env->cpuid_ext2_features;
1877
1878 /* The Linux kernel checks for the CMPLegacy bit and
1879 * discards multiple thread information if it is set.
1880 * So dont set it here for Intel to make Linux guests happy.
1881 */
ce3960eb 1882 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 1883 uint32_t tebx, tecx, tedx;
1884 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1885 if (tebx != CPUID_VENDOR_INTEL_1 ||
1886 tedx != CPUID_VENDOR_INTEL_2 ||
1887 tecx != CPUID_VENDOR_INTEL_3) {
1888 *ecx |= 1 << 1; /* CmpLegacy bit */
1889 }
1890 }
c6dc6f63
AP		 1891 break;
1892 case 0x80000002:
1893 case 0x80000003:
1894 case 0x80000004:
1895 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1896 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1897 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1898 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1899 break;
1900 case 0x80000005:
1901 /* cache info (L1 cache) */
1902 *eax = 0x01ff01ff;
1903 *ebx = 0x01ff01ff;
1904 *ecx = 0x40020140;
1905 *edx = 0x40020140;
1906 break;
1907 case 0x80000006:
1908 /* cache info (L2 cache) */
1909 *eax = 0;
1910 *ebx = 0x42004200;
1911 *ecx = 0x02008140;
1912 *edx = 0;
1913 break;
1914 case 0x80000008:
1915 /* virtual & phys address size in low 2 bytes. */
1916/* XXX: This value must match the one used in the MMU code. */
1917 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1918 /* 64 bit processor */
1919/* XXX: The physical address space is limited to 42 bits in exec.c. */
1920 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1921 } else {
1922 if (env->cpuid_features & CPUID_PSE36)
1923 *eax = 0x00000024; /* 36 bits physical */
1924 else
1925 *eax = 0x00000020; /* 32 bits physical */
1926 }
1927 *ebx = 0;
1928 *ecx = 0;
1929 *edx = 0;
ce3960eb
AF		 1930 if (cs->nr_cores * cs->nr_threads > 1) {
1931 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 1932 }
1933 break;
1934 case 0x8000000A:
9f3fb565
EH		 1935 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1936 *eax = 0x00000001; /* SVM Revision */
1937 *ebx = 0x00000010; /* nr of ASIDs */
1938 *ecx = 0;
1939 *edx = env->cpuid_svm_features; /* optional features */
1940 } else {
1941 *eax = 0;
1942 *ebx = 0;
1943 *ecx = 0;
1944 *edx = 0;
1945 }
c6dc6f63 1946 break;
b3baa152 1947 case 0xC0000000:
1948 *eax = env->cpuid_xlevel2;
1949 *ebx = 0;
1950 *ecx = 0;
1951 *edx = 0;
1952 break;
1953 case 0xC0000001:
1954 /* Support for VIA CPU's CPUID instruction */
1955 *eax = env->cpuid_version;
1956 *ebx = 0;
1957 *ecx = 0;
1958 *edx = env->cpuid_ext4_features;
1959 break;
1960 case 0xC0000002:
1961 case 0xC0000003:
1962 case 0xC0000004:
1963 /* Reserved for the future, and now filled with zero */
1964 *eax = 0;
1965 *ebx = 0;
1966 *ecx = 0;
1967 *edx = 0;
1968 break;
c6dc6f63
AP		 1969 default:
1970 /* reserved values: zero */
1971 *eax = 0;
1972 *ebx = 0;
1973 *ecx = 0;
1974 *edx = 0;
1975 break;
1976 }
1977}
5fd2087a
AF		 1978
1979/* CPUClass::reset() */
1980static void x86_cpu_reset(CPUState *s)
1981{
1982 X86CPU *cpu = X86_CPU(s);
1983 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1984 CPUX86State *env = &cpu->env;
c1958aea
AF		 1985 int i;
1986
1987 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 1988 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
6fd2a026 1989 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
c1958aea 1990 }
5fd2087a
AF		 1991
1992 xcc->parent_reset(s);
1993
c1958aea
AF		 1994
1995 memset(env, 0, offsetof(CPUX86State, breakpoints));
1996
1997 tlb_flush(env, 1);
1998
1999 env->old_exception = -1;
2000
2001 /* init to reset state */
2002
2003#ifdef CONFIG_SOFTMMU
2004 env->hflags |= HF_SOFTMMU_MASK;
2005#endif
2006 env->hflags2 |= HF2_GIF_MASK;
2007
2008 cpu_x86_update_cr0(env, 0x60000010);
2009 env->a20_mask = ~0x0;
2010 env->smbase = 0x30000;
2011
2012 env->idt.limit = 0xffff;
2013 env->gdt.limit = 0xffff;
2014 env->ldt.limit = 0xffff;
2015 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2016 env->tr.limit = 0xffff;
2017 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2018
2019 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2020 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2021 DESC_R_MASK | DESC_A_MASK);
2022 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2023 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2024 DESC_A_MASK);
2025 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2026 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2027 DESC_A_MASK);
2028 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2029 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2030 DESC_A_MASK);
2031 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2032 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2033 DESC_A_MASK);
2034 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2035 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2036 DESC_A_MASK);
2037
2038 env->eip = 0xfff0;
2039 env->regs[R_EDX] = env->cpuid_version;
2040
2041 env->eflags = 0x2;
2042
2043 /* FPU init */
2044 for (i = 0; i < 8; i++) {
2045 env->fptags[i] = 1;
2046 }
2047 env->fpuc = 0x37f;
2048
2049 env->mxcsr = 0x1f80;
2050
2051 env->pat = 0x0007040600070406ULL;
2052 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2053
2054 memset(env->dr, 0, sizeof(env->dr));
2055 env->dr[6] = DR6_FIXED_1;
2056 env->dr[7] = DR7_FIXED_1;
2057 cpu_breakpoint_remove_all(env, BP_CPU);
2058 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 2059
2060#if !defined(CONFIG_USER_ONLY)
2061 /* We hard-wire the BSP to the first CPU. */
55e5c285 2062 if (s->cpu_index == 0) {
dd673288
IM		 2063 apic_designate_bsp(env->apic_state);
2064 }
2065
2066 env->halted = !cpu_is_bsp(cpu);
2067#endif
5fd2087a
AF		 2068}
2069
dd673288
IM		 2070#ifndef CONFIG_USER_ONLY
2071bool cpu_is_bsp(X86CPU *cpu)
2072{
2073 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2074}
65dee380
IM		 2075
2076/* TODO: remove me, when reset over QOM tree is implemented */
2077static void x86_cpu_machine_reset_cb(void *opaque)
2078{
2079 X86CPU *cpu = opaque;
2080 cpu_reset(CPU(cpu));
2081}
dd673288
IM		 2082#endif
2083
de024815
AF		 2084static void mce_init(X86CPU *cpu)
2085{
2086 CPUX86State *cenv = &cpu->env;
2087 unsigned int bank;
2088
2089 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2090 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2091 (CPUID_MCE | CPUID_MCA)) {
2092 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2093 cenv->mcg_ctl = ~(uint64_t)0;
2094 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2095 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2096 }
2097 }
2098}
2099
bdeec802
IM		 2100#define MSI_ADDR_BASE 0xfee00000
2101
2102#ifndef CONFIG_USER_ONLY
2103static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2104{
2105 static int apic_mapped;
2106 CPUX86State *env = &cpu->env;
449994eb 2107 APICCommonState *apic;
bdeec802
IM		 2108 const char *apic_type = "apic";
2109
2110 if (kvm_irqchip_in_kernel()) {
2111 apic_type = "kvm-apic";
2112 } else if (xen_enabled()) {
2113 apic_type = "xen-apic";
2114 }
2115
2116 env->apic_state = qdev_try_create(NULL, apic_type);
2117 if (env->apic_state == NULL) {
2118 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2119 return;
2120 }
2121
2122 object_property_add_child(OBJECT(cpu), "apic",
2123 OBJECT(env->apic_state), NULL);
2124 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2125 /* TODO: convert to link<> */
449994eb 2126 apic = APIC_COMMON(env->apic_state);
60671e58 2127 apic->cpu = cpu;
bdeec802
IM		 2128
2129 if (qdev_init(env->apic_state)) {
2130 error_setg(errp, "APIC device '%s' could not be initialized",
2131 object_get_typename(OBJECT(env->apic_state)));
2132 return;
2133 }
2134
2135 /* XXX: mapping more APICs at the same memory location */
2136 if (apic_mapped == 0) {
2137 /* NOTE: the APIC is directly connected to the CPU - it is not
2138 on the global memory bus. */
2139 /* XXX: what if the base changes? */
2140 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2141 apic_mapped = 1;
2142 }
2143}
2144#endif
2145
7a059953
AF		 2146void x86_cpu_realize(Object *obj, Error **errp)
2147{
2148 X86CPU *cpu = X86_CPU(obj);
b34d12d1
IM		 2149 CPUX86State *env = &cpu->env;
2150
2151 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2152 env->cpuid_level = 7;
2153 }
7a059953 2154
9b15cd9e
IM		 2155 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2156 * CPUID[1].EDX.
2157 */
2158 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2159 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2160 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2161 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2162 env->cpuid_ext2_features |= (env->cpuid_features
2163 & CPUID_EXT2_AMD_ALIASES);
2164 }
2165
4586f157
IM		 2166 if (!kvm_enabled()) {
2167 env->cpuid_features &= TCG_FEATURES;
2168 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2169 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2170#ifdef TARGET_X86_64
2171 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2172#endif
2173 );
2174 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2175 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2176 } else {
2177#ifdef CONFIG_KVM
2178 filter_features_for_kvm(cpu);
2179#endif
2180 }
2181
65dee380
IM		 2182#ifndef CONFIG_USER_ONLY
2183 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802
IM		 2184
2185 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2186 x86_cpu_apic_init(cpu, errp);
2187 if (error_is_set(errp)) {
2188 return;
2189 }
2190 }
65dee380
IM		 2191#endif
2192
7a059953
AF		 2193 mce_init(cpu);
2194 qemu_init_vcpu(&cpu->env);
65dee380 2195 cpu_reset(CPU(cpu));
7a059953
AF		 2196}
2197
de024815
AF		 2198static void x86_cpu_initfn(Object *obj)
2199{
55e5c285 2200 CPUState *cs = CPU(obj);
de024815
AF		 2201 X86CPU *cpu = X86_CPU(obj);
2202 CPUX86State *env = &cpu->env;
d65e9815 2203 static int inited;
de024815
AF		 2204
2205 cpu_exec_init(env);
71ad61d3
AF		 2206
2207 object_property_add(obj, "family", "int",
95b8519d 2208 x86_cpuid_version_get_family,
71ad61d3 2209 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2210 object_property_add(obj, "model", "int",
67e30c83 2211 x86_cpuid_version_get_model,
c5291a4f 2212 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2213 object_property_add(obj, "stepping", "int",
35112e41 2214 x86_cpuid_version_get_stepping,
036e2222 2215 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2216 object_property_add(obj, "level", "int",
2217 x86_cpuid_get_level,
2218 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2219 object_property_add(obj, "xlevel", "int",
2220 x86_cpuid_get_xlevel,
2221 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2222 object_property_add_str(obj, "vendor",
2223 x86_cpuid_get_vendor,
2224 x86_cpuid_set_vendor, NULL);
938d4c25 2225 object_property_add_str(obj, "model-id",
63e886eb 2226 x86_cpuid_get_model_id,
938d4c25 2227 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2228 object_property_add(obj, "tsc-frequency", "int",
2229 x86_cpuid_get_tsc_freq,
2230 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 2231
55e5c285 2232 env->cpuid_apic_id = cs->cpu_index;
d65e9815
IM		 2233
2234 /* init various static tables used in TCG mode */
2235 if (tcg_enabled() && !inited) {
2236 inited = 1;
2237 optimize_flags_init();
2238#ifndef CONFIG_USER_ONLY
2239 cpu_set_debug_excp_handler(breakpoint_handler);
2240#endif
2241 }
de024815
AF		 2242}
2243
5fd2087a
AF		 2244static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2245{
2246 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2247 CPUClass *cc = CPU_CLASS(oc);
2248
2249 xcc->parent_reset = cc->reset;
2250 cc->reset = x86_cpu_reset;
2251}
2252
2253static const TypeInfo x86_cpu_type_info = {
2254 .name = TYPE_X86_CPU,
2255 .parent = TYPE_CPU,
2256 .instance_size = sizeof(X86CPU),
de024815 2257 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 2258 .abstract = false,
2259 .class_size = sizeof(X86CPUClass),
2260 .class_init = x86_cpu_common_class_init,
2261};
2262
2263static void x86_cpu_register_types(void)
2264{
2265 type_register_static(&x86_cpu_type_info);
2266}
2267
2268type_init(x86_cpu_register_types)
Qemu copy for testing