3 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/ArmGicLib.h>
17 #include <Ppi/ArmMpCoreInfo.h>
19 #include "PrePeiCore.h"
22 * This is the main function for secondary cores. They loop around until a non Null value is written to
23 * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
24 * Note:The secondary cores, while executing secondary_main, assumes that:
25 * : SGI 0 is configured as Non-secure interrupt
26 * : Priority Mask is configured to allow SGI 0
27 * : Interrupt Distributor and CPU interfaces are enabled
39 EFI_PEI_PPI_DESCRIPTOR
*PpiList
;
40 ARM_MP_CORE_INFO_PPI
*ArmMpCoreInfoPpi
;
43 ARM_CORE_INFO
*ArmCoreInfoTable
;
46 VOID (*SecondaryStart
)(VOID
);
47 UINTN SecondaryEntryAddr
;
48 UINTN AcknowledgeInterrupt
;
51 ClusterId
= GET_CLUSTER_ID(MpId
);
52 CoreId
= GET_CORE_ID(MpId
);
54 // Get the gArmMpCoreInfoPpiGuid
56 ArmPlatformGetPlatformPpiList (&PpiListSize
, &PpiList
);
57 PpiListCount
= PpiListSize
/ sizeof(EFI_PEI_PPI_DESCRIPTOR
);
58 for (Index
= 0; Index
< PpiListCount
; Index
++, PpiList
++) {
59 if (CompareGuid (PpiList
->Guid
, &gArmMpCoreInfoPpiGuid
) == TRUE
) {
64 // On MP Core Platform we must implement the ARM MP Core Info PPI
65 ASSERT (Index
!= PpiListCount
);
67 ArmMpCoreInfoPpi
= PpiList
->Ppi
;
69 Status
= ArmMpCoreInfoPpi
->GetMpCoreInfo (&ArmCoreCount
, &ArmCoreInfoTable
);
70 ASSERT_EFI_ERROR (Status
);
72 // Find the core in the ArmCoreTable
73 for (Index
= 0; Index
< ArmCoreCount
; Index
++) {
74 if ((ArmCoreInfoTable
[Index
].ClusterId
== ClusterId
) && (ArmCoreInfoTable
[Index
].CoreId
== CoreId
)) {
79 // The ARM Core Info Table must define every core
80 ASSERT (Index
!= ArmCoreCount
);
82 // Clear Secondary cores MailBox
83 MmioWrite32 (ArmCoreInfoTable
[Index
].MailboxClearAddress
, ArmCoreInfoTable
[Index
].MailboxClearValue
);
89 SecondaryEntryAddr
= MmioRead32 (ArmCoreInfoTable
[Index
].MailboxGetAddress
);
91 // Acknowledge the interrupt and send End of Interrupt signal.
92 AcknowledgeInterrupt
= ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase
), &InterruptId
);
93 // Check if it is a valid interrupt ID
94 if (InterruptId
< ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase
))) {
95 // Got a valid SGI number hence signal End of Interrupt
96 ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase
), AcknowledgeInterrupt
);
98 } while (SecondaryEntryAddr
== 0);
100 // Jump to secondary core entry point.
101 SecondaryStart
= (VOID (*)())SecondaryEntryAddr
;
104 // The secondaries shouldn't reach here
111 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
114 EFI_SEC_PEI_HAND_OFF SecCoreData
;
116 EFI_PEI_PPI_DESCRIPTOR
*PpiList
;
117 UINTN TemporaryRamBase
;
118 UINTN TemporaryRamSize
;
120 CreatePpiList (&PpiListSize
, &PpiList
);
122 // Enable the GIC Distributor
123 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase
));
125 // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
126 if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores
)) {
127 // Sending SGI to all the Secondary CPU interfaces
128 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E, PcdGet32 (PcdGicSgiIntId
));
131 // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
132 // the base of the primary core stack
133 PpiListSize
= ALIGN_VALUE(PpiListSize
, CPU_STACK_ALIGNMENT
);
134 TemporaryRamBase
= (UINTN
)PcdGet64 (PcdCPUCoresStackBase
) + PpiListSize
;
135 TemporaryRamSize
= (UINTN
)PcdGet32 (PcdCPUCorePrimaryStackSize
) - PpiListSize
;
138 // Bind this information into the SEC hand-off state
139 // Note: this must be in sync with the stuff in the asm file
140 // Note also: HOBs (pei temp ram) MUST be above stack
142 SecCoreData
.DataSize
= sizeof(EFI_SEC_PEI_HAND_OFF
);
143 SecCoreData
.BootFirmwareVolumeBase
= (VOID
*)(UINTN
)PcdGet64 (PcdFvBaseAddress
);
144 SecCoreData
.BootFirmwareVolumeSize
= PcdGet32 (PcdFvSize
);
145 SecCoreData
.TemporaryRamBase
= (VOID
*)TemporaryRamBase
; // We run on the primary core (and so we use the first stack)
146 SecCoreData
.TemporaryRamSize
= TemporaryRamSize
;
147 SecCoreData
.PeiTemporaryRamBase
= SecCoreData
.TemporaryRamBase
;
148 SecCoreData
.PeiTemporaryRamSize
= ALIGN_VALUE (SecCoreData
.TemporaryRamSize
/ 2, CPU_STACK_ALIGNMENT
);
149 SecCoreData
.StackBase
= (VOID
*)((UINTN
)SecCoreData
.TemporaryRamBase
+ SecCoreData
.PeiTemporaryRamSize
);
150 SecCoreData
.StackSize
= (TemporaryRamBase
+ TemporaryRamSize
) - (UINTN
)SecCoreData
.StackBase
;
152 // Jump to PEI core entry point
153 PeiCoreEntryPoint (&SecCoreData
, PpiList
);