Cleanup Cache an MMU operations.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10348 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index 43f9e8a7e81de4152750600cd859ce1199ae5260..c9dbce3e1248e9ba4c48904fc5d2b601cded4ca2 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -41,6 +41,7 @@
 .set IC_ON, (0x1<<12)
 
 
+
 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line       
   dsb
@@ -83,17 +84,8 @@ ASM_PFX(ArmCleanDataCacheEntryBySetWay):
   bx      lr
 
 
-ASM_PFX(ArmDrainWriteBuffer):
-  mcr     p15, 0, r0, c7, c10, 4       @ Drain write buffer for sync
-  dsb
-  isb
-  bx      lr
-  
-
 ASM_PFX(ArmInvalidateInstructionCache):
-  mov     R0,#0
   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
-  mov     R0,#0
   dsb
   isb
   bx      LR
@@ -109,16 +101,15 @@ ASM_PFX(ArmEnableMmu):
 ASM_PFX(ArmMmuEnabled):
   mrc     p15,0,R0,c1,c0,0
   and     R0,R0,#1
-  isb
   bx      LR
 
-
 ASM_PFX(ArmDisableMmu):
-  mov     R0,#0
-  mcr     p15,0,R0,c13,c0,0     @FCSE PID register must be cleared before disabling MMU
   mrc     p15,0,R0,c1,c0,0
   bic     R0,R0,#1
   mcr     p15,0,R0,c1,c0,0      @Disable MMU
+
+       mcr             p15,0,R0,c8,c7,0      @Invalidate TLB
+  mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
   dsb
   isb
   bx      LR
@@ -225,6 +216,7 @@ L_Skip:
   bgt   Loop1
   
 L_Finished:
+  dsb
   ldmfd SP!, {r4-r12, lr}
   bx    LR
 
@@ -233,6 +225,7 @@ ASM_PFX(ArmDataMemoryBarrier):
   bx      LR
   
 ASM_PFX(ArmDataSyncronizationBarrier):
+ASM_PFX(ArmDrainWriteBuffer):
   dsb
   bx      LR
   

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 72f4ec2cf54970b409476e14a2c31db1d30c5713..6d65b7e7278be7c2c4a6f1c2d7f93a48c4182bad 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -84,17 +84,8 @@ ArmCleanDataCacheEntryBySetWay
   bx      lr
 
 
-ArmDrainWriteBuffer
-  mcr     p15, 0, r0, c7, c10, 4       ; Drain write buffer for sync
-  dsb
-  isb
-  bx      lr
-
-
 ArmInvalidateInstructionCache
-  mov     R0,#0
   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
-  mov     R0,#0
   dsb
   isb
   bx      LR
@@ -110,15 +101,15 @@ ArmEnableMmu
 ArmMmuEnabled
   mrc     p15,0,R0,c1,c0,0
   and     R0,R0,#1
-  isb
   bx      LR
 
 ArmDisableMmu
-  mov     R0,#0
-  mcr     p15,0,R0,c13,c0,0     ;FCSE PID register must be cleared before disabling MMU
   mrc     p15,0,R0,c1,c0,0
   bic     R0,R0,#1
   mcr     p15,0,R0,c1,c0,0      ;Disable MMU
+
+       mcr             p15,0,R0,c8,c7,0      ;Invalidate TLB
+  mcr     p15,0,R0,c7,c5,6      ;Invalidate Branch predictor array
   dsb
   isb
   bx      LR
@@ -127,7 +118,7 @@ ArmEnableDataCache
   ldr     R1,=DC_ON
   mrc     p15,0,R0,c1,c0,0      ;Read control register configuration data
   orr     R0,R0,R1              ;Set C bit
-  mcr     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  mcr     p15,0,R0,c1,c0,0      ;Write control register configuration data
   dsb
   isb
   bx      LR
@@ -136,7 +127,7 @@ ArmDisableDataCache
   ldr     R1,=DC_ON
   mrc     p15,0,R0,c1,c0,0      ;Read control register configuration data
   bic     R0,R0,R1              ;Clear C bit
-  mcr     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  mcr     p15,0,R0,c1,c0,0      ;Write control register configuration data
   isb
   bx      LR
 
@@ -144,7 +135,7 @@ ArmEnableInstructionCache
   ldr     R1,=IC_ON
   mrc     p15,0,R0,c1,c0,0      ;Read control register configuration data
   orr     R0,R0,R1              ;Set I bit
-  mcr     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  mcr     p15,0,R0,c1,c0,0      ;Write control register configuration data
   dsb
   isb
   bx      LR
@@ -153,7 +144,7 @@ ArmDisableInstructionCache
   ldr     R1,=IC_ON
   mrc     p15,0,R0,c1,c0,0     ;Read control register configuration data
   BIC     R0,R0,R1             ;Clear I bit.
-  mcr     p15,0,r0,c1,c0,0     ;Write control register configuration data
+  mcr     p15,0,R0,c1,c0,0     ;Write control register configuration data
   isb
   bx      LR
 
@@ -217,6 +208,7 @@ Skip
   bgt   Loop1
   
 Finished
+  dsb
   ldmfd SP!, {r4-r12, lr}
   bx    LR
 
@@ -226,6 +218,7 @@ ArmDataMemoryBarrier
   bx      LR
   
 ArmDataSyncronizationBarrier
+ArmDrainWriteBuffer
   dsb
   bx      LR