[mirror_edk2.git] / ArmPkg / ArmPkg.dec

#/** @file\r
# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.\r
#\r
#    SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
#**/\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = ArmPkg\r
  PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
  PACKAGE_VERSION                = 0.1\r
\r
################################################################################\r
#\r
# Include Section - list of Include Paths that are provided by this package.\r
#                   Comments are used for Keywords and Module Types.\r
#\r
# Supported Module Types:\r
#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
#\r
################################################################################\r
[Includes.common]\r
  Include                        # Root include for the package\r
\r
[LibraryClasses.common]\r
  ArmLib|Include/Library/ArmLib.h\r
  ArmMmuLib|Include/Library/ArmMmuLib.h\r
  SemihostLib|Include/Library/Semihosting.h\r
  DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
  ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
  ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
  ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h\r
  ArmSvcLib|Include/Library/ArmSvcLib.h\r
  OpteeLib|Include/Library/OpteeLib.h\r
  StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r
\r
[Guids.common]\r
  gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
\r
  ## ARM MPCore table\r
  # Include/Guid/ArmMpCoreInfo.h\r
  gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
\r
[Protocols.common]\r
  ## Arm System Control and Management Interface(SCMI) Base protocol\r
  ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r
  gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r
\r
  ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
  ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r
  gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r
  gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r
\r
  ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
  ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r
  gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r
\r
[Ppis]\r
  ## Include/Ppi/ArmMpCoreInfo.h\r
  gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
\r
[PcdsFeatureFlag.common]\r
  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
\r
  # On ARM Architecture with the Security Extension, the address for the\r
  # Vector Table can be mapped anywhere in the memory map. It means we can\r
  # point the Exception Vector Table to its location in CpuDxe.\r
  # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)\r
  gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r
  # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
  # it has been configured by the CPU DXE\r
  gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
\r
  # Define if the GICv3 controller should use the GICv2 legacy\r
  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
\r
[PcdsFeatureFlag.ARM]\r
  # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
  # TRUE may be appropriate to fix performance problems if you don't care about\r
  # hardware coherency (i.e., no virtualization or cache coherent DMA)\r
  gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r
\r
[PcdsFixedAtBuild.common]\r
  gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r
\r
  # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
  # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
  gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
\r
  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r
  gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
  #\r
  # ARM Secure Firmware PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r
  gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r
  gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r
  gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r
\r
  #\r
  # ARM Hypervisor Firmware PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r
  gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
  gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
  gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r
\r
  # Use ClusterId + CoreId to identify the PrimaryCore\r
  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
  # The Primary Core is ClusterId[0] & CoreId[0]\r
  gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r
\r
  #\r
  # ARM L2x0 PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
\r
  #\r
  # ARM Normal (or Non Secure) Firmware PCDs\r
  #\r
  gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
  gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
\r
  #\r
  # Value to add to a host address to obtain a device address, using\r
  # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r
  # means we can rely on truncation on overflow to specify negative\r
  # offsets.\r
  #\r
  gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r
\r
[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
  gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
  gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
\r
[PcdsFixedAtBuild.ARM]\r
  #\r
  # ARM Security Extension\r
  #\r
\r
  # Secure Configuration Register\r
  # - BIT0 : NS - Non Secure bit\r
  # - BIT1 : IRQ Handler\r
  # - BIT2 : FIQ Handler\r
  # - BIT3 : EA - External Abort\r
  # - BIT4 : FW - F bit writable\r
  # - BIT5 : AW - A bit writable\r
  # - BIT6 : nET - Not Early Termination\r
  # - BIT7 : SCD - Secure Monitor Call Disable\r
  # - BIT8 : HCE - Hyp Call enable\r
  # - BIT9 : SIF - Secure Instruction Fetch\r
  # 0x31 = NS | EA | FW\r
  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
\r
  # By default we do not do a transition to non-secure mode\r
  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
\r
  # Non Secure Access Control Register\r
  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
  # 0xC00 = cp10 | cp11\r
  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
\r
[PcdsFixedAtBuild.AARCH64]\r
  #\r
  # AArch64 Security Extension\r
  #\r
\r
  # Secure Configuration Register\r
  # - BIT0 : NS - Non Secure bit\r
  # - BIT1 : IRQ Handler\r
  # - BIT2 : FIQ Handler\r
  # - BIT3 : EA - External Abort\r
  # - BIT4 : FW - F bit writable\r
  # - BIT5 : AW - A bit writable\r
  # - BIT6 : nET - Not Early Termination\r
  # - BIT7 : SCD - Secure Monitor Call Disable\r
  # - BIT8 : HCE - Hyp Call enable\r
  # - BIT9 : SIF - Secure Instruction Fetch\r
  # - BIT10: RW -  Register width control for lower exception levels\r
  # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
  # - BIT12: TWI - Trap WFI\r
  # - BIT13: TWE - Trap WFE\r
  # 0x501 = NS | HCE | RW\r
  gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
\r
  # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
  #        Mode Description              Bits\r
  # NS EL2 SP2 all interrupts disabled =  0x3c9\r
  # NS EL1 SP1 all interrupts disabled =  0x3c5\r
  # Other modes include using SP0 or switching to Aarch32, but these are\r
  # not currently supported.\r
  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
\r
\r
#\r
# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
# redefined when using UEFI in a context of virtual machine.\r
#\r
[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
\r
  # System Memory (DRAM): These PCDs define the region of in-built system memory\r
  # Some platforms can get DRAM extensions, these additional regions may be\r
  # declared to UEFI using separate resource descriptor HOBs\r
  gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
  gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
\r
  gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r
  gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r
\r
[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
  #\r
  # ARM Architectural Timer\r
  #\r
  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r
\r
  # ARM Architectural Timer Interrupt(GIC PPI) numbers\r
  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r
  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
\r
  #\r
  # ARM Generic Watchdog\r
  #\r
\r
  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r
  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r
  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
\r
  #\r
  # ARM Generic Interrupt Controller\r
  #\r
  gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r
  # Base address for the GIC Redistributor region that contains the boot CPU\r
  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r
  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r
  gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
\r
  #\r
  # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
  # Note that "IO" is just another MMIO range that simulates IO space; there\r
  # are no special instructions to access it.\r
  #\r
  # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
  # specific to their containing address spaces. In order to get the physical\r
  # address for the CPU, for a given access, the respective translation value\r
  # has to be added.\r
  #\r
  # The translations always have to be initialized like this, using UINT64:\r
  #\r
  #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space\r
  #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
  #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
  #\r
  #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;\r
  #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
  #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
  #\r
  # because (a) the target address space (ie. the cpu-physical space) is\r
  # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
  # arithmetic.\r
  #\r
  # Accordingly, the translation itself needs to be implemented as:\r
  #\r
  #   UINT64 UntranslatedIoAddress;     // input parameter\r
  #   UINT32 UntranslatedMmio32Address; // input parameter\r
  #   UINT64 UntranslatedMmio64Address; // input parameter\r
  #\r
  #   UINT64 TranslatedIoAddress;       // output parameter\r
  #   UINT64 TranslatedMmio32Address;   // output parameter\r
  #   UINT64 TranslatedMmio64Address;   // output parameter\r
  #\r
  #   TranslatedIoAddress     = UntranslatedIoAddress +\r
  #                             PcdPciIoTranslation;\r
  #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
  #                             PcdPciMmio32Translation;\r
  #   TranslatedMmio64Address = UntranslatedMmio64Address +\r
  #                             PcdPciMmio64Translation;\r
  #\r
  #  The modular arithmetic performed in UINT64 ensures that the translation\r
  #  works correctly regardless of the relation between IoCpuBase and\r
  #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
  #  PcdPciMmio64Base.\r
  #\r
  gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
  gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
  gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
  gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
  gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
  gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
  gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
  gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
  gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
\r
  #\r
  # Inclusive range of allowed PCI buses.\r
  #\r
  gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
  gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r
Commit	Line	Data
8bbf0f09 A	1	#/** @file\r
	2	# ARM processor package.\r
	3	#\r
d6ebcab7	4	# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
38a00bae	5	# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.\r
8bbf0f09	6	#\r
4059386c	7	# SPDX-License-Identifier: BSD-2-Clause-Patent\r
8bbf0f09 A	8	#\r
	9	#**/\r
	10	\r
2ef2b01e A	11	[Defines]\r
	12	DEC_SPECIFICATION = 0x00010005\r
	13	PACKAGE_NAME = ArmPkg\r
	14	PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
	15	PACKAGE_VERSION = 0.1\r
	16	\r
	17	################################################################################\r
	18	#\r
	19	# Include Section - list of Include Paths that are provided by this package.\r
	20	# Comments are used for Keywords and Module Types.\r
	21	#\r
	22	# Supported Module Types:\r
	23	# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
	24	#\r
	25	################################################################################\r
	26	[Includes.common]\r
	27	Include # Root include for the package\r
	28	\r
	29	[LibraryClasses.common]\r
8bbf0f09	30	ArmLib\|Include/Library/ArmLib.h\r
12728e11	31	ArmMmuLib\|Include/Library/ArmMmuLib.h\r
2ef2b01e	32	SemihostLib\|Include/Library/Semihosting.h\r
11c20f4e	33	DefaultExceptionHandlerLib\|Include/Library/DefaultExceptionHandlerLib.h\r
097bd461	34	ArmDisassemblerLib\|Include/Library/ArmDisassemblerLib.h\r
8d13298b	35	ArmGicArchLib\|Include/Library/ArmGicArchLib.h\r
38a00bae	36	ArmMtlLib\|ArmPlatformPkg/Include/Library/ArmMtlLib.h\r
4d163696	37	ArmSvcLib\|Include/Library/ArmSvcLib.h\r
d65b78f1	38	OpteeLib\|Include/Library/OpteeLib.h\r
eed947be	39	StandaloneMmMmuLib\|Include/Library/StandaloneMmMmuLib.h\r
c32aaba9	40	\r
2ef2b01e A	41	[Guids.common]\r
	42	gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
	43	\r
44788bae	44	## ARM MPCore table\r
	45	# Include/Guid/ArmMpCoreInfo.h\r
	46	gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
	47	\r
4f2494cf GP	48	[Protocols.common]\r
	49	## Arm System Control and Management Interface(SCMI) Base protocol\r
	50	## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r
	51	gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r
	52	\r
	53	## Arm System Control and Management Interface(SCMI) Clock management protocol\r
	54	## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r
	55	gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r
559a07d8	56	gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r
4f2494cf GP	57	\r
	58	## Arm System Control and Management Interface(SCMI) Clock management protocol\r
	59	## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r
	60	gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r
	61	\r
44788bae	62	[Ppis]\r
	63	## Include/Ppi/ArmMpCoreInfo.h\r
	64	gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
	65	\r
2ef2b01e A	66	[PcdsFeatureFlag.common]\r
	67	gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport\|FALSE\|BOOLEAN\|0x00000001\r
	68	\r
1bfda055	69	# On ARM Architecture with the Security Extension, the address for the\r
	70	# Vector Table can be mapped anywhere in the memory map. It means we can\r
	71	# point the Exception Vector Table to its location in CpuDxe.\r
f0bbcdf8	72	# By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r
1bfda055	73	gArmTokenSpaceGuid.PcdRelocateVectorTable\|TRUE\|BOOLEAN\|0x00000022\r
eeec69c5	74	# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r
	75	# it has been configured by the CPU DXE\r
	76	gArmTokenSpaceGuid.PcdDebuggerExceptionSupport\|FALSE\|BOOLEAN\|0x00000032\r
c32aaba9	77	\r
f6d46e29 AB	78	# Define if the GICv3 controller should use the GICv2 legacy\r
	79	gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy\|FALSE\|BOOLEAN\|0x00000042\r
	80	\r
65ceda91 AB	81	[PcdsFeatureFlag.ARM]\r
	82	# Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
	83	# TRUE may be appropriate to fix performance problems if you don't care about\r
	84	# hardware coherency (i.e., no virtualization or cache coherent DMA)\r
	85	gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride\|FALSE\|BOOLEAN\|0x00000043\r
	86	\r
2ef2b01e	87	[PcdsFixedAtBuild.common]\r
12c5ae23	88	gArmTokenSpaceGuid.PcdTrustzoneSupport\|FALSE\|BOOLEAN\|0x00000006\r
12c5ae23	89	\r
1bfda055	90	# This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r
	91	# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
	92	gArmTokenSpaceGuid.PcdVFPEnabled\|0\|UINT32\|0x00000024\r
	93	\r
f0bbcdf8	94	gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\|0xffff0000\|UINT64\|0x00000004\r
2ef2b01e	95	gArmTokenSpaceGuid.PcdCpuResetAddress\|0x00000000\|UINT32\|0x00000005\r
c32aaba9	96	\r
1bfda055	97	#\r
262a9b04	98	# ARM Secure Firmware PCDs\r
1bfda055	99	#\r
bb5420bb	100	gArmTokenSpaceGuid.PcdSecureFdBaseAddress\|0\|UINT64\|0x00000015\r
1bfda055	101	gArmTokenSpaceGuid.PcdSecureFdSize\|0\|UINT32\|0x00000016\r
bb5420bb	102	gArmTokenSpaceGuid.PcdSecureFvBaseAddress\|0x0\|UINT64\|0x0000002F\r
1ad14bc8	103	gArmTokenSpaceGuid.PcdSecureFvSize\|0x0\|UINT32\|0x00000030\r
1bfda055	104	\r
7245b435	105	#\r
7245b435	106	# ARM Hypervisor Firmware PCDs\r
c32aaba9	107	#\r
7245b435	108	gArmTokenSpaceGuid.PcdHypFdBaseAddress\|0\|UINT32\|0x0000003A\r
	109	gArmTokenSpaceGuid.PcdHypFdSize\|0\|UINT32\|0x0000003B\r
	110	gArmTokenSpaceGuid.PcdHypFvBaseAddress\|0\|UINT32\|0x0000003C\r
	111	gArmTokenSpaceGuid.PcdHypFvSize\|0\|UINT32\|0x0000003D\r
d6dc67ba	112	\r
0787bc61	113	# Use ClusterId + CoreId to identify the PrimaryCore\r
0787bc61	114	gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\|0xF03\|UINT32\|0x00000031\r
c32aaba9	115	# The Primary Core is ClusterId[0] & CoreId[0]\r
0787bc61	116	gArmTokenSpaceGuid.PcdArmPrimaryCore\|0\|UINT32\|0x00000037\r
0787bc61	117	\r
1bfda055	118	#\r
	119	# ARM L2x0 PCDs\r
	120	#\r
	121	gArmTokenSpaceGuid.PcdL2x0ControllerBase\|0\|UINT32\|0x0000001B\r
c32aaba9	122	\r
523b5266 AB	123	#\r
	124	# ARM Normal (or Non Secure) Firmware PCDs\r
	125	#\r
	126	gArmTokenSpaceGuid.PcdFdSize\|0\|UINT32\|0x0000002C\r
	127	gArmTokenSpaceGuid.PcdFvSize\|0\|UINT32\|0x0000002E\r
	128	\r
bfe34275 AB	129	#\r
	130	# Value to add to a host address to obtain a device address, using\r
	131	# unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r
	132	# means we can rely on truncation on overflow to specify negative\r
	133	# offsets.\r
	134	#\r
	135	gArmTokenSpaceGuid.PcdArmDmaDeviceOffset\|0x0\|UINT64\|0x0000044\r
	136	\r
523b5266 AB	137	[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
	138	gArmTokenSpaceGuid.PcdFdBaseAddress\|0\|UINT64\|0x0000002B\r
	139	gArmTokenSpaceGuid.PcdFvBaseAddress\|0\|UINT64\|0x0000002D\r
387653a4	140	\r
387653a4	141	[PcdsFixedAtBuild.ARM]\r
cc935544 OM	142	#\r
	143	# ARM Security Extension\r
	144	#\r
	145	\r
	146	# Secure Configuration Register\r
	147	# - BIT0 : NS - Non Secure bit\r
	148	# - BIT1 : IRQ Handler\r
	149	# - BIT2 : FIQ Handler\r
	150	# - BIT3 : EA - External Abort\r
	151	# - BIT4 : FW - F bit writable\r
	152	# - BIT5 : AW - A bit writable\r
	153	# - BIT6 : nET - Not Early Termination\r
	154	# - BIT7 : SCD - Secure Monitor Call Disable\r
	155	# - BIT8 : HCE - Hyp Call enable\r
	156	# - BIT9 : SIF - Secure Instruction Fetch\r
	157	# 0x31 = NS \| EA \| FW\r
	158	gArmTokenSpaceGuid.PcdArmScr\|0x31\|UINT32\|0x00000038\r
	159	\r
387653a4	160	# By default we do not do a transition to non-secure mode\r
387653a4	161	gArmTokenSpaceGuid.PcdArmNonSecModeTransition\|0x0\|UINT32\|0x0000003E\r
2425e1d4	162	\r
d6dc67ba OM	163	# Non Secure Access Control Register\r
	164	# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
	165	# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
	166	# - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r
	167	# - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r
	168	# 0xC00 = cp10 \| cp11\r
	169	gArmTokenSpaceGuid.PcdArmNsacr\|0xC00\|UINT32\|0x00000039\r
	170	\r
25402f5d	171	[PcdsFixedAtBuild.AARCH64]\r
cc935544 OM	172	#\r
	173	# AArch64 Security Extension\r
	174	#\r
	175	\r
	176	# Secure Configuration Register\r
	177	# - BIT0 : NS - Non Secure bit\r
	178	# - BIT1 : IRQ Handler\r
	179	# - BIT2 : FIQ Handler\r
	180	# - BIT3 : EA - External Abort\r
	181	# - BIT4 : FW - F bit writable\r
	182	# - BIT5 : AW - A bit writable\r
	183	# - BIT6 : nET - Not Early Termination\r
	184	# - BIT7 : SCD - Secure Monitor Call Disable\r
	185	# - BIT8 : HCE - Hyp Call enable\r
	186	# - BIT9 : SIF - Secure Instruction Fetch\r
	187	# - BIT10: RW - Register width control for lower exception levels\r
	188	# - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
	189	# - BIT12: TWI - Trap WFI\r
	190	# - BIT13: TWE - Trap WFE\r
	191	# 0x501 = NS \| HCE \| RW\r
	192	gArmTokenSpaceGuid.PcdArmScr\|0x501\|UINT32\|0x00000038\r
	193	\r
25402f5d HL	194	# By default we do transition to EL2 non-secure mode with Stack for EL2.\r
25402f5d HL	195	# Mode Description Bits\r
c32aaba9 OM	196	# NS EL2 SP2 all interrupts disabled = 0x3c9\r
c32aaba9 OM	197	# NS EL1 SP1 all interrupts disabled = 0x3c5\r
25402f5d HL	198	# Other modes include using SP0 or switching to Aarch32, but these are\r
	199	# not currently supported.\r
	200	gArmTokenSpaceGuid.PcdArmNonSecModeTransition\|0x3c9\|UINT32\|0x0000003E\r
e1e2e66c AB	201	\r
e1e2e66c AB	202	\r
dc63be24	203	#\r
523b5266 AB	204	# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
523b5266 AB	205	# redefined when using UEFI in a context of virtual machine.\r
dc63be24	206	#\r
523b5266 AB	207	[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
523b5266 AB	208	\r
f8d7d6e1	209	# System Memory (DRAM): These PCDs define the region of in-built system memory\r
142fa386 AB	210	# Some platforms can get DRAM extensions, these additional regions may be\r
142fa386 AB	211	# declared to UEFI using separate resource descriptor HOBs\r
f8d7d6e1 AB	212	gArmTokenSpaceGuid.PcdSystemMemoryBase\|0\|UINT64\|0x00000029\r
	213	gArmTokenSpaceGuid.PcdSystemMemorySize\|0\|UINT64\|0x0000002A\r
	214	\r
767febf8 AG	215	gArmTokenSpaceGuid.PcdMmBufferBase\|0\|UINT64\|0x00000045\r
	216	gArmTokenSpaceGuid.PcdMmBufferSize\|0\|UINT64\|0x00000046\r
	217	\r
523b5266	218	[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
e1e2e66c AB	219	#\r
	220	# ARM Architectural Timer\r
	221	#\r
	222	gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz\|0\|UINT32\|0x00000034\r
	223	\r
	224	# ARM Architectural Timer Interrupt(GIC PPI) numbers\r
	225	gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum\|29\|UINT32\|0x00000035\r
	226	gArmTokenSpaceGuid.PcdArmArchTimerIntrNum\|30\|UINT32\|0x00000036\r
	227	gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum\|26\|UINT32\|0x00000040\r
	228	gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum\|27\|UINT32\|0x00000041\r
dc63be24	229	\r
0b4d97a0 RC	230	#\r
	231	# ARM Generic Watchdog\r
	232	#\r
	233	\r
7c609a14 A	234	gArmTokenSpaceGuid.PcdGenericWatchdogControlBase\|0x2A440000\|UINT64\|0x00000007\r
7c609a14 A	235	gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase\|0x2A450000\|UINT64\|0x00000008\r
0b4d97a0 RC	236	gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum\|93\|UINT32\|0x00000009\r
0b4d97a0 RC	237	\r
dc63be24 AB	238	#\r
	239	# ARM Generic Interrupt Controller\r
	240	#\r
8a1f2378	241	gArmTokenSpaceGuid.PcdGicDistributorBase\|0\|UINT64\|0x0000000C\r
919697ae	242	# Base address for the GIC Redistributor region that contains the boot CPU\r
8a1f2378 DC	243	gArmTokenSpaceGuid.PcdGicRedistributorsBase\|0\|UINT64\|0x0000000E\r
8a1f2378 DC	244	gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\|0\|UINT64\|0x0000000D\r
dc63be24	245	gArmTokenSpaceGuid.PcdGicSgiIntId\|0\|UINT32\|0x00000025\r
d7c06eb0 AB	246	\r
	247	#\r
	248	# Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
	249	# Note that "IO" is just another MMIO range that simulates IO space; there\r
	250	# are no special instructions to access it.\r
	251	#\r
	252	# The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
	253	# specific to their containing address spaces. In order to get the physical\r
	254	# address for the CPU, for a given access, the respective translation value\r
	255	# has to be added.\r
	256	#\r
	257	# The translations always have to be initialized like this, using UINT64:\r
	258	#\r
	259	# UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
	260	# UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
	261	# UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
	262	#\r
	263	# PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
	264	# PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
	265	# PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
	266	#\r
	267	# because (a) the target address space (ie. the cpu-physical space) is\r
	268	# 64-bit, and (b) the translation values are meant as offsets for modular\r
	269	# arithmetic.\r
	270	#\r
	271	# Accordingly, the translation itself needs to be implemented as:\r
	272	#\r
	273	# UINT64 UntranslatedIoAddress; // input parameter\r
	274	# UINT32 UntranslatedMmio32Address; // input parameter\r
	275	# UINT64 UntranslatedMmio64Address; // input parameter\r
	276	#\r
	277	# UINT64 TranslatedIoAddress; // output parameter\r
	278	# UINT64 TranslatedMmio32Address; // output parameter\r
	279	# UINT64 TranslatedMmio64Address; // output parameter\r
	280	#\r
	281	# TranslatedIoAddress = UntranslatedIoAddress +\r
	282	# PcdPciIoTranslation;\r
	283	# TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
	284	# PcdPciMmio32Translation;\r
	285	# TranslatedMmio64Address = UntranslatedMmio64Address +\r
	286	# PcdPciMmio64Translation;\r
	287	#\r
	288	# The modular arithmetic performed in UINT64 ensures that the translation\r
	289	# works correctly regardless of the relation between IoCpuBase and\r
	290	# PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
	291	# PcdPciMmio64Base.\r
	292	#\r
	293	gArmTokenSpaceGuid.PcdPciIoBase\|0x0\|UINT64\|0x00000050\r
	294	gArmTokenSpaceGuid.PcdPciIoSize\|0x0\|UINT64\|0x00000051\r
	295	gArmTokenSpaceGuid.PcdPciIoTranslation\|0x0\|UINT64\|0x00000052\r
	296	gArmTokenSpaceGuid.PcdPciMmio32Base\|0x0\|UINT32\|0x00000053\r
	297	gArmTokenSpaceGuid.PcdPciMmio32Size\|0x0\|UINT32\|0x00000054\r
	298	gArmTokenSpaceGuid.PcdPciMmio32Translation\|0x0\|UINT64\|0x00000055\r
	299	gArmTokenSpaceGuid.PcdPciMmio64Base\|0x0\|UINT64\|0x00000056\r
	300	gArmTokenSpaceGuid.PcdPciMmio64Size\|0x0\|UINT64\|0x00000057\r
	301	gArmTokenSpaceGuid.PcdPciMmio64Translation\|0x0\|UINT64\|0x00000058\r
	302	\r
	303	#\r
	304	# Inclusive range of allowed PCI buses.\r
	305	#\r
	306	gArmTokenSpaceGuid.PcdPciBusMin\|0x0\|UINT32\|0x00000059\r
	307	gArmTokenSpaceGuid.PcdPciBusMax\|0x0\|UINT32\|0x0000005A\r