[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h

/** @file\r
*\r
*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef __ARMGIC_H\r
#define __ARMGIC_H\r
\r
#include <Library/ArmGicArchLib.h>\r
\r
// GIC Distributor\r
#define ARM_GIC_ICDDCR          0x000 // Distributor Control Register\r
#define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
#define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register\r
\r
// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
#define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers\r
#define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers\r
#define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers\r
#define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers\r
#define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers\r
#define ARM_GIC_ICDABR          0x300 // Active Bit Registers\r
\r
// Each reg base below repeats for Number of interrupts / 4\r
#define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers\r
\r
// Each reg base below repeats for Number of interrupts\r
#define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers\r
#define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers\r
\r
#define ARM_GIC_ICDPPISR        0xD00 // PPI Status register\r
\r
// just one of these\r
#define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register\r
\r
// GICv3 specific registers\r
#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers\r
\r
// GICD_CTLR bits\r
#define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)\r
#define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)\r
\r
// GICD_ICDICFR bits\r
#define ARM_GIC_ICDICFR_WIDTH            32   // ICDICFR is a 32 bit register\r
#define ARM_GIC_ICDICFR_BYTES            (ARM_GIC_ICDICFR_WIDTH / 8)\r
#define ARM_GIC_ICDICFR_F_WIDTH          2    // Each F field is 2 bits\r
#define ARM_GIC_ICDICFR_F_STRIDE         16   // (32/2) F fields per register\r
#define ARM_GIC_ICDICFR_F_CONFIG1_BIT    1    // Bit number within F field\r
#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED  0x0  // Level triggered interrupt\r
#define ARM_GIC_ICDICFR_EDGE_TRIGGERED   0x1  // Edge triggered interrupt\r
\r
\r
// GIC Redistributor\r
#define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB\r
#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
\r
// GIC Redistributor Control frame\r
#define ARM_GICR_TYPER          0x0008  // Redistributor Type Register\r
\r
// GIC SGI & PPI Redistributor frame\r
#define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers\r
#define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers\r
\r
// GIC Cpu interface\r
#define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register\r
#define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register\r
#define ARM_GIC_ICCBPR          0x08  // Binary Point Register\r
#define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register\r
#define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register\r
#define ARM_GIC_ICCRPR          0x14  // Running Priority Register\r
#define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register\r
#define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register\r
#define ARM_GIC_ICCIIDR         0xFC  // Identification Register\r
\r
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0\r
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1\r
#define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2\r
\r
// Bit-masks to configure the CPU Interface Control register\r
#define ARM_GIC_ICCICR_ENABLE_SECURE            0x01\r
#define ARM_GIC_ICCICR_ENABLE_NS                0x02\r
#define ARM_GIC_ICCICR_ACK_CTL                  0x04\r
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08\r
#define ARM_GIC_ICCICR_USE_SBPR                 0x10\r
\r
// Bit Mask for GICC_IIDR\r
#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)\r
#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)\r
\r
// Bit Mask for\r
#define ARM_GIC_ICCIAR_ACKINTID                 0x3FF\r
\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
// GIC Secure interfaces\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
  IN  UINTN         MpId,\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicSetSecureInterrupts (\r
  IN  UINTN         GicDistributorBase,\r
  IN  UINTN*        GicSecureInterruptMask,\r
  IN  UINTN         GicSecureInterruptMaskSize\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableDistributor (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          TargetListFilter,\r
  IN  INTN          CPUTargetList,\r
  IN  INTN          SgiId\r
  );\r
\r
/*\r
 * Acknowledge and return the value of the Interrupt Acknowledge Register\r
 *\r
 * InterruptId is returned separately from the register value because in\r
 * the GICv2 the register value contains the CpuId and InterruptId while\r
 * in the GICv3 the register value is only the InterruptId.\r
 *\r
 * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface\r
 * @param InterruptId                 InterruptId read from the Interrupt\r
 *                                    Acknowledge Register\r
 *\r
 * @retval value returned by the Interrupt Acknowledge Register\r
 *\r
 */\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
  IN  UINTN          GicInterruptInterfaceBase,\r
  OUT UINTN          *InterruptId\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEndOfInterrupt (\r
  IN  UINTN                 GicInterruptInterfaceBase,\r
  IN UINTN                  Source\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicSetPriorityMask (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          PriorityMask\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
// GIC revision 2 specific declarations\r
\r
// Interrupts from 1020 to 1023 are considered as special interrupts\r
// (eg: spurious interrupts)\r
#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \\r
          (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
\r
VOID\r
EFIAPI\r
ArmGicV2SetupNonSecure (\r
  IN  UINTN         MpId,\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2EnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2DisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicV2AcknowledgeInterrupt (\r
  IN  UINTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2EndOfInterrupt (\r
  IN UINTN                  GicInterruptInterfaceBase,\r
  IN UINTN                  Source\r
  );\r
\r
// GIC revision 3 specific declarations\r
\r
#define ICC_SRE_EL2_SRE         (1 << 0)\r
\r
#define ARM_GICD_IROUTER_IRM BIT31\r
\r
UINT32\r
EFIAPI\r
ArmGicV3GetControlSystemRegisterEnable (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3SetControlSystemRegisterEnable (\r
  IN UINT32         ControlSystemRegisterEnable\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3EnableInterruptInterface (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3DisableInterruptInterface (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicV3AcknowledgeInterrupt (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3EndOfInterrupt (\r
  IN UINTN                  Source\r
  );\r
\r
VOID\r
ArmGicV3SetBinaryPointer (\r
  IN UINTN                  BinaryPoint\r
  );\r
\r
VOID\r
ArmGicV3SetPriorityMask (\r
  IN UINTN                  Priority\r
  );\r
\r
#endif\r
Commit	Line	Data
55a0d64b	1	/** @file\r
55a0d64b	2	*\r
b0393756	3	* Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
55a0d64b	4	*\r
1cb13673 OM	5	* This program and the accompanying materials\r
	6	* are licensed and made available under the terms and conditions of the BSD License\r
	7	* which accompanies this distribution. The full text of the license may be found at\r
	8	* http://opensource.org/licenses/bsd-license.php\r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
55a0d64b	12	*\r
	13	**/\r
	14	\r
017baa1c OM	15	#ifndef __ARMGIC_H\r
017baa1c OM	16	#define __ARMGIC_H\r
55a0d64b	17	\r
8d13298b	18	#include <Library/ArmGicArchLib.h>\r
55a0d64b	19	\r
55a0d64b	20	// GIC Distributor\r
55a0d64b	21	#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
	22	#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
	23	#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
	24	\r
919697ae	25	// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
55a0d64b	26	#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
	27	#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
	28	#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
	29	#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
	30	#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
	31	#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
	32	\r
919697ae	33	// Each reg base below repeats for Number of interrupts / 4\r
55a0d64b	34	#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
55a0d64b	35	\r
919697ae	36	// Each reg base below repeats for Number of interrupts\r
55a0d64b	37	#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
	38	#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
	39	\r
	40	#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
	41	\r
	42	// just one of these\r
	43	#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
	44	\r
919697ae OM	45	// GICv3 specific registers\r
	46	#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
	47	\r
c7fefb69 AB	48	// GICD_CTLR bits\r
	49	#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)\r
	50	#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)\r
f6d46e29	51	\r
8659306a AB	52	// GICD_ICDICFR bits\r
	53	#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register\r
	54	#define ARM_GIC_ICDICFR_BYTES (ARM_GIC_ICDICFR_WIDTH / 8)\r
	55	#define ARM_GIC_ICDICFR_F_WIDTH 2 // Each F field is 2 bits\r
	56	#define ARM_GIC_ICDICFR_F_STRIDE 16 // (32/2) F fields per register\r
	57	#define ARM_GIC_ICDICFR_F_CONFIG1_BIT 1 // Bit number within F field\r
	58	#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt\r
	59	#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt\r
	60	\r
919697ae	61	\r
8659306a	62	// GIC Redistributor\r
919697ae OM	63	#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
	64	#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
	65	\r
	66	// GIC Redistributor Control frame\r
	67	#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r
	68	\r
	69	// GIC SGI & PPI Redistributor frame\r
	70	#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
	71	#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
	72	\r
55a0d64b	73	// GIC Cpu interface\r
55a0d64b	74	#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
	75	#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
	76	#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
	77	#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
	78	#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
	79	#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
	80	#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
	81	#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
e700a1fc	82	#define ARM_GIC_ICCIIDR 0xFC // Identification Register\r
55a0d64b	83	\r
	84	#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
	85	#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
	86	#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r
	87	\r
	88	// Bit-masks to configure the CPU Interface Control register\r
	89	#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r
	90	#define ARM_GIC_ICCICR_ENABLE_NS 0x02\r
	91	#define ARM_GIC_ICCICR_ACK_CTL 0x04\r
	92	#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
	93	#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
	94	\r
1cb13673	95	// Bit Mask for GICC_IIDR\r
e700a1fc OM	96	#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r
	97	#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
	98	#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
	99	#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
55a0d64b	100	\r
5f81082e OM	101	// Bit Mask for\r
	102	#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
	103	\r
e700a1fc OM	104	UINTN\r
	105	EFIAPI\r
	106	ArmGicGetInterfaceIdentification (\r
	107	IN INTN GicInterruptInterfaceBase\r
	108	);\r
	109	\r
92534106	110	// GIC Secure interfaces\r
55a0d64b	111	VOID\r
	112	EFIAPI\r
	113	ArmGicSetupNonSecure (\r
5e773144	114	IN UINTN MpId,\r
55a0d64b	115	IN INTN GicDistributorBase,\r
	116	IN INTN GicInterruptInterfaceBase\r
	117	);\r
	118	\r
92534106	119	VOID\r
	120	EFIAPI\r
	121	ArmGicSetSecureInterrupts (\r
	122	IN UINTN GicDistributorBase,\r
	123	IN UINTN* GicSecureInterruptMask,\r
	124	IN UINTN GicSecureInterruptMaskSize\r
	125	);\r
	126	\r
55a0d64b	127	VOID\r
	128	EFIAPI\r
	129	ArmGicEnableInterruptInterface (\r
	130	IN INTN GicInterruptInterfaceBase\r
	131	);\r
	132	\r
9736c297	133	VOID\r
	134	EFIAPI\r
	135	ArmGicDisableInterruptInterface (\r
	136	IN INTN GicInterruptInterfaceBase\r
	137	);\r
	138	\r
55a0d64b	139	VOID\r
	140	EFIAPI\r
	141	ArmGicEnableDistributor (\r
	142	IN INTN GicDistributorBase\r
	143	);\r
	144	\r
e700a1fc OM	145	VOID\r
	146	EFIAPI\r
	147	ArmGicDisableDistributor (\r
	148	IN INTN GicDistributorBase\r
	149	);\r
	150	\r
e9f7c58f	151	UINTN\r
	152	EFIAPI\r
	153	ArmGicGetMaxNumInterrupts (\r
	154	IN INTN GicDistributorBase\r
	155	);\r
	156	\r
55a0d64b	157	VOID\r
	158	EFIAPI\r
	159	ArmGicSendSgiTo (\r
	160	IN INTN GicDistributorBase,\r
	161	IN INTN TargetListFilter,\r
4c19ece3	162	IN INTN CPUTargetList,\r
4c19ece3	163	IN INTN SgiId\r
55a0d64b	164	);\r
55a0d64b	165	\r
1b0ac0de OM	166	/*\r
	167	* Acknowledge and return the value of the Interrupt Acknowledge Register\r
	168	*\r
	169	* InterruptId is returned separately from the register value because in\r
	170	* the GICv2 the register value contains the CpuId and InterruptId while\r
	171	* in the GICv3 the register value is only the InterruptId.\r
	172	*\r
	173	* @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
b0393756 EL	174	* @param InterruptId InterruptId read from the Interrupt\r
b0393756 EL	175	* Acknowledge Register\r
1b0ac0de OM	176	*\r
	177	* @retval value returned by the Interrupt Acknowledge Register\r
	178	*\r
	179	*/\r
2ca815a4	180	UINTN\r
55a0d64b	181	EFIAPI\r
315649cd	182	ArmGicAcknowledgeInterrupt (\r
1b0ac0de OM	183	IN UINTN GicInterruptInterfaceBase,\r
1b0ac0de OM	184	OUT UINTN *InterruptId\r
55a0d64b	185	);\r
55a0d64b	186	\r
d80401a1 OM	187	VOID\r
	188	EFIAPI\r
	189	ArmGicEndOfInterrupt (\r
	190	IN UINTN GicInterruptInterfaceBase,\r
	191	IN UINTN Source\r
	192	);\r
	193	\r
55a0d64b	194	UINTN\r
	195	EFIAPI\r
	196	ArmGicSetPriorityMask (\r
	197	IN INTN GicInterruptInterfaceBase,\r
	198	IN INTN PriorityMask\r
	199	);\r
	200	\r
e700a1fc OM	201	VOID\r
	202	EFIAPI\r
	203	ArmGicEnableInterrupt (\r
	204	IN UINTN GicDistributorBase,\r
41fb5d46	205	IN UINTN GicRedistributorBase,\r
e700a1fc OM	206	IN UINTN Source\r
	207	);\r
	208	\r
	209	VOID\r
	210	EFIAPI\r
	211	ArmGicDisableInterrupt (\r
	212	IN UINTN GicDistributorBase,\r
41fb5d46	213	IN UINTN GicRedistributorBase,\r
e700a1fc OM	214	IN UINTN Source\r
	215	);\r
	216	\r
	217	BOOLEAN\r
	218	EFIAPI\r
	219	ArmGicIsInterruptEnabled (\r
	220	IN UINTN GicDistributorBase,\r
41fb5d46	221	IN UINTN GicRedistributorBase,\r
e700a1fc OM	222	IN UINTN Source\r
	223	);\r
	224	\r
bce29e30	225	// GIC revision 2 specific declarations\r
bce29e30	226	\r
b0393756 EL	227	// Interrupts from 1020 to 1023 are considered as special interrupts\r
	228	// (eg: spurious interrupts)\r
	229	#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \\r
	230	(((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
bce29e30 AB	231	\r
	232	VOID\r
	233	EFIAPI\r
	234	ArmGicV2SetupNonSecure (\r
	235	IN UINTN MpId,\r
	236	IN INTN GicDistributorBase,\r
	237	IN INTN GicInterruptInterfaceBase\r
	238	);\r
	239	\r
	240	VOID\r
	241	EFIAPI\r
	242	ArmGicV2EnableInterruptInterface (\r
	243	IN INTN GicInterruptInterfaceBase\r
	244	);\r
	245	\r
	246	VOID\r
	247	EFIAPI\r
	248	ArmGicV2DisableInterruptInterface (\r
	249	IN INTN GicInterruptInterfaceBase\r
	250	);\r
	251	\r
	252	UINTN\r
	253	EFIAPI\r
	254	ArmGicV2AcknowledgeInterrupt (\r
	255	IN UINTN GicInterruptInterfaceBase\r
	256	);\r
	257	\r
	258	VOID\r
	259	EFIAPI\r
	260	ArmGicV2EndOfInterrupt (\r
	261	IN UINTN GicInterruptInterfaceBase,\r
	262	IN UINTN Source\r
	263	);\r
	264	\r
bce29e30	265	// GIC revision 3 specific declarations\r
bce29e30 AB	266	\r
	267	#define ICC_SRE_EL2_SRE (1 << 0)\r
	268	\r
	269	#define ARM_GICD_IROUTER_IRM BIT31\r
	270	\r
	271	UINT32\r
	272	EFIAPI\r
	273	ArmGicV3GetControlSystemRegisterEnable (\r
	274	VOID\r
	275	);\r
	276	\r
	277	VOID\r
	278	EFIAPI\r
	279	ArmGicV3SetControlSystemRegisterEnable (\r
	280	IN UINT32 ControlSystemRegisterEnable\r
	281	);\r
	282	\r
	283	VOID\r
	284	EFIAPI\r
	285	ArmGicV3EnableInterruptInterface (\r
	286	VOID\r
	287	);\r
	288	\r
	289	VOID\r
	290	EFIAPI\r
	291	ArmGicV3DisableInterruptInterface (\r
	292	VOID\r
	293	);\r
	294	\r
	295	UINTN\r
	296	EFIAPI\r
	297	ArmGicV3AcknowledgeInterrupt (\r
	298	VOID\r
	299	);\r
	300	\r
	301	VOID\r
	302	EFIAPI\r
	303	ArmGicV3EndOfInterrupt (\r
	304	IN UINTN Source\r
	305	);\r
	306	\r
	307	VOID\r
	308	ArmGicV3SetBinaryPointer (\r
	309	IN UINTN BinaryPoint\r
	310	);\r
	311	\r
	312	VOID\r
	313	ArmGicV3SetPriorityMask (\r
	314	IN UINTN Priority\r
	315	);\r
	316	\r
55a0d64b	317	#endif\r