[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h

/** @file\r
*\r
*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef __ARMGIC_H\r
#define __ARMGIC_H\r
\r
#include <Library/ArmGicArchLib.h>\r
\r
//\r
// GIC Distributor\r
//\r
#define ARM_GIC_ICDDCR          0x000 // Distributor Control Register\r
#define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register\r
#define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register\r
\r
// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
#define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers\r
#define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers\r
#define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers\r
#define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers\r
#define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers\r
#define ARM_GIC_ICDABR          0x300 // Active Bit Registers\r
\r
// Each reg base below repeats for Number of interrupts / 4\r
#define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers\r
\r
// Each reg base below repeats for Number of interrupts\r
#define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers\r
#define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers\r
\r
#define ARM_GIC_ICDPPISR        0xD00 // PPI Status register\r
\r
// just one of these\r
#define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register\r
\r
// GICv3 specific registers\r
#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers\r
\r
// the Affinity Routing Enable (ARE) bit in GICD_CTLR\r
#define ARM_GIC_ICDDCR_ARE      (1 << 4)\r
\r
//\r
// GIC Redistributor\r
//\r
\r
#define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB\r
#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
\r
// GIC Redistributor Control frame\r
#define ARM_GICR_TYPER          0x0008  // Redistributor Type Register\r
\r
// GIC SGI & PPI Redistributor frame\r
#define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers\r
#define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers\r
\r
//\r
// GIC Cpu interface\r
//\r
#define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register\r
#define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register\r
#define ARM_GIC_ICCBPR          0x08  // Binary Point Register\r
#define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register\r
#define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register\r
#define ARM_GIC_ICCRPR          0x14  // Running Priority Register\r
#define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register\r
#define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register\r
#define ARM_GIC_ICCIIDR         0xFC  // Identification Register\r
\r
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0\r
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1\r
#define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2\r
\r
// Bit-masks to configure the CPU Interface Control register\r
#define ARM_GIC_ICCICR_ENABLE_SECURE            0x01\r
#define ARM_GIC_ICCICR_ENABLE_NS                0x02\r
#define ARM_GIC_ICCICR_ACK_CTL                  0x04\r
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08\r
#define ARM_GIC_ICCICR_USE_SBPR                 0x10\r
\r
// Bit Mask for GICC_IIDR\r
#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)\r
#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)\r
#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)\r
\r
// Bit Mask for\r
#define ARM_GIC_ICCIAR_ACKINTID                 0x3FF\r
\r
UINTN\r
EFIAPI\r
ArmGicGetInterfaceIdentification (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
//\r
// GIC Secure interfaces\r
//\r
VOID\r
EFIAPI\r
ArmGicSetupNonSecure (\r
  IN  UINTN         MpId,\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicSetSecureInterrupts (\r
  IN  UINTN         GicDistributorBase,\r
  IN  UINTN*        GicSecureInterruptMask,\r
  IN  UINTN         GicSecureInterruptMaskSize\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableDistributor (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicGetMaxNumInterrupts (\r
  IN  INTN          GicDistributorBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicSendSgiTo (\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          TargetListFilter,\r
  IN  INTN          CPUTargetList,\r
  IN  INTN          SgiId\r
  );\r
\r
/*\r
 * Acknowledge and return the value of the Interrupt Acknowledge Register\r
 *\r
 * InterruptId is returned separately from the register value because in\r
 * the GICv2 the register value contains the CpuId and InterruptId while\r
 * in the GICv3 the register value is only the InterruptId.\r
 *\r
 * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface\r
 * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register\r
 *\r
 * @retval value returned by the Interrupt Acknowledge Register\r
 *\r
 */\r
UINTN\r
EFIAPI\r
ArmGicAcknowledgeInterrupt (\r
  IN  UINTN          GicInterruptInterfaceBase,\r
  OUT UINTN          *InterruptId\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEndOfInterrupt (\r
  IN  UINTN                 GicInterruptInterfaceBase,\r
  IN UINTN                  Source\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicSetPriorityMask (\r
  IN  INTN          GicInterruptInterfaceBase,\r
  IN  INTN          PriorityMask\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicEnableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicDisableInterrupt (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGicIsInterruptEnabled (\r
  IN UINTN                  GicDistributorBase,\r
  IN UINTN                  GicRedistributorBase,\r
  IN UINTN                  Source\r
  );\r
\r
//\r
// GIC revision 2 specific declarations\r
//\r
\r
// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)\r
#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
\r
VOID\r
EFIAPI\r
ArmGicV2SetupNonSecure (\r
  IN  UINTN         MpId,\r
  IN  INTN          GicDistributorBase,\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2EnableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2DisableInterruptInterface (\r
  IN  INTN          GicInterruptInterfaceBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicV2AcknowledgeInterrupt (\r
  IN  UINTN          GicInterruptInterfaceBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV2EndOfInterrupt (\r
  IN UINTN                  GicInterruptInterfaceBase,\r
  IN UINTN                  Source\r
  );\r
\r
//\r
// GIC revision 3 specific declarations\r
//\r
\r
#define ICC_SRE_EL2_SRE         (1 << 0)\r
\r
#define ARM_GICD_IROUTER_IRM BIT31\r
\r
UINT32\r
EFIAPI\r
ArmGicV3GetControlSystemRegisterEnable (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3SetControlSystemRegisterEnable (\r
  IN UINT32         ControlSystemRegisterEnable\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3EnableInterruptInterface (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3DisableInterruptInterface (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmGicV3AcknowledgeInterrupt (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmGicV3EndOfInterrupt (\r
  IN UINTN                  Source\r
  );\r
\r
VOID\r
ArmGicV3SetBinaryPointer (\r
  IN UINTN                  BinaryPoint\r
  );\r
\r
VOID\r
ArmGicV3SetPriorityMask (\r
  IN UINTN                  Priority\r
  );\r
\r
#endif\r
Commit	Line	Data
55a0d64b	1	/** @file\r
55a0d64b	2	*\r
919697ae	3	* Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
55a0d64b	4	*\r
1cb13673 OM	5	* This program and the accompanying materials\r
	6	* are licensed and made available under the terms and conditions of the BSD License\r
	7	* which accompanies this distribution. The full text of the license may be found at\r
	8	* http://opensource.org/licenses/bsd-license.php\r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
55a0d64b	12	*\r
	13	**/\r
	14	\r
017baa1c OM	15	#ifndef __ARMGIC_H\r
017baa1c OM	16	#define __ARMGIC_H\r
55a0d64b	17	\r
8d13298b	18	#include <Library/ArmGicArchLib.h>\r
55a0d64b	19	\r
	20	//\r
	21	// GIC Distributor\r
	22	//\r
	23	#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
	24	#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
	25	#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
	26	\r
919697ae	27	// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
55a0d64b	28	#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
	29	#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
	30	#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
	31	#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
	32	#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
	33	#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
	34	\r
919697ae	35	// Each reg base below repeats for Number of interrupts / 4\r
55a0d64b	36	#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
55a0d64b	37	\r
919697ae	38	// Each reg base below repeats for Number of interrupts\r
55a0d64b	39	#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
	40	#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
	41	\r
	42	#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
	43	\r
	44	// just one of these\r
	45	#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
	46	\r
919697ae OM	47	// GICv3 specific registers\r
	48	#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
	49	\r
f6d46e29 AB	50	// the Affinity Routing Enable (ARE) bit in GICD_CTLR\r
	51	#define ARM_GIC_ICDDCR_ARE (1 << 4)\r
	52	\r
919697ae OM	53	//\r
	54	// GIC Redistributor\r
	55	//\r
	56	\r
	57	#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
	58	#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
	59	\r
	60	// GIC Redistributor Control frame\r
	61	#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r
	62	\r
	63	// GIC SGI & PPI Redistributor frame\r
	64	#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
	65	#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
	66	\r
55a0d64b	67	//\r
	68	// GIC Cpu interface\r
	69	//\r
	70	#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
	71	#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
	72	#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
	73	#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
	74	#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
	75	#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
	76	#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
	77	#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
e700a1fc	78	#define ARM_GIC_ICCIIDR 0xFC // Identification Register\r
55a0d64b	79	\r
	80	#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
	81	#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
	82	#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r
	83	\r
	84	// Bit-masks to configure the CPU Interface Control register\r
	85	#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r
	86	#define ARM_GIC_ICCICR_ENABLE_NS 0x02\r
	87	#define ARM_GIC_ICCICR_ACK_CTL 0x04\r
	88	#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
	89	#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
	90	\r
1cb13673	91	// Bit Mask for GICC_IIDR\r
e700a1fc OM	92	#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r
	93	#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
	94	#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
	95	#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
55a0d64b	96	\r
5f81082e OM	97	// Bit Mask for\r
	98	#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
	99	\r
e700a1fc OM	100	UINTN\r
	101	EFIAPI\r
	102	ArmGicGetInterfaceIdentification (\r
	103	IN INTN GicInterruptInterfaceBase\r
	104	);\r
	105	\r
55a0d64b	106	//\r
92534106	107	// GIC Secure interfaces\r
55a0d64b	108	//\r
	109	VOID\r
	110	EFIAPI\r
	111	ArmGicSetupNonSecure (\r
5e773144	112	IN UINTN MpId,\r
55a0d64b	113	IN INTN GicDistributorBase,\r
	114	IN INTN GicInterruptInterfaceBase\r
	115	);\r
	116	\r
92534106	117	VOID\r
	118	EFIAPI\r
	119	ArmGicSetSecureInterrupts (\r
	120	IN UINTN GicDistributorBase,\r
	121	IN UINTN* GicSecureInterruptMask,\r
	122	IN UINTN GicSecureInterruptMaskSize\r
	123	);\r
	124	\r
55a0d64b	125	VOID\r
	126	EFIAPI\r
	127	ArmGicEnableInterruptInterface (\r
	128	IN INTN GicInterruptInterfaceBase\r
	129	);\r
	130	\r
9736c297	131	VOID\r
	132	EFIAPI\r
	133	ArmGicDisableInterruptInterface (\r
	134	IN INTN GicInterruptInterfaceBase\r
	135	);\r
	136	\r
55a0d64b	137	VOID\r
	138	EFIAPI\r
	139	ArmGicEnableDistributor (\r
	140	IN INTN GicDistributorBase\r
	141	);\r
	142	\r
e700a1fc OM	143	VOID\r
	144	EFIAPI\r
	145	ArmGicDisableDistributor (\r
	146	IN INTN GicDistributorBase\r
	147	);\r
	148	\r
e9f7c58f	149	UINTN\r
	150	EFIAPI\r
	151	ArmGicGetMaxNumInterrupts (\r
	152	IN INTN GicDistributorBase\r
	153	);\r
	154	\r
55a0d64b	155	VOID\r
	156	EFIAPI\r
	157	ArmGicSendSgiTo (\r
	158	IN INTN GicDistributorBase,\r
	159	IN INTN TargetListFilter,\r
4c19ece3	160	IN INTN CPUTargetList,\r
4c19ece3	161	IN INTN SgiId\r
55a0d64b	162	);\r
55a0d64b	163	\r
1b0ac0de OM	164	/*\r
	165	* Acknowledge and return the value of the Interrupt Acknowledge Register\r
	166	*\r
	167	* InterruptId is returned separately from the register value because in\r
	168	* the GICv2 the register value contains the CpuId and InterruptId while\r
	169	* in the GICv3 the register value is only the InterruptId.\r
	170	*\r
	171	* @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
	172	* @param InterruptId InterruptId read from the Interrupt Acknowledge Register\r
	173	*\r
	174	* @retval value returned by the Interrupt Acknowledge Register\r
	175	*\r
	176	*/\r
2ca815a4	177	UINTN\r
55a0d64b	178	EFIAPI\r
315649cd	179	ArmGicAcknowledgeInterrupt (\r
1b0ac0de OM	180	IN UINTN GicInterruptInterfaceBase,\r
1b0ac0de OM	181	OUT UINTN *InterruptId\r
55a0d64b	182	);\r
55a0d64b	183	\r
d80401a1 OM	184	VOID\r
	185	EFIAPI\r
	186	ArmGicEndOfInterrupt (\r
	187	IN UINTN GicInterruptInterfaceBase,\r
	188	IN UINTN Source\r
	189	);\r
	190	\r
55a0d64b	191	UINTN\r
	192	EFIAPI\r
	193	ArmGicSetPriorityMask (\r
	194	IN INTN GicInterruptInterfaceBase,\r
	195	IN INTN PriorityMask\r
	196	);\r
	197	\r
e700a1fc OM	198	VOID\r
	199	EFIAPI\r
	200	ArmGicEnableInterrupt (\r
	201	IN UINTN GicDistributorBase,\r
41fb5d46	202	IN UINTN GicRedistributorBase,\r
e700a1fc OM	203	IN UINTN Source\r
	204	);\r
	205	\r
	206	VOID\r
	207	EFIAPI\r
	208	ArmGicDisableInterrupt (\r
	209	IN UINTN GicDistributorBase,\r
41fb5d46	210	IN UINTN GicRedistributorBase,\r
e700a1fc OM	211	IN UINTN Source\r
	212	);\r
	213	\r
	214	BOOLEAN\r
	215	EFIAPI\r
	216	ArmGicIsInterruptEnabled (\r
	217	IN UINTN GicDistributorBase,\r
41fb5d46	218	IN UINTN GicRedistributorBase,\r
e700a1fc OM	219	IN UINTN Source\r
	220	);\r
	221	\r
bce29e30 AB	222	//\r
	223	// GIC revision 2 specific declarations\r
	224	//\r
	225	\r
	226	// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)\r
	227	#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
	228	\r
	229	VOID\r
	230	EFIAPI\r
	231	ArmGicV2SetupNonSecure (\r
	232	IN UINTN MpId,\r
	233	IN INTN GicDistributorBase,\r
	234	IN INTN GicInterruptInterfaceBase\r
	235	);\r
	236	\r
	237	VOID\r
	238	EFIAPI\r
	239	ArmGicV2EnableInterruptInterface (\r
	240	IN INTN GicInterruptInterfaceBase\r
	241	);\r
	242	\r
	243	VOID\r
	244	EFIAPI\r
	245	ArmGicV2DisableInterruptInterface (\r
	246	IN INTN GicInterruptInterfaceBase\r
	247	);\r
	248	\r
	249	UINTN\r
	250	EFIAPI\r
	251	ArmGicV2AcknowledgeInterrupt (\r
	252	IN UINTN GicInterruptInterfaceBase\r
	253	);\r
	254	\r
	255	VOID\r
	256	EFIAPI\r
	257	ArmGicV2EndOfInterrupt (\r
	258	IN UINTN GicInterruptInterfaceBase,\r
	259	IN UINTN Source\r
	260	);\r
	261	\r
	262	//\r
	263	// GIC revision 3 specific declarations\r
	264	//\r
	265	\r
	266	#define ICC_SRE_EL2_SRE (1 << 0)\r
	267	\r
	268	#define ARM_GICD_IROUTER_IRM BIT31\r
	269	\r
	270	UINT32\r
	271	EFIAPI\r
	272	ArmGicV3GetControlSystemRegisterEnable (\r
	273	VOID\r
	274	);\r
	275	\r
	276	VOID\r
	277	EFIAPI\r
	278	ArmGicV3SetControlSystemRegisterEnable (\r
	279	IN UINT32 ControlSystemRegisterEnable\r
	280	);\r
	281	\r
	282	VOID\r
	283	EFIAPI\r
	284	ArmGicV3EnableInterruptInterface (\r
	285	VOID\r
286	);\r
287	\r
288	VOID\r
289	EFIAPI\r
290	ArmGicV3DisableInterruptInterface (\r
291	VOID\r
292	);\r
293	\r
294	UINTN\r
295	EFIAPI\r
296	ArmGicV3AcknowledgeInterrupt (\r
297	VOID\r
298	);\r
299	\r
300	VOID\r
301	EFIAPI\r
302	ArmGicV3EndOfInterrupt (\r
303	IN UINTN Source\r
304	);\r
305	\r
306	VOID\r
307	ArmGicV3SetBinaryPointer (\r
308	IN UINTN BinaryPoint\r
309	);\r
310	\r
311	VOID\r
312	ArmGicV3SetPriorityMask (\r
313	IN UINTN Priority\r
314	);\r
315	\r
55a0d64b	316	#endif\r