]> git.proxmox.com Git - mirror_edk2.git/blame - ArmPkg/Include/Library/ArmGicLib.h
ArmPkg/ArmLib: move ArmReadIdPfr0/1 into private header ArmV7Lib.h
[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h
CommitLineData
55a0d64b 1/** @file\r
2*\r
301402fa 3* Copyright (c) 2011-2018, ARM Limited. All rights reserved.\r
55a0d64b 4*\r
4059386c 5* SPDX-License-Identifier: BSD-2-Clause-Patent\r
55a0d64b 6*\r
7**/\r
8\r
017baa1c
OM
9#ifndef __ARMGIC_H\r
10#define __ARMGIC_H\r
55a0d64b 11\r
8d13298b 12#include <Library/ArmGicArchLib.h>\r
55a0d64b 13\r
55a0d64b 14// GIC Distributor\r
55a0d64b 15#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
16#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
17#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
18\r
919697ae 19// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)\r
55a0d64b 20#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
21#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
22#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
23#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
24#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
25#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
26\r
919697ae 27// Each reg base below repeats for Number of interrupts / 4\r
55a0d64b 28#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
29\r
919697ae 30// Each reg base below repeats for Number of interrupts\r
55a0d64b 31#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
32#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
33\r
34#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
35\r
36// just one of these\r
37#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
38\r
919697ae
OM
39// GICv3 specific registers\r
40#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
41\r
c7fefb69
AB
42// GICD_CTLR bits\r
43#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)\r
44#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)\r
f6d46e29 45\r
8659306a
AB
46// GICD_ICDICFR bits\r
47#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register\r
48#define ARM_GIC_ICDICFR_BYTES (ARM_GIC_ICDICFR_WIDTH / 8)\r
49#define ARM_GIC_ICDICFR_F_WIDTH 2 // Each F field is 2 bits\r
50#define ARM_GIC_ICDICFR_F_STRIDE 16 // (32/2) F fields per register\r
51#define ARM_GIC_ICDICFR_F_CONFIG1_BIT 1 // Bit number within F field\r
52#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt\r
53#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt\r
54\r
919697ae 55\r
8659306a 56// GIC Redistributor\r
301402fa
SM
57#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
58#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
59#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB\r
60#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB\r
919697ae
OM
61\r
62// GIC Redistributor Control frame\r
63#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r
64\r
301402fa
SM
65// GIC Redistributor TYPER bit assignments\r
66#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs\r
67#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs\r
68#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs\r
69#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series\r
70#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group\r
71 // Selection Support\r
72#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number\r
73#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity\r
74#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity\r
75\r
76#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \\r
77 ARM_GICR_TYPER_AFFINITY) >> 32)\r
78\r
919697ae
OM
79// GIC SGI & PPI Redistributor frame\r
80#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
81#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
82\r
55a0d64b 83// GIC Cpu interface\r
55a0d64b 84#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
85#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
86#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
87#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
88#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
89#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
90#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
91#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
e700a1fc 92#define ARM_GIC_ICCIIDR 0xFC // Identification Register\r
55a0d64b 93\r
94#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
95#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
96#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r
97\r
98// Bit-masks to configure the CPU Interface Control register\r
99#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r
100#define ARM_GIC_ICCICR_ENABLE_NS 0x02\r
101#define ARM_GIC_ICCICR_ACK_CTL 0x04\r
102#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
103#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
104\r
1cb13673 105// Bit Mask for GICC_IIDR\r
e700a1fc
OM
106#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)\r
107#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)\r
108#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)\r
109#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)\r
55a0d64b 110\r
5f81082e
OM
111// Bit Mask for\r
112#define ARM_GIC_ICCIAR_ACKINTID 0x3FF\r
113\r
e700a1fc
OM
114UINTN\r
115EFIAPI\r
116ArmGicGetInterfaceIdentification (\r
117 IN INTN GicInterruptInterfaceBase\r
118 );\r
119\r
92534106 120// GIC Secure interfaces\r
55a0d64b 121VOID\r
122EFIAPI\r
123ArmGicSetupNonSecure (\r
5e773144 124 IN UINTN MpId,\r
55a0d64b 125 IN INTN GicDistributorBase,\r
126 IN INTN GicInterruptInterfaceBase\r
127 );\r
128\r
92534106 129VOID\r
130EFIAPI\r
131ArmGicSetSecureInterrupts (\r
132 IN UINTN GicDistributorBase,\r
133 IN UINTN* GicSecureInterruptMask,\r
134 IN UINTN GicSecureInterruptMaskSize\r
135 );\r
136\r
55a0d64b 137VOID\r
138EFIAPI\r
139ArmGicEnableInterruptInterface (\r
140 IN INTN GicInterruptInterfaceBase\r
141 );\r
142\r
9736c297 143VOID\r
144EFIAPI\r
145ArmGicDisableInterruptInterface (\r
146 IN INTN GicInterruptInterfaceBase\r
147 );\r
148\r
55a0d64b 149VOID\r
150EFIAPI\r
151ArmGicEnableDistributor (\r
152 IN INTN GicDistributorBase\r
153 );\r
154\r
e700a1fc
OM
155VOID\r
156EFIAPI\r
157ArmGicDisableDistributor (\r
158 IN INTN GicDistributorBase\r
159 );\r
160\r
e9f7c58f 161UINTN\r
162EFIAPI\r
163ArmGicGetMaxNumInterrupts (\r
164 IN INTN GicDistributorBase\r
165 );\r
166\r
55a0d64b 167VOID\r
168EFIAPI\r
169ArmGicSendSgiTo (\r
170 IN INTN GicDistributorBase,\r
171 IN INTN TargetListFilter,\r
4c19ece3 172 IN INTN CPUTargetList,\r
173 IN INTN SgiId\r
55a0d64b 174 );\r
175\r
1b0ac0de
OM
176/*\r
177 * Acknowledge and return the value of the Interrupt Acknowledge Register\r
178 *\r
179 * InterruptId is returned separately from the register value because in\r
180 * the GICv2 the register value contains the CpuId and InterruptId while\r
181 * in the GICv3 the register value is only the InterruptId.\r
182 *\r
183 * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface\r
b0393756
EL
184 * @param InterruptId InterruptId read from the Interrupt\r
185 * Acknowledge Register\r
1b0ac0de
OM
186 *\r
187 * @retval value returned by the Interrupt Acknowledge Register\r
188 *\r
189 */\r
2ca815a4 190UINTN\r
55a0d64b 191EFIAPI\r
315649cd 192ArmGicAcknowledgeInterrupt (\r
1b0ac0de
OM
193 IN UINTN GicInterruptInterfaceBase,\r
194 OUT UINTN *InterruptId\r
55a0d64b 195 );\r
196\r
d80401a1
OM
197VOID\r
198EFIAPI\r
199ArmGicEndOfInterrupt (\r
200 IN UINTN GicInterruptInterfaceBase,\r
201 IN UINTN Source\r
202 );\r
203\r
55a0d64b 204UINTN\r
205EFIAPI\r
206ArmGicSetPriorityMask (\r
207 IN INTN GicInterruptInterfaceBase,\r
208 IN INTN PriorityMask\r
209 );\r
210\r
e700a1fc
OM
211VOID\r
212EFIAPI\r
213ArmGicEnableInterrupt (\r
214 IN UINTN GicDistributorBase,\r
41fb5d46 215 IN UINTN GicRedistributorBase,\r
e700a1fc
OM
216 IN UINTN Source\r
217 );\r
218\r
219VOID\r
220EFIAPI\r
221ArmGicDisableInterrupt (\r
222 IN UINTN GicDistributorBase,\r
41fb5d46 223 IN UINTN GicRedistributorBase,\r
e700a1fc
OM
224 IN UINTN Source\r
225 );\r
226\r
227BOOLEAN\r
228EFIAPI\r
229ArmGicIsInterruptEnabled (\r
230 IN UINTN GicDistributorBase,\r
41fb5d46 231 IN UINTN GicRedistributorBase,\r
e700a1fc
OM
232 IN UINTN Source\r
233 );\r
234\r
bce29e30 235// GIC revision 2 specific declarations\r
bce29e30 236\r
b0393756
EL
237// Interrupts from 1020 to 1023 are considered as special interrupts\r
238// (eg: spurious interrupts)\r
239#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \\r
240 (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
bce29e30
AB
241\r
242VOID\r
243EFIAPI\r
244ArmGicV2SetupNonSecure (\r
245 IN UINTN MpId,\r
246 IN INTN GicDistributorBase,\r
247 IN INTN GicInterruptInterfaceBase\r
248 );\r
249\r
250VOID\r
251EFIAPI\r
252ArmGicV2EnableInterruptInterface (\r
253 IN INTN GicInterruptInterfaceBase\r
254 );\r
255\r
256VOID\r
257EFIAPI\r
258ArmGicV2DisableInterruptInterface (\r
259 IN INTN GicInterruptInterfaceBase\r
260 );\r
261\r
262UINTN\r
263EFIAPI\r
264ArmGicV2AcknowledgeInterrupt (\r
265 IN UINTN GicInterruptInterfaceBase\r
266 );\r
267\r
268VOID\r
269EFIAPI\r
270ArmGicV2EndOfInterrupt (\r
271 IN UINTN GicInterruptInterfaceBase,\r
272 IN UINTN Source\r
273 );\r
274\r
bce29e30 275// GIC revision 3 specific declarations\r
bce29e30
AB
276\r
277#define ICC_SRE_EL2_SRE (1 << 0)\r
278\r
279#define ARM_GICD_IROUTER_IRM BIT31\r
280\r
281UINT32\r
282EFIAPI\r
283ArmGicV3GetControlSystemRegisterEnable (\r
284 VOID\r
285 );\r
286\r
287VOID\r
288EFIAPI\r
289ArmGicV3SetControlSystemRegisterEnable (\r
290 IN UINT32 ControlSystemRegisterEnable\r
291 );\r
292\r
293VOID\r
294EFIAPI\r
295ArmGicV3EnableInterruptInterface (\r
296 VOID\r
297 );\r
298\r
299VOID\r
300EFIAPI\r
301ArmGicV3DisableInterruptInterface (\r
302 VOID\r
303 );\r
304\r
305UINTN\r
306EFIAPI\r
307ArmGicV3AcknowledgeInterrupt (\r
308 VOID\r
309 );\r
310\r
311VOID\r
312EFIAPI\r
313ArmGicV3EndOfInterrupt (\r
314 IN UINTN Source\r
315 );\r
316\r
317VOID\r
318ArmGicV3SetBinaryPointer (\r
319 IN UINTN BinaryPoint\r
320 );\r
321\r
322VOID\r
323ArmGicV3SetPriorityMask (\r
324 IN UINTN Priority\r
325 );\r
326\r
55a0d64b 327#endif\r