projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 11c20f4e | 1 | //\r |
| bebda7ce | 2 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
| 11c20f4e | 3 | //\r |
| f4dfad05 | 4 | // SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 11c20f4e | 5 | //\r |
| 6 | //\r | |
| 7 | \r | |
| 8 | #include <AsmMacroIoLib.h>\r | |
| 11c20f4e | 9 | \r |
| 13dc7fa5 | 10 | ASM_FUNC(_ModuleEntryPoint)\r |
| b5a57223 | 11 | // Do early platform specific actions\r |
| 12 | bl ASM_PFX(ArmPlatformPeiBootAction)\r | |
| 13 | \r | |
| 2dbcb8f0 | 14 | // Identify CPU ID\r |
| 0787bc61 | 15 | bl ASM_PFX(ArmReadMpidr)\r |
| bebda7ce | 16 | // Keep a copy of the MpId register value\r |
| 17 | mov r5, r0\r | |
| 18 | \r | |
| 19 | // Is it the Primary Core ?\r | |
| 20 | bl ASM_PFX(ArmPlatformIsPrimaryCore)\r | |
| 21 | \r | |
| 1377db63 | 22 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
| 13dc7fa5 | 23 | MOV32 (r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))\r |
| 2dbcb8f0 | 24 | \r |
| bebda7ce | 25 | // r0 is equal to 1 if I am the primary core\r |
| 26 | cmp r0, #1\r | |
| 2dbcb8f0 | 27 | beq _SetupPrimaryCoreStack\r |
| 28 | \r | |
| 29 | _SetupSecondaryCoreStack:\r | |
| 1377db63 | 30 | // r1 contains the base of the secondary stacks\r |
| 2dbcb8f0 | 31 | \r |
| 2d45f194 | 32 | // Get the Core Position\r |
| 33 | mov r6, r1 // Save base of the secondary stacks\r | |
| 34 | mov r0, r5\r | |
| 35 | bl ASM_PFX(ArmPlatformGetCorePosition)\r | |
| 2dbcb8f0 | 36 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
| 1377db63 | 37 | add r0, r0, #1\r |
| 2dbcb8f0 | 38 | \r |
| 2dbcb8f0 | 39 | // StackOffset = CorePos * StackSize\r |
| 13dc7fa5 | 40 | MOV32 (r2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))\r |
| 1377db63 | 41 | mul r0, r0, r2\r |
| 2dbcb8f0 | 42 | // SP = StackBase + StackOffset\r |
| 2d45f194 | 43 | add sp, r6, r0\r |
| 11c20f4e | 44 | \r |
| 45 | _PrepareArguments:\r | |
| 2dbcb8f0 | 46 | // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r |
| 13dc7fa5 AB |
47 | MOV32 (r2, FixedPcdGet32(PcdFvBaseAddress))\r |
| 48 | ldr r1, [r2, #4]\r | |
| 11c20f4e | 49 | \r |
| 1377db63 | 50 | // Move sec startup address into a data register\r |
| 51 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
| 13dc7fa5 | 52 | ldr r3, =ASM_PFX(CEntryPoint)\r |
| 3402aac7 | 53 | \r |
| 1377db63 | 54 | // Jump to PrePeiCore C code\r |
| 2dbcb8f0 | 55 | // r0 = mp_id\r |
| 56 | // r1 = pei_core_address\r | |
| 1377db63 | 57 | mov r0, r5\r |
| 58 | blx r3\r | |
| 59 | \r | |
| 60 | _SetupPrimaryCoreStack:\r | |
| 3707dee3 | 61 | mov sp, r1\r |
| 7e2a8dfe AB |
62 | MOV32 (r8, FixedPcdGet64 (PcdCPUCoresStackBase))\r |
| 63 | MOV32 (r9, FixedPcdGet32 (PcdInitValueInTempStack))\r | |
| 64 | mov r10, r9\r | |
| 65 | mov r11, r9\r | |
| 66 | mov r12, r9\r | |
| 67 | 0:stm r8!, {r9-r12}\r | |
| 68 | cmp r8, r1\r | |
| 69 | blt 0b\r | |
| 1377db63 | 70 | b _PrepareArguments\r |
| 2dbcb8f0 | 71 | \r |
| 72 | _NeverReturn:\r | |
| 73 | b _NeverReturn\r |