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1d5d0ae9 1//\r
bebda7ce 2// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
1d5d0ae9 3//\r
f4dfad05 4// SPDX-License-Identifier: BSD-2-Clause-Patent\r
1d5d0ae9 5//\r
6//\r
7\r
1d5d0ae9 8#include <AutoGen.h>\r
9\r
10 INCLUDE AsmMacroIoLib.inc\r
3402aac7 11\r
1d5d0ae9 12 IMPORT CEntryPoint\r
2d45f194 13 IMPORT ArmPlatformGetCorePosition\r
bebda7ce 14 IMPORT ArmPlatformIsPrimaryCore\r
0787bc61 15 IMPORT ArmReadMpidr\r
b5a57223 16 IMPORT ArmPlatformPeiBootAction\r
1d5d0ae9 17 EXPORT _ModuleEntryPoint\r
3402aac7 18\r
1d5d0ae9 19 PRESERVE8\r
20 AREA PrePeiCoreEntryPoint, CODE, READONLY\r
3402aac7 21\r
1d5d0ae9 22StartupAddr DCD CEntryPoint\r
23\r
1d5d0ae9 24_ModuleEntryPoint\r
b5a57223 25 // Do early platform specific actions\r
26 bl ArmPlatformPeiBootAction\r
27\r
1d5d0ae9 28 // Identify CPU ID\r
0787bc61 29 bl ArmReadMpidr\r
bebda7ce 30 // Keep a copy of the MpId register value\r
31 mov r5, r0\r
3402aac7 32\r
bebda7ce 33 // Is it the Primary Core ?\r
91c38d4e 34 bl ArmPlatformIsPrimaryCore\r
bebda7ce 35\r
1377db63 36 // Get the top of the primary stacks (and the base of the secondary stacks)\r
66edb631 37 mov32 r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize)\r
2dbcb8f0 38\r
bebda7ce 39 // r0 is equal to 1 if I am the primary core\r
40 cmp r0, #1\r
2dbcb8f0 41 beq _SetupPrimaryCoreStack\r
42\r
43_SetupSecondaryCoreStack\r
1377db63 44 // r1 contains the base of the secondary stacks\r
2dbcb8f0 45\r
2d45f194 46 // Get the Core Position\r
47 mov r6, r1 // Save base of the secondary stacks\r
48 mov r0, r5\r
49 bl ArmPlatformGetCorePosition\r
2dbcb8f0 50 // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
1377db63 51 add r0, r0, #1\r
1d5d0ae9 52\r
2dbcb8f0 53 // StackOffset = CorePos * StackSize\r
66edb631 54 mov32 r2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)\r
1377db63 55 mul r0, r0, r2\r
2dbcb8f0 56 // SP = StackBase + StackOffset\r
2d45f194 57 add sp, r6, r0\r
47a8e12f 58\r
59_PrepareArguments\r
1d5d0ae9 60 // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
66edb631
AB
61 mov32 r2, FixedPcdGet32(PcdFvBaseAddress)\r
62 ldr r1, [r2, #4]\r
1d5d0ae9 63\r
1377db63 64 // Move sec startup address into a data register\r
65 // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
66 ldr r3, StartupAddr\r
3402aac7 67\r
1377db63 68 // Jump to PrePeiCore C code\r
0787bc61 69 // r0 = mp_id\r
1d5d0ae9 70 // r1 = pei_core_address\r
1377db63 71 mov r0, r5\r
72 blx r3\r
73\r
74_SetupPrimaryCoreStack\r
3707dee3 75 mov sp, r1\r
7e2a8dfe
AB
76 mov32 r8, FixedPcdGet64 (PcdCPUCoresStackBase)\r
77 mov32 r9, FixedPcdGet32 (PcdInitValueInTempStack)\r
78 mov r10, r9\r
79 mov r11, r9\r
80 mov r12, r9\r
810:stm r8!, {r9-r12}\r
82 cmp r8, r1\r
83 blt 0b\r
1377db63 84 b _PrepareArguments\r
1d5d0ae9 85\r
2dbcb8f0 86_NeverReturn\r
87 b _NeverReturn\r
88\r
1d5d0ae9 89 END\r