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92870c98 | 1 | /** @file\r |
2 | \r | |
3 | XHCI transfer scheduling routines.\r | |
4 | \r | |
d1102dba | 5 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r |
92870c98 | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "Xhci.h"\r | |
17 | \r | |
92870c98 | 18 | /**\r |
19 | Create a command transfer TRB to support XHCI command interfaces.\r | |
20 | \r | |
a9292c13 | 21 | @param Xhc The XHCI Instance.\r |
92870c98 | 22 | @param CmdTrb The cmd TRB to be executed.\r |
23 | \r | |
24 | @return Created URB or NULL.\r | |
25 | \r | |
26 | **/\r | |
27 | URB*\r | |
28 | XhcCreateCmdTrb (\r | |
a9292c13 | 29 | IN USB_XHCI_INSTANCE *Xhc,\r |
30 | IN TRB_TEMPLATE *CmdTrb\r | |
92870c98 | 31 | )\r |
32 | {\r | |
33 | URB *Urb;\r | |
34 | \r | |
35 | Urb = AllocateZeroPool (sizeof (URB));\r | |
36 | if (Urb == NULL) {\r | |
37 | return NULL;\r | |
38 | }\r | |
39 | \r | |
40 | Urb->Signature = XHC_URB_SIG;\r | |
41 | \r | |
42 | Urb->Ring = &Xhc->CmdRing;\r | |
43 | XhcSyncTrsRing (Xhc, Urb->Ring);\r | |
44 | Urb->TrbNum = 1;\r | |
45 | Urb->TrbStart = Urb->Ring->RingEnqueue;\r | |
a9292c13 | 46 | CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));\r |
92870c98 | 47 | Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;\r |
48 | Urb->TrbEnd = Urb->TrbStart;\r | |
49 | \r | |
92870c98 | 50 | return Urb;\r |
51 | }\r | |
52 | \r | |
53 | /**\r | |
54 | Execute a XHCI cmd TRB pointed by CmdTrb.\r | |
55 | \r | |
a9292c13 | 56 | @param Xhc The XHCI Instance.\r |
92870c98 | 57 | @param CmdTrb The cmd TRB to be executed.\r |
a9292c13 | 58 | @param Timeout Indicates the maximum time, in millisecond, which the\r |
92870c98 | 59 | transfer is allowed to complete.\r |
60 | @param EvtTrb The event TRB corresponding to the cmd TRB.\r | |
61 | \r | |
62 | @retval EFI_SUCCESS The transfer was completed successfully.\r | |
63 | @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r | |
64 | @retval EFI_TIMEOUT The transfer failed due to timeout.\r | |
65 | @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r | |
66 | \r | |
67 | **/\r | |
68 | EFI_STATUS\r | |
69 | EFIAPI\r | |
70 | XhcCmdTransfer (\r | |
a9292c13 | 71 | IN USB_XHCI_INSTANCE *Xhc,\r |
72 | IN TRB_TEMPLATE *CmdTrb,\r | |
73 | IN UINTN Timeout,\r | |
74 | OUT TRB_TEMPLATE **EvtTrb\r | |
92870c98 | 75 | )\r |
76 | {\r | |
77 | EFI_STATUS Status;\r | |
78 | URB *Urb;\r | |
79 | \r | |
80 | //\r | |
81 | // Validate the parameters\r | |
82 | //\r | |
83 | if ((Xhc == NULL) || (CmdTrb == NULL)) {\r | |
84 | return EFI_INVALID_PARAMETER;\r | |
85 | }\r | |
86 | \r | |
87 | Status = EFI_DEVICE_ERROR;\r | |
88 | \r | |
89 | if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r | |
90 | DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));\r | |
91 | goto ON_EXIT;\r | |
92 | }\r | |
93 | \r | |
94 | //\r | |
95 | // Create a new URB, then poll the execution status.\r | |
96 | //\r | |
97 | Urb = XhcCreateCmdTrb (Xhc, CmdTrb);\r | |
98 | \r | |
99 | if (Urb == NULL) {\r | |
100 | DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));\r | |
101 | Status = EFI_OUT_OF_RESOURCES;\r | |
102 | goto ON_EXIT;\r | |
103 | }\r | |
104 | \r | |
a9292c13 | 105 | Status = XhcExecTransfer (Xhc, TRUE, Urb, Timeout);\r |
a50f7c4c | 106 | *EvtTrb = Urb->EvtTrb;\r |
92870c98 | 107 | \r |
108 | if (Urb->Result == EFI_USB_NOERROR) {\r | |
109 | Status = EFI_SUCCESS;\r | |
110 | }\r | |
111 | \r | |
1847ed0b | 112 | XhcFreeUrb (Xhc, Urb);\r |
92870c98 | 113 | \r |
114 | ON_EXIT:\r | |
115 | return Status;\r | |
116 | }\r | |
117 | \r | |
118 | /**\r | |
119 | Create a new URB for a new transaction.\r | |
120 | \r | |
a9292c13 | 121 | @param Xhc The XHCI Instance\r |
6b4483cd | 122 | @param BusAddr The logical device address assigned by UsbBus driver\r |
92870c98 | 123 | @param EpAddr Endpoint addrress\r |
124 | @param DevSpeed The device speed\r | |
125 | @param MaxPacket The max packet length of the endpoint\r | |
126 | @param Type The transaction type\r | |
127 | @param Request The standard USB request for control transfer\r | |
128 | @param Data The user data to transfer\r | |
129 | @param DataLen The length of data buffer\r | |
130 | @param Callback The function to call when data is transferred\r | |
131 | @param Context The context to the callback\r | |
132 | \r | |
133 | @return Created URB or NULL\r | |
134 | \r | |
135 | **/\r | |
136 | URB*\r | |
137 | XhcCreateUrb (\r | |
a9292c13 | 138 | IN USB_XHCI_INSTANCE *Xhc,\r |
6b4483cd | 139 | IN UINT8 BusAddr,\r |
92870c98 | 140 | IN UINT8 EpAddr,\r |
141 | IN UINT8 DevSpeed,\r | |
142 | IN UINTN MaxPacket,\r | |
143 | IN UINTN Type,\r | |
144 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
145 | IN VOID *Data,\r | |
146 | IN UINTN DataLen,\r | |
147 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r | |
148 | IN VOID *Context\r | |
149 | )\r | |
150 | {\r | |
151 | USB_ENDPOINT *Ep;\r | |
152 | EFI_STATUS Status;\r | |
153 | URB *Urb;\r | |
154 | \r | |
155 | Urb = AllocateZeroPool (sizeof (URB));\r | |
156 | if (Urb == NULL) {\r | |
157 | return NULL;\r | |
158 | }\r | |
159 | \r | |
160 | Urb->Signature = XHC_URB_SIG;\r | |
161 | InitializeListHead (&Urb->UrbList);\r | |
162 | \r | |
163 | Ep = &Urb->Ep;\r | |
6b4483cd | 164 | Ep->BusAddr = BusAddr;\r |
ce9b5900 | 165 | Ep->EpAddr = (UINT8)(EpAddr & 0x0F);\r |
92870c98 | 166 | Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r |
167 | Ep->DevSpeed = DevSpeed;\r | |
168 | Ep->MaxPacket = MaxPacket;\r | |
169 | Ep->Type = Type;\r | |
170 | \r | |
171 | Urb->Request = Request;\r | |
172 | Urb->Data = Data;\r | |
173 | Urb->DataLen = DataLen;\r | |
174 | Urb->Callback = Callback;\r | |
175 | Urb->Context = Context;\r | |
176 | \r | |
177 | Status = XhcCreateTransferTrb (Xhc, Urb);\r | |
7538d536 | 178 | ASSERT_EFI_ERROR (Status);\r |
260fbf53 EL |
179 | if (EFI_ERROR (Status)) {\r |
180 | DEBUG ((EFI_D_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));\r | |
181 | FreePool (Urb);\r | |
182 | Urb = NULL;\r | |
183 | }\r | |
92870c98 | 184 | \r |
185 | return Urb;\r | |
186 | }\r | |
187 | \r | |
1847ed0b EL |
188 | /**\r |
189 | Free an allocated URB.\r | |
190 | \r | |
191 | @param Xhc The XHCI device.\r | |
192 | @param Urb The URB to free.\r | |
193 | \r | |
194 | **/\r | |
195 | VOID\r | |
196 | XhcFreeUrb (\r | |
197 | IN USB_XHCI_INSTANCE *Xhc,\r | |
198 | IN URB *Urb\r | |
199 | )\r | |
200 | {\r | |
201 | if ((Xhc == NULL) || (Urb == NULL)) {\r | |
202 | return;\r | |
203 | }\r | |
d1102dba | 204 | \r |
1847ed0b EL |
205 | if (Urb->DataMap != NULL) {\r |
206 | Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);\r | |
207 | }\r | |
208 | \r | |
209 | FreePool (Urb);\r | |
210 | }\r | |
211 | \r | |
92870c98 | 212 | /**\r |
213 | Create a transfer TRB.\r | |
214 | \r | |
a9292c13 | 215 | @param Xhc The XHCI Instance\r |
92870c98 | 216 | @param Urb The urb used to construct the transfer TRB.\r |
217 | \r | |
218 | @return Created TRB or NULL\r | |
219 | \r | |
220 | **/\r | |
221 | EFI_STATUS\r | |
92870c98 | 222 | XhcCreateTransferTrb (\r |
a9292c13 | 223 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 224 | IN URB *Urb\r |
225 | )\r | |
226 | {\r | |
6b4483cd | 227 | VOID *OutputContext;\r |
92870c98 | 228 | TRANSFER_RING *EPRing;\r |
229 | UINT8 EPType;\r | |
230 | UINT8 SlotId;\r | |
231 | UINT8 Dci;\r | |
232 | TRB *TrbStart;\r | |
233 | UINTN TotalLen;\r | |
234 | UINTN Len;\r | |
235 | UINTN TrbNum;\r | |
1847ed0b EL |
236 | EFI_PCI_IO_PROTOCOL_OPERATION MapOp;\r |
237 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
238 | VOID *Map;\r | |
239 | EFI_STATUS Status;\r | |
92870c98 | 240 | \r |
6b4483cd | 241 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r |
242 | if (SlotId == 0) {\r | |
243 | return EFI_DEVICE_ERROR;\r | |
244 | }\r | |
245 | \r | |
a50f7c4c | 246 | Urb->Finished = FALSE;\r |
247 | Urb->StartDone = FALSE;\r | |
248 | Urb->EndDone = FALSE;\r | |
249 | Urb->Completed = 0;\r | |
250 | Urb->Result = EFI_USB_NOERROR;\r | |
251 | \r | |
ce9b5900 | 252 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r |
a9292c13 | 253 | ASSERT (Dci < 32);\r |
254 | EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];\r | |
92870c98 | 255 | Urb->Ring = EPRing;\r |
1847ed0b | 256 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r |
6b4483cd | 257 | if (Xhc->HcCParams.Data.Csz == 0) {\r |
258 | EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;\r | |
259 | } else {\r | |
260 | EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;\r | |
261 | }\r | |
0b9c0c65 SZ |
262 | \r |
263 | //\r | |
264 | // No need to remap.\r | |
265 | //\r | |
266 | if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {\r | |
1847ed0b EL |
267 | if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {\r |
268 | MapOp = EfiPciIoOperationBusMasterWrite;\r | |
269 | } else {\r | |
270 | MapOp = EfiPciIoOperationBusMasterRead;\r | |
271 | }\r | |
d1102dba | 272 | \r |
1847ed0b EL |
273 | Len = Urb->DataLen;\r |
274 | Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);\r | |
d1102dba | 275 | \r |
1847ed0b EL |
276 | if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {\r |
277 | DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));\r | |
278 | return EFI_OUT_OF_RESOURCES;\r | |
279 | }\r | |
d1102dba | 280 | \r |
1847ed0b EL |
281 | Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);\r |
282 | Urb->DataMap = Map;\r | |
283 | }\r | |
92870c98 | 284 | \r |
285 | //\r | |
286 | // Construct the TRB\r | |
287 | //\r | |
288 | XhcSyncTrsRing (Xhc, EPRing);\r | |
289 | Urb->TrbStart = EPRing->RingEnqueue;\r | |
290 | switch (EPType) {\r | |
291 | case ED_CONTROL_BIDIR:\r | |
92870c98 | 292 | //\r |
293 | // For control transfer, create SETUP_STAGE_TRB first.\r | |
294 | //\r | |
a9292c13 | 295 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
296 | TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;\r | |
297 | TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;\r | |
298 | TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;\r | |
299 | TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;\r | |
300 | TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;\r | |
39e97c39 | 301 | TrbStart->TrbCtrSetup.Length = 8;\r |
6b4483cd | 302 | TrbStart->TrbCtrSetup.IntTarget = 0;\r |
a9292c13 | 303 | TrbStart->TrbCtrSetup.IOC = 1;\r |
304 | TrbStart->TrbCtrSetup.IDT = 1;\r | |
305 | TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;\r | |
92870c98 | 306 | if (Urb->Ep.Direction == EfiUsbDataIn) {\r |
a9292c13 | 307 | TrbStart->TrbCtrSetup.TRT = 3;\r |
92870c98 | 308 | } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r |
a9292c13 | 309 | TrbStart->TrbCtrSetup.TRT = 2;\r |
92870c98 | 310 | } else {\r |
a9292c13 | 311 | TrbStart->TrbCtrSetup.TRT = 0;\r |
92870c98 | 312 | }\r |
313 | //\r | |
314 | // Update the cycle bit\r | |
315 | //\r | |
a9292c13 | 316 | TrbStart->TrbCtrSetup.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 317 | Urb->TrbNum++;\r |
318 | \r | |
319 | //\r | |
320 | // For control transfer, create DATA_STAGE_TRB.\r | |
321 | //\r | |
322 | if (Urb->DataLen > 0) {\r | |
323 | XhcSyncTrsRing (Xhc, EPRing);\r | |
a9292c13 | 324 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
1847ed0b EL |
325 | TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);\r |
326 | TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);\r | |
39e97c39 | 327 | TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;\r |
a9292c13 | 328 | TrbStart->TrbCtrData.TDSize = 0;\r |
6b4483cd | 329 | TrbStart->TrbCtrData.IntTarget = 0;\r |
a9292c13 | 330 | TrbStart->TrbCtrData.ISP = 1;\r |
331 | TrbStart->TrbCtrData.IOC = 1;\r | |
332 | TrbStart->TrbCtrData.IDT = 0;\r | |
333 | TrbStart->TrbCtrData.CH = 0;\r | |
334 | TrbStart->TrbCtrData.Type = TRB_TYPE_DATA_STAGE;\r | |
92870c98 | 335 | if (Urb->Ep.Direction == EfiUsbDataIn) {\r |
a9292c13 | 336 | TrbStart->TrbCtrData.DIR = 1;\r |
92870c98 | 337 | } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r |
a9292c13 | 338 | TrbStart->TrbCtrData.DIR = 0;\r |
92870c98 | 339 | } else {\r |
a9292c13 | 340 | TrbStart->TrbCtrData.DIR = 0;\r |
92870c98 | 341 | }\r |
342 | //\r | |
343 | // Update the cycle bit\r | |
344 | //\r | |
a9292c13 | 345 | TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 346 | Urb->TrbNum++;\r |
347 | }\r | |
348 | //\r | |
349 | // For control transfer, create STATUS_STAGE_TRB.\r | |
350 | // Get the pointer to next TRB for status stage use\r | |
351 | //\r | |
352 | XhcSyncTrsRing (Xhc, EPRing);\r | |
a9292c13 | 353 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
6b4483cd | 354 | TrbStart->TrbCtrStatus.IntTarget = 0;\r |
a9292c13 | 355 | TrbStart->TrbCtrStatus.IOC = 1;\r |
356 | TrbStart->TrbCtrStatus.CH = 0;\r | |
357 | TrbStart->TrbCtrStatus.Type = TRB_TYPE_STATUS_STAGE;\r | |
92870c98 | 358 | if (Urb->Ep.Direction == EfiUsbDataIn) {\r |
a9292c13 | 359 | TrbStart->TrbCtrStatus.DIR = 0;\r |
92870c98 | 360 | } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r |
a9292c13 | 361 | TrbStart->TrbCtrStatus.DIR = 1;\r |
92870c98 | 362 | } else {\r |
a9292c13 | 363 | TrbStart->TrbCtrStatus.DIR = 0;\r |
92870c98 | 364 | }\r |
365 | //\r | |
366 | // Update the cycle bit\r | |
367 | //\r | |
a9292c13 | 368 | TrbStart->TrbCtrStatus.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 369 | //\r |
370 | // Update the enqueue pointer\r | |
371 | //\r | |
372 | XhcSyncTrsRing (Xhc, EPRing);\r | |
373 | Urb->TrbNum++;\r | |
a9292c13 | 374 | Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r |
92870c98 | 375 | \r |
376 | break;\r | |
377 | \r | |
378 | case ED_BULK_OUT:\r | |
379 | case ED_BULK_IN:\r | |
92870c98 | 380 | TotalLen = 0;\r |
381 | Len = 0;\r | |
382 | TrbNum = 0;\r | |
a9292c13 | 383 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
92870c98 | 384 | while (TotalLen < Urb->DataLen) {\r |
385 | if ((TotalLen + 0x10000) >= Urb->DataLen) {\r | |
386 | Len = Urb->DataLen - TotalLen;\r | |
387 | } else {\r | |
388 | Len = 0x10000;\r | |
389 | }\r | |
a9292c13 | 390 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
1847ed0b EL |
391 | TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r |
392 | TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r | |
39e97c39 | 393 | TrbStart->TrbNormal.Length = (UINT32) Len;\r |
a9292c13 | 394 | TrbStart->TrbNormal.TDSize = 0;\r |
6b4483cd | 395 | TrbStart->TrbNormal.IntTarget = 0;\r |
a9292c13 | 396 | TrbStart->TrbNormal.ISP = 1;\r |
397 | TrbStart->TrbNormal.IOC = 1;\r | |
398 | TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;\r | |
92870c98 | 399 | //\r |
400 | // Update the cycle bit\r | |
401 | //\r | |
a9292c13 | 402 | TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 403 | \r |
404 | XhcSyncTrsRing (Xhc, EPRing);\r | |
405 | TrbNum++;\r | |
406 | TotalLen += Len;\r | |
407 | }\r | |
408 | \r | |
409 | Urb->TrbNum = TrbNum;\r | |
a9292c13 | 410 | Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r |
92870c98 | 411 | break;\r |
412 | \r | |
413 | case ED_INTERRUPT_OUT:\r | |
414 | case ED_INTERRUPT_IN:\r | |
92870c98 | 415 | TotalLen = 0;\r |
416 | Len = 0;\r | |
417 | TrbNum = 0;\r | |
a9292c13 | 418 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
92870c98 | 419 | while (TotalLen < Urb->DataLen) {\r |
420 | if ((TotalLen + 0x10000) >= Urb->DataLen) {\r | |
421 | Len = Urb->DataLen - TotalLen;\r | |
422 | } else {\r | |
423 | Len = 0x10000;\r | |
424 | }\r | |
a9292c13 | 425 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
1847ed0b EL |
426 | TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r |
427 | TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r | |
39e97c39 | 428 | TrbStart->TrbNormal.Length = (UINT32) Len;\r |
a9292c13 | 429 | TrbStart->TrbNormal.TDSize = 0;\r |
6b4483cd | 430 | TrbStart->TrbNormal.IntTarget = 0;\r |
a9292c13 | 431 | TrbStart->TrbNormal.ISP = 1;\r |
432 | TrbStart->TrbNormal.IOC = 1;\r | |
433 | TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;\r | |
92870c98 | 434 | //\r |
435 | // Update the cycle bit\r | |
436 | //\r | |
a9292c13 | 437 | TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 438 | \r |
439 | XhcSyncTrsRing (Xhc, EPRing);\r | |
440 | TrbNum++;\r | |
441 | TotalLen += Len;\r | |
442 | }\r | |
443 | \r | |
444 | Urb->TrbNum = TrbNum;\r | |
a9292c13 | 445 | Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r |
92870c98 | 446 | break;\r |
447 | \r | |
448 | default:\r | |
449 | DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));\r | |
450 | ASSERT (FALSE);\r | |
451 | break;\r | |
452 | }\r | |
453 | \r | |
454 | return EFI_SUCCESS;\r | |
455 | }\r | |
456 | \r | |
457 | \r | |
458 | /**\r | |
459 | Initialize the XHCI host controller for schedule.\r | |
460 | \r | |
a9292c13 | 461 | @param Xhc The XHCI Instance to be initialized.\r |
92870c98 | 462 | \r |
463 | **/\r | |
464 | VOID\r | |
465 | XhcInitSched (\r | |
a9292c13 | 466 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 467 | )\r |
468 | {\r | |
469 | VOID *Dcbaa;\r | |
1847ed0b | 470 | EFI_PHYSICAL_ADDRESS DcbaaPhy;\r |
92870c98 | 471 | UINT64 CmdRing;\r |
d1102dba | 472 | EFI_PHYSICAL_ADDRESS CmdRingPhy;\r |
92870c98 | 473 | UINTN Entries;\r |
474 | UINT32 MaxScratchpadBufs;\r | |
475 | UINT64 *ScratchBuf;\r | |
1847ed0b EL |
476 | EFI_PHYSICAL_ADDRESS ScratchPhy;\r |
477 | UINT64 *ScratchEntry;\r | |
478 | EFI_PHYSICAL_ADDRESS ScratchEntryPhy;\r | |
92870c98 | 479 | UINT32 Index;\r |
1847ed0b EL |
480 | UINTN *ScratchEntryMap;\r |
481 | EFI_STATUS Status;\r | |
482 | \r | |
483 | //\r | |
484 | // Initialize memory management.\r | |
485 | //\r | |
486 | Xhc->MemPool = UsbHcInitMemPool (Xhc->PciIo);\r | |
487 | ASSERT (Xhc->MemPool != NULL);\r | |
92870c98 | 488 | \r |
489 | //\r | |
490 | // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)\r | |
491 | // to enable the device slots that system software is going to use.\r | |
492 | //\r | |
493 | Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;\r | |
494 | ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);\r | |
495 | XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);\r | |
496 | \r | |
497 | //\r | |
498 | // The Device Context Base Address Array entry associated with each allocated Device Slot\r | |
499 | // shall contain a 64-bit pointer to the base of the associated Device Context.\r | |
500 | // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.\r | |
501 | // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.\r | |
502 | //\r | |
503 | Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);\r | |
1847ed0b | 504 | Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);\r |
92870c98 | 505 | ASSERT (Dcbaa != NULL);\r |
a9292c13 | 506 | ZeroMem (Dcbaa, Entries);\r |
92870c98 | 507 | \r |
508 | //\r | |
509 | // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.\r | |
510 | // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run\r | |
511 | // mode (Run/Stop(R/S) ='1').\r | |
512 | //\r | |
513 | MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);\r | |
514 | Xhc->MaxScratchpadBufs = MaxScratchpadBufs;\r | |
ce9b5900 | 515 | ASSERT (MaxScratchpadBufs <= 1023);\r |
92870c98 | 516 | if (MaxScratchpadBufs != 0) {\r |
1847ed0b EL |
517 | //\r |
518 | // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them\r | |
519 | //\r | |
520 | ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);\r | |
521 | ASSERT (ScratchEntryMap != NULL);\r | |
522 | Xhc->ScratchEntryMap = ScratchEntryMap;\r | |
d1102dba | 523 | \r |
1847ed0b EL |
524 | //\r |
525 | // Allocate the buffer to record the host address for each entry\r | |
526 | //\r | |
527 | ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);\r | |
528 | ASSERT (ScratchEntry != NULL);\r | |
529 | Xhc->ScratchEntry = ScratchEntry;\r | |
530 | \r | |
414f5bd1 | 531 | ScratchPhy = 0;\r |
1847ed0b EL |
532 | Status = UsbHcAllocateAlignedPages (\r |
533 | Xhc->PciIo,\r | |
534 | EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),\r | |
535 | Xhc->PageSize,\r | |
d1102dba | 536 | (VOID **) &ScratchBuf,\r |
1847ed0b EL |
537 | &ScratchPhy,\r |
538 | &Xhc->ScratchMap\r | |
539 | );\r | |
540 | ASSERT_EFI_ERROR (Status);\r | |
541 | \r | |
a9292c13 | 542 | ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));\r |
92870c98 | 543 | Xhc->ScratchBuf = ScratchBuf;\r |
544 | \r | |
1847ed0b EL |
545 | //\r |
546 | // Allocate each scratch buffer\r | |
547 | //\r | |
92870c98 | 548 | for (Index = 0; Index < MaxScratchpadBufs; Index++) {\r |
414f5bd1 | 549 | ScratchEntryPhy = 0;\r |
1847ed0b EL |
550 | Status = UsbHcAllocateAlignedPages (\r |
551 | Xhc->PciIo,\r | |
552 | EFI_SIZE_TO_PAGES (Xhc->PageSize),\r | |
553 | Xhc->PageSize,\r | |
554 | (VOID **) &ScratchEntry[Index],\r | |
555 | &ScratchEntryPhy,\r | |
556 | (VOID **) &ScratchEntryMap[Index]\r | |
557 | );\r | |
558 | ASSERT_EFI_ERROR (Status);\r | |
559 | ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);\r | |
560 | //\r | |
561 | // Fill with the PCI device address\r | |
562 | //\r | |
563 | *ScratchBuf++ = ScratchEntryPhy;\r | |
92870c98 | 564 | }\r |
92870c98 | 565 | //\r |
566 | // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the\r | |
567 | // Device Context Base Address Array points to the Scratchpad Buffer Array.\r | |
568 | //\r | |
1847ed0b | 569 | *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;\r |
92870c98 | 570 | }\r |
571 | \r | |
572 | //\r | |
573 | // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with\r | |
574 | // a 64-bit address pointing to where the Device Context Base Address Array is located.\r | |
575 | //\r | |
a9292c13 | 576 | Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;\r |
6b4483cd | 577 | //\r |
578 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r | |
579 | // So divide it to two 32-bytes width register access.\r | |
580 | //\r | |
1847ed0b EL |
581 | DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);\r |
582 | XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));\r | |
583 | XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));\r | |
584 | \r | |
ce9b5900 | 585 | DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));\r |
92870c98 | 586 | \r |
587 | //\r | |
588 | // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register\r | |
589 | // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.\r | |
590 | // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall\r | |
591 | // always be '0'.\r | |
592 | //\r | |
593 | CreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);\r | |
594 | //\r | |
595 | // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a\r | |
596 | // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.\r | |
597 | // So we set RCS as inverted PCS init value to let Command Ring empty\r | |
598 | //\r | |
599 | CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;\r | |
1847ed0b EL |
600 | CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);\r |
601 | ASSERT ((CmdRingPhy & 0x3F) == 0);\r | |
602 | CmdRingPhy |= XHC_CRCR_RCS;\r | |
6b4483cd | 603 | //\r |
604 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r | |
605 | // So divide it to two 32-bytes width register access.\r | |
606 | //\r | |
1847ed0b EL |
607 | XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));\r |
608 | XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));\r | |
92870c98 | 609 | \r |
92870c98 | 610 | //\r |
611 | // Disable the 'interrupter enable' bit in USB_CMD\r | |
612 | // and clear IE & IP bit in all Interrupter X Management Registers.\r | |
613 | //\r | |
614 | XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);\r | |
615 | for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {\r | |
616 | XhcClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);\r | |
617 | XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);\r | |
618 | }\r | |
619 | \r | |
620 | //\r | |
621 | // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer\r | |
622 | //\r | |
6b4483cd | 623 | CreateEventRing (Xhc, &Xhc->EventRing);\r |
396ae94d RN |
624 | DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",\r |
625 | Xhc->CmdRing.RingSeg0, (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,\r | |
626 | Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER\r | |
627 | ));\r | |
92870c98 | 628 | }\r |
629 | \r | |
630 | /**\r | |
631 | System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r | |
632 | condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r | |
633 | Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r | |
634 | reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r | |
635 | Stopped to the Running state.\r | |
636 | \r | |
a9292c13 | 637 | @param Xhc The XHCI Instance.\r |
92870c98 | 638 | @param Urb The urb which makes the endpoint halted.\r |
639 | \r | |
640 | @retval EFI_SUCCESS The recovery is successful.\r | |
641 | @retval Others Failed to recovery halted endpoint.\r | |
642 | \r | |
643 | **/\r | |
644 | EFI_STATUS\r | |
645 | EFIAPI\r | |
646 | XhcRecoverHaltedEndpoint (\r | |
a9292c13 | 647 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 648 | IN URB *Urb\r |
649 | )\r | |
650 | {\r | |
a9292c13 | 651 | EFI_STATUS Status;\r |
a9292c13 | 652 | UINT8 Dci;\r |
653 | UINT8 SlotId;\r | |
92870c98 | 654 | \r |
6b4483cd | 655 | Status = EFI_SUCCESS;\r |
656 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r | |
657 | if (SlotId == 0) {\r | |
658 | return EFI_DEVICE_ERROR;\r | |
659 | }\r | |
660 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r | |
661 | ASSERT (Dci < 32);\r | |
d1102dba | 662 | \r |
92870c98 | 663 | DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));\r |
664 | \r | |
665 | //\r | |
666 | // 1) Send Reset endpoint command to transit from halt to stop state\r | |
667 | //\r | |
12e6c738 | 668 | Status = XhcResetEndpoint(Xhc, SlotId, Dci);\r |
260fbf53 EL |
669 | if (EFI_ERROR(Status)) {\r |
670 | DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));\r | |
671 | goto Done;\r | |
672 | }\r | |
92870c98 | 673 | \r |
674 | //\r | |
675 | // 2)Set dequeue pointer\r | |
676 | //\r | |
12e6c738 FT |
677 | Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);\r |
678 | if (EFI_ERROR(Status)) {\r | |
679 | DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));\r | |
680 | goto Done;\r | |
681 | }\r | |
682 | \r | |
683 | //\r | |
684 | // 3)Ring the doorbell to transit from stop to active\r | |
685 | //\r | |
686 | XhcRingDoorBell (Xhc, SlotId, Dci);\r | |
687 | \r | |
688 | Done:\r | |
689 | return Status;\r | |
690 | }\r | |
691 | \r | |
692 | /**\r | |
693 | System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r | |
694 | Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r | |
695 | the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r | |
696 | state.\r | |
697 | \r | |
698 | @param Xhc The XHCI Instance.\r | |
699 | @param Urb The urb which doesn't get completed in a specified timeout range.\r | |
700 | \r | |
701 | @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r | |
49be9c3c | 702 | @retval EFI_ALREADY_STARTED The Urb is finished so no deque is needed.\r |
12e6c738 FT |
703 | @retval Others Failed to stop the endpoint and dequeue the TDs.\r |
704 | \r | |
705 | **/\r | |
706 | EFI_STATUS\r | |
707 | EFIAPI\r | |
708 | XhcDequeueTrbFromEndpoint (\r | |
709 | IN USB_XHCI_INSTANCE *Xhc,\r | |
710 | IN URB *Urb\r | |
711 | )\r | |
712 | {\r | |
713 | EFI_STATUS Status;\r | |
714 | UINT8 Dci;\r | |
715 | UINT8 SlotId;\r | |
716 | \r | |
717 | Status = EFI_SUCCESS;\r | |
718 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r | |
719 | if (SlotId == 0) {\r | |
720 | return EFI_DEVICE_ERROR;\r | |
721 | }\r | |
722 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r | |
723 | ASSERT (Dci < 32);\r | |
d1102dba | 724 | \r |
12e6c738 FT |
725 | DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));\r |
726 | \r | |
727 | //\r | |
728 | // 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint\r | |
729 | //\r | |
49be9c3c | 730 | Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);\r |
12e6c738 FT |
731 | if (EFI_ERROR(Status)) {\r |
732 | DEBUG ((EFI_D_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));\r | |
733 | goto Done;\r | |
734 | }\r | |
735 | \r | |
736 | //\r | |
737 | // 2)Set dequeue pointer\r | |
738 | //\r | |
49be9c3c RN |
739 | if (Urb->Finished && Urb->Result == EFI_USB_NOERROR) {\r |
740 | //\r | |
741 | // Return Already Started to indicate the pending URB is finished.\r | |
742 | // This fixes BULK data loss when transfer is detected as timeout\r | |
743 | // but finished just before stopping endpoint.\r | |
744 | //\r | |
745 | Status = EFI_ALREADY_STARTED;\r | |
746 | DEBUG ((DEBUG_INFO, "XhcDequeueTrbFromEndpoint: Pending URB is finished: Length Actual/Expect = %d/%d!\n", Urb->Completed, Urb->DataLen));\r | |
747 | } else {\r | |
748 | Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);\r | |
749 | if (EFI_ERROR (Status)) {\r | |
750 | DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));\r | |
751 | goto Done;\r | |
752 | }\r | |
260fbf53 | 753 | }\r |
92870c98 | 754 | \r |
755 | //\r | |
756 | // 3)Ring the doorbell to transit from stop to active\r | |
757 | //\r | |
758 | XhcRingDoorBell (Xhc, SlotId, Dci);\r | |
759 | \r | |
260fbf53 | 760 | Done:\r |
92870c98 | 761 | return Status;\r |
762 | }\r | |
763 | \r | |
764 | /**\r | |
765 | Create XHCI event ring.\r | |
766 | \r | |
a9292c13 | 767 | @param Xhc The XHCI Instance.\r |
92870c98 | 768 | @param EventRing The created event ring.\r |
769 | \r | |
770 | **/\r | |
771 | VOID\r | |
92870c98 | 772 | CreateEventRing (\r |
a9292c13 | 773 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 774 | OUT EVENT_RING *EventRing\r |
775 | )\r | |
776 | {\r | |
777 | VOID *Buf;\r | |
778 | EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;\r | |
1847ed0b EL |
779 | UINTN Size;\r |
780 | EFI_PHYSICAL_ADDRESS ERSTPhy;\r | |
781 | EFI_PHYSICAL_ADDRESS DequeuePhy;\r | |
92870c98 | 782 | \r |
783 | ASSERT (EventRing != NULL);\r | |
784 | \r | |
1847ed0b EL |
785 | Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;\r |
786 | Buf = UsbHcAllocateMem (Xhc->MemPool, Size);\r | |
92870c98 | 787 | ASSERT (Buf != NULL);\r |
788 | ASSERT (((UINTN) Buf & 0x3F) == 0);\r | |
1847ed0b | 789 | ZeroMem (Buf, Size);\r |
92870c98 | 790 | \r |
791 | EventRing->EventRingSeg0 = Buf;\r | |
92870c98 | 792 | EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;\r |
a9292c13 | 793 | EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r |
794 | EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r | |
d1102dba | 795 | \r |
1847ed0b | 796 | DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);\r |
d1102dba | 797 | \r |
92870c98 | 798 | //\r |
799 | // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'\r | |
800 | // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.\r | |
801 | //\r | |
802 | EventRing->EventRingCCS = 1;\r | |
803 | \r | |
e1f2dfec | 804 | Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;\r |
1847ed0b | 805 | Buf = UsbHcAllocateMem (Xhc->MemPool, Size);\r |
92870c98 | 806 | ASSERT (Buf != NULL);\r |
807 | ASSERT (((UINTN) Buf & 0x3F) == 0);\r | |
1847ed0b | 808 | ZeroMem (Buf, Size);\r |
92870c98 | 809 | \r |
810 | ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;\r | |
811 | EventRing->ERSTBase = ERSTBase;\r | |
1847ed0b EL |
812 | ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);\r |
813 | ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);\r | |
92870c98 | 814 | ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;\r |
815 | \r | |
1847ed0b EL |
816 | ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);\r |
817 | \r | |
92870c98 | 818 | //\r |
819 | // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)\r | |
820 | //\r | |
821 | XhcWriteRuntimeReg (\r | |
822 | Xhc,\r | |
6b4483cd | 823 | XHC_ERSTSZ_OFFSET,\r |
92870c98 | 824 | ERST_NUMBER\r |
825 | );\r | |
826 | //\r | |
827 | // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)\r | |
828 | //\r | |
6b4483cd | 829 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r |
830 | // So divide it to two 32-bytes width register access.\r | |
831 | //\r | |
832 | XhcWriteRuntimeReg (\r | |
833 | Xhc,\r | |
834 | XHC_ERDP_OFFSET,\r | |
1847ed0b | 835 | XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)\r |
6b4483cd | 836 | );\r |
837 | XhcWriteRuntimeReg (\r | |
92870c98 | 838 | Xhc,\r |
6b4483cd | 839 | XHC_ERDP_OFFSET + 4,\r |
1847ed0b | 840 | XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)\r |
92870c98 | 841 | );\r |
842 | //\r | |
843 | // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)\r | |
844 | //\r | |
6b4483cd | 845 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r |
846 | // So divide it to two 32-bytes width register access.\r | |
847 | //\r | |
848 | XhcWriteRuntimeReg (\r | |
849 | Xhc,\r | |
850 | XHC_ERSTBA_OFFSET,\r | |
1847ed0b | 851 | XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)\r |
6b4483cd | 852 | );\r |
853 | XhcWriteRuntimeReg (\r | |
92870c98 | 854 | Xhc,\r |
6b4483cd | 855 | XHC_ERSTBA_OFFSET + 4,\r |
1847ed0b | 856 | XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)\r |
92870c98 | 857 | );\r |
858 | //\r | |
859 | // Need set IMAN IE bit to enble the ring interrupt\r | |
860 | //\r | |
6b4483cd | 861 | XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET, XHC_IMAN_IE);\r |
92870c98 | 862 | }\r |
863 | \r | |
864 | /**\r | |
865 | Create XHCI transfer ring.\r | |
866 | \r | |
a9292c13 | 867 | @param Xhc The XHCI Instance.\r |
92870c98 | 868 | @param TrbNum The number of TRB in the ring.\r |
869 | @param TransferRing The created transfer ring.\r | |
870 | \r | |
871 | **/\r | |
872 | VOID\r | |
92870c98 | 873 | CreateTransferRing (\r |
a9292c13 | 874 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 875 | IN UINTN TrbNum,\r |
876 | OUT TRANSFER_RING *TransferRing\r | |
877 | )\r | |
878 | {\r | |
879 | VOID *Buf;\r | |
a9292c13 | 880 | LINK_TRB *EndTrb;\r |
1847ed0b | 881 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
92870c98 | 882 | \r |
1847ed0b | 883 | Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);\r |
92870c98 | 884 | ASSERT (Buf != NULL);\r |
885 | ASSERT (((UINTN) Buf & 0x3F) == 0);\r | |
a9292c13 | 886 | ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r |
92870c98 | 887 | \r |
888 | TransferRing->RingSeg0 = Buf;\r | |
889 | TransferRing->TrbNumber = TrbNum;\r | |
a9292c13 | 890 | TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r |
891 | TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r | |
92870c98 | 892 | TransferRing->RingPCS = 1;\r |
893 | //\r | |
894 | // 4.9.2 Transfer Ring Management\r | |
895 | // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to\r | |
896 | // point to the first TRB in the ring.\r | |
897 | //\r | |
a9292c13 | 898 | EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));\r |
92870c98 | 899 | EndTrb->Type = TRB_TYPE_LINK;\r |
1847ed0b EL |
900 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r |
901 | EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
902 | EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
92870c98 | 903 | //\r |
904 | // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.\r | |
905 | //\r | |
906 | EndTrb->TC = 1;\r | |
907 | //\r | |
908 | // Set Cycle bit as other TRB PCS init value\r | |
909 | //\r | |
910 | EndTrb->CycleBit = 0;\r | |
911 | }\r | |
912 | \r | |
913 | /**\r | |
914 | Free XHCI event ring.\r | |
915 | \r | |
a9292c13 | 916 | @param Xhc The XHCI Instance.\r |
92870c98 | 917 | @param EventRing The event ring to be freed.\r |
918 | \r | |
919 | **/\r | |
920 | EFI_STATUS\r | |
921 | EFIAPI\r | |
922 | XhcFreeEventRing (\r | |
a9292c13 | 923 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 924 | IN EVENT_RING *EventRing\r |
925 | )\r | |
926 | {\r | |
92870c98 | 927 | if(EventRing->EventRingSeg0 == NULL) {\r |
928 | return EFI_SUCCESS;\r | |
929 | }\r | |
930 | \r | |
92870c98 | 931 | //\r |
1847ed0b | 932 | // Free EventRing Segment 0\r |
92870c98 | 933 | //\r |
1847ed0b | 934 | UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);\r |
92870c98 | 935 | \r |
936 | //\r | |
1847ed0b | 937 | // Free ESRT table\r |
92870c98 | 938 | //\r |
1847ed0b | 939 | UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);\r |
92870c98 | 940 | return EFI_SUCCESS;\r |
941 | }\r | |
942 | \r | |
943 | /**\r | |
944 | Free the resouce allocated at initializing schedule.\r | |
945 | \r | |
a9292c13 | 946 | @param Xhc The XHCI Instance.\r |
92870c98 | 947 | \r |
948 | **/\r | |
949 | VOID\r | |
950 | XhcFreeSched (\r | |
a9292c13 | 951 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 952 | )\r |
953 | {\r | |
1847ed0b EL |
954 | UINT32 Index;\r |
955 | UINT64 *ScratchEntry;\r | |
d1102dba | 956 | \r |
92870c98 | 957 | if (Xhc->ScratchBuf != NULL) {\r |
1847ed0b | 958 | ScratchEntry = Xhc->ScratchEntry;\r |
92870c98 | 959 | for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {\r |
1847ed0b EL |
960 | //\r |
961 | // Free Scratchpad Buffers\r | |
962 | //\r | |
963 | UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);\r | |
92870c98 | 964 | }\r |
1847ed0b EL |
965 | //\r |
966 | // Free Scratchpad Buffer Array\r | |
967 | //\r | |
968 | UsbHcFreeAlignedPages (Xhc->PciIo, Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);\r | |
969 | FreePool (Xhc->ScratchEntryMap);\r | |
970 | FreePool (Xhc->ScratchEntry);\r | |
971 | }\r | |
972 | \r | |
973 | if (Xhc->CmdRing.RingSeg0 != NULL) {\r | |
974 | UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);\r | |
975 | Xhc->CmdRing.RingSeg0 = NULL;\r | |
92870c98 | 976 | }\r |
d1102dba | 977 | \r |
1847ed0b | 978 | XhcFreeEventRing (Xhc,&Xhc->EventRing);\r |
92870c98 | 979 | \r |
980 | if (Xhc->DCBAA != NULL) {\r | |
1847ed0b | 981 | UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));\r |
92870c98 | 982 | Xhc->DCBAA = NULL;\r |
983 | }\r | |
d1102dba | 984 | \r |
1847ed0b EL |
985 | //\r |
986 | // Free memory pool at last\r | |
987 | //\r | |
988 | if (Xhc->MemPool != NULL) {\r | |
989 | UsbHcFreeMemPool (Xhc->MemPool);\r | |
990 | Xhc->MemPool = NULL;\r | |
92870c98 | 991 | }\r |
92870c98 | 992 | }\r |
993 | \r | |
994 | /**\r | |
5a4b3388 | 995 | Check if the Trb is a transaction of the URB.\r |
a50f7c4c | 996 | \r |
9750503a | 997 | @param Xhc The XHCI Instance.\r |
5a4b3388 RN |
998 | @param Trb The TRB to be checked\r |
999 | @param Urb The URB to be checked.\r | |
a50f7c4c | 1000 | \r |
5a4b3388 RN |
1001 | @retval TRUE It is a transaction of the URB.\r |
1002 | @retval FALSE It is not any transaction of the URB.\r | |
a50f7c4c | 1003 | \r |
1004 | **/\r | |
1005 | BOOLEAN\r | |
5a4b3388 | 1006 | IsTransferRingTrb (\r |
a50f7c4c | 1007 | IN USB_XHCI_INSTANCE *Xhc,\r |
1008 | IN TRB_TEMPLATE *Trb,\r | |
5a4b3388 | 1009 | IN URB *Urb\r |
a50f7c4c | 1010 | )\r |
1011 | {\r | |
5a4b3388 RN |
1012 | LINK_TRB *LinkTrb;\r |
1013 | TRB_TEMPLATE *CheckedTrb;\r | |
1014 | UINTN Index;\r | |
1015 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
a50f7c4c | 1016 | \r |
5a4b3388 RN |
1017 | CheckedTrb = Urb->TrbStart;\r |
1018 | for (Index = 0; Index < Urb->TrbNum; Index++) {\r | |
1019 | if (Trb == CheckedTrb) {\r | |
1020 | return TRUE;\r | |
1021 | }\r | |
1022 | CheckedTrb++;\r | |
1023 | //\r | |
1024 | // If the checked TRB is the link TRB at the end of the transfer ring,\r | |
1025 | // recircle it to the head of the ring.\r | |
1026 | //\r | |
1027 | if (CheckedTrb->Type == TRB_TYPE_LINK) {\r | |
1028 | LinkTrb = (LINK_TRB *) CheckedTrb;\r | |
1029 | PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32));\r | |
1030 | CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));\r | |
1031 | ASSERT (CheckedTrb == Urb->Ring->RingSeg0);\r | |
a50f7c4c | 1032 | }\r |
1033 | }\r | |
1034 | \r | |
1035 | return FALSE;\r | |
1036 | }\r | |
1037 | \r | |
1038 | /**\r | |
5a4b3388 | 1039 | Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.\r |
92870c98 | 1040 | \r |
5a4b3388 RN |
1041 | @param Xhc The XHCI Instance.\r |
1042 | @param Trb The TRB to be checked.\r | |
1043 | @param Urb The pointer to the matched Urb.\r | |
92870c98 | 1044 | \r |
5a4b3388 RN |
1045 | @retval TRUE The Trb is matched with a transaction of the URBs in the async list.\r |
1046 | @retval FALSE The Trb is not matched with any URBs in the async list.\r | |
92870c98 | 1047 | \r |
1048 | **/\r | |
1049 | BOOLEAN\r | |
5a4b3388 RN |
1050 | IsAsyncIntTrb (\r |
1051 | IN USB_XHCI_INSTANCE *Xhc,\r | |
a50f7c4c | 1052 | IN TRB_TEMPLATE *Trb,\r |
5a4b3388 | 1053 | OUT URB **Urb\r |
92870c98 | 1054 | )\r |
1055 | {\r | |
5a4b3388 RN |
1056 | LIST_ENTRY *Entry;\r |
1057 | LIST_ENTRY *Next;\r | |
1058 | URB *CheckedUrb;\r | |
92870c98 | 1059 | \r |
5a4b3388 RN |
1060 | EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r |
1061 | CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r | |
1062 | if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {\r | |
1063 | *Urb = CheckedUrb;\r | |
a50f7c4c | 1064 | return TRUE;\r |
92870c98 | 1065 | }\r |
92870c98 | 1066 | }\r |
1067 | \r | |
a50f7c4c | 1068 | return FALSE;\r |
92870c98 | 1069 | }\r |
1070 | \r | |
5a4b3388 | 1071 | \r |
92870c98 | 1072 | /**\r |
1073 | Check the URB's execution result and update the URB's\r | |
1074 | result accordingly.\r | |
1075 | \r | |
a9292c13 | 1076 | @param Xhc The XHCI Instance.\r |
92870c98 | 1077 | @param Urb The URB to check result.\r |
1078 | \r | |
1079 | @return Whether the result of URB transfer is finialized.\r | |
1080 | \r | |
1081 | **/\r | |
a40a5c08 | 1082 | BOOLEAN\r |
92870c98 | 1083 | XhcCheckUrbResult (\r |
a9292c13 | 1084 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1085 | IN URB *Urb\r |
1086 | )\r | |
1087 | {\r | |
92870c98 | 1088 | EVT_TRB_TRANSFER *EvtTrb;\r |
a9292c13 | 1089 | TRB_TEMPLATE *TRBPtr;\r |
92870c98 | 1090 | UINTN Index;\r |
1091 | UINT8 TRBType;\r | |
1092 | EFI_STATUS Status;\r | |
a50f7c4c | 1093 | URB *AsyncUrb;\r |
1094 | URB *CheckedUrb;\r | |
1095 | UINT64 XhcDequeue;\r | |
1096 | UINT32 High;\r | |
1097 | UINT32 Low;\r | |
1847ed0b | 1098 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
92870c98 | 1099 | \r |
1100 | ASSERT ((Xhc != NULL) && (Urb != NULL));\r | |
1101 | \r | |
09e4dbeb | 1102 | Status = EFI_SUCCESS;\r |
1103 | AsyncUrb = NULL;\r | |
a50f7c4c | 1104 | \r |
1105 | if (Urb->Finished) {\r | |
1106 | goto EXIT;\r | |
1107 | }\r | |
1108 | \r | |
1109 | EvtTrb = NULL;\r | |
92870c98 | 1110 | \r |
1111 | if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r | |
1112 | Urb->Result |= EFI_USB_ERR_SYSTEM;\r | |
92870c98 | 1113 | goto EXIT;\r |
1114 | }\r | |
1115 | \r | |
1116 | //\r | |
a50f7c4c | 1117 | // Traverse the event ring to find out all new events from the previous check.\r |
92870c98 | 1118 | //\r |
a50f7c4c | 1119 | XhcSyncEventRing (Xhc, &Xhc->EventRing);\r |
1120 | for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {\r | |
1121 | Status = XhcCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));\r | |
92870c98 | 1122 | if (Status == EFI_NOT_READY) {\r |
a50f7c4c | 1123 | //\r |
1124 | // All new events are handled, return directly.\r | |
1125 | //\r | |
92870c98 | 1126 | goto EXIT;\r |
1127 | }\r | |
1128 | \r | |
6b4483cd | 1129 | //\r |
1130 | // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.\r | |
1131 | //\r | |
1132 | if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {\r | |
1133 | continue;\r | |
1134 | }\r | |
d1102dba | 1135 | \r |
1847ed0b EL |
1136 | //\r |
1137 | // Need convert pci device address to host address\r | |
1138 | //\r | |
1139 | PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));\r | |
1140 | TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));\r | |
92870c98 | 1141 | \r |
a50f7c4c | 1142 | //\r |
49be9c3c RN |
1143 | // Update the status of URB including the pending URB, the URB that is currently checked,\r |
1144 | // and URBs in the XHCI's async interrupt transfer list.\r | |
a50f7c4c | 1145 | // This way is used to avoid that those completed async transfer events don't get\r |
1146 | // handled in time and are flushed by newer coming events.\r | |
1147 | //\r | |
49be9c3c RN |
1148 | if (Xhc->PendingUrb != NULL && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {\r |
1149 | CheckedUrb = Xhc->PendingUrb;\r | |
1150 | } else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {\r | |
a50f7c4c | 1151 | CheckedUrb = Urb;\r |
d1102dba | 1152 | } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {\r |
a50f7c4c | 1153 | CheckedUrb = AsyncUrb;\r |
1154 | } else {\r | |
1155 | continue;\r | |
1156 | }\r | |
d1102dba | 1157 | \r |
a50f7c4c | 1158 | switch (EvtTrb->Completecode) {\r |
1159 | case TRB_COMPLETION_STALL_ERROR:\r | |
1160 | CheckedUrb->Result |= EFI_USB_ERR_STALL;\r | |
1161 | CheckedUrb->Finished = TRUE;\r | |
1162 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r | |
c3f44a77 | 1163 | goto EXIT;\r |
92870c98 | 1164 | \r |
a50f7c4c | 1165 | case TRB_COMPLETION_BABBLE_ERROR:\r |
1166 | CheckedUrb->Result |= EFI_USB_ERR_BABBLE;\r | |
1167 | CheckedUrb->Finished = TRUE;\r | |
1168 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r | |
c3f44a77 | 1169 | goto EXIT;\r |
6b4483cd | 1170 | \r |
a50f7c4c | 1171 | case TRB_COMPLETION_DATA_BUFFER_ERROR:\r |
1172 | CheckedUrb->Result |= EFI_USB_ERR_BUFFER;\r | |
1173 | CheckedUrb->Finished = TRUE;\r | |
1174 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));\r | |
c3f44a77 | 1175 | goto EXIT;\r |
a50f7c4c | 1176 | \r |
1177 | case TRB_COMPLETION_USB_TRANSACTION_ERROR:\r | |
1178 | CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r | |
1179 | CheckedUrb->Finished = TRUE;\r | |
1180 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r | |
c3f44a77 | 1181 | goto EXIT;\r |
a50f7c4c | 1182 | \r |
49be9c3c RN |
1183 | case TRB_COMPLETION_STOPPED:\r |
1184 | case TRB_COMPLETION_STOPPED_LENGTH_INVALID:\r | |
1185 | CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r | |
1186 | CheckedUrb->Finished = TRUE;\r | |
1187 | //\r | |
1188 | // The pending URB is timeout and force stopped when stopping endpoint.\r | |
1189 | // Continue the loop to receive the Command Complete Event for stopping endpoint.\r | |
1190 | //\r | |
1191 | continue;\r | |
1192 | \r | |
a50f7c4c | 1193 | case TRB_COMPLETION_SHORT_PACKET:\r |
1194 | case TRB_COMPLETION_SUCCESS:\r | |
1195 | if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {\r | |
90d6dfb9 | 1196 | DEBUG ((EFI_D_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));\r |
a50f7c4c | 1197 | }\r |
1198 | \r | |
1199 | TRBType = (UINT8) (TRBPtr->Type);\r | |
1200 | if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r | |
1201 | (TRBType == TRB_TYPE_NORMAL) ||\r | |
1202 | (TRBType == TRB_TYPE_ISOCH)) {\r | |
5956af2b | 1203 | CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);\r |
a50f7c4c | 1204 | }\r |
1205 | \r | |
1206 | break;\r | |
1207 | \r | |
1208 | default:\r | |
1209 | DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));\r | |
1210 | CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r | |
1211 | CheckedUrb->Finished = TRUE;\r | |
c3f44a77 | 1212 | goto EXIT;\r |
a50f7c4c | 1213 | }\r |
1214 | \r | |
1215 | //\r | |
1216 | // Only check first and end Trb event address\r | |
1217 | //\r | |
1218 | if (TRBPtr == CheckedUrb->TrbStart) {\r | |
1219 | CheckedUrb->StartDone = TRUE;\r | |
1220 | }\r | |
1221 | \r | |
1222 | if (TRBPtr == CheckedUrb->TrbEnd) {\r | |
1223 | CheckedUrb->EndDone = TRUE;\r | |
1224 | }\r | |
1225 | \r | |
1226 | if (CheckedUrb->StartDone && CheckedUrb->EndDone) {\r | |
1227 | CheckedUrb->Finished = TRUE;\r | |
1228 | CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;\r | |
92870c98 | 1229 | }\r |
1230 | }\r | |
1231 | \r | |
1232 | EXIT:\r | |
a50f7c4c | 1233 | \r |
1234 | //\r | |
1235 | // Advance event ring to last available entry\r | |
1236 | //\r | |
1237 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r | |
1238 | // So divide it to two 32-bytes width register access.\r | |
1239 | //\r | |
1240 | Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);\r | |
1241 | High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);\r | |
1242 | XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);\r | |
1243 | \r | |
1847ed0b EL |
1244 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));\r |
1245 | \r | |
1246 | if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {\r | |
a50f7c4c | 1247 | //\r |
1248 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r | |
1249 | // So divide it to two 32-bytes width register access.\r | |
1250 | //\r | |
1847ed0b EL |
1251 | XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);\r |
1252 | XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));\r | |
a50f7c4c | 1253 | }\r |
1254 | \r | |
a40a5c08 | 1255 | return Urb->Finished;\r |
92870c98 | 1256 | }\r |
1257 | \r | |
1258 | \r | |
1259 | /**\r | |
1260 | Execute the transfer by polling the URB. This is a synchronous operation.\r | |
1261 | \r | |
a9292c13 | 1262 | @param Xhc The XHCI Instance.\r |
92870c98 | 1263 | @param CmdTransfer The executed URB is for cmd transfer or not.\r |
1264 | @param Urb The URB to execute.\r | |
a9292c13 | 1265 | @param Timeout The time to wait before abort, in millisecond.\r |
92870c98 | 1266 | \r |
1267 | @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r | |
1268 | @return EFI_TIMEOUT The transfer failed due to time out.\r | |
1269 | @return EFI_SUCCESS The transfer finished OK.\r | |
1270 | \r | |
1271 | **/\r | |
1272 | EFI_STATUS\r | |
1273 | XhcExecTransfer (\r | |
a9292c13 | 1274 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1275 | IN BOOLEAN CmdTransfer,\r |
1276 | IN URB *Urb,\r | |
a9292c13 | 1277 | IN UINTN Timeout\r |
92870c98 | 1278 | )\r |
1279 | {\r | |
1280 | EFI_STATUS Status;\r | |
1281 | UINTN Index;\r | |
26cd2d6d | 1282 | UINT64 Loop;\r |
92870c98 | 1283 | UINT8 SlotId;\r |
1284 | UINT8 Dci;\r | |
a40a5c08 | 1285 | BOOLEAN Finished;\r |
92870c98 | 1286 | \r |
1287 | if (CmdTransfer) {\r | |
1288 | SlotId = 0;\r | |
1289 | Dci = 0;\r | |
1290 | } else {\r | |
6b4483cd | 1291 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r |
1292 | if (SlotId == 0) {\r | |
1293 | return EFI_DEVICE_ERROR;\r | |
1294 | }\r | |
1295 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r | |
1296 | ASSERT (Dci < 32);\r | |
92870c98 | 1297 | }\r |
1298 | \r | |
1299 | Status = EFI_SUCCESS;\r | |
ca243131 | 1300 | Loop = Timeout * XHC_1_MILLISECOND;\r |
a9292c13 | 1301 | if (Timeout == 0) {\r |
92870c98 | 1302 | Loop = 0xFFFFFFFF;\r |
1303 | }\r | |
1304 | \r | |
1305 | XhcRingDoorBell (Xhc, SlotId, Dci);\r | |
1306 | \r | |
1307 | for (Index = 0; Index < Loop; Index++) {\r | |
a40a5c08 FT |
1308 | Finished = XhcCheckUrbResult (Xhc, Urb);\r |
1309 | if (Finished) {\r | |
92870c98 | 1310 | break;\r |
1311 | }\r | |
ca243131 | 1312 | gBS->Stall (XHC_1_MICROSECOND);\r |
92870c98 | 1313 | }\r |
1314 | \r | |
a50f7c4c | 1315 | if (Index == Loop) {\r |
1316 | Urb->Result = EFI_USB_ERR_TIMEOUT;\r | |
a40a5c08 FT |
1317 | Status = EFI_TIMEOUT;\r |
1318 | } else if (Urb->Result != EFI_USB_NOERROR) {\r | |
1319 | Status = EFI_DEVICE_ERROR;\r | |
a50f7c4c | 1320 | }\r |
1321 | \r | |
92870c98 | 1322 | return Status;\r |
1323 | }\r | |
1324 | \r | |
1325 | /**\r | |
1326 | Delete a single asynchronous interrupt transfer for\r | |
1327 | the device and endpoint.\r | |
1328 | \r | |
a9292c13 | 1329 | @param Xhc The XHCI Instance.\r |
6b4483cd | 1330 | @param BusAddr The logical device address assigned by UsbBus driver.\r |
92870c98 | 1331 | @param EpNum The endpoint of the target.\r |
1332 | \r | |
1333 | @retval EFI_SUCCESS An asynchronous transfer is removed.\r | |
1334 | @retval EFI_NOT_FOUND No transfer for the device is found.\r | |
1335 | \r | |
1336 | **/\r | |
1337 | EFI_STATUS\r | |
1338 | XhciDelAsyncIntTransfer (\r | |
a9292c13 | 1339 | IN USB_XHCI_INSTANCE *Xhc,\r |
6b4483cd | 1340 | IN UINT8 BusAddr,\r |
92870c98 | 1341 | IN UINT8 EpNum\r |
1342 | )\r | |
1343 | {\r | |
1344 | LIST_ENTRY *Entry;\r | |
1345 | LIST_ENTRY *Next;\r | |
1346 | URB *Urb;\r | |
1347 | EFI_USB_DATA_DIRECTION Direction;\r | |
b33b1055 | 1348 | EFI_STATUS Status;\r |
92870c98 | 1349 | \r |
1350 | Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r | |
1351 | EpNum &= 0x0F;\r | |
1352 | \r | |
6b4483cd | 1353 | Urb = NULL;\r |
92870c98 | 1354 | \r |
1355 | EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r | |
1356 | Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r | |
6b4483cd | 1357 | if ((Urb->Ep.BusAddr == BusAddr) &&\r |
92870c98 | 1358 | (Urb->Ep.EpAddr == EpNum) &&\r |
1359 | (Urb->Ep.Direction == Direction)) {\r | |
b33b1055 RN |
1360 | //\r |
1361 | // Device doesn't finish the IntTransfer until real data comes\r | |
1362 | // So the TRB should be removed as well.\r | |
1363 | //\r | |
1364 | Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);\r | |
1365 | if (EFI_ERROR (Status)) {\r | |
1366 | DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));\r | |
1367 | }\r | |
1368 | \r | |
92870c98 | 1369 | RemoveEntryList (&Urb->UrbList);\r |
1370 | FreePool (Urb->Data);\r | |
1847ed0b | 1371 | XhcFreeUrb (Xhc, Urb);\r |
92870c98 | 1372 | return EFI_SUCCESS;\r |
1373 | }\r | |
1374 | }\r | |
1375 | \r | |
1376 | return EFI_NOT_FOUND;\r | |
1377 | }\r | |
1378 | \r | |
1379 | /**\r | |
1380 | Remove all the asynchronous interrutp transfers.\r | |
1381 | \r | |
a9292c13 | 1382 | @param Xhc The XHCI Instance.\r |
92870c98 | 1383 | \r |
1384 | **/\r | |
1385 | VOID\r | |
1386 | XhciDelAllAsyncIntTransfers (\r | |
a9292c13 | 1387 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 1388 | )\r |
1389 | {\r | |
1390 | LIST_ENTRY *Entry;\r | |
1391 | LIST_ENTRY *Next;\r | |
1392 | URB *Urb;\r | |
b33b1055 | 1393 | EFI_STATUS Status;\r |
92870c98 | 1394 | \r |
1395 | EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r | |
1396 | Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r | |
b33b1055 | 1397 | \r |
b0b626ea RN |
1398 | //\r |
1399 | // Device doesn't finish the IntTransfer until real data comes\r | |
1400 | // So the TRB should be removed as well.\r | |
1401 | //\r | |
b33b1055 RN |
1402 | Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);\r |
1403 | if (EFI_ERROR (Status)) {\r | |
1404 | DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));\r | |
1405 | }\r | |
1406 | \r | |
92870c98 | 1407 | RemoveEntryList (&Urb->UrbList);\r |
1408 | FreePool (Urb->Data);\r | |
1847ed0b | 1409 | XhcFreeUrb (Xhc, Urb);\r |
92870c98 | 1410 | }\r |
1411 | }\r | |
1412 | \r | |
1413 | /**\r | |
1414 | Update the queue head for next round of asynchronous transfer\r | |
1415 | \r | |
a9292c13 | 1416 | @param Xhc The XHCI Instance.\r |
92870c98 | 1417 | @param Urb The URB to update\r |
1418 | \r | |
1419 | **/\r | |
1420 | VOID\r | |
1421 | XhcUpdateAsyncRequest (\r | |
a9292c13 | 1422 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1423 | IN URB *Urb\r |
1424 | )\r | |
1425 | {\r | |
1426 | EFI_STATUS Status;\r | |
1427 | \r | |
1428 | if (Urb->Result == EFI_USB_NOERROR) {\r | |
1429 | Status = XhcCreateTransferTrb (Xhc, Urb);\r | |
6b4483cd | 1430 | if (EFI_ERROR (Status)) {\r |
1431 | return;\r | |
1432 | }\r | |
92870c98 | 1433 | Status = RingIntTransferDoorBell (Xhc, Urb);\r |
6b4483cd | 1434 | if (EFI_ERROR (Status)) {\r |
1435 | return;\r | |
1436 | }\r | |
92870c98 | 1437 | }\r |
1438 | }\r | |
1439 | \r | |
1847ed0b EL |
1440 | /**\r |
1441 | Flush data from PCI controller specific address to mapped system\r | |
1442 | memory address.\r | |
1443 | \r | |
1444 | @param Xhc The XHCI device.\r | |
1445 | @param Urb The URB to unmap.\r | |
1446 | \r | |
1447 | @retval EFI_SUCCESS Success to flush data to mapped system memory.\r | |
1448 | @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.\r | |
1449 | \r | |
1450 | **/\r | |
1451 | EFI_STATUS\r | |
1452 | XhcFlushAsyncIntMap (\r | |
1453 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1454 | IN URB *Urb\r | |
1455 | )\r | |
1456 | {\r | |
1457 | EFI_STATUS Status;\r | |
1458 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
1459 | EFI_PCI_IO_PROTOCOL_OPERATION MapOp;\r | |
1460 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
1461 | UINTN Len;\r | |
1462 | VOID *Map;\r | |
1463 | \r | |
1464 | PciIo = Xhc->PciIo;\r | |
1465 | Len = Urb->DataLen;\r | |
1466 | \r | |
1467 | if (Urb->Ep.Direction == EfiUsbDataIn) {\r | |
1468 | MapOp = EfiPciIoOperationBusMasterWrite;\r | |
1469 | } else {\r | |
1470 | MapOp = EfiPciIoOperationBusMasterRead;\r | |
1471 | }\r | |
1472 | \r | |
1473 | if (Urb->DataMap != NULL) {\r | |
1474 | Status = PciIo->Unmap (PciIo, Urb->DataMap);\r | |
1475 | if (EFI_ERROR (Status)) {\r | |
1476 | goto ON_ERROR;\r | |
1477 | }\r | |
1478 | }\r | |
1479 | \r | |
1480 | Urb->DataMap = NULL;\r | |
1481 | \r | |
1482 | Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);\r | |
1483 | if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {\r | |
1484 | goto ON_ERROR;\r | |
1485 | }\r | |
1486 | \r | |
1487 | Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);\r | |
1488 | Urb->DataMap = Map;\r | |
1489 | return EFI_SUCCESS;\r | |
1490 | \r | |
1491 | ON_ERROR:\r | |
1492 | return EFI_DEVICE_ERROR;\r | |
1493 | }\r | |
92870c98 | 1494 | \r |
1495 | /**\r | |
1496 | Interrupt transfer periodic check handler.\r | |
1497 | \r | |
1498 | @param Event Interrupt event.\r | |
a9292c13 | 1499 | @param Context Pointer to USB_XHCI_INSTANCE.\r |
92870c98 | 1500 | \r |
1501 | **/\r | |
1502 | VOID\r | |
1503 | EFIAPI\r | |
1504 | XhcMonitorAsyncRequests (\r | |
1505 | IN EFI_EVENT Event,\r | |
1506 | IN VOID *Context\r | |
1507 | )\r | |
1508 | {\r | |
a9292c13 | 1509 | USB_XHCI_INSTANCE *Xhc;\r |
92870c98 | 1510 | LIST_ENTRY *Entry;\r |
1511 | LIST_ENTRY *Next;\r | |
1512 | UINT8 *ProcBuf;\r | |
1513 | URB *Urb;\r | |
1514 | UINT8 SlotId;\r | |
1847ed0b | 1515 | EFI_STATUS Status;\r |
92870c98 | 1516 | EFI_TPL OldTpl;\r |
1517 | \r | |
1518 | OldTpl = gBS->RaiseTPL (XHC_TPL);\r | |
1519 | \r | |
a9292c13 | 1520 | Xhc = (USB_XHCI_INSTANCE*) Context;\r |
92870c98 | 1521 | \r |
1522 | EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r | |
1523 | Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r | |
1524 | \r | |
1525 | //\r | |
1526 | // Make sure that the device is available before every check.\r | |
1527 | //\r | |
6b4483cd | 1528 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r |
92870c98 | 1529 | if (SlotId == 0) {\r |
1530 | continue;\r | |
1531 | }\r | |
1532 | \r | |
1533 | //\r | |
1534 | // Check the result of URB execution. If it is still\r | |
1535 | // active, check the next one.\r | |
1536 | //\r | |
b6cb9c39 | 1537 | XhcCheckUrbResult (Xhc, Urb);\r |
92870c98 | 1538 | \r |
a50f7c4c | 1539 | if (!Urb->Finished) {\r |
92870c98 | 1540 | continue;\r |
1541 | }\r | |
1542 | \r | |
1847ed0b EL |
1543 | //\r |
1544 | // Flush any PCI posted write transactions from a PCI host\r | |
1545 | // bridge to system memory.\r | |
1546 | //\r | |
1547 | Status = XhcFlushAsyncIntMap (Xhc, Urb);\r | |
1548 | if (EFI_ERROR (Status)) {\r | |
1549 | DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));\r | |
1550 | }\r | |
1551 | \r | |
92870c98 | 1552 | //\r |
1553 | // Allocate a buffer then copy the transferred data for user.\r | |
1554 | // If failed to allocate the buffer, update the URB for next\r | |
1555 | // round of transfer. Ignore the data of this round.\r | |
1556 | //\r | |
1557 | ProcBuf = NULL;\r | |
1558 | if (Urb->Result == EFI_USB_NOERROR) {\r | |
1559 | ASSERT (Urb->Completed <= Urb->DataLen);\r | |
1560 | \r | |
a9292c13 | 1561 | ProcBuf = AllocateZeroPool (Urb->Completed);\r |
92870c98 | 1562 | \r |
1563 | if (ProcBuf == NULL) {\r | |
1564 | XhcUpdateAsyncRequest (Xhc, Urb);\r | |
1565 | continue;\r | |
1566 | }\r | |
1567 | \r | |
1568 | CopyMem (ProcBuf, Urb->Data, Urb->Completed);\r | |
1569 | }\r | |
1570 | \r | |
92870c98 | 1571 | //\r |
1572 | // Leave error recovery to its related device driver. A\r | |
1573 | // common case of the error recovery is to re-submit the\r | |
1574 | // interrupt transfer which is linked to the head of the\r | |
1575 | // list. This function scans from head to tail. So the\r | |
1576 | // re-submitted interrupt transfer's callback function\r | |
1577 | // will not be called again in this round. Don't touch this\r | |
1578 | // URB after the callback, it may have been removed by the\r | |
1579 | // callback.\r | |
1580 | //\r | |
1581 | if (Urb->Callback != NULL) {\r | |
1582 | //\r | |
1583 | // Restore the old TPL, USB bus maybe connect device in\r | |
1584 | // his callback. Some drivers may has a lower TPL restriction.\r | |
1585 | //\r | |
1586 | gBS->RestoreTPL (OldTpl);\r | |
1587 | (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r | |
1588 | OldTpl = gBS->RaiseTPL (XHC_TPL);\r | |
1589 | }\r | |
1590 | \r | |
1591 | if (ProcBuf != NULL) {\r | |
1592 | gBS->FreePool (ProcBuf);\r | |
1593 | }\r | |
a50f7c4c | 1594 | \r |
1595 | XhcUpdateAsyncRequest (Xhc, Urb);\r | |
92870c98 | 1596 | }\r |
1597 | gBS->RestoreTPL (OldTpl);\r | |
1598 | }\r | |
1599 | \r | |
1600 | /**\r | |
1601 | Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r | |
1602 | \r | |
a9292c13 | 1603 | @param Xhc The XHCI Instance.\r |
92870c98 | 1604 | @param ParentRouteChart The route string pointed to the parent device if it exists.\r |
1605 | @param Port The port to be polled.\r | |
1606 | @param PortState The port state.\r | |
1607 | \r | |
1608 | @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r | |
1609 | @retval Others Should not appear.\r | |
1610 | \r | |
1611 | **/\r | |
1612 | EFI_STATUS\r | |
1613 | EFIAPI\r | |
1614 | XhcPollPortStatusChange (\r | |
a9292c13 | 1615 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1616 | IN USB_DEV_ROUTE ParentRouteChart,\r |
1617 | IN UINT8 Port,\r | |
1618 | IN EFI_USB_PORT_STATUS *PortState\r | |
1619 | )\r | |
1620 | {\r | |
1621 | EFI_STATUS Status;\r | |
1622 | UINT8 Speed;\r | |
1623 | UINT8 SlotId;\r | |
1624 | USB_DEV_ROUTE RouteChart;\r | |
1625 | \r | |
1626 | Status = EFI_SUCCESS;\r | |
1627 | \r | |
c3f44a77 FT |
1628 | if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {\r |
1629 | return EFI_SUCCESS;\r | |
1630 | }\r | |
1631 | \r | |
92870c98 | 1632 | if (ParentRouteChart.Dword == 0) {\r |
a9292c13 | 1633 | RouteChart.Route.RouteString = 0;\r |
1634 | RouteChart.Route.RootPortNum = Port + 1;\r | |
1635 | RouteChart.Route.TierNum = 1;\r | |
92870c98 | 1636 | } else {\r |
1637 | if(Port < 14) {\r | |
a9292c13 | 1638 | RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));\r |
92870c98 | 1639 | } else {\r |
a9292c13 | 1640 | RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));\r |
92870c98 | 1641 | }\r |
a9292c13 | 1642 | RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;\r |
1643 | RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;\r | |
92870c98 | 1644 | }\r |
1645 | \r | |
c3f44a77 FT |
1646 | SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r |
1647 | if (SlotId != 0) {\r | |
1648 | if (Xhc->HcCParams.Data.Csz == 0) {\r | |
1649 | Status = XhcDisableSlotCmd (Xhc, SlotId);\r | |
1650 | } else {\r | |
1651 | Status = XhcDisableSlotCmd64 (Xhc, SlotId);\r | |
1652 | }\r | |
1653 | }\r | |
1654 | \r | |
92870c98 | 1655 | if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&\r |
1656 | ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {\r | |
1657 | //\r | |
1658 | // Has a device attached, Identify device speed after port is enabled.\r | |
1659 | //\r | |
1660 | Speed = EFI_USB_SPEED_FULL;\r | |
1661 | if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {\r | |
1662 | Speed = EFI_USB_SPEED_LOW;\r | |
1663 | } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {\r | |
1664 | Speed = EFI_USB_SPEED_HIGH;\r | |
1665 | } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {\r | |
1666 | Speed = EFI_USB_SPEED_SUPER;\r | |
1667 | }\r | |
1668 | //\r | |
1669 | // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.\r | |
1670 | //\r | |
a9292c13 | 1671 | SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r |
c3f44a77 | 1672 | if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {\r |
6b4483cd | 1673 | if (Xhc->HcCParams.Data.Csz == 0) {\r |
1674 | Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r | |
1675 | } else {\r | |
1676 | Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r | |
1677 | }\r | |
92870c98 | 1678 | }\r |
d1102dba | 1679 | }\r |
c3f44a77 | 1680 | \r |
92870c98 | 1681 | return Status;\r |
1682 | }\r | |
1683 | \r | |
1684 | \r | |
1685 | /**\r | |
1686 | Calculate the device context index by endpoint address and direction.\r | |
1687 | \r | |
1688 | @param EpAddr The target endpoint number.\r | |
1689 | @param Direction The direction of the target endpoint.\r | |
1690 | \r | |
1691 | @return The device context index of endpoint.\r | |
1692 | \r | |
1693 | **/\r | |
1694 | UINT8\r | |
1695 | XhcEndpointToDci (\r | |
1696 | IN UINT8 EpAddr,\r | |
1697 | IN UINT8 Direction\r | |
1698 | )\r | |
1699 | {\r | |
1700 | UINT8 Index;\r | |
1701 | \r | |
1702 | if (EpAddr == 0) {\r | |
1703 | return 1;\r | |
1704 | } else {\r | |
ce9b5900 | 1705 | Index = (UINT8) (2 * EpAddr);\r |
92870c98 | 1706 | if (Direction == EfiUsbDataIn) {\r |
1707 | Index += 1;\r | |
1708 | }\r | |
1709 | return Index;\r | |
1710 | }\r | |
1711 | }\r | |
1712 | \r | |
92870c98 | 1713 | /**\r |
1714 | Find out the actual device address according to the requested device address from UsbBus.\r | |
1715 | \r | |
a9292c13 | 1716 | @param Xhc The XHCI Instance.\r |
1717 | @param BusDevAddr The requested device address by UsbBus upper driver.\r | |
92870c98 | 1718 | \r |
1719 | @return The actual device address assigned to the device.\r | |
1720 | \r | |
1721 | **/\r | |
1722 | UINT8\r | |
1723 | EFIAPI\r | |
1724 | XhcBusDevAddrToSlotId (\r | |
a9292c13 | 1725 | IN USB_XHCI_INSTANCE *Xhc,\r |
1726 | IN UINT8 BusDevAddr\r | |
92870c98 | 1727 | )\r |
1728 | {\r | |
1729 | UINT8 Index;\r | |
1730 | \r | |
1731 | for (Index = 0; Index < 255; Index++) {\r | |
a9292c13 | 1732 | if (Xhc->UsbDevContext[Index + 1].Enabled &&\r |
1733 | (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r | |
1734 | (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {\r | |
92870c98 | 1735 | break;\r |
1736 | }\r | |
1737 | }\r | |
1738 | \r | |
1739 | if (Index == 255) {\r | |
1740 | return 0;\r | |
1741 | }\r | |
1742 | \r | |
a9292c13 | 1743 | return Xhc->UsbDevContext[Index + 1].SlotId;\r |
92870c98 | 1744 | }\r |
1745 | \r | |
1746 | /**\r | |
1747 | Find out the slot id according to the device's route string.\r | |
1748 | \r | |
a9292c13 | 1749 | @param Xhc The XHCI Instance.\r |
1750 | @param RouteString The route string described the device location.\r | |
92870c98 | 1751 | \r |
1752 | @return The slot id used by the device.\r | |
1753 | \r | |
1754 | **/\r | |
1755 | UINT8\r | |
1756 | EFIAPI\r | |
1757 | XhcRouteStringToSlotId (\r | |
a9292c13 | 1758 | IN USB_XHCI_INSTANCE *Xhc,\r |
1759 | IN USB_DEV_ROUTE RouteString\r | |
92870c98 | 1760 | )\r |
1761 | {\r | |
1762 | UINT8 Index;\r | |
1763 | \r | |
1764 | for (Index = 0; Index < 255; Index++) {\r | |
a9292c13 | 1765 | if (Xhc->UsbDevContext[Index + 1].Enabled &&\r |
1766 | (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r | |
1767 | (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {\r | |
92870c98 | 1768 | break;\r |
1769 | }\r | |
1770 | }\r | |
1771 | \r | |
1772 | if (Index == 255) {\r | |
1773 | return 0;\r | |
1774 | }\r | |
1775 | \r | |
a9292c13 | 1776 | return Xhc->UsbDevContext[Index + 1].SlotId;\r |
92870c98 | 1777 | }\r |
1778 | \r | |
1779 | /**\r | |
1780 | Synchronize the specified event ring to update the enqueue and dequeue pointer.\r | |
1781 | \r | |
a9292c13 | 1782 | @param Xhc The XHCI Instance.\r |
92870c98 | 1783 | @param EvtRing The event ring to sync.\r |
1784 | \r | |
1785 | @retval EFI_SUCCESS The event ring is synchronized successfully.\r | |
1786 | \r | |
1787 | **/\r | |
1788 | EFI_STATUS\r | |
1789 | EFIAPI\r | |
1790 | XhcSyncEventRing (\r | |
a9292c13 | 1791 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1792 | IN EVENT_RING *EvtRing\r |
1793 | )\r | |
1794 | {\r | |
1795 | UINTN Index;\r | |
a9292c13 | 1796 | TRB_TEMPLATE *EvtTrb1;\r |
92870c98 | 1797 | \r |
1798 | ASSERT (EvtRing != NULL);\r | |
1799 | \r | |
1800 | //\r | |
1801 | // Calculate the EventRingEnqueue and EventRingCCS.\r | |
1802 | // Note: only support single Segment\r | |
1803 | //\r | |
a50f7c4c | 1804 | EvtTrb1 = EvtRing->EventRingDequeue;\r |
92870c98 | 1805 | \r |
1806 | for (Index = 0; Index < EvtRing->TrbNumber; Index++) {\r | |
a50f7c4c | 1807 | if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {\r |
92870c98 | 1808 | break;\r |
1809 | }\r | |
a50f7c4c | 1810 | \r |
92870c98 | 1811 | EvtTrb1++;\r |
a50f7c4c | 1812 | \r |
1813 | if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r | |
1814 | EvtTrb1 = EvtRing->EventRingSeg0;\r | |
1815 | EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;\r | |
1816 | }\r | |
92870c98 | 1817 | }\r |
1818 | \r | |
1819 | if (Index < EvtRing->TrbNumber) {\r | |
1820 | EvtRing->EventRingEnqueue = EvtTrb1;\r | |
92870c98 | 1821 | } else {\r |
a50f7c4c | 1822 | ASSERT (FALSE);\r |
92870c98 | 1823 | }\r |
1824 | \r | |
1825 | return EFI_SUCCESS;\r | |
1826 | }\r | |
1827 | \r | |
1828 | /**\r | |
1829 | Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r | |
1830 | \r | |
a9292c13 | 1831 | @param Xhc The XHCI Instance.\r |
92870c98 | 1832 | @param TrsRing The transfer ring to sync.\r |
1833 | \r | |
1834 | @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r | |
1835 | \r | |
1836 | **/\r | |
1837 | EFI_STATUS\r | |
1838 | EFIAPI\r | |
1839 | XhcSyncTrsRing (\r | |
a9292c13 | 1840 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1841 | IN TRANSFER_RING *TrsRing\r |
1842 | )\r | |
1843 | {\r | |
1844 | UINTN Index;\r | |
a9292c13 | 1845 | TRB_TEMPLATE *TrsTrb;\r |
92870c98 | 1846 | \r |
1847 | ASSERT (TrsRing != NULL);\r | |
1848 | //\r | |
1849 | // Calculate the latest RingEnqueue and RingPCS\r | |
1850 | //\r | |
1851 | TrsTrb = TrsRing->RingEnqueue;\r | |
1852 | ASSERT (TrsTrb != NULL);\r | |
1853 | \r | |
1854 | for (Index = 0; Index < TrsRing->TrbNumber; Index++) {\r | |
1855 | if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {\r | |
1856 | break;\r | |
1857 | }\r | |
1858 | TrsTrb++;\r | |
1859 | if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {\r | |
a9292c13 | 1860 | ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);\r |
92870c98 | 1861 | //\r |
1862 | // set cycle bit in Link TRB as normal\r | |
1863 | //\r | |
a9292c13 | 1864 | ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;\r |
92870c98 | 1865 | //\r |
1866 | // Toggle PCS maintained by software\r | |
1867 | //\r | |
1868 | TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;\r | |
1847ed0b | 1869 | TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address\r |
92870c98 | 1870 | }\r |
1871 | }\r | |
1872 | \r | |
1873 | ASSERT (Index != TrsRing->TrbNumber);\r | |
1874 | \r | |
1875 | if (TrsTrb != TrsRing->RingEnqueue) {\r | |
1876 | TrsRing->RingEnqueue = TrsTrb;\r | |
1877 | }\r | |
1878 | \r | |
1879 | //\r | |
1880 | // Clear the Trb context for enqueue, but reserve the PCS bit\r | |
1881 | //\r | |
a9292c13 | 1882 | TrsTrb->Parameter1 = 0;\r |
1883 | TrsTrb->Parameter2 = 0;\r | |
1884 | TrsTrb->Status = 0;\r | |
1885 | TrsTrb->RsvdZ1 = 0;\r | |
1886 | TrsTrb->Type = 0;\r | |
1887 | TrsTrb->Control = 0;\r | |
92870c98 | 1888 | \r |
1889 | return EFI_SUCCESS;\r | |
1890 | }\r | |
1891 | \r | |
1892 | /**\r | |
1893 | Check if there is a new generated event.\r | |
1894 | \r | |
a9292c13 | 1895 | @param Xhc The XHCI Instance.\r |
92870c98 | 1896 | @param EvtRing The event ring to check.\r |
1897 | @param NewEvtTrb The new event TRB found.\r | |
1898 | \r | |
1899 | @retval EFI_SUCCESS Found a new event TRB at the event ring.\r | |
1900 | @retval EFI_NOT_READY The event ring has no new event.\r | |
1901 | \r | |
1902 | **/\r | |
1903 | EFI_STATUS\r | |
1904 | EFIAPI\r | |
1905 | XhcCheckNewEvent (\r | |
a9292c13 | 1906 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1907 | IN EVENT_RING *EvtRing,\r |
a9292c13 | 1908 | OUT TRB_TEMPLATE **NewEvtTrb\r |
92870c98 | 1909 | )\r |
1910 | {\r | |
92870c98 | 1911 | ASSERT (EvtRing != NULL);\r |
1912 | \r | |
92870c98 | 1913 | *NewEvtTrb = EvtRing->EventRingDequeue;\r |
1914 | \r | |
1915 | if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {\r | |
1916 | return EFI_NOT_READY;\r | |
1917 | }\r | |
1918 | \r | |
92870c98 | 1919 | EvtRing->EventRingDequeue++;\r |
1920 | //\r | |
1921 | // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.\r | |
1922 | //\r | |
a50f7c4c | 1923 | if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r |
92870c98 | 1924 | EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;\r |
1925 | }\r | |
1926 | \r | |
b6cb9c39 | 1927 | return EFI_SUCCESS;\r |
92870c98 | 1928 | }\r |
1929 | \r | |
1930 | /**\r | |
1931 | Ring the door bell to notify XHCI there is a transaction to be executed.\r | |
1932 | \r | |
a9292c13 | 1933 | @param Xhc The XHCI Instance.\r |
92870c98 | 1934 | @param SlotId The slot id of the target device.\r |
1935 | @param Dci The device context index of the target slot or endpoint.\r | |
1936 | \r | |
1937 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
1938 | \r | |
1939 | **/\r | |
1940 | EFI_STATUS\r | |
1941 | EFIAPI\r | |
1942 | XhcRingDoorBell (\r | |
a9292c13 | 1943 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1944 | IN UINT8 SlotId,\r |
1945 | IN UINT8 Dci\r | |
1946 | )\r | |
1947 | {\r | |
1948 | if (SlotId == 0) {\r | |
1949 | XhcWriteDoorBellReg (Xhc, 0, 0);\r | |
1950 | } else {\r | |
1951 | XhcWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);\r | |
1952 | }\r | |
1953 | \r | |
1954 | return EFI_SUCCESS;\r | |
1955 | }\r | |
1956 | \r | |
1957 | /**\r | |
1958 | Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r | |
1959 | \r | |
a9292c13 | 1960 | @param Xhc The XHCI Instance.\r |
92870c98 | 1961 | @param Urb The URB to be rung.\r |
1962 | \r | |
1963 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
1964 | \r | |
1965 | **/\r | |
1966 | EFI_STATUS\r | |
1967 | RingIntTransferDoorBell (\r | |
a9292c13 | 1968 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1969 | IN URB *Urb\r |
1970 | )\r | |
1971 | {\r | |
1972 | UINT8 SlotId;\r | |
1973 | UINT8 Dci;\r | |
1974 | \r | |
6b4483cd | 1975 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r |
1976 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r | |
92870c98 | 1977 | XhcRingDoorBell (Xhc, SlotId, Dci);\r |
1978 | return EFI_SUCCESS;\r | |
1979 | }\r | |
1980 | \r | |
1981 | /**\r | |
1982 | Assign and initialize the device slot for a new device.\r | |
1983 | \r | |
a9292c13 | 1984 | @param Xhc The XHCI Instance.\r |
92870c98 | 1985 | @param ParentRouteChart The route string pointed to the parent device.\r |
1986 | @param ParentPort The port at which the device is located.\r | |
1987 | @param RouteChart The route string pointed to the device.\r | |
1988 | @param DeviceSpeed The device speed.\r | |
1989 | \r | |
1990 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r | |
1991 | \r | |
1992 | **/\r | |
1993 | EFI_STATUS\r | |
1994 | EFIAPI\r | |
1995 | XhcInitializeDeviceSlot (\r | |
a9292c13 | 1996 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1997 | IN USB_DEV_ROUTE ParentRouteChart,\r |
1998 | IN UINT16 ParentPort,\r | |
1999 | IN USB_DEV_ROUTE RouteChart,\r | |
2000 | IN UINT8 DeviceSpeed\r | |
2001 | )\r | |
2002 | {\r | |
a9292c13 | 2003 | EFI_STATUS Status;\r |
2004 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
2005 | INPUT_CONTEXT *InputContext;\r | |
2006 | DEVICE_CONTEXT *OutputContext;\r | |
2007 | TRANSFER_RING *EndpointTransferRing;\r | |
2008 | CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r | |
2009 | UINT8 DeviceAddress;\r | |
2010 | CMD_TRB_ENABLE_SLOT CmdTrb;\r | |
2011 | UINT8 SlotId;\r | |
2012 | UINT8 ParentSlotId;\r | |
2013 | DEVICE_CONTEXT *ParentDeviceContext;\r | |
1847ed0b | 2014 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
a9292c13 | 2015 | \r |
2016 | ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r | |
92870c98 | 2017 | CmdTrb.CycleBit = 1;\r |
2018 | CmdTrb.Type = TRB_TYPE_EN_SLOT;\r | |
2019 | \r | |
2020 | Status = XhcCmdTransfer (\r | |
2021 | Xhc,\r | |
a9292c13 | 2022 | (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r |
92870c98 | 2023 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 2024 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 2025 | );\r |
260fbf53 EL |
2026 | if (EFI_ERROR (Status)) {\r |
2027 | DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));\r | |
2028 | return Status;\r | |
2029 | }\r | |
92870c98 | 2030 | ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r |
2031 | DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r | |
2032 | SlotId = (UINT8)EvtTrb->SlotId;\r | |
2033 | ASSERT (SlotId != 0);\r | |
2034 | \r | |
a9292c13 | 2035 | ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r |
2036 | Xhc->UsbDevContext[SlotId].Enabled = TRUE;\r | |
2037 | Xhc->UsbDevContext[SlotId].SlotId = SlotId;\r | |
2038 | Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;\r | |
2039 | Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;\r | |
92870c98 | 2040 | \r |
2041 | //\r | |
2042 | // 4.3.3 Device Slot Initialization\r | |
2043 | // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r | |
2044 | //\r | |
1847ed0b | 2045 | InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));\r |
92870c98 | 2046 | ASSERT (InputContext != NULL);\r |
2047 | ASSERT (((UINTN) InputContext & 0x3F) == 0);\r | |
a9292c13 | 2048 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r |
92870c98 | 2049 | \r |
a9292c13 | 2050 | Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r |
92870c98 | 2051 | \r |
2052 | //\r | |
2053 | // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r | |
2054 | // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input\r | |
2055 | // Context are affected by the command.\r | |
2056 | //\r | |
2057 | InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);\r | |
2058 | \r | |
2059 | //\r | |
2060 | // 3) Initialize the Input Slot Context data structure\r | |
2061 | //\r | |
a9292c13 | 2062 | InputContext->Slot.RouteString = RouteChart.Route.RouteString;\r |
92870c98 | 2063 | InputContext->Slot.Speed = DeviceSpeed + 1;\r |
2064 | InputContext->Slot.ContextEntries = 1;\r | |
a9292c13 | 2065 | InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;\r |
92870c98 | 2066 | \r |
a9292c13 | 2067 | if (RouteChart.Route.RouteString) {\r |
92870c98 | 2068 | //\r |
2069 | // The device is behind of hub device.\r | |
2070 | //\r | |
a9292c13 | 2071 | ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);\r |
92870c98 | 2072 | ASSERT (ParentSlotId != 0);\r |
2073 | //\r | |
2074 | //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r | |
2075 | //\r | |
a9292c13 | 2076 | ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r |
92870c98 | 2077 | if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r |
2078 | (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r | |
2079 | if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r | |
2080 | //\r | |
2081 | // Full/Low device attached to High speed hub port that isolates the high speed signaling\r | |
2082 | // environment from Full/Low speed signaling environment for a device\r | |
2083 | //\r | |
2084 | InputContext->Slot.TTPortNum = ParentPort;\r | |
2085 | InputContext->Slot.TTHubSlotId = ParentSlotId;\r | |
2086 | }\r | |
2087 | } else {\r | |
2088 | //\r | |
2089 | // Inherit the TT parameters from parent device.\r | |
2090 | //\r | |
2091 | InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;\r | |
2092 | InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;\r | |
2093 | //\r | |
2094 | // If the device is a High speed device then down the speed to be the same as its parent Hub\r | |
2095 | //\r | |
2096 | if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r | |
2097 | InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;\r | |
2098 | }\r | |
2099 | }\r | |
2100 | }\r | |
2101 | \r | |
2102 | //\r | |
2103 | // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r | |
2104 | //\r | |
a9292c13 | 2105 | EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r |
2106 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r | |
2107 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r | |
92870c98 | 2108 | //\r |
2109 | // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r | |
2110 | //\r | |
2111 | InputContext->EP[0].EPType = ED_CONTROL_BIDIR;\r | |
2112 | \r | |
2113 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
2114 | InputContext->EP[0].MaxPacketSize = 512;\r | |
2115 | } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r | |
2116 | InputContext->EP[0].MaxPacketSize = 64;\r | |
2117 | } else {\r | |
2118 | InputContext->EP[0].MaxPacketSize = 8;\r | |
2119 | }\r | |
2120 | //\r | |
2121 | // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r | |
2122 | // 1KB, and Bulk and Isoch endpoints 3KB.\r | |
2123 | //\r | |
2124 | InputContext->EP[0].AverageTRBLength = 8;\r | |
2125 | InputContext->EP[0].MaxBurstSize = 0;\r | |
2126 | InputContext->EP[0].Interval = 0;\r | |
2127 | InputContext->EP[0].MaxPStreams = 0;\r | |
2128 | InputContext->EP[0].Mult = 0;\r | |
2129 | InputContext->EP[0].CErr = 3;\r | |
2130 | \r | |
2131 | //\r | |
2132 | // Init the DCS(dequeue cycle state) as the transfer ring's CCS\r | |
2133 | //\r | |
1847ed0b EL |
2134 | PhyAddr = UsbHcGetPciAddrForHostAddr (\r |
2135 | Xhc->MemPool,\r | |
2136 | ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r | |
2137 | sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r | |
2138 | );\r | |
2139 | InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;\r | |
2140 | InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
92870c98 | 2141 | \r |
2142 | //\r | |
2143 | // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r | |
2144 | //\r | |
1847ed0b | 2145 | OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));\r |
a9292c13 | 2146 | ASSERT (OutputContext != NULL);\r |
2147 | ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r | |
2148 | ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));\r | |
92870c98 | 2149 | \r |
a9292c13 | 2150 | Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r |
92870c98 | 2151 | //\r |
2152 | // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r | |
2153 | // a pointer to the Output Device Context data structure (6.2.1).\r | |
2154 | //\r | |
1847ed0b EL |
2155 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));\r |
2156 | //\r | |
2157 | // Fill DCBAA with PCI device address\r | |
2158 | //\r | |
2159 | Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;\r | |
92870c98 | 2160 | \r |
2161 | //\r | |
2162 | // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r | |
2163 | // Context data structure described above.\r | |
2164 | //\r | |
26b85012 FT |
2165 | // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request\r |
2166 | // to device.\r | |
2167 | //\r | |
2168 | gBS->Stall (XHC_RESET_RECOVERY_DELAY);\r | |
92870c98 | 2169 | ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r |
1847ed0b EL |
2170 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r |
2171 | CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
2172 | CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
92870c98 | 2173 | CmdTrbAddr.CycleBit = 1;\r |
2174 | CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r | |
a9292c13 | 2175 | CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r |
92870c98 | 2176 | Status = XhcCmdTransfer (\r |
2177 | Xhc,\r | |
a9292c13 | 2178 | (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r |
92870c98 | 2179 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 2180 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 2181 | );\r |
260fbf53 EL |
2182 | if (!EFI_ERROR (Status)) {\r |
2183 | DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;\r | |
2184 | DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));\r | |
2185 | Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r | |
2186 | }\r | |
92870c98 | 2187 | \r |
2188 | return Status;\r | |
2189 | }\r | |
2190 | \r | |
2191 | /**\r | |
6b4483cd | 2192 | Assign and initialize the device slot for a new device.\r |
92870c98 | 2193 | \r |
6b4483cd | 2194 | @param Xhc The XHCI Instance.\r |
2195 | @param ParentRouteChart The route string pointed to the parent device.\r | |
2196 | @param ParentPort The port at which the device is located.\r | |
2197 | @param RouteChart The route string pointed to the device.\r | |
2198 | @param DeviceSpeed The device speed.\r | |
92870c98 | 2199 | \r |
6b4483cd | 2200 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r |
92870c98 | 2201 | \r |
2202 | **/\r | |
2203 | EFI_STATUS\r | |
2204 | EFIAPI\r | |
6b4483cd | 2205 | XhcInitializeDeviceSlot64 (\r |
2206 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2207 | IN USB_DEV_ROUTE ParentRouteChart,\r | |
2208 | IN UINT16 ParentPort,\r | |
2209 | IN USB_DEV_ROUTE RouteChart,\r | |
2210 | IN UINT8 DeviceSpeed\r | |
92870c98 | 2211 | )\r |
2212 | {\r | |
6b4483cd | 2213 | EFI_STATUS Status;\r |
2214 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
2215 | INPUT_CONTEXT_64 *InputContext;\r | |
2216 | DEVICE_CONTEXT_64 *OutputContext;\r | |
2217 | TRANSFER_RING *EndpointTransferRing;\r | |
2218 | CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r | |
2219 | UINT8 DeviceAddress;\r | |
2220 | CMD_TRB_ENABLE_SLOT CmdTrb;\r | |
2221 | UINT8 SlotId;\r | |
2222 | UINT8 ParentSlotId;\r | |
2223 | DEVICE_CONTEXT_64 *ParentDeviceContext;\r | |
1847ed0b | 2224 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
92870c98 | 2225 | \r |
6b4483cd | 2226 | ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r |
2227 | CmdTrb.CycleBit = 1;\r | |
2228 | CmdTrb.Type = TRB_TYPE_EN_SLOT;\r | |
92870c98 | 2229 | \r |
6b4483cd | 2230 | Status = XhcCmdTransfer (\r |
2231 | Xhc,\r | |
2232 | (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r | |
2233 | XHC_GENERIC_TIMEOUT,\r | |
2234 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2235 | );\r | |
260fbf53 EL |
2236 | if (EFI_ERROR (Status)) {\r |
2237 | DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));\r | |
2238 | return Status;\r | |
2239 | }\r | |
6b4483cd | 2240 | ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r |
2241 | DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r | |
2242 | SlotId = (UINT8)EvtTrb->SlotId;\r | |
2243 | ASSERT (SlotId != 0);\r | |
92870c98 | 2244 | \r |
6b4483cd | 2245 | ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r |
2246 | Xhc->UsbDevContext[SlotId].Enabled = TRUE;\r | |
2247 | Xhc->UsbDevContext[SlotId].SlotId = SlotId;\r | |
2248 | Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;\r | |
2249 | Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;\r | |
92870c98 | 2250 | \r |
2251 | //\r | |
6b4483cd | 2252 | // 4.3.3 Device Slot Initialization\r |
2253 | // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r | |
92870c98 | 2254 | //\r |
1847ed0b | 2255 | InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));\r |
6b4483cd | 2256 | ASSERT (InputContext != NULL);\r |
2257 | ASSERT (((UINTN) InputContext & 0x3F) == 0);\r | |
2258 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r | |
2259 | \r | |
2260 | Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r | |
92870c98 | 2261 | \r |
92870c98 | 2262 | //\r |
6b4483cd | 2263 | // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r |
2264 | // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input\r | |
2265 | // Context are affected by the command.\r | |
92870c98 | 2266 | //\r |
6b4483cd | 2267 | InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);\r |
92870c98 | 2268 | \r |
2269 | //\r | |
6b4483cd | 2270 | // 3) Initialize the Input Slot Context data structure\r |
92870c98 | 2271 | //\r |
6b4483cd | 2272 | InputContext->Slot.RouteString = RouteChart.Route.RouteString;\r |
2273 | InputContext->Slot.Speed = DeviceSpeed + 1;\r | |
2274 | InputContext->Slot.ContextEntries = 1;\r | |
2275 | InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;\r | |
92870c98 | 2276 | \r |
6b4483cd | 2277 | if (RouteChart.Route.RouteString) {\r |
2278 | //\r | |
2279 | // The device is behind of hub device.\r | |
2280 | //\r | |
2281 | ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);\r | |
2282 | ASSERT (ParentSlotId != 0);\r | |
2283 | //\r | |
2284 | //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r | |
2285 | //\r | |
2286 | ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r | |
2287 | if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r | |
2288 | (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r | |
2289 | if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r | |
2290 | //\r | |
2291 | // Full/Low device attached to High speed hub port that isolates the high speed signaling\r | |
2292 | // environment from Full/Low speed signaling environment for a device\r | |
2293 | //\r | |
2294 | InputContext->Slot.TTPortNum = ParentPort;\r | |
2295 | InputContext->Slot.TTHubSlotId = ParentSlotId;\r | |
2296 | }\r | |
2297 | } else {\r | |
2298 | //\r | |
2299 | // Inherit the TT parameters from parent device.\r | |
2300 | //\r | |
2301 | InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;\r | |
2302 | InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;\r | |
2303 | //\r | |
2304 | // If the device is a High speed device then down the speed to be the same as its parent Hub\r | |
2305 | //\r | |
2306 | if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r | |
2307 | InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;\r | |
2308 | }\r | |
92870c98 | 2309 | }\r |
2310 | }\r | |
2311 | \r | |
92870c98 | 2312 | //\r |
6b4483cd | 2313 | // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r |
92870c98 | 2314 | //\r |
6b4483cd | 2315 | EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r |
2316 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r | |
2317 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r | |
2318 | //\r | |
2319 | // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r | |
2320 | //\r | |
2321 | InputContext->EP[0].EPType = ED_CONTROL_BIDIR;\r | |
2322 | \r | |
2323 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
2324 | InputContext->EP[0].MaxPacketSize = 512;\r | |
2325 | } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r | |
2326 | InputContext->EP[0].MaxPacketSize = 64;\r | |
2327 | } else {\r | |
2328 | InputContext->EP[0].MaxPacketSize = 8;\r | |
2329 | }\r | |
2330 | //\r | |
2331 | // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r | |
2332 | // 1KB, and Bulk and Isoch endpoints 3KB.\r | |
2333 | //\r | |
2334 | InputContext->EP[0].AverageTRBLength = 8;\r | |
2335 | InputContext->EP[0].MaxBurstSize = 0;\r | |
2336 | InputContext->EP[0].Interval = 0;\r | |
2337 | InputContext->EP[0].MaxPStreams = 0;\r | |
2338 | InputContext->EP[0].Mult = 0;\r | |
2339 | InputContext->EP[0].CErr = 3;\r | |
2340 | \r | |
2341 | //\r | |
2342 | // Init the DCS(dequeue cycle state) as the transfer ring's CCS\r | |
2343 | //\r | |
1847ed0b EL |
2344 | PhyAddr = UsbHcGetPciAddrForHostAddr (\r |
2345 | Xhc->MemPool,\r | |
2346 | ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,\r | |
2347 | sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r | |
2348 | );\r | |
2349 | InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;\r | |
2350 | InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
6b4483cd | 2351 | \r |
2352 | //\r | |
2353 | // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r | |
2354 | //\r | |
1847ed0b | 2355 | OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));\r |
6b4483cd | 2356 | ASSERT (OutputContext != NULL);\r |
2357 | ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r | |
2358 | ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));\r | |
2359 | \r | |
2360 | Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r | |
2361 | //\r | |
2362 | // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r | |
2363 | // a pointer to the Output Device Context data structure (6.2.1).\r | |
2364 | //\r | |
1847ed0b EL |
2365 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));\r |
2366 | //\r | |
2367 | // Fill DCBAA with PCI device address\r | |
2368 | //\r | |
2369 | Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;\r | |
6b4483cd | 2370 | \r |
2371 | //\r | |
2372 | // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r | |
2373 | // Context data structure described above.\r | |
2374 | //\r | |
26b85012 FT |
2375 | // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request\r |
2376 | // to device.\r | |
2377 | //\r | |
2378 | gBS->Stall (XHC_RESET_RECOVERY_DELAY);\r | |
6b4483cd | 2379 | ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r |
1847ed0b EL |
2380 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r |
2381 | CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
2382 | CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
6b4483cd | 2383 | CmdTrbAddr.CycleBit = 1;\r |
2384 | CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r | |
2385 | CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
2386 | Status = XhcCmdTransfer (\r | |
2387 | Xhc,\r | |
2388 | (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r | |
2389 | XHC_GENERIC_TIMEOUT,\r | |
2390 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2391 | );\r | |
260fbf53 EL |
2392 | if (!EFI_ERROR (Status)) {\r |
2393 | DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;\r | |
2394 | DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));\r | |
2395 | Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r | |
2396 | }\r | |
6b4483cd | 2397 | return Status;\r |
2398 | }\r | |
2399 | \r | |
2400 | \r | |
2401 | /**\r | |
2402 | Disable the specified device slot.\r | |
2403 | \r | |
2404 | @param Xhc The XHCI Instance.\r | |
2405 | @param SlotId The slot id to be disabled.\r | |
2406 | \r | |
2407 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
2408 | \r | |
2409 | **/\r | |
2410 | EFI_STATUS\r | |
2411 | EFIAPI\r | |
2412 | XhcDisableSlotCmd (\r | |
2413 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2414 | IN UINT8 SlotId\r | |
2415 | )\r | |
2416 | {\r | |
2417 | EFI_STATUS Status;\r | |
2418 | TRB_TEMPLATE *EvtTrb;\r | |
2419 | CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;\r | |
2420 | UINT8 Index;\r | |
2421 | VOID *RingSeg;\r | |
2422 | \r | |
2423 | //\r | |
2424 | // Disable the device slots occupied by these devices on its downstream ports.\r | |
2425 | // Entry 0 is reserved.\r | |
2426 | //\r | |
2427 | for (Index = 0; Index < 255; Index++) {\r | |
2428 | if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r | |
2429 | (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r | |
2430 | (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r | |
2431 | continue;\r | |
2432 | }\r | |
2433 | \r | |
2434 | Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r | |
2435 | \r | |
2436 | if (EFI_ERROR (Status)) {\r | |
2437 | DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r | |
2438 | Xhc->UsbDevContext[Index + 1].SlotId = 0;\r | |
2439 | }\r | |
2440 | }\r | |
2441 | \r | |
2442 | //\r | |
2443 | // Construct the disable slot command\r | |
2444 | //\r | |
2445 | DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));\r | |
2446 | \r | |
2447 | ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r | |
2448 | CmdTrbDisSlot.CycleBit = 1;\r | |
2449 | CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r | |
2450 | CmdTrbDisSlot.SlotId = SlotId;\r | |
2451 | Status = XhcCmdTransfer (\r | |
2452 | Xhc,\r | |
2453 | (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r | |
2454 | XHC_GENERIC_TIMEOUT,\r | |
2455 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2456 | );\r | |
260fbf53 EL |
2457 | if (EFI_ERROR (Status)) {\r |
2458 | DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));\r | |
2459 | return Status;\r | |
2460 | }\r | |
6b4483cd | 2461 | //\r |
2462 | // Free the slot's device context entry\r | |
2463 | //\r | |
2464 | Xhc->DCBAA[SlotId] = 0;\r | |
2465 | \r | |
2466 | //\r | |
2467 | // Free the slot related data structure\r | |
2468 | //\r | |
2469 | for (Index = 0; Index < 31; Index++) {\r | |
2470 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r | |
2471 | RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r | |
2472 | if (RingSeg != NULL) {\r | |
1847ed0b | 2473 | UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r |
6b4483cd | 2474 | }\r |
2475 | FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r | |
1847ed0b | 2476 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;\r |
6b4483cd | 2477 | }\r |
2478 | }\r | |
2479 | \r | |
2480 | for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r | |
2481 | if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {\r | |
2482 | FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r | |
2483 | }\r | |
2484 | }\r | |
2485 | \r | |
e1f2dfec SZ |
2486 | if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {\r |
2487 | FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);\r | |
2488 | }\r | |
2489 | \r | |
6b4483cd | 2490 | if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r |
1847ed0b | 2491 | UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));\r |
6b4483cd | 2492 | }\r |
2493 | \r | |
2494 | if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r | |
1847ed0b | 2495 | UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));\r |
6b4483cd | 2496 | }\r |
2497 | //\r | |
2498 | // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r | |
2499 | // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r | |
2500 | // remove urb from XHCI's asynchronous transfer list.\r | |
2501 | //\r | |
2502 | Xhc->UsbDevContext[SlotId].Enabled = FALSE;\r | |
2503 | Xhc->UsbDevContext[SlotId].SlotId = 0;\r | |
2504 | \r | |
2505 | return Status;\r | |
2506 | }\r | |
2507 | \r | |
2508 | /**\r | |
2509 | Disable the specified device slot.\r | |
2510 | \r | |
2511 | @param Xhc The XHCI Instance.\r | |
2512 | @param SlotId The slot id to be disabled.\r | |
2513 | \r | |
2514 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
2515 | \r | |
2516 | **/\r | |
2517 | EFI_STATUS\r | |
2518 | EFIAPI\r | |
2519 | XhcDisableSlotCmd64 (\r | |
2520 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2521 | IN UINT8 SlotId\r | |
2522 | )\r | |
2523 | {\r | |
2524 | EFI_STATUS Status;\r | |
2525 | TRB_TEMPLATE *EvtTrb;\r | |
2526 | CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;\r | |
2527 | UINT8 Index;\r | |
2528 | VOID *RingSeg;\r | |
2529 | \r | |
2530 | //\r | |
2531 | // Disable the device slots occupied by these devices on its downstream ports.\r | |
2532 | // Entry 0 is reserved.\r | |
2533 | //\r | |
2534 | for (Index = 0; Index < 255; Index++) {\r | |
2535 | if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r | |
2536 | (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r | |
2537 | (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r | |
2538 | continue;\r | |
2539 | }\r | |
2540 | \r | |
2541 | Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r | |
2542 | \r | |
2543 | if (EFI_ERROR (Status)) {\r | |
2544 | DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r | |
2545 | Xhc->UsbDevContext[Index + 1].SlotId = 0;\r | |
2546 | }\r | |
2547 | }\r | |
2548 | \r | |
2549 | //\r | |
2550 | // Construct the disable slot command\r | |
2551 | //\r | |
2552 | DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));\r | |
2553 | \r | |
2554 | ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r | |
2555 | CmdTrbDisSlot.CycleBit = 1;\r | |
2556 | CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r | |
2557 | CmdTrbDisSlot.SlotId = SlotId;\r | |
2558 | Status = XhcCmdTransfer (\r | |
2559 | Xhc,\r | |
2560 | (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r | |
2561 | XHC_GENERIC_TIMEOUT,\r | |
2562 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2563 | );\r | |
260fbf53 EL |
2564 | if (EFI_ERROR (Status)) {\r |
2565 | DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));\r | |
2566 | return Status;\r | |
2567 | }\r | |
6b4483cd | 2568 | //\r |
2569 | // Free the slot's device context entry\r | |
2570 | //\r | |
2571 | Xhc->DCBAA[SlotId] = 0;\r | |
2572 | \r | |
2573 | //\r | |
2574 | // Free the slot related data structure\r | |
2575 | //\r | |
2576 | for (Index = 0; Index < 31; Index++) {\r | |
2577 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r | |
2578 | RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r | |
2579 | if (RingSeg != NULL) {\r | |
1847ed0b | 2580 | UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r |
6b4483cd | 2581 | }\r |
2582 | FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r | |
1847ed0b | 2583 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;\r |
6b4483cd | 2584 | }\r |
2585 | }\r | |
2586 | \r | |
2587 | for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r | |
2588 | if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {\r | |
2589 | FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r | |
2590 | }\r | |
2591 | }\r | |
2592 | \r | |
e1f2dfec SZ |
2593 | if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {\r |
2594 | FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);\r | |
2595 | }\r | |
2596 | \r | |
6b4483cd | 2597 | if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r |
1847ed0b | 2598 | UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));\r |
6b4483cd | 2599 | }\r |
2600 | \r | |
2601 | if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r | |
1847ed0b | 2602 | UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));\r |
6b4483cd | 2603 | }\r |
2604 | //\r | |
2605 | // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r | |
2606 | // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r | |
2607 | // remove urb from XHCI's asynchronous transfer list.\r | |
2608 | //\r | |
2609 | Xhc->UsbDevContext[SlotId].Enabled = FALSE;\r | |
2610 | Xhc->UsbDevContext[SlotId].SlotId = 0;\r | |
2611 | \r | |
2612 | return Status;\r | |
2613 | }\r | |
2614 | \r | |
e1f2dfec SZ |
2615 | /**\r |
2616 | Initialize endpoint context in input context.\r | |
2617 | \r | |
2618 | @param Xhc The XHCI Instance.\r | |
2619 | @param SlotId The slot id to be configured.\r | |
2620 | @param DeviceSpeed The device's speed.\r | |
2621 | @param InputContext The pointer to the input context.\r | |
2622 | @param IfDesc The pointer to the usb device interface descriptor.\r | |
2623 | \r | |
2624 | @return The maximum device context index of endpoint.\r | |
2625 | \r | |
2626 | **/\r | |
2627 | UINT8\r | |
2628 | EFIAPI\r | |
2629 | XhcInitializeEndpointContext (\r | |
2630 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2631 | IN UINT8 SlotId,\r | |
2632 | IN UINT8 DeviceSpeed,\r | |
2633 | IN INPUT_CONTEXT *InputContext,\r | |
2634 | IN USB_INTERFACE_DESCRIPTOR *IfDesc\r | |
2635 | )\r | |
2636 | {\r | |
2637 | USB_ENDPOINT_DESCRIPTOR *EpDesc;\r | |
2638 | UINTN NumEp;\r | |
2639 | UINTN EpIndex;\r | |
2640 | UINT8 EpAddr;\r | |
2641 | UINT8 Direction;\r | |
2642 | UINT8 Dci;\r | |
2643 | UINT8 MaxDci;\r | |
2644 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
2645 | UINT8 Interval;\r | |
2646 | TRANSFER_RING *EndpointTransferRing;\r | |
2647 | \r | |
2648 | MaxDci = 0;\r | |
2649 | \r | |
2650 | NumEp = IfDesc->NumEndpoints;\r | |
2651 | \r | |
2652 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r | |
2653 | for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r | |
2654 | while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r | |
2655 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2656 | }\r | |
2657 | \r | |
fd5d2dd2 FT |
2658 | if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {\r |
2659 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2660 | continue;\r | |
2661 | }\r | |
2662 | \r | |
e1f2dfec SZ |
2663 | EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r |
2664 | Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r | |
2665 | \r | |
2666 | Dci = XhcEndpointToDci (EpAddr, Direction);\r | |
2667 | ASSERT (Dci < 32);\r | |
2668 | if (Dci > MaxDci) {\r | |
2669 | MaxDci = Dci;\r | |
2670 | }\r | |
2671 | \r | |
2672 | InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r | |
2673 | InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r | |
2674 | \r | |
2675 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
2676 | //\r | |
2677 | // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r | |
2678 | //\r | |
2679 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2680 | } else {\r | |
2681 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2682 | }\r | |
2683 | \r | |
2684 | switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r | |
2685 | case USB_ENDPOINT_BULK:\r | |
2686 | if (Direction == EfiUsbDataIn) {\r | |
2687 | InputContext->EP[Dci-1].CErr = 3;\r | |
2688 | InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r | |
2689 | } else {\r | |
2690 | InputContext->EP[Dci-1].CErr = 3;\r | |
2691 | InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r | |
2692 | }\r | |
2693 | \r | |
2694 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2695 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r | |
2696 | EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r | |
2697 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r | |
2698 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r | |
396ae94d RN |
2699 | DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",\r |
2700 | EpDesc->EndpointAddress,\r | |
2701 | EndpointTransferRing->RingSeg0,\r | |
2702 | (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)\r | |
2703 | ));\r | |
e1f2dfec SZ |
2704 | }\r |
2705 | \r | |
2706 | break;\r | |
2707 | case USB_ENDPOINT_ISO:\r | |
2708 | if (Direction == EfiUsbDataIn) {\r | |
2709 | InputContext->EP[Dci-1].CErr = 0;\r | |
2710 | InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r | |
2711 | } else {\r | |
2712 | InputContext->EP[Dci-1].CErr = 0;\r | |
2713 | InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r | |
2714 | }\r | |
3719c2aa HW |
2715 | //\r |
2716 | // Get the bInterval from descriptor and init the the interval field of endpoint context.\r | |
2717 | // Refer to XHCI 1.1 spec section 6.2.3.6.\r | |
2718 | //\r | |
2719 | if (DeviceSpeed == EFI_USB_SPEED_FULL) {\r | |
2720 | Interval = EpDesc->Interval;\r | |
2721 | ASSERT (Interval >= 1 && Interval <= 16);\r | |
2722 | InputContext->EP[Dci-1].Interval = Interval + 2;\r | |
2723 | } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r | |
2724 | Interval = EpDesc->Interval;\r | |
2725 | ASSERT (Interval >= 1 && Interval <= 16);\r | |
2726 | InputContext->EP[Dci-1].Interval = Interval - 1;\r | |
2727 | }\r | |
2728 | \r | |
acedecdd EL |
2729 | //\r |
2730 | // Do not support isochronous transfer now.\r | |
2731 | //\r | |
2732 | DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r | |
2733 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2734 | continue;\r | |
e1f2dfec SZ |
2735 | case USB_ENDPOINT_INTERRUPT:\r |
2736 | if (Direction == EfiUsbDataIn) {\r | |
2737 | InputContext->EP[Dci-1].CErr = 3;\r | |
2738 | InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r | |
2739 | } else {\r | |
2740 | InputContext->EP[Dci-1].CErr = 3;\r | |
2741 | InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r | |
2742 | }\r | |
2743 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2744 | InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r | |
2745 | //\r | |
2746 | // Get the bInterval from descriptor and init the the interval field of endpoint context\r | |
2747 | //\r | |
2748 | if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r | |
2749 | Interval = EpDesc->Interval;\r | |
2750 | //\r | |
2751 | // Calculate through the bInterval field of Endpoint descriptor.\r | |
2752 | //\r | |
2753 | ASSERT (Interval != 0);\r | |
2754 | InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;\r | |
2755 | } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r | |
2756 | Interval = EpDesc->Interval;\r | |
2757 | ASSERT (Interval >= 1 && Interval <= 16);\r | |
2758 | //\r | |
2759 | // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r | |
2760 | //\r | |
2761 | InputContext->EP[Dci-1].Interval = Interval - 1;\r | |
2762 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2763 | InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r | |
2764 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2765 | InputContext->EP[Dci-1].CErr = 3;\r | |
2766 | }\r | |
2767 | \r | |
2768 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r | |
2769 | EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r | |
2770 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r | |
2771 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r | |
396ae94d RN |
2772 | DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",\r |
2773 | EpDesc->EndpointAddress,\r | |
2774 | EndpointTransferRing->RingSeg0,\r | |
2775 | (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)\r | |
2776 | ));\r | |
e1f2dfec SZ |
2777 | }\r |
2778 | break;\r | |
2779 | \r | |
2780 | case USB_ENDPOINT_CONTROL:\r | |
acedecdd EL |
2781 | //\r |
2782 | // Do not support control transfer now.\r | |
2783 | //\r | |
2784 | DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r | |
e1f2dfec | 2785 | default:\r |
acedecdd EL |
2786 | DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));\r |
2787 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2788 | continue;\r | |
e1f2dfec SZ |
2789 | }\r |
2790 | \r | |
2791 | PhyAddr = UsbHcGetPciAddrForHostAddr (\r | |
2792 | Xhc->MemPool,\r | |
2793 | ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r | |
2794 | sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r | |
2795 | );\r | |
6e1e5405 FT |
2796 | PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r |
2797 | PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r | |
e1f2dfec SZ |
2798 | InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r |
2799 | InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
2800 | \r | |
2801 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2802 | }\r | |
2803 | \r | |
2804 | return MaxDci;\r | |
2805 | }\r | |
2806 | \r | |
2807 | /**\r | |
2808 | Initialize endpoint context in input context.\r | |
2809 | \r | |
2810 | @param Xhc The XHCI Instance.\r | |
2811 | @param SlotId The slot id to be configured.\r | |
2812 | @param DeviceSpeed The device's speed.\r | |
2813 | @param InputContext The pointer to the input context.\r | |
2814 | @param IfDesc The pointer to the usb device interface descriptor.\r | |
2815 | \r | |
2816 | @return The maximum device context index of endpoint.\r | |
2817 | \r | |
2818 | **/\r | |
2819 | UINT8\r | |
2820 | EFIAPI\r | |
2821 | XhcInitializeEndpointContext64 (\r | |
2822 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2823 | IN UINT8 SlotId,\r | |
2824 | IN UINT8 DeviceSpeed,\r | |
2825 | IN INPUT_CONTEXT_64 *InputContext,\r | |
2826 | IN USB_INTERFACE_DESCRIPTOR *IfDesc\r | |
2827 | )\r | |
2828 | {\r | |
2829 | USB_ENDPOINT_DESCRIPTOR *EpDesc;\r | |
2830 | UINTN NumEp;\r | |
2831 | UINTN EpIndex;\r | |
2832 | UINT8 EpAddr;\r | |
2833 | UINT8 Direction;\r | |
2834 | UINT8 Dci;\r | |
2835 | UINT8 MaxDci;\r | |
2836 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
2837 | UINT8 Interval;\r | |
2838 | TRANSFER_RING *EndpointTransferRing;\r | |
2839 | \r | |
2840 | MaxDci = 0;\r | |
2841 | \r | |
2842 | NumEp = IfDesc->NumEndpoints;\r | |
2843 | \r | |
2844 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r | |
2845 | for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r | |
2846 | while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r | |
2847 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2848 | }\r | |
2849 | \r | |
fd5d2dd2 FT |
2850 | if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {\r |
2851 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2852 | continue;\r | |
2853 | }\r | |
2854 | \r | |
e1f2dfec SZ |
2855 | EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r |
2856 | Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r | |
2857 | \r | |
2858 | Dci = XhcEndpointToDci (EpAddr, Direction);\r | |
2859 | ASSERT (Dci < 32);\r | |
2860 | if (Dci > MaxDci) {\r | |
2861 | MaxDci = Dci;\r | |
2862 | }\r | |
2863 | \r | |
2864 | InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r | |
2865 | InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r | |
2866 | \r | |
2867 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
2868 | //\r | |
2869 | // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r | |
2870 | //\r | |
2871 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2872 | } else {\r | |
2873 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2874 | }\r | |
2875 | \r | |
2876 | switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r | |
2877 | case USB_ENDPOINT_BULK:\r | |
2878 | if (Direction == EfiUsbDataIn) {\r | |
2879 | InputContext->EP[Dci-1].CErr = 3;\r | |
2880 | InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r | |
2881 | } else {\r | |
2882 | InputContext->EP[Dci-1].CErr = 3;\r | |
2883 | InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r | |
2884 | }\r | |
2885 | \r | |
2886 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2887 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r | |
2888 | EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r | |
2889 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r | |
2890 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r | |
396ae94d RN |
2891 | DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",\r |
2892 | EpDesc->EndpointAddress,\r | |
2893 | EndpointTransferRing->RingSeg0,\r | |
2894 | (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)\r | |
2895 | ));\r | |
e1f2dfec SZ |
2896 | }\r |
2897 | \r | |
2898 | break;\r | |
2899 | case USB_ENDPOINT_ISO:\r | |
2900 | if (Direction == EfiUsbDataIn) {\r | |
2901 | InputContext->EP[Dci-1].CErr = 0;\r | |
2902 | InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r | |
2903 | } else {\r | |
2904 | InputContext->EP[Dci-1].CErr = 0;\r | |
2905 | InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r | |
2906 | }\r | |
3719c2aa HW |
2907 | //\r |
2908 | // Get the bInterval from descriptor and init the the interval field of endpoint context.\r | |
2909 | // Refer to XHCI 1.1 spec section 6.2.3.6.\r | |
2910 | //\r | |
2911 | if (DeviceSpeed == EFI_USB_SPEED_FULL) {\r | |
2912 | Interval = EpDesc->Interval;\r | |
2913 | ASSERT (Interval >= 1 && Interval <= 16);\r | |
2914 | InputContext->EP[Dci-1].Interval = Interval + 2;\r | |
2915 | } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r | |
2916 | Interval = EpDesc->Interval;\r | |
2917 | ASSERT (Interval >= 1 && Interval <= 16);\r | |
2918 | InputContext->EP[Dci-1].Interval = Interval - 1;\r | |
2919 | }\r | |
2920 | \r | |
acedecdd EL |
2921 | //\r |
2922 | // Do not support isochronous transfer now.\r | |
2923 | //\r | |
2924 | DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));\r | |
2925 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2926 | continue;\r | |
e1f2dfec SZ |
2927 | case USB_ENDPOINT_INTERRUPT:\r |
2928 | if (Direction == EfiUsbDataIn) {\r | |
2929 | InputContext->EP[Dci-1].CErr = 3;\r | |
2930 | InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r | |
2931 | } else {\r | |
2932 | InputContext->EP[Dci-1].CErr = 3;\r | |
2933 | InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r | |
2934 | }\r | |
2935 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2936 | InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r | |
2937 | //\r | |
2938 | // Get the bInterval from descriptor and init the the interval field of endpoint context\r | |
2939 | //\r | |
2940 | if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r | |
2941 | Interval = EpDesc->Interval;\r | |
2942 | //\r | |
2943 | // Calculate through the bInterval field of Endpoint descriptor.\r | |
2944 | //\r | |
2945 | ASSERT (Interval != 0);\r | |
2946 | InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;\r | |
2947 | } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r | |
2948 | Interval = EpDesc->Interval;\r | |
2949 | ASSERT (Interval >= 1 && Interval <= 16);\r | |
2950 | //\r | |
2951 | // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r | |
2952 | //\r | |
2953 | InputContext->EP[Dci-1].Interval = Interval - 1;\r | |
2954 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2955 | InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r | |
2956 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2957 | InputContext->EP[Dci-1].CErr = 3;\r | |
2958 | }\r | |
2959 | \r | |
2960 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r | |
2961 | EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r | |
2962 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r | |
2963 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r | |
396ae94d RN |
2964 | DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",\r |
2965 | EpDesc->EndpointAddress,\r | |
2966 | EndpointTransferRing->RingSeg0,\r | |
2967 | (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)\r | |
2968 | ));\r | |
e1f2dfec SZ |
2969 | }\r |
2970 | break;\r | |
2971 | \r | |
2972 | case USB_ENDPOINT_CONTROL:\r | |
acedecdd EL |
2973 | //\r |
2974 | // Do not support control transfer now.\r | |
2975 | //\r | |
2976 | DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));\r | |
e1f2dfec | 2977 | default:\r |
acedecdd EL |
2978 | DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));\r |
2979 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2980 | continue;\r | |
e1f2dfec SZ |
2981 | }\r |
2982 | \r | |
2983 | PhyAddr = UsbHcGetPciAddrForHostAddr (\r | |
2984 | Xhc->MemPool,\r | |
2985 | ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,\r | |
2986 | sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER\r | |
2987 | );\r | |
6e1e5405 FT |
2988 | PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);\r |
2989 | PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r | |
e1f2dfec SZ |
2990 | InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);\r |
2991 | InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
2992 | \r | |
2993 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2994 | }\r | |
2995 | \r | |
2996 | return MaxDci;\r | |
2997 | }\r | |
6b4483cd | 2998 | \r |
2999 | /**\r | |
3000 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
3001 | \r | |
3002 | @param Xhc The XHCI Instance.\r | |
3003 | @param SlotId The slot id to be configured.\r | |
3004 | @param DeviceSpeed The device's speed.\r | |
3005 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
3006 | \r | |
3007 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
3008 | \r | |
3009 | **/\r | |
3010 | EFI_STATUS\r | |
3011 | EFIAPI\r | |
3012 | XhcSetConfigCmd (\r | |
3013 | IN USB_XHCI_INSTANCE *Xhc,\r | |
3014 | IN UINT8 SlotId,\r | |
3015 | IN UINT8 DeviceSpeed,\r | |
3016 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r | |
3017 | )\r | |
3018 | {\r | |
3019 | EFI_STATUS Status;\r | |
6b4483cd | 3020 | USB_INTERFACE_DESCRIPTOR *IfDesc;\r |
6b4483cd | 3021 | UINT8 Index;\r |
6b4483cd | 3022 | UINT8 Dci;\r |
3023 | UINT8 MaxDci;\r | |
1847ed0b | 3024 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
6b4483cd | 3025 | \r |
6b4483cd | 3026 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r |
3027 | INPUT_CONTEXT *InputContext;\r | |
3028 | DEVICE_CONTEXT *OutputContext;\r | |
3029 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
3030 | //\r | |
3031 | // 4.6.6 Configure Endpoint\r | |
3032 | //\r | |
3033 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
3034 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
3035 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r | |
3036 | CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));\r | |
3037 | \r | |
3038 | ASSERT (ConfigDesc != NULL);\r | |
3039 | \r | |
3040 | MaxDci = 0;\r | |
3041 | \r | |
3042 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r | |
3043 | for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r | |
e1f2dfec | 3044 | while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {\r |
6b4483cd | 3045 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r |
3046 | }\r | |
3047 | \r | |
fd5d2dd2 FT |
3048 | if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {\r |
3049 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r | |
3050 | continue;\r | |
3051 | }\r | |
3052 | \r | |
e1f2dfec SZ |
3053 | Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);\r |
3054 | if (Dci > MaxDci) {\r | |
3055 | MaxDci = Dci;\r | |
6b4483cd | 3056 | }\r |
e1f2dfec | 3057 | \r |
6b4483cd | 3058 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r |
3059 | }\r | |
3060 | \r | |
3061 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
3062 | InputContext->Slot.ContextEntries = MaxDci;\r | |
3063 | //\r | |
3064 | // configure endpoint\r | |
3065 | //\r | |
3066 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
1847ed0b EL |
3067 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r |
3068 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
3069 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
6b4483cd | 3070 | CmdTrbCfgEP.CycleBit = 1;\r |
3071 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
3072 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
3073 | DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));\r | |
3074 | Status = XhcCmdTransfer (\r | |
3075 | Xhc,\r | |
3076 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r | |
3077 | XHC_GENERIC_TIMEOUT,\r | |
3078 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
3079 | );\r | |
260fbf53 EL |
3080 | if (EFI_ERROR (Status)) {\r |
3081 | DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));\r | |
e1f2dfec SZ |
3082 | } else {\r |
3083 | Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;\r | |
260fbf53 | 3084 | }\r |
e1f2dfec | 3085 | \r |
92870c98 | 3086 | return Status;\r |
3087 | }\r | |
3088 | \r | |
3089 | /**\r | |
3090 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
3091 | \r | |
a9292c13 | 3092 | @param Xhc The XHCI Instance.\r |
92870c98 | 3093 | @param SlotId The slot id to be configured.\r |
3094 | @param DeviceSpeed The device's speed.\r | |
3095 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
3096 | \r | |
3097 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
3098 | \r | |
3099 | **/\r | |
3100 | EFI_STATUS\r | |
3101 | EFIAPI\r | |
6b4483cd | 3102 | XhcSetConfigCmd64 (\r |
a9292c13 | 3103 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 3104 | IN UINT8 SlotId,\r |
a9292c13 | 3105 | IN UINT8 DeviceSpeed,\r |
92870c98 | 3106 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r |
3107 | )\r | |
3108 | {\r | |
a9292c13 | 3109 | EFI_STATUS Status;\r |
a9292c13 | 3110 | USB_INTERFACE_DESCRIPTOR *IfDesc;\r |
a9292c13 | 3111 | UINT8 Index;\r |
a9292c13 | 3112 | UINT8 Dci;\r |
3113 | UINT8 MaxDci;\r | |
1847ed0b | 3114 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
a9292c13 | 3115 | \r |
a9292c13 | 3116 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r |
6b4483cd | 3117 | INPUT_CONTEXT_64 *InputContext;\r |
3118 | DEVICE_CONTEXT_64 *OutputContext;\r | |
a9292c13 | 3119 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r |
92870c98 | 3120 | //\r |
3121 | // 4.6.6 Configure Endpoint\r | |
3122 | //\r | |
a9292c13 | 3123 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r |
3124 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
6b4483cd | 3125 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r |
3126 | CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));\r | |
92870c98 | 3127 | \r |
3128 | ASSERT (ConfigDesc != NULL);\r | |
3129 | \r | |
3130 | MaxDci = 0;\r | |
3131 | \r | |
3132 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r | |
3133 | for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r | |
e1f2dfec | 3134 | while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {\r |
92870c98 | 3135 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r |
3136 | }\r | |
3137 | \r | |
fd5d2dd2 FT |
3138 | if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {\r |
3139 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r | |
3140 | continue;\r | |
3141 | }\r | |
3142 | \r | |
e1f2dfec SZ |
3143 | Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);\r |
3144 | if (Dci > MaxDci) {\r | |
3145 | MaxDci = Dci;\r | |
92870c98 | 3146 | }\r |
d1102dba | 3147 | \r |
92870c98 | 3148 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r |
3149 | }\r | |
3150 | \r | |
3151 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
3152 | InputContext->Slot.ContextEntries = MaxDci;\r | |
3153 | //\r | |
3154 | // configure endpoint\r | |
3155 | //\r | |
3156 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
1847ed0b EL |
3157 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r |
3158 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
3159 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
92870c98 | 3160 | CmdTrbCfgEP.CycleBit = 1;\r |
3161 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
a9292c13 | 3162 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r |
92870c98 | 3163 | DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));\r |
3164 | Status = XhcCmdTransfer (\r | |
3165 | Xhc,\r | |
a9292c13 | 3166 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r |
92870c98 | 3167 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 3168 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 3169 | );\r |
260fbf53 EL |
3170 | if (EFI_ERROR (Status)) {\r |
3171 | DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));\r | |
e1f2dfec SZ |
3172 | } else {\r |
3173 | Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;\r | |
3174 | }\r | |
3175 | \r | |
3176 | return Status;\r | |
3177 | }\r | |
3178 | \r | |
3179 | /**\r | |
3180 | Stop endpoint through XHCI's Stop_Endpoint cmd.\r | |
3181 | \r | |
3182 | @param Xhc The XHCI Instance.\r | |
3183 | @param SlotId The slot id to be configured.\r | |
3184 | @param Dci The device context index of endpoint.\r | |
49be9c3c | 3185 | @param PendingUrb The pending URB to check completion status when stopping the end point.\r |
e1f2dfec SZ |
3186 | \r |
3187 | @retval EFI_SUCCESS Stop endpoint successfully.\r | |
3188 | @retval Others Failed to stop endpoint.\r | |
3189 | \r | |
3190 | **/\r | |
3191 | EFI_STATUS\r | |
3192 | EFIAPI\r | |
3193 | XhcStopEndpoint (\r | |
3194 | IN USB_XHCI_INSTANCE *Xhc,\r | |
3195 | IN UINT8 SlotId,\r | |
49be9c3c RN |
3196 | IN UINT8 Dci,\r |
3197 | IN URB *PendingUrb OPTIONAL\r | |
e1f2dfec SZ |
3198 | )\r |
3199 | {\r | |
3200 | EFI_STATUS Status;\r | |
3201 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
3202 | CMD_TRB_STOP_ENDPOINT CmdTrbStopED;\r | |
3203 | \r | |
3204 | DEBUG ((EFI_D_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));\r | |
3205 | \r | |
49be9c3c RN |
3206 | //\r |
3207 | // When XhcCheckUrbResult waits for the Stop_Endpoint completion, it also checks\r | |
3208 | // the PendingUrb completion status, because it's possible that the PendingUrb is\r | |
3209 | // finished just before stopping the end point, but after the looping check.\r | |
3210 | //\r | |
3211 | // The PendingUrb could be passed to XhcCmdTransfer to XhcExecTransfer to XhcCheckUrbResult\r | |
3212 | // through function parameter, but That will cause every consumer of XhcCmdTransfer,\r | |
3213 | // XhcExecTransfer and XhcCheckUrbResult pass a NULL PendingUrb.\r | |
3214 | // But actually only XhcCheckUrbResult is aware of the PendingUrb.\r | |
3215 | // So we choose to save the PendingUrb into the USB_XHCI_INSTANCE and use it in XhcCheckUrbResult.\r | |
3216 | //\r | |
3217 | ASSERT (Xhc->PendingUrb == NULL);\r | |
3218 | Xhc->PendingUrb = PendingUrb;\r | |
3219 | //\r | |
3220 | // Reset the URB result from Timeout to NoError.\r | |
3221 | // The USB result will be:\r | |
3222 | // changed to Timeout when Stop/StopInvalidLength Transfer Event is received, or\r | |
3223 | // remain NoError when Success/ShortPacket Transfer Event is received.\r | |
3224 | //\r | |
3225 | if (PendingUrb != NULL) {\r | |
3226 | PendingUrb->Result = EFI_USB_NOERROR;\r | |
3227 | }\r | |
3228 | \r | |
e1f2dfec SZ |
3229 | //\r |
3230 | // Send stop endpoint command to transit Endpoint from running to stop state\r | |
3231 | //\r | |
3232 | ZeroMem (&CmdTrbStopED, sizeof (CmdTrbStopED));\r | |
3233 | CmdTrbStopED.CycleBit = 1;\r | |
3234 | CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;\r | |
3235 | CmdTrbStopED.EDID = Dci;\r | |
3236 | CmdTrbStopED.SlotId = SlotId;\r | |
3237 | Status = XhcCmdTransfer (\r | |
3238 | Xhc,\r | |
3239 | (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,\r | |
3240 | XHC_GENERIC_TIMEOUT,\r | |
3241 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
3242 | );\r | |
3243 | if (EFI_ERROR(Status)) {\r | |
3244 | DEBUG ((EFI_D_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));\r | |
3245 | }\r | |
3246 | \r | |
49be9c3c RN |
3247 | Xhc->PendingUrb = NULL;\r |
3248 | \r | |
e1f2dfec SZ |
3249 | return Status;\r |
3250 | }\r | |
3251 | \r | |
12e6c738 FT |
3252 | /**\r |
3253 | Reset endpoint through XHCI's Reset_Endpoint cmd.\r | |
3254 | \r | |
3255 | @param Xhc The XHCI Instance.\r | |
3256 | @param SlotId The slot id to be configured.\r | |
3257 | @param Dci The device context index of endpoint.\r | |
3258 | \r | |
3259 | @retval EFI_SUCCESS Reset endpoint successfully.\r | |
3260 | @retval Others Failed to reset endpoint.\r | |
3261 | \r | |
3262 | **/\r | |
3263 | EFI_STATUS\r | |
3264 | EFIAPI\r | |
3265 | XhcResetEndpoint (\r | |
3266 | IN USB_XHCI_INSTANCE *Xhc,\r | |
3267 | IN UINT8 SlotId,\r | |
3268 | IN UINT8 Dci\r | |
3269 | )\r | |
3270 | {\r | |
3271 | EFI_STATUS Status;\r | |
3272 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
3273 | CMD_TRB_RESET_ENDPOINT CmdTrbResetED;\r | |
3274 | \r | |
3275 | DEBUG ((EFI_D_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));\r | |
3276 | \r | |
3277 | //\r | |
3278 | // Send stop endpoint command to transit Endpoint from running to stop state\r | |
3279 | //\r | |
3280 | ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));\r | |
3281 | CmdTrbResetED.CycleBit = 1;\r | |
3282 | CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;\r | |
3283 | CmdTrbResetED.EDID = Dci;\r | |
3284 | CmdTrbResetED.SlotId = SlotId;\r | |
3285 | Status = XhcCmdTransfer (\r | |
3286 | Xhc,\r | |
3287 | (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,\r | |
3288 | XHC_GENERIC_TIMEOUT,\r | |
3289 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
3290 | );\r | |
3291 | if (EFI_ERROR(Status)) {\r | |
3292 | DEBUG ((EFI_D_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));\r | |
3293 | }\r | |
3294 | \r | |
3295 | return Status;\r | |
3296 | }\r | |
3297 | \r | |
3298 | /**\r | |
3299 | Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r | |
3300 | \r | |
3301 | @param Xhc The XHCI Instance.\r | |
3302 | @param SlotId The slot id to be configured.\r | |
3303 | @param Dci The device context index of endpoint.\r | |
3304 | @param Urb The dequeue pointer of the transfer ring specified\r | |
3305 | by the urb to be updated.\r | |
3306 | \r | |
3307 | @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r | |
3308 | @retval Others Failed to set transfer ring dequeue pointer.\r | |
3309 | \r | |
3310 | **/\r | |
3311 | EFI_STATUS\r | |
3312 | EFIAPI\r | |
3313 | XhcSetTrDequeuePointer (\r | |
3314 | IN USB_XHCI_INSTANCE *Xhc,\r | |
3315 | IN UINT8 SlotId,\r | |
3316 | IN UINT8 Dci,\r | |
3317 | IN URB *Urb\r | |
3318 | )\r | |
3319 | {\r | |
3320 | EFI_STATUS Status;\r | |
3321 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
3322 | CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;\r | |
3323 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
3324 | \r | |
3325 | DEBUG ((EFI_D_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));\r | |
3326 | \r | |
3327 | //\r | |
3328 | // Send stop endpoint command to transit Endpoint from running to stop state\r | |
3329 | //\r | |
3330 | ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));\r | |
3331 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));\r | |
3332 | CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;\r | |
3333 | CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
3334 | CmdSetTRDeq.CycleBit = 1;\r | |
3335 | CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;\r | |
3336 | CmdSetTRDeq.Endpoint = Dci;\r | |
3337 | CmdSetTRDeq.SlotId = SlotId;\r | |
3338 | Status = XhcCmdTransfer (\r | |
3339 | Xhc,\r | |
3340 | (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,\r | |
3341 | XHC_GENERIC_TIMEOUT,\r | |
3342 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
3343 | );\r | |
3344 | if (EFI_ERROR(Status)) {\r | |
3345 | DEBUG ((EFI_D_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));\r | |
3346 | }\r | |
3347 | \r | |
3348 | return Status;\r | |
3349 | }\r | |
3350 | \r | |
e1f2dfec SZ |
3351 | /**\r |
3352 | Set interface through XHCI's Configure_Endpoint cmd.\r | |
3353 | \r | |
3354 | @param Xhc The XHCI Instance.\r | |
3355 | @param SlotId The slot id to be configured.\r | |
3356 | @param DeviceSpeed The device's speed.\r | |
3357 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
3358 | @param Request USB device request to send.\r | |
3359 | \r | |
3360 | @retval EFI_SUCCESS Successfully set interface.\r | |
3361 | \r | |
3362 | **/\r | |
3363 | EFI_STATUS\r | |
3364 | EFIAPI\r | |
3365 | XhcSetInterface (\r | |
3366 | IN USB_XHCI_INSTANCE *Xhc,\r | |
3367 | IN UINT8 SlotId,\r | |
3368 | IN UINT8 DeviceSpeed,\r | |
3369 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r | |
3370 | IN EFI_USB_DEVICE_REQUEST *Request\r | |
3371 | )\r | |
3372 | {\r | |
3373 | EFI_STATUS Status;\r | |
3374 | USB_INTERFACE_DESCRIPTOR *IfDescActive;\r | |
3375 | USB_INTERFACE_DESCRIPTOR *IfDescSet;\r | |
3376 | USB_INTERFACE_DESCRIPTOR *IfDesc;\r | |
3377 | USB_ENDPOINT_DESCRIPTOR *EpDesc;\r | |
3378 | UINTN NumEp;\r | |
3379 | UINTN EpIndex;\r | |
3380 | UINT8 EpAddr;\r | |
3381 | UINT8 Direction;\r | |
3382 | UINT8 Dci;\r | |
3383 | UINT8 MaxDci;\r | |
3384 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
3385 | VOID *RingSeg;\r | |
3386 | \r | |
3387 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r | |
3388 | INPUT_CONTEXT *InputContext;\r | |
3389 | DEVICE_CONTEXT *OutputContext;\r | |
3390 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
3391 | \r | |
3392 | Status = EFI_SUCCESS;\r | |
3393 | \r | |
3394 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
3395 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
3396 | //\r | |
3397 | // XHCI 4.6.6 Configure Endpoint\r | |
3398 | // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop\r | |
3399 | // Context and Add Context flags as follows:\r | |
3400 | // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop\r | |
3401 | // Context and Add Context flags to '0'.\r | |
3402 | //\r | |
3403 | // Except the interface indicated by Reqeust->Index, no impact to other interfaces.\r | |
3404 | // So the default Drop Context and Add Context flags can be '0' to cover 1).\r | |
3405 | //\r | |
3406 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r | |
3407 | CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));\r | |
3408 | \r | |
3409 | ASSERT (ConfigDesc != NULL);\r | |
3410 | \r | |
3411 | MaxDci = 0;\r | |
3412 | \r | |
3413 | IfDescActive = NULL;\r | |
3414 | IfDescSet = NULL;\r | |
3415 | \r | |
3416 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r | |
3417 | while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {\r | |
fd5d2dd2 | 3418 | if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {\r |
e1f2dfec SZ |
3419 | if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {\r |
3420 | if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {\r | |
3421 | //\r | |
3422 | // Find out the active interface descriptor.\r | |
3423 | //\r | |
3424 | IfDescActive = IfDesc;\r | |
3425 | } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {\r | |
3426 | //\r | |
3427 | // Find out the interface descriptor to set.\r | |
3428 | //\r | |
3429 | IfDescSet = IfDesc;\r | |
3430 | }\r | |
3431 | }\r | |
3432 | }\r | |
3433 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r | |
3434 | }\r | |
3435 | \r | |
3436 | //\r | |
3437 | // XHCI 4.6.6 Configure Endpoint\r | |
3438 | // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop\r | |
3439 | // Context and Add Context flags as follows:\r | |
3440 | // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set\r | |
3441 | // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.\r | |
3442 | // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set\r | |
3443 | // the Drop Context flag to '1' and Add Context flag to '0'.\r | |
3444 | // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context\r | |
3445 | // and Add Context flags shall be set to '1'.\r | |
3446 | //\r | |
3447 | // Below codes are to cover 2), 3) and 4).\r | |
3448 | //\r | |
3449 | \r | |
3450 | if ((IfDescActive != NULL) && (IfDescSet != NULL)) {\r | |
3451 | NumEp = IfDescActive->NumEndpoints;\r | |
3452 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);\r | |
3453 | for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r | |
3454 | while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r | |
3455 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
3456 | }\r | |
3457 | \r | |
fd5d2dd2 FT |
3458 | if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {\r |
3459 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
3460 | continue;\r | |
3461 | }\r | |
3462 | \r | |
e1f2dfec SZ |
3463 | EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);\r |
3464 | Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r | |
3465 | \r | |
3466 | Dci = XhcEndpointToDci (EpAddr, Direction);\r | |
3467 | ASSERT (Dci < 32);\r | |
3468 | if (Dci > MaxDci) {\r | |
3469 | MaxDci = Dci;\r | |
3470 | }\r | |
3471 | //\r | |
3472 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3473 | // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.\r | |
3474 | //\r | |
49be9c3c | 3475 | Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);\r |
e1f2dfec SZ |
3476 | if (EFI_ERROR (Status)) {\r |
3477 | return Status;\r | |
3478 | }\r | |
3479 | //\r | |
3480 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3481 | // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.\r | |
3482 | //\r | |
3483 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {\r | |
3484 | RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;\r | |
3485 | if (RingSeg != NULL) {\r | |
3486 | UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r | |
3487 | }\r | |
3488 | FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);\r | |
3489 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;\r | |
3490 | }\r | |
3491 | \r | |
3492 | //\r | |
3493 | // Set the Drop Context flag to '1'.\r | |
3494 | //\r | |
3495 | InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);\r | |
3496 | \r | |
3497 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
3498 | }\r | |
3499 | \r | |
3500 | //\r | |
3501 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3502 | // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate\r | |
3503 | // Interface setting, to '0'.\r | |
3504 | //\r | |
3505 | // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.\r | |
3506 | //\r | |
3507 | \r | |
3508 | //\r | |
3509 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3510 | // 4) For each endpoint enabled by the Configure Endpoint Command:\r | |
3511 | // a. Allocate a Transfer Ring.\r | |
3512 | // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.\r | |
3513 | // c. Initialize the Endpoint Context data structure.\r | |
3514 | //\r | |
3515 | Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);\r | |
3516 | if (Dci > MaxDci) {\r | |
3517 | MaxDci = Dci;\r | |
3518 | }\r | |
3519 | \r | |
3520 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
3521 | InputContext->Slot.ContextEntries = MaxDci;\r | |
3522 | //\r | |
3523 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3524 | // 5) Issue and successfully complete a Configure Endpoint Command.\r | |
3525 | //\r | |
3526 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
3527 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r | |
3528 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
3529 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
3530 | CmdTrbCfgEP.CycleBit = 1;\r | |
3531 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
3532 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
3533 | DEBUG ((EFI_D_INFO, "SetInterface: Configure Endpoint\n"));\r | |
3534 | Status = XhcCmdTransfer (\r | |
3535 | Xhc,\r | |
3536 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r | |
3537 | XHC_GENERIC_TIMEOUT,\r | |
3538 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
3539 | );\r | |
3540 | if (EFI_ERROR (Status)) {\r | |
3541 | DEBUG ((EFI_D_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));\r | |
3542 | } else {\r | |
3543 | //\r | |
3544 | // Update the active AlternateSetting.\r | |
3545 | //\r | |
3546 | Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;\r | |
3547 | }\r | |
260fbf53 | 3548 | }\r |
92870c98 | 3549 | \r |
3550 | return Status;\r | |
3551 | }\r | |
3552 | \r | |
e1f2dfec SZ |
3553 | /**\r |
3554 | Set interface through XHCI's Configure_Endpoint cmd.\r | |
3555 | \r | |
3556 | @param Xhc The XHCI Instance.\r | |
3557 | @param SlotId The slot id to be configured.\r | |
3558 | @param DeviceSpeed The device's speed.\r | |
3559 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
3560 | @param Request USB device request to send.\r | |
3561 | \r | |
3562 | @retval EFI_SUCCESS Successfully set interface.\r | |
3563 | \r | |
3564 | **/\r | |
3565 | EFI_STATUS\r | |
3566 | EFIAPI\r | |
3567 | XhcSetInterface64 (\r | |
3568 | IN USB_XHCI_INSTANCE *Xhc,\r | |
3569 | IN UINT8 SlotId,\r | |
3570 | IN UINT8 DeviceSpeed,\r | |
3571 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r | |
3572 | IN EFI_USB_DEVICE_REQUEST *Request\r | |
3573 | )\r | |
3574 | {\r | |
3575 | EFI_STATUS Status;\r | |
3576 | USB_INTERFACE_DESCRIPTOR *IfDescActive;\r | |
3577 | USB_INTERFACE_DESCRIPTOR *IfDescSet;\r | |
3578 | USB_INTERFACE_DESCRIPTOR *IfDesc;\r | |
3579 | USB_ENDPOINT_DESCRIPTOR *EpDesc;\r | |
3580 | UINTN NumEp;\r | |
3581 | UINTN EpIndex;\r | |
3582 | UINT8 EpAddr;\r | |
3583 | UINT8 Direction;\r | |
3584 | UINT8 Dci;\r | |
3585 | UINT8 MaxDci;\r | |
3586 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
3587 | VOID *RingSeg;\r | |
3588 | \r | |
3589 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r | |
3590 | INPUT_CONTEXT_64 *InputContext;\r | |
3591 | DEVICE_CONTEXT_64 *OutputContext;\r | |
3592 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
3593 | \r | |
3594 | Status = EFI_SUCCESS;\r | |
3595 | \r | |
3596 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
3597 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
3598 | //\r | |
3599 | // XHCI 4.6.6 Configure Endpoint\r | |
3600 | // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop\r | |
3601 | // Context and Add Context flags as follows:\r | |
3602 | // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop\r | |
3603 | // Context and Add Context flags to '0'.\r | |
3604 | //\r | |
3605 | // Except the interface indicated by Reqeust->Index, no impact to other interfaces.\r | |
3606 | // So the default Drop Context and Add Context flags can be '0' to cover 1).\r | |
3607 | //\r | |
3608 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r | |
3609 | CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));\r | |
3610 | \r | |
3611 | ASSERT (ConfigDesc != NULL);\r | |
3612 | \r | |
3613 | MaxDci = 0;\r | |
3614 | \r | |
3615 | IfDescActive = NULL;\r | |
3616 | IfDescSet = NULL;\r | |
3617 | \r | |
3618 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r | |
3619 | while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {\r | |
fd5d2dd2 | 3620 | if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {\r |
e1f2dfec SZ |
3621 | if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {\r |
3622 | if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {\r | |
3623 | //\r | |
3624 | // Find out the active interface descriptor.\r | |
3625 | //\r | |
3626 | IfDescActive = IfDesc;\r | |
3627 | } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {\r | |
3628 | //\r | |
3629 | // Find out the interface descriptor to set.\r | |
3630 | //\r | |
3631 | IfDescSet = IfDesc;\r | |
3632 | }\r | |
3633 | }\r | |
3634 | }\r | |
3635 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r | |
3636 | }\r | |
3637 | \r | |
3638 | //\r | |
3639 | // XHCI 4.6.6 Configure Endpoint\r | |
3640 | // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop\r | |
3641 | // Context and Add Context flags as follows:\r | |
3642 | // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set\r | |
3643 | // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.\r | |
3644 | // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set\r | |
3645 | // the Drop Context flag to '1' and Add Context flag to '0'.\r | |
3646 | // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context\r | |
3647 | // and Add Context flags shall be set to '1'.\r | |
3648 | //\r | |
3649 | // Below codes are to cover 2), 3) and 4).\r | |
3650 | //\r | |
3651 | \r | |
3652 | if ((IfDescActive != NULL) && (IfDescSet != NULL)) {\r | |
3653 | NumEp = IfDescActive->NumEndpoints;\r | |
3654 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);\r | |
3655 | for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r | |
3656 | while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r | |
3657 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
3658 | }\r | |
3659 | \r | |
fd5d2dd2 FT |
3660 | if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {\r |
3661 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
3662 | continue;\r | |
3663 | }\r | |
3664 | \r | |
e1f2dfec SZ |
3665 | EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);\r |
3666 | Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r | |
3667 | \r | |
3668 | Dci = XhcEndpointToDci (EpAddr, Direction);\r | |
3669 | ASSERT (Dci < 32);\r | |
3670 | if (Dci > MaxDci) {\r | |
3671 | MaxDci = Dci;\r | |
3672 | }\r | |
3673 | //\r | |
3674 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3675 | // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.\r | |
3676 | //\r | |
49be9c3c | 3677 | Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);\r |
e1f2dfec SZ |
3678 | if (EFI_ERROR (Status)) {\r |
3679 | return Status;\r | |
3680 | }\r | |
3681 | //\r | |
3682 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3683 | // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.\r | |
3684 | //\r | |
3685 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {\r | |
3686 | RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;\r | |
3687 | if (RingSeg != NULL) {\r | |
3688 | UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);\r | |
3689 | }\r | |
3690 | FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);\r | |
3691 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;\r | |
3692 | }\r | |
3693 | \r | |
3694 | //\r | |
3695 | // Set the Drop Context flag to '1'.\r | |
3696 | //\r | |
3697 | InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);\r | |
3698 | \r | |
3699 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
3700 | }\r | |
3701 | \r | |
3702 | //\r | |
3703 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3704 | // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate\r | |
3705 | // Interface setting, to '0'.\r | |
3706 | //\r | |
3707 | // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.\r | |
3708 | //\r | |
3709 | \r | |
3710 | //\r | |
3711 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3712 | // 4) For each endpoint enabled by the Configure Endpoint Command:\r | |
3713 | // a. Allocate a Transfer Ring.\r | |
3714 | // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.\r | |
3715 | // c. Initialize the Endpoint Context data structure.\r | |
3716 | //\r | |
3717 | Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);\r | |
3718 | if (Dci > MaxDci) {\r | |
3719 | MaxDci = Dci;\r | |
3720 | }\r | |
3721 | \r | |
3722 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
3723 | InputContext->Slot.ContextEntries = MaxDci;\r | |
3724 | //\r | |
3725 | // XHCI 4.3.6 - Setting Alternate Interfaces\r | |
3726 | // 5) Issue and successfully complete a Configure Endpoint Command.\r | |
3727 | //\r | |
3728 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
3729 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r | |
3730 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
3731 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
3732 | CmdTrbCfgEP.CycleBit = 1;\r | |
3733 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
3734 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
3735 | DEBUG ((EFI_D_INFO, "SetInterface64: Configure Endpoint\n"));\r | |
3736 | Status = XhcCmdTransfer (\r | |
3737 | Xhc,\r | |
3738 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r | |
3739 | XHC_GENERIC_TIMEOUT,\r | |
3740 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
3741 | );\r | |
3742 | if (EFI_ERROR (Status)) {\r | |
3743 | DEBUG ((EFI_D_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));\r | |
3744 | } else {\r | |
3745 | //\r | |
3746 | // Update the active AlternateSetting.\r | |
3747 | //\r | |
3748 | Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;\r | |
3749 | }\r | |
3750 | }\r | |
3751 | \r | |
3752 | return Status;\r | |
3753 | }\r | |
6b4483cd | 3754 | \r |
92870c98 | 3755 | /**\r |
3756 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
3757 | \r | |
a9292c13 | 3758 | @param Xhc The XHCI Instance.\r |
92870c98 | 3759 | @param SlotId The slot id to be evaluated.\r |
3760 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
3761 | \r | |
3762 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
3763 | \r | |
3764 | **/\r | |
3765 | EFI_STATUS\r | |
3766 | EFIAPI\r | |
3767 | XhcEvaluateContext (\r | |
a9292c13 | 3768 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 3769 | IN UINT8 SlotId,\r |
3770 | IN UINT32 MaxPacketSize\r | |
3771 | )\r | |
3772 | {\r | |
a9292c13 | 3773 | EFI_STATUS Status;\r |
3774 | CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r | |
3775 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
3776 | INPUT_CONTEXT *InputContext;\r | |
1847ed0b | 3777 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
92870c98 | 3778 | \r |
a9292c13 | 3779 | ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r |
92870c98 | 3780 | \r |
3781 | //\r | |
3782 | // 4.6.7 Evaluate Context\r | |
3783 | //\r | |
a9292c13 | 3784 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r |
92870c98 | 3785 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r |
3786 | \r | |
3787 | InputContext->InputControlContext.Dword2 |= BIT1;\r | |
3788 | InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r | |
3789 | \r | |
3790 | ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r | |
1847ed0b EL |
3791 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r |
3792 | CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
3793 | CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
92870c98 | 3794 | CmdTrbEvalu.CycleBit = 1;\r |
3795 | CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;\r | |
a9292c13 | 3796 | CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r |
92870c98 | 3797 | DEBUG ((EFI_D_INFO, "Evaluate context\n"));\r |
3798 | Status = XhcCmdTransfer (\r | |
3799 | Xhc,\r | |
a9292c13 | 3800 | (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r |
92870c98 | 3801 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 3802 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 3803 | );\r |
260fbf53 EL |
3804 | if (EFI_ERROR (Status)) {\r |
3805 | DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));\r | |
3806 | }\r | |
92870c98 | 3807 | return Status;\r |
3808 | }\r | |
3809 | \r | |
6b4483cd | 3810 | /**\r |
3811 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
3812 | \r | |
3813 | @param Xhc The XHCI Instance.\r | |
3814 | @param SlotId The slot id to be evaluated.\r | |
3815 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
3816 | \r | |
3817 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
3818 | \r | |
3819 | **/\r | |
3820 | EFI_STATUS\r | |
3821 | EFIAPI\r | |
3822 | XhcEvaluateContext64 (\r | |
3823 | IN USB_XHCI_INSTANCE *Xhc,\r | |
3824 | IN UINT8 SlotId,\r | |
3825 | IN UINT32 MaxPacketSize\r | |
3826 | )\r | |
3827 | {\r | |
3828 | EFI_STATUS Status;\r | |
3829 | CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r | |
3830 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
3831 | INPUT_CONTEXT_64 *InputContext;\r | |
1847ed0b | 3832 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
6b4483cd | 3833 | \r |
3834 | ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r | |
3835 | \r | |
3836 | //\r | |
3837 | // 4.6.7 Evaluate Context\r | |
3838 | //\r | |
3839 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
3840 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r | |
3841 | \r | |
3842 | InputContext->InputControlContext.Dword2 |= BIT1;\r | |
3843 | InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r | |
3844 | \r | |
3845 | ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r | |
1847ed0b EL |
3846 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r |
3847 | CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
3848 | CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
6b4483cd | 3849 | CmdTrbEvalu.CycleBit = 1;\r |
3850 | CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;\r | |
3851 | CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
3852 | DEBUG ((EFI_D_INFO, "Evaluate context\n"));\r | |
3853 | Status = XhcCmdTransfer (\r | |
3854 | Xhc,\r | |
3855 | (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r | |
3856 | XHC_GENERIC_TIMEOUT,\r | |
3857 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
3858 | );\r | |
260fbf53 EL |
3859 | if (EFI_ERROR (Status)) {\r |
3860 | DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));\r | |
3861 | }\r | |
6b4483cd | 3862 | return Status;\r |
3863 | }\r | |
3864 | \r | |
3865 | \r | |
92870c98 | 3866 | /**\r |
3867 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
3868 | \r | |
a9292c13 | 3869 | @param Xhc The XHCI Instance.\r |
92870c98 | 3870 | @param SlotId The slot id to be configured.\r |
3871 | @param PortNum The total number of downstream port supported by the hub.\r | |
3872 | @param TTT The TT think time of the hub device.\r | |
3873 | @param MTT The multi-TT of the hub device.\r | |
3874 | \r | |
3875 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
3876 | \r | |
3877 | **/\r | |
3878 | EFI_STATUS\r | |
3879 | XhcConfigHubContext (\r | |
a9292c13 | 3880 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 3881 | IN UINT8 SlotId,\r |
3882 | IN UINT8 PortNum,\r | |
3883 | IN UINT8 TTT,\r | |
3884 | IN UINT8 MTT\r | |
3885 | )\r | |
3886 | {\r | |
a9292c13 | 3887 | EFI_STATUS Status;\r |
a9292c13 | 3888 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r |
3889 | INPUT_CONTEXT *InputContext;\r | |
3890 | DEVICE_CONTEXT *OutputContext;\r | |
3891 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r | |
1847ed0b | 3892 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
92870c98 | 3893 | \r |
a9292c13 | 3894 | ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r |
3895 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
3896 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
92870c98 | 3897 | \r |
3898 | //\r | |
3899 | // 4.6.7 Evaluate Context\r | |
3900 | //\r | |
3901 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r | |
3902 | \r | |
3903 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
3904 | \r | |
3905 | //\r | |
3906 | // Copy the slot context from OutputContext to Input context\r | |
3907 | //\r | |
a9292c13 | 3908 | CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));\r |
92870c98 | 3909 | InputContext->Slot.Hub = 1;\r |
3910 | InputContext->Slot.PortNum = PortNum;\r | |
3911 | InputContext->Slot.TTT = TTT;\r | |
3912 | InputContext->Slot.MTT = MTT;\r | |
3913 | \r | |
3914 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
1847ed0b EL |
3915 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));\r |
3916 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
3917 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
92870c98 | 3918 | CmdTrbCfgEP.CycleBit = 1;\r |
3919 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
a9292c13 | 3920 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r |
92870c98 | 3921 | DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r |
3922 | Status = XhcCmdTransfer (\r | |
3923 | Xhc,\r | |
a9292c13 | 3924 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r |
92870c98 | 3925 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 3926 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 3927 | );\r |
260fbf53 EL |
3928 | if (EFI_ERROR (Status)) {\r |
3929 | DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));\r | |
3930 | }\r | |
92870c98 | 3931 | return Status;\r |
3932 | }\r | |
3933 | \r | |
6b4483cd | 3934 | /**\r |
3935 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
3936 | \r | |
3937 | @param Xhc The XHCI Instance.\r | |
3938 | @param SlotId The slot id to be configured.\r | |
3939 | @param PortNum The total number of downstream port supported by the hub.\r | |
3940 | @param TTT The TT think time of the hub device.\r | |
3941 | @param MTT The multi-TT of the hub device.\r | |
3942 | \r | |
3943 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
3944 | \r | |
3945 | **/\r | |
3946 | EFI_STATUS\r | |
3947 | XhcConfigHubContext64 (\r | |
3948 | IN USB_XHCI_INSTANCE *Xhc,\r | |
3949 | IN UINT8 SlotId,\r | |
3950 | IN UINT8 PortNum,\r | |
3951 | IN UINT8 TTT,\r | |
3952 | IN UINT8 MTT\r | |
3953 | )\r | |
3954 | {\r | |
3955 | EFI_STATUS Status;\r | |
6b4483cd | 3956 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r |
3957 | INPUT_CONTEXT_64 *InputContext;\r | |
3958 | DEVICE_CONTEXT_64 *OutputContext;\r | |
3959 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r | |
1847ed0b | 3960 | EFI_PHYSICAL_ADDRESS PhyAddr;\r |
6b4483cd | 3961 | \r |
3962 | ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r | |
3963 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
3964 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
3965 | \r | |
3966 | //\r | |
3967 | // 4.6.7 Evaluate Context\r | |
3968 | //\r | |
3969 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r | |
3970 | \r | |
3971 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
3972 | \r | |
3973 | //\r | |
3974 | // Copy the slot context from OutputContext to Input context\r | |
3975 | //\r | |
3976 | CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));\r | |
3977 | InputContext->Slot.Hub = 1;\r | |
3978 | InputContext->Slot.PortNum = PortNum;\r | |
3979 | InputContext->Slot.TTT = TTT;\r | |
3980 | InputContext->Slot.MTT = MTT;\r | |
3981 | \r | |
3982 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
1847ed0b EL |
3983 | PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));\r |
3984 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);\r | |
3985 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);\r | |
6b4483cd | 3986 | CmdTrbCfgEP.CycleBit = 1;\r |
3987 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
3988 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
3989 | DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r | |
3990 | Status = XhcCmdTransfer (\r | |
3991 | Xhc,\r | |
3992 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r | |
3993 | XHC_GENERIC_TIMEOUT,\r | |
3994 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
3995 | );\r | |
260fbf53 EL |
3996 | if (EFI_ERROR (Status)) {\r |
3997 | DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));\r | |
3998 | }\r | |
6b4483cd | 3999 | return Status;\r |
4000 | }\r | |
4001 | \r | |
4002 | \r |