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MdeModulePkg/PciBusDxe: Fix small memory leak in FreePciDevice
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.c
1 /** @file
2
3 XHCI transfer scheduling routines.
4
5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include "Xhci.h"
17
18 /**
19 Create a command transfer TRB to support XHCI command interfaces.
20
21 @param Xhc The XHCI Instance.
22 @param CmdTrb The cmd TRB to be executed.
23
24 @return Created URB or NULL.
25
26 **/
27 URB*
28 XhcCreateCmdTrb (
29 IN USB_XHCI_INSTANCE *Xhc,
30 IN TRB_TEMPLATE *CmdTrb
31 )
32 {
33 URB *Urb;
34
35 Urb = AllocateZeroPool (sizeof (URB));
36 if (Urb == NULL) {
37 return NULL;
38 }
39
40 Urb->Signature = XHC_URB_SIG;
41
42 Urb->Ring = &Xhc->CmdRing;
43 XhcSyncTrsRing (Xhc, Urb->Ring);
44 Urb->TrbNum = 1;
45 Urb->TrbStart = Urb->Ring->RingEnqueue;
46 CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
47 Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
48 Urb->TrbEnd = Urb->TrbStart;
49
50 return Urb;
51 }
52
53 /**
54 Execute a XHCI cmd TRB pointed by CmdTrb.
55
56 @param Xhc The XHCI Instance.
57 @param CmdTrb The cmd TRB to be executed.
58 @param Timeout Indicates the maximum time, in millisecond, which the
59 transfer is allowed to complete.
60 @param EvtTrb The event TRB corresponding to the cmd TRB.
61
62 @retval EFI_SUCCESS The transfer was completed successfully.
63 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
64 @retval EFI_TIMEOUT The transfer failed due to timeout.
65 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
66
67 **/
68 EFI_STATUS
69 EFIAPI
70 XhcCmdTransfer (
71 IN USB_XHCI_INSTANCE *Xhc,
72 IN TRB_TEMPLATE *CmdTrb,
73 IN UINTN Timeout,
74 OUT TRB_TEMPLATE **EvtTrb
75 )
76 {
77 EFI_STATUS Status;
78 URB *Urb;
79
80 //
81 // Validate the parameters
82 //
83 if ((Xhc == NULL) || (CmdTrb == NULL)) {
84 return EFI_INVALID_PARAMETER;
85 }
86
87 Status = EFI_DEVICE_ERROR;
88
89 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
90 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));
91 goto ON_EXIT;
92 }
93
94 //
95 // Create a new URB, then poll the execution status.
96 //
97 Urb = XhcCreateCmdTrb (Xhc, CmdTrb);
98
99 if (Urb == NULL) {
100 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));
101 Status = EFI_OUT_OF_RESOURCES;
102 goto ON_EXIT;
103 }
104
105 Status = XhcExecTransfer (Xhc, TRUE, Urb, Timeout);
106 *EvtTrb = Urb->EvtTrb;
107
108 if (Urb->Result == EFI_USB_NOERROR) {
109 Status = EFI_SUCCESS;
110 }
111
112 XhcFreeUrb (Xhc, Urb);
113
114 ON_EXIT:
115 return Status;
116 }
117
118 /**
119 Create a new URB for a new transaction.
120
121 @param Xhc The XHCI Instance
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
132
133 @return Created URB or NULL
134
135 **/
136 URB*
137 XhcCreateUrb (
138 IN USB_XHCI_INSTANCE *Xhc,
139 IN UINT8 BusAddr,
140 IN UINT8 EpAddr,
141 IN UINT8 DevSpeed,
142 IN UINTN MaxPacket,
143 IN UINTN Type,
144 IN EFI_USB_DEVICE_REQUEST *Request,
145 IN VOID *Data,
146 IN UINTN DataLen,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
148 IN VOID *Context
149 )
150 {
151 USB_ENDPOINT *Ep;
152 EFI_STATUS Status;
153 URB *Urb;
154
155 Urb = AllocateZeroPool (sizeof (URB));
156 if (Urb == NULL) {
157 return NULL;
158 }
159
160 Urb->Signature = XHC_URB_SIG;
161 InitializeListHead (&Urb->UrbList);
162
163 Ep = &Urb->Ep;
164 Ep->BusAddr = BusAddr;
165 Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
166 Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
167 Ep->DevSpeed = DevSpeed;
168 Ep->MaxPacket = MaxPacket;
169 Ep->Type = Type;
170
171 Urb->Request = Request;
172 Urb->Data = Data;
173 Urb->DataLen = DataLen;
174 Urb->Callback = Callback;
175 Urb->Context = Context;
176
177 Status = XhcCreateTransferTrb (Xhc, Urb);
178 ASSERT_EFI_ERROR (Status);
179 if (EFI_ERROR (Status)) {
180 DEBUG ((EFI_D_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
181 FreePool (Urb);
182 Urb = NULL;
183 }
184
185 return Urb;
186 }
187
188 /**
189 Free an allocated URB.
190
191 @param Xhc The XHCI device.
192 @param Urb The URB to free.
193
194 **/
195 VOID
196 XhcFreeUrb (
197 IN USB_XHCI_INSTANCE *Xhc,
198 IN URB *Urb
199 )
200 {
201 if ((Xhc == NULL) || (Urb == NULL)) {
202 return;
203 }
204
205 if (Urb->DataMap != NULL) {
206 Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
207 }
208
209 FreePool (Urb);
210 }
211
212 /**
213 Create a transfer TRB.
214
215 @param Xhc The XHCI Instance
216 @param Urb The urb used to construct the transfer TRB.
217
218 @return Created TRB or NULL
219
220 **/
221 EFI_STATUS
222 XhcCreateTransferTrb (
223 IN USB_XHCI_INSTANCE *Xhc,
224 IN URB *Urb
225 )
226 {
227 VOID *OutputContext;
228 TRANSFER_RING *EPRing;
229 UINT8 EPType;
230 UINT8 SlotId;
231 UINT8 Dci;
232 TRB *TrbStart;
233 UINTN TotalLen;
234 UINTN Len;
235 UINTN TrbNum;
236 EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
237 EFI_PHYSICAL_ADDRESS PhyAddr;
238 VOID *Map;
239 EFI_STATUS Status;
240
241 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
242 if (SlotId == 0) {
243 return EFI_DEVICE_ERROR;
244 }
245
246 Urb->Finished = FALSE;
247 Urb->StartDone = FALSE;
248 Urb->EndDone = FALSE;
249 Urb->Completed = 0;
250 Urb->Result = EFI_USB_NOERROR;
251
252 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
253 ASSERT (Dci < 32);
254 EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
255 Urb->Ring = EPRing;
256 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
257 if (Xhc->HcCParams.Data.Csz == 0) {
258 EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
259 } else {
260 EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
261 }
262
263 //
264 // No need to remap.
265 //
266 if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
267 if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
268 MapOp = EfiPciIoOperationBusMasterWrite;
269 } else {
270 MapOp = EfiPciIoOperationBusMasterRead;
271 }
272
273 Len = Urb->DataLen;
274 Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
275
276 if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
277 DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
278 return EFI_OUT_OF_RESOURCES;
279 }
280
281 Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
282 Urb->DataMap = Map;
283 }
284
285 //
286 // Construct the TRB
287 //
288 XhcSyncTrsRing (Xhc, EPRing);
289 Urb->TrbStart = EPRing->RingEnqueue;
290 switch (EPType) {
291 case ED_CONTROL_BIDIR:
292 //
293 // For control transfer, create SETUP_STAGE_TRB first.
294 //
295 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
296 TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
297 TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
298 TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
299 TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;
300 TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;
301 TrbStart->TrbCtrSetup.Length = 8;
302 TrbStart->TrbCtrSetup.IntTarget = 0;
303 TrbStart->TrbCtrSetup.IOC = 1;
304 TrbStart->TrbCtrSetup.IDT = 1;
305 TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;
306 if (Urb->Ep.Direction == EfiUsbDataIn) {
307 TrbStart->TrbCtrSetup.TRT = 3;
308 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
309 TrbStart->TrbCtrSetup.TRT = 2;
310 } else {
311 TrbStart->TrbCtrSetup.TRT = 0;
312 }
313 //
314 // Update the cycle bit
315 //
316 TrbStart->TrbCtrSetup.CycleBit = EPRing->RingPCS & BIT0;
317 Urb->TrbNum++;
318
319 //
320 // For control transfer, create DATA_STAGE_TRB.
321 //
322 if (Urb->DataLen > 0) {
323 XhcSyncTrsRing (Xhc, EPRing);
324 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
325 TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
326 TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
327 TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
328 TrbStart->TrbCtrData.TDSize = 0;
329 TrbStart->TrbCtrData.IntTarget = 0;
330 TrbStart->TrbCtrData.ISP = 1;
331 TrbStart->TrbCtrData.IOC = 1;
332 TrbStart->TrbCtrData.IDT = 0;
333 TrbStart->TrbCtrData.CH = 0;
334 TrbStart->TrbCtrData.Type = TRB_TYPE_DATA_STAGE;
335 if (Urb->Ep.Direction == EfiUsbDataIn) {
336 TrbStart->TrbCtrData.DIR = 1;
337 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
338 TrbStart->TrbCtrData.DIR = 0;
339 } else {
340 TrbStart->TrbCtrData.DIR = 0;
341 }
342 //
343 // Update the cycle bit
344 //
345 TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
346 Urb->TrbNum++;
347 }
348 //
349 // For control transfer, create STATUS_STAGE_TRB.
350 // Get the pointer to next TRB for status stage use
351 //
352 XhcSyncTrsRing (Xhc, EPRing);
353 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
354 TrbStart->TrbCtrStatus.IntTarget = 0;
355 TrbStart->TrbCtrStatus.IOC = 1;
356 TrbStart->TrbCtrStatus.CH = 0;
357 TrbStart->TrbCtrStatus.Type = TRB_TYPE_STATUS_STAGE;
358 if (Urb->Ep.Direction == EfiUsbDataIn) {
359 TrbStart->TrbCtrStatus.DIR = 0;
360 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
361 TrbStart->TrbCtrStatus.DIR = 1;
362 } else {
363 TrbStart->TrbCtrStatus.DIR = 0;
364 }
365 //
366 // Update the cycle bit
367 //
368 TrbStart->TrbCtrStatus.CycleBit = EPRing->RingPCS & BIT0;
369 //
370 // Update the enqueue pointer
371 //
372 XhcSyncTrsRing (Xhc, EPRing);
373 Urb->TrbNum++;
374 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
375
376 break;
377
378 case ED_BULK_OUT:
379 case ED_BULK_IN:
380 TotalLen = 0;
381 Len = 0;
382 TrbNum = 0;
383 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
384 while (TotalLen < Urb->DataLen) {
385 if ((TotalLen + 0x10000) >= Urb->DataLen) {
386 Len = Urb->DataLen - TotalLen;
387 } else {
388 Len = 0x10000;
389 }
390 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
391 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
392 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
393 TrbStart->TrbNormal.Length = (UINT32) Len;
394 TrbStart->TrbNormal.TDSize = 0;
395 TrbStart->TrbNormal.IntTarget = 0;
396 TrbStart->TrbNormal.ISP = 1;
397 TrbStart->TrbNormal.IOC = 1;
398 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;
399 //
400 // Update the cycle bit
401 //
402 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
403
404 XhcSyncTrsRing (Xhc, EPRing);
405 TrbNum++;
406 TotalLen += Len;
407 }
408
409 Urb->TrbNum = TrbNum;
410 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
411 break;
412
413 case ED_INTERRUPT_OUT:
414 case ED_INTERRUPT_IN:
415 TotalLen = 0;
416 Len = 0;
417 TrbNum = 0;
418 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
419 while (TotalLen < Urb->DataLen) {
420 if ((TotalLen + 0x10000) >= Urb->DataLen) {
421 Len = Urb->DataLen - TotalLen;
422 } else {
423 Len = 0x10000;
424 }
425 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
426 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
427 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
428 TrbStart->TrbNormal.Length = (UINT32) Len;
429 TrbStart->TrbNormal.TDSize = 0;
430 TrbStart->TrbNormal.IntTarget = 0;
431 TrbStart->TrbNormal.ISP = 1;
432 TrbStart->TrbNormal.IOC = 1;
433 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;
434 //
435 // Update the cycle bit
436 //
437 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
438
439 XhcSyncTrsRing (Xhc, EPRing);
440 TrbNum++;
441 TotalLen += Len;
442 }
443
444 Urb->TrbNum = TrbNum;
445 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
446 break;
447
448 default:
449 DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
450 ASSERT (FALSE);
451 break;
452 }
453
454 return EFI_SUCCESS;
455 }
456
457
458 /**
459 Initialize the XHCI host controller for schedule.
460
461 @param Xhc The XHCI Instance to be initialized.
462
463 **/
464 VOID
465 XhcInitSched (
466 IN USB_XHCI_INSTANCE *Xhc
467 )
468 {
469 VOID *Dcbaa;
470 EFI_PHYSICAL_ADDRESS DcbaaPhy;
471 UINT64 CmdRing;
472 EFI_PHYSICAL_ADDRESS CmdRingPhy;
473 UINTN Entries;
474 UINT32 MaxScratchpadBufs;
475 UINT64 *ScratchBuf;
476 EFI_PHYSICAL_ADDRESS ScratchPhy;
477 UINT64 *ScratchEntry;
478 EFI_PHYSICAL_ADDRESS ScratchEntryPhy;
479 UINT32 Index;
480 UINTN *ScratchEntryMap;
481 EFI_STATUS Status;
482
483 //
484 // Initialize memory management.
485 //
486 Xhc->MemPool = UsbHcInitMemPool (Xhc->PciIo);
487 ASSERT (Xhc->MemPool != NULL);
488
489 //
490 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
491 // to enable the device slots that system software is going to use.
492 //
493 Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;
494 ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);
495 XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);
496
497 //
498 // The Device Context Base Address Array entry associated with each allocated Device Slot
499 // shall contain a 64-bit pointer to the base of the associated Device Context.
500 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
501 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
502 //
503 Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
504 Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
505 ASSERT (Dcbaa != NULL);
506 ZeroMem (Dcbaa, Entries);
507
508 //
509 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
510 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
511 // mode (Run/Stop(R/S) ='1').
512 //
513 MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);
514 Xhc->MaxScratchpadBufs = MaxScratchpadBufs;
515 ASSERT (MaxScratchpadBufs <= 1023);
516 if (MaxScratchpadBufs != 0) {
517 //
518 // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
519 //
520 ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);
521 ASSERT (ScratchEntryMap != NULL);
522 Xhc->ScratchEntryMap = ScratchEntryMap;
523
524 //
525 // Allocate the buffer to record the host address for each entry
526 //
527 ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);
528 ASSERT (ScratchEntry != NULL);
529 Xhc->ScratchEntry = ScratchEntry;
530
531 ScratchPhy = 0;
532 Status = UsbHcAllocateAlignedPages (
533 Xhc->PciIo,
534 EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
535 Xhc->PageSize,
536 (VOID **) &ScratchBuf,
537 &ScratchPhy,
538 &Xhc->ScratchMap
539 );
540 ASSERT_EFI_ERROR (Status);
541
542 ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
543 Xhc->ScratchBuf = ScratchBuf;
544
545 //
546 // Allocate each scratch buffer
547 //
548 for (Index = 0; Index < MaxScratchpadBufs; Index++) {
549 ScratchEntryPhy = 0;
550 Status = UsbHcAllocateAlignedPages (
551 Xhc->PciIo,
552 EFI_SIZE_TO_PAGES (Xhc->PageSize),
553 Xhc->PageSize,
554 (VOID **) &ScratchEntry[Index],
555 &ScratchEntryPhy,
556 (VOID **) &ScratchEntryMap[Index]
557 );
558 ASSERT_EFI_ERROR (Status);
559 ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
560 //
561 // Fill with the PCI device address
562 //
563 *ScratchBuf++ = ScratchEntryPhy;
564 }
565 //
566 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
567 // Device Context Base Address Array points to the Scratchpad Buffer Array.
568 //
569 *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;
570 }
571
572 //
573 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
574 // a 64-bit address pointing to where the Device Context Base Address Array is located.
575 //
576 Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;
577 //
578 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
579 // So divide it to two 32-bytes width register access.
580 //
581 DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
582 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
583 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
584
585 DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
586
587 //
588 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
589 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
590 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
591 // always be '0'.
592 //
593 CreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);
594 //
595 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
596 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
597 // So we set RCS as inverted PCS init value to let Command Ring empty
598 //
599 CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
600 CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
601 ASSERT ((CmdRingPhy & 0x3F) == 0);
602 CmdRingPhy |= XHC_CRCR_RCS;
603 //
604 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
605 // So divide it to two 32-bytes width register access.
606 //
607 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
608 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
609
610 //
611 // Disable the 'interrupter enable' bit in USB_CMD
612 // and clear IE & IP bit in all Interrupter X Management Registers.
613 //
614 XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);
615 for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {
616 XhcClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);
617 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);
618 }
619
620 //
621 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
622 //
623 CreateEventRing (Xhc, &Xhc->EventRing);
624 DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
625 Xhc->CmdRing.RingSeg0, (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
626 Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
627 ));
628 }
629
630 /**
631 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
632 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
633 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
634 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
635 Stopped to the Running state.
636
637 @param Xhc The XHCI Instance.
638 @param Urb The urb which makes the endpoint halted.
639
640 @retval EFI_SUCCESS The recovery is successful.
641 @retval Others Failed to recovery halted endpoint.
642
643 **/
644 EFI_STATUS
645 EFIAPI
646 XhcRecoverHaltedEndpoint (
647 IN USB_XHCI_INSTANCE *Xhc,
648 IN URB *Urb
649 )
650 {
651 EFI_STATUS Status;
652 UINT8 Dci;
653 UINT8 SlotId;
654
655 Status = EFI_SUCCESS;
656 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
657 if (SlotId == 0) {
658 return EFI_DEVICE_ERROR;
659 }
660 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
661 ASSERT (Dci < 32);
662
663 DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
664
665 //
666 // 1) Send Reset endpoint command to transit from halt to stop state
667 //
668 Status = XhcResetEndpoint(Xhc, SlotId, Dci);
669 if (EFI_ERROR(Status)) {
670 DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
671 goto Done;
672 }
673
674 //
675 // 2)Set dequeue pointer
676 //
677 Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
678 if (EFI_ERROR(Status)) {
679 DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
680 goto Done;
681 }
682
683 //
684 // 3)Ring the doorbell to transit from stop to active
685 //
686 XhcRingDoorBell (Xhc, SlotId, Dci);
687
688 Done:
689 return Status;
690 }
691
692 /**
693 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
694 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
695 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
696 state.
697
698 @param Xhc The XHCI Instance.
699 @param Urb The urb which doesn't get completed in a specified timeout range.
700
701 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
702 @retval EFI_ALREADY_STARTED The Urb is finished so no deque is needed.
703 @retval Others Failed to stop the endpoint and dequeue the TDs.
704
705 **/
706 EFI_STATUS
707 EFIAPI
708 XhcDequeueTrbFromEndpoint (
709 IN USB_XHCI_INSTANCE *Xhc,
710 IN URB *Urb
711 )
712 {
713 EFI_STATUS Status;
714 UINT8 Dci;
715 UINT8 SlotId;
716
717 Status = EFI_SUCCESS;
718 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
719 if (SlotId == 0) {
720 return EFI_DEVICE_ERROR;
721 }
722 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
723 ASSERT (Dci < 32);
724
725 DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
726
727 //
728 // 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
729 //
730 Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);
731 if (EFI_ERROR(Status)) {
732 DEBUG ((EFI_D_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
733 goto Done;
734 }
735
736 //
737 // 2)Set dequeue pointer
738 //
739 if (Urb->Finished && Urb->Result == EFI_USB_NOERROR) {
740 //
741 // Return Already Started to indicate the pending URB is finished.
742 // This fixes BULK data loss when transfer is detected as timeout
743 // but finished just before stopping endpoint.
744 //
745 Status = EFI_ALREADY_STARTED;
746 DEBUG ((DEBUG_INFO, "XhcDequeueTrbFromEndpoint: Pending URB is finished: Length Actual/Expect = %d/%d!\n", Urb->Completed, Urb->DataLen));
747 } else {
748 Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
749 if (EFI_ERROR (Status)) {
750 DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
751 goto Done;
752 }
753 }
754
755 //
756 // 3)Ring the doorbell to transit from stop to active
757 //
758 XhcRingDoorBell (Xhc, SlotId, Dci);
759
760 Done:
761 return Status;
762 }
763
764 /**
765 Create XHCI event ring.
766
767 @param Xhc The XHCI Instance.
768 @param EventRing The created event ring.
769
770 **/
771 VOID
772 CreateEventRing (
773 IN USB_XHCI_INSTANCE *Xhc,
774 OUT EVENT_RING *EventRing
775 )
776 {
777 VOID *Buf;
778 EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
779 UINTN Size;
780 EFI_PHYSICAL_ADDRESS ERSTPhy;
781 EFI_PHYSICAL_ADDRESS DequeuePhy;
782
783 ASSERT (EventRing != NULL);
784
785 Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
786 Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
787 ASSERT (Buf != NULL);
788 ASSERT (((UINTN) Buf & 0x3F) == 0);
789 ZeroMem (Buf, Size);
790
791 EventRing->EventRingSeg0 = Buf;
792 EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
793 EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
794 EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
795
796 DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
797
798 //
799 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
800 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
801 //
802 EventRing->EventRingCCS = 1;
803
804 Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
805 Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
806 ASSERT (Buf != NULL);
807 ASSERT (((UINTN) Buf & 0x3F) == 0);
808 ZeroMem (Buf, Size);
809
810 ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
811 EventRing->ERSTBase = ERSTBase;
812 ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
813 ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
814 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
815
816 ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);
817
818 //
819 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
820 //
821 XhcWriteRuntimeReg (
822 Xhc,
823 XHC_ERSTSZ_OFFSET,
824 ERST_NUMBER
825 );
826 //
827 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
828 //
829 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
830 // So divide it to two 32-bytes width register access.
831 //
832 XhcWriteRuntimeReg (
833 Xhc,
834 XHC_ERDP_OFFSET,
835 XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)
836 );
837 XhcWriteRuntimeReg (
838 Xhc,
839 XHC_ERDP_OFFSET + 4,
840 XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)
841 );
842 //
843 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
844 //
845 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
846 // So divide it to two 32-bytes width register access.
847 //
848 XhcWriteRuntimeReg (
849 Xhc,
850 XHC_ERSTBA_OFFSET,
851 XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)
852 );
853 XhcWriteRuntimeReg (
854 Xhc,
855 XHC_ERSTBA_OFFSET + 4,
856 XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)
857 );
858 //
859 // Need set IMAN IE bit to enble the ring interrupt
860 //
861 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET, XHC_IMAN_IE);
862 }
863
864 /**
865 Create XHCI transfer ring.
866
867 @param Xhc The XHCI Instance.
868 @param TrbNum The number of TRB in the ring.
869 @param TransferRing The created transfer ring.
870
871 **/
872 VOID
873 CreateTransferRing (
874 IN USB_XHCI_INSTANCE *Xhc,
875 IN UINTN TrbNum,
876 OUT TRANSFER_RING *TransferRing
877 )
878 {
879 VOID *Buf;
880 LINK_TRB *EndTrb;
881 EFI_PHYSICAL_ADDRESS PhyAddr;
882
883 Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
884 ASSERT (Buf != NULL);
885 ASSERT (((UINTN) Buf & 0x3F) == 0);
886 ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
887
888 TransferRing->RingSeg0 = Buf;
889 TransferRing->TrbNumber = TrbNum;
890 TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
891 TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
892 TransferRing->RingPCS = 1;
893 //
894 // 4.9.2 Transfer Ring Management
895 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
896 // point to the first TRB in the ring.
897 //
898 EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
899 EndTrb->Type = TRB_TYPE_LINK;
900 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
901 EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
902 EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
903 //
904 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
905 //
906 EndTrb->TC = 1;
907 //
908 // Set Cycle bit as other TRB PCS init value
909 //
910 EndTrb->CycleBit = 0;
911 }
912
913 /**
914 Free XHCI event ring.
915
916 @param Xhc The XHCI Instance.
917 @param EventRing The event ring to be freed.
918
919 **/
920 EFI_STATUS
921 EFIAPI
922 XhcFreeEventRing (
923 IN USB_XHCI_INSTANCE *Xhc,
924 IN EVENT_RING *EventRing
925 )
926 {
927 if(EventRing->EventRingSeg0 == NULL) {
928 return EFI_SUCCESS;
929 }
930
931 //
932 // Free EventRing Segment 0
933 //
934 UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
935
936 //
937 // Free ESRT table
938 //
939 UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
940 return EFI_SUCCESS;
941 }
942
943 /**
944 Free the resouce allocated at initializing schedule.
945
946 @param Xhc The XHCI Instance.
947
948 **/
949 VOID
950 XhcFreeSched (
951 IN USB_XHCI_INSTANCE *Xhc
952 )
953 {
954 UINT32 Index;
955 UINT64 *ScratchEntry;
956
957 if (Xhc->ScratchBuf != NULL) {
958 ScratchEntry = Xhc->ScratchEntry;
959 for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
960 //
961 // Free Scratchpad Buffers
962 //
963 UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
964 }
965 //
966 // Free Scratchpad Buffer Array
967 //
968 UsbHcFreeAlignedPages (Xhc->PciIo, Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);
969 FreePool (Xhc->ScratchEntryMap);
970 FreePool (Xhc->ScratchEntry);
971 }
972
973 if (Xhc->CmdRing.RingSeg0 != NULL) {
974 UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
975 Xhc->CmdRing.RingSeg0 = NULL;
976 }
977
978 XhcFreeEventRing (Xhc,&Xhc->EventRing);
979
980 if (Xhc->DCBAA != NULL) {
981 UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
982 Xhc->DCBAA = NULL;
983 }
984
985 //
986 // Free memory pool at last
987 //
988 if (Xhc->MemPool != NULL) {
989 UsbHcFreeMemPool (Xhc->MemPool);
990 Xhc->MemPool = NULL;
991 }
992 }
993
994 /**
995 Check if the Trb is a transaction of the URB.
996
997 @param Xhc The XHCI Instance.
998 @param Trb The TRB to be checked
999 @param Urb The URB to be checked.
1000
1001 @retval TRUE It is a transaction of the URB.
1002 @retval FALSE It is not any transaction of the URB.
1003
1004 **/
1005 BOOLEAN
1006 IsTransferRingTrb (
1007 IN USB_XHCI_INSTANCE *Xhc,
1008 IN TRB_TEMPLATE *Trb,
1009 IN URB *Urb
1010 )
1011 {
1012 LINK_TRB *LinkTrb;
1013 TRB_TEMPLATE *CheckedTrb;
1014 UINTN Index;
1015 EFI_PHYSICAL_ADDRESS PhyAddr;
1016
1017 CheckedTrb = Urb->TrbStart;
1018 for (Index = 0; Index < Urb->TrbNum; Index++) {
1019 if (Trb == CheckedTrb) {
1020 return TRUE;
1021 }
1022 CheckedTrb++;
1023 //
1024 // If the checked TRB is the link TRB at the end of the transfer ring,
1025 // recircle it to the head of the ring.
1026 //
1027 if (CheckedTrb->Type == TRB_TYPE_LINK) {
1028 LinkTrb = (LINK_TRB *) CheckedTrb;
1029 PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32));
1030 CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
1031 ASSERT (CheckedTrb == Urb->Ring->RingSeg0);
1032 }
1033 }
1034
1035 return FALSE;
1036 }
1037
1038 /**
1039 Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
1040
1041 @param Xhc The XHCI Instance.
1042 @param Trb The TRB to be checked.
1043 @param Urb The pointer to the matched Urb.
1044
1045 @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
1046 @retval FALSE The Trb is not matched with any URBs in the async list.
1047
1048 **/
1049 BOOLEAN
1050 IsAsyncIntTrb (
1051 IN USB_XHCI_INSTANCE *Xhc,
1052 IN TRB_TEMPLATE *Trb,
1053 OUT URB **Urb
1054 )
1055 {
1056 LIST_ENTRY *Entry;
1057 LIST_ENTRY *Next;
1058 URB *CheckedUrb;
1059
1060 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1061 CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1062 if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {
1063 *Urb = CheckedUrb;
1064 return TRUE;
1065 }
1066 }
1067
1068 return FALSE;
1069 }
1070
1071
1072 /**
1073 Check the URB's execution result and update the URB's
1074 result accordingly.
1075
1076 @param Xhc The XHCI Instance.
1077 @param Urb The URB to check result.
1078
1079 @return Whether the result of URB transfer is finialized.
1080
1081 **/
1082 BOOLEAN
1083 XhcCheckUrbResult (
1084 IN USB_XHCI_INSTANCE *Xhc,
1085 IN URB *Urb
1086 )
1087 {
1088 EVT_TRB_TRANSFER *EvtTrb;
1089 TRB_TEMPLATE *TRBPtr;
1090 UINTN Index;
1091 UINT8 TRBType;
1092 EFI_STATUS Status;
1093 URB *AsyncUrb;
1094 URB *CheckedUrb;
1095 UINT64 XhcDequeue;
1096 UINT32 High;
1097 UINT32 Low;
1098 EFI_PHYSICAL_ADDRESS PhyAddr;
1099
1100 ASSERT ((Xhc != NULL) && (Urb != NULL));
1101
1102 Status = EFI_SUCCESS;
1103 AsyncUrb = NULL;
1104
1105 if (Urb->Finished) {
1106 goto EXIT;
1107 }
1108
1109 EvtTrb = NULL;
1110
1111 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
1112 Urb->Result |= EFI_USB_ERR_SYSTEM;
1113 goto EXIT;
1114 }
1115
1116 //
1117 // Traverse the event ring to find out all new events from the previous check.
1118 //
1119 XhcSyncEventRing (Xhc, &Xhc->EventRing);
1120 for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {
1121 Status = XhcCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
1122 if (Status == EFI_NOT_READY) {
1123 //
1124 // All new events are handled, return directly.
1125 //
1126 goto EXIT;
1127 }
1128
1129 //
1130 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
1131 //
1132 if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
1133 continue;
1134 }
1135
1136 //
1137 // Need convert pci device address to host address
1138 //
1139 PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
1140 TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
1141
1142 //
1143 // Update the status of URB including the pending URB, the URB that is currently checked,
1144 // and URBs in the XHCI's async interrupt transfer list.
1145 // This way is used to avoid that those completed async transfer events don't get
1146 // handled in time and are flushed by newer coming events.
1147 //
1148 if (Xhc->PendingUrb != NULL && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
1149 CheckedUrb = Xhc->PendingUrb;
1150 } else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {
1151 CheckedUrb = Urb;
1152 } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {
1153 CheckedUrb = AsyncUrb;
1154 } else {
1155 continue;
1156 }
1157
1158 switch (EvtTrb->Completecode) {
1159 case TRB_COMPLETION_STALL_ERROR:
1160 CheckedUrb->Result |= EFI_USB_ERR_STALL;
1161 CheckedUrb->Finished = TRUE;
1162 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1163 goto EXIT;
1164
1165 case TRB_COMPLETION_BABBLE_ERROR:
1166 CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
1167 CheckedUrb->Finished = TRUE;
1168 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1169 goto EXIT;
1170
1171 case TRB_COMPLETION_DATA_BUFFER_ERROR:
1172 CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
1173 CheckedUrb->Finished = TRUE;
1174 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
1175 goto EXIT;
1176
1177 case TRB_COMPLETION_USB_TRANSACTION_ERROR:
1178 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1179 CheckedUrb->Finished = TRUE;
1180 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1181 goto EXIT;
1182
1183 case TRB_COMPLETION_STOPPED:
1184 case TRB_COMPLETION_STOPPED_LENGTH_INVALID:
1185 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1186 CheckedUrb->Finished = TRUE;
1187 //
1188 // The pending URB is timeout and force stopped when stopping endpoint.
1189 // Continue the loop to receive the Command Complete Event for stopping endpoint.
1190 //
1191 continue;
1192
1193 case TRB_COMPLETION_SHORT_PACKET:
1194 case TRB_COMPLETION_SUCCESS:
1195 if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
1196 DEBUG ((EFI_D_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
1197 }
1198
1199 TRBType = (UINT8) (TRBPtr->Type);
1200 if ((TRBType == TRB_TYPE_DATA_STAGE) ||
1201 (TRBType == TRB_TYPE_NORMAL) ||
1202 (TRBType == TRB_TYPE_ISOCH)) {
1203 CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
1204 }
1205
1206 break;
1207
1208 default:
1209 DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
1210 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1211 CheckedUrb->Finished = TRUE;
1212 goto EXIT;
1213 }
1214
1215 //
1216 // Only check first and end Trb event address
1217 //
1218 if (TRBPtr == CheckedUrb->TrbStart) {
1219 CheckedUrb->StartDone = TRUE;
1220 }
1221
1222 if (TRBPtr == CheckedUrb->TrbEnd) {
1223 CheckedUrb->EndDone = TRUE;
1224 }
1225
1226 if (CheckedUrb->StartDone && CheckedUrb->EndDone) {
1227 CheckedUrb->Finished = TRUE;
1228 CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;
1229 }
1230 }
1231
1232 EXIT:
1233
1234 //
1235 // Advance event ring to last available entry
1236 //
1237 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1238 // So divide it to two 32-bytes width register access.
1239 //
1240 Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
1241 High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
1242 XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
1243
1244 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
1245
1246 if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {
1247 //
1248 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1249 // So divide it to two 32-bytes width register access.
1250 //
1251 XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);
1252 XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));
1253 }
1254
1255 return Urb->Finished;
1256 }
1257
1258
1259 /**
1260 Execute the transfer by polling the URB. This is a synchronous operation.
1261
1262 @param Xhc The XHCI Instance.
1263 @param CmdTransfer The executed URB is for cmd transfer or not.
1264 @param Urb The URB to execute.
1265 @param Timeout The time to wait before abort, in millisecond.
1266
1267 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1268 @return EFI_TIMEOUT The transfer failed due to time out.
1269 @return EFI_SUCCESS The transfer finished OK.
1270
1271 **/
1272 EFI_STATUS
1273 XhcExecTransfer (
1274 IN USB_XHCI_INSTANCE *Xhc,
1275 IN BOOLEAN CmdTransfer,
1276 IN URB *Urb,
1277 IN UINTN Timeout
1278 )
1279 {
1280 EFI_STATUS Status;
1281 UINTN Index;
1282 UINT64 Loop;
1283 UINT8 SlotId;
1284 UINT8 Dci;
1285 BOOLEAN Finished;
1286
1287 if (CmdTransfer) {
1288 SlotId = 0;
1289 Dci = 0;
1290 } else {
1291 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1292 if (SlotId == 0) {
1293 return EFI_DEVICE_ERROR;
1294 }
1295 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1296 ASSERT (Dci < 32);
1297 }
1298
1299 Status = EFI_SUCCESS;
1300 Loop = Timeout * XHC_1_MILLISECOND;
1301 if (Timeout == 0) {
1302 Loop = 0xFFFFFFFF;
1303 }
1304
1305 XhcRingDoorBell (Xhc, SlotId, Dci);
1306
1307 for (Index = 0; Index < Loop; Index++) {
1308 Finished = XhcCheckUrbResult (Xhc, Urb);
1309 if (Finished) {
1310 break;
1311 }
1312 gBS->Stall (XHC_1_MICROSECOND);
1313 }
1314
1315 if (Index == Loop) {
1316 Urb->Result = EFI_USB_ERR_TIMEOUT;
1317 Status = EFI_TIMEOUT;
1318 } else if (Urb->Result != EFI_USB_NOERROR) {
1319 Status = EFI_DEVICE_ERROR;
1320 }
1321
1322 return Status;
1323 }
1324
1325 /**
1326 Delete a single asynchronous interrupt transfer for
1327 the device and endpoint.
1328
1329 @param Xhc The XHCI Instance.
1330 @param BusAddr The logical device address assigned by UsbBus driver.
1331 @param EpNum The endpoint of the target.
1332
1333 @retval EFI_SUCCESS An asynchronous transfer is removed.
1334 @retval EFI_NOT_FOUND No transfer for the device is found.
1335
1336 **/
1337 EFI_STATUS
1338 XhciDelAsyncIntTransfer (
1339 IN USB_XHCI_INSTANCE *Xhc,
1340 IN UINT8 BusAddr,
1341 IN UINT8 EpNum
1342 )
1343 {
1344 LIST_ENTRY *Entry;
1345 LIST_ENTRY *Next;
1346 URB *Urb;
1347 EFI_USB_DATA_DIRECTION Direction;
1348 EFI_STATUS Status;
1349
1350 Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
1351 EpNum &= 0x0F;
1352
1353 Urb = NULL;
1354
1355 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1356 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1357 if ((Urb->Ep.BusAddr == BusAddr) &&
1358 (Urb->Ep.EpAddr == EpNum) &&
1359 (Urb->Ep.Direction == Direction)) {
1360 //
1361 // Device doesn't finish the IntTransfer until real data comes
1362 // So the TRB should be removed as well.
1363 //
1364 Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
1365 if (EFI_ERROR (Status)) {
1366 DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
1367 }
1368
1369 RemoveEntryList (&Urb->UrbList);
1370 FreePool (Urb->Data);
1371 XhcFreeUrb (Xhc, Urb);
1372 return EFI_SUCCESS;
1373 }
1374 }
1375
1376 return EFI_NOT_FOUND;
1377 }
1378
1379 /**
1380 Remove all the asynchronous interrutp transfers.
1381
1382 @param Xhc The XHCI Instance.
1383
1384 **/
1385 VOID
1386 XhciDelAllAsyncIntTransfers (
1387 IN USB_XHCI_INSTANCE *Xhc
1388 )
1389 {
1390 LIST_ENTRY *Entry;
1391 LIST_ENTRY *Next;
1392 URB *Urb;
1393 EFI_STATUS Status;
1394
1395 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1396 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1397
1398 //
1399 // Device doesn't finish the IntTransfer until real data comes
1400 // So the TRB should be removed as well.
1401 //
1402 Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
1403 if (EFI_ERROR (Status)) {
1404 DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
1405 }
1406
1407 RemoveEntryList (&Urb->UrbList);
1408 FreePool (Urb->Data);
1409 XhcFreeUrb (Xhc, Urb);
1410 }
1411 }
1412
1413 /**
1414 Update the queue head for next round of asynchronous transfer
1415
1416 @param Xhc The XHCI Instance.
1417 @param Urb The URB to update
1418
1419 **/
1420 VOID
1421 XhcUpdateAsyncRequest (
1422 IN USB_XHCI_INSTANCE *Xhc,
1423 IN URB *Urb
1424 )
1425 {
1426 EFI_STATUS Status;
1427
1428 if (Urb->Result == EFI_USB_NOERROR) {
1429 Status = XhcCreateTransferTrb (Xhc, Urb);
1430 if (EFI_ERROR (Status)) {
1431 return;
1432 }
1433 Status = RingIntTransferDoorBell (Xhc, Urb);
1434 if (EFI_ERROR (Status)) {
1435 return;
1436 }
1437 }
1438 }
1439
1440 /**
1441 Flush data from PCI controller specific address to mapped system
1442 memory address.
1443
1444 @param Xhc The XHCI device.
1445 @param Urb The URB to unmap.
1446
1447 @retval EFI_SUCCESS Success to flush data to mapped system memory.
1448 @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.
1449
1450 **/
1451 EFI_STATUS
1452 XhcFlushAsyncIntMap (
1453 IN USB_XHCI_INSTANCE *Xhc,
1454 IN URB *Urb
1455 )
1456 {
1457 EFI_STATUS Status;
1458 EFI_PHYSICAL_ADDRESS PhyAddr;
1459 EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
1460 EFI_PCI_IO_PROTOCOL *PciIo;
1461 UINTN Len;
1462 VOID *Map;
1463
1464 PciIo = Xhc->PciIo;
1465 Len = Urb->DataLen;
1466
1467 if (Urb->Ep.Direction == EfiUsbDataIn) {
1468 MapOp = EfiPciIoOperationBusMasterWrite;
1469 } else {
1470 MapOp = EfiPciIoOperationBusMasterRead;
1471 }
1472
1473 if (Urb->DataMap != NULL) {
1474 Status = PciIo->Unmap (PciIo, Urb->DataMap);
1475 if (EFI_ERROR (Status)) {
1476 goto ON_ERROR;
1477 }
1478 }
1479
1480 Urb->DataMap = NULL;
1481
1482 Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
1483 if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
1484 goto ON_ERROR;
1485 }
1486
1487 Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
1488 Urb->DataMap = Map;
1489 return EFI_SUCCESS;
1490
1491 ON_ERROR:
1492 return EFI_DEVICE_ERROR;
1493 }
1494
1495 /**
1496 Interrupt transfer periodic check handler.
1497
1498 @param Event Interrupt event.
1499 @param Context Pointer to USB_XHCI_INSTANCE.
1500
1501 **/
1502 VOID
1503 EFIAPI
1504 XhcMonitorAsyncRequests (
1505 IN EFI_EVENT Event,
1506 IN VOID *Context
1507 )
1508 {
1509 USB_XHCI_INSTANCE *Xhc;
1510 LIST_ENTRY *Entry;
1511 LIST_ENTRY *Next;
1512 UINT8 *ProcBuf;
1513 URB *Urb;
1514 UINT8 SlotId;
1515 EFI_STATUS Status;
1516 EFI_TPL OldTpl;
1517
1518 OldTpl = gBS->RaiseTPL (XHC_TPL);
1519
1520 Xhc = (USB_XHCI_INSTANCE*) Context;
1521
1522 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1523 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1524
1525 //
1526 // Make sure that the device is available before every check.
1527 //
1528 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1529 if (SlotId == 0) {
1530 continue;
1531 }
1532
1533 //
1534 // Check the result of URB execution. If it is still
1535 // active, check the next one.
1536 //
1537 XhcCheckUrbResult (Xhc, Urb);
1538
1539 if (!Urb->Finished) {
1540 continue;
1541 }
1542
1543 //
1544 // Flush any PCI posted write transactions from a PCI host
1545 // bridge to system memory.
1546 //
1547 Status = XhcFlushAsyncIntMap (Xhc, Urb);
1548 if (EFI_ERROR (Status)) {
1549 DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
1550 }
1551
1552 //
1553 // Allocate a buffer then copy the transferred data for user.
1554 // If failed to allocate the buffer, update the URB for next
1555 // round of transfer. Ignore the data of this round.
1556 //
1557 ProcBuf = NULL;
1558 if (Urb->Result == EFI_USB_NOERROR) {
1559 ASSERT (Urb->Completed <= Urb->DataLen);
1560
1561 ProcBuf = AllocateZeroPool (Urb->Completed);
1562
1563 if (ProcBuf == NULL) {
1564 XhcUpdateAsyncRequest (Xhc, Urb);
1565 continue;
1566 }
1567
1568 CopyMem (ProcBuf, Urb->Data, Urb->Completed);
1569 }
1570
1571 //
1572 // Leave error recovery to its related device driver. A
1573 // common case of the error recovery is to re-submit the
1574 // interrupt transfer which is linked to the head of the
1575 // list. This function scans from head to tail. So the
1576 // re-submitted interrupt transfer's callback function
1577 // will not be called again in this round. Don't touch this
1578 // URB after the callback, it may have been removed by the
1579 // callback.
1580 //
1581 if (Urb->Callback != NULL) {
1582 //
1583 // Restore the old TPL, USB bus maybe connect device in
1584 // his callback. Some drivers may has a lower TPL restriction.
1585 //
1586 gBS->RestoreTPL (OldTpl);
1587 (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
1588 OldTpl = gBS->RaiseTPL (XHC_TPL);
1589 }
1590
1591 if (ProcBuf != NULL) {
1592 gBS->FreePool (ProcBuf);
1593 }
1594
1595 XhcUpdateAsyncRequest (Xhc, Urb);
1596 }
1597 gBS->RestoreTPL (OldTpl);
1598 }
1599
1600 /**
1601 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1602
1603 @param Xhc The XHCI Instance.
1604 @param ParentRouteChart The route string pointed to the parent device if it exists.
1605 @param Port The port to be polled.
1606 @param PortState The port state.
1607
1608 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1609 @retval Others Should not appear.
1610
1611 **/
1612 EFI_STATUS
1613 EFIAPI
1614 XhcPollPortStatusChange (
1615 IN USB_XHCI_INSTANCE *Xhc,
1616 IN USB_DEV_ROUTE ParentRouteChart,
1617 IN UINT8 Port,
1618 IN EFI_USB_PORT_STATUS *PortState
1619 )
1620 {
1621 EFI_STATUS Status;
1622 UINT8 Speed;
1623 UINT8 SlotId;
1624 USB_DEV_ROUTE RouteChart;
1625
1626 Status = EFI_SUCCESS;
1627
1628 if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {
1629 return EFI_SUCCESS;
1630 }
1631
1632 if (ParentRouteChart.Dword == 0) {
1633 RouteChart.Route.RouteString = 0;
1634 RouteChart.Route.RootPortNum = Port + 1;
1635 RouteChart.Route.TierNum = 1;
1636 } else {
1637 if(Port < 14) {
1638 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
1639 } else {
1640 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
1641 }
1642 RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
1643 RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
1644 }
1645
1646 SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
1647 if (SlotId != 0) {
1648 if (Xhc->HcCParams.Data.Csz == 0) {
1649 Status = XhcDisableSlotCmd (Xhc, SlotId);
1650 } else {
1651 Status = XhcDisableSlotCmd64 (Xhc, SlotId);
1652 }
1653 }
1654
1655 if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
1656 ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
1657 //
1658 // Has a device attached, Identify device speed after port is enabled.
1659 //
1660 Speed = EFI_USB_SPEED_FULL;
1661 if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {
1662 Speed = EFI_USB_SPEED_LOW;
1663 } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {
1664 Speed = EFI_USB_SPEED_HIGH;
1665 } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
1666 Speed = EFI_USB_SPEED_SUPER;
1667 }
1668 //
1669 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1670 //
1671 SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
1672 if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {
1673 if (Xhc->HcCParams.Data.Csz == 0) {
1674 Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
1675 } else {
1676 Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);
1677 }
1678 }
1679 }
1680
1681 return Status;
1682 }
1683
1684
1685 /**
1686 Calculate the device context index by endpoint address and direction.
1687
1688 @param EpAddr The target endpoint number.
1689 @param Direction The direction of the target endpoint.
1690
1691 @return The device context index of endpoint.
1692
1693 **/
1694 UINT8
1695 XhcEndpointToDci (
1696 IN UINT8 EpAddr,
1697 IN UINT8 Direction
1698 )
1699 {
1700 UINT8 Index;
1701
1702 if (EpAddr == 0) {
1703 return 1;
1704 } else {
1705 Index = (UINT8) (2 * EpAddr);
1706 if (Direction == EfiUsbDataIn) {
1707 Index += 1;
1708 }
1709 return Index;
1710 }
1711 }
1712
1713 /**
1714 Find out the actual device address according to the requested device address from UsbBus.
1715
1716 @param Xhc The XHCI Instance.
1717 @param BusDevAddr The requested device address by UsbBus upper driver.
1718
1719 @return The actual device address assigned to the device.
1720
1721 **/
1722 UINT8
1723 EFIAPI
1724 XhcBusDevAddrToSlotId (
1725 IN USB_XHCI_INSTANCE *Xhc,
1726 IN UINT8 BusDevAddr
1727 )
1728 {
1729 UINT8 Index;
1730
1731 for (Index = 0; Index < 255; Index++) {
1732 if (Xhc->UsbDevContext[Index + 1].Enabled &&
1733 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
1734 (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
1735 break;
1736 }
1737 }
1738
1739 if (Index == 255) {
1740 return 0;
1741 }
1742
1743 return Xhc->UsbDevContext[Index + 1].SlotId;
1744 }
1745
1746 /**
1747 Find out the slot id according to the device's route string.
1748
1749 @param Xhc The XHCI Instance.
1750 @param RouteString The route string described the device location.
1751
1752 @return The slot id used by the device.
1753
1754 **/
1755 UINT8
1756 EFIAPI
1757 XhcRouteStringToSlotId (
1758 IN USB_XHCI_INSTANCE *Xhc,
1759 IN USB_DEV_ROUTE RouteString
1760 )
1761 {
1762 UINT8 Index;
1763
1764 for (Index = 0; Index < 255; Index++) {
1765 if (Xhc->UsbDevContext[Index + 1].Enabled &&
1766 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
1767 (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
1768 break;
1769 }
1770 }
1771
1772 if (Index == 255) {
1773 return 0;
1774 }
1775
1776 return Xhc->UsbDevContext[Index + 1].SlotId;
1777 }
1778
1779 /**
1780 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1781
1782 @param Xhc The XHCI Instance.
1783 @param EvtRing The event ring to sync.
1784
1785 @retval EFI_SUCCESS The event ring is synchronized successfully.
1786
1787 **/
1788 EFI_STATUS
1789 EFIAPI
1790 XhcSyncEventRing (
1791 IN USB_XHCI_INSTANCE *Xhc,
1792 IN EVENT_RING *EvtRing
1793 )
1794 {
1795 UINTN Index;
1796 TRB_TEMPLATE *EvtTrb1;
1797
1798 ASSERT (EvtRing != NULL);
1799
1800 //
1801 // Calculate the EventRingEnqueue and EventRingCCS.
1802 // Note: only support single Segment
1803 //
1804 EvtTrb1 = EvtRing->EventRingDequeue;
1805
1806 for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
1807 if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {
1808 break;
1809 }
1810
1811 EvtTrb1++;
1812
1813 if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
1814 EvtTrb1 = EvtRing->EventRingSeg0;
1815 EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
1816 }
1817 }
1818
1819 if (Index < EvtRing->TrbNumber) {
1820 EvtRing->EventRingEnqueue = EvtTrb1;
1821 } else {
1822 ASSERT (FALSE);
1823 }
1824
1825 return EFI_SUCCESS;
1826 }
1827
1828 /**
1829 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1830
1831 @param Xhc The XHCI Instance.
1832 @param TrsRing The transfer ring to sync.
1833
1834 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1835
1836 **/
1837 EFI_STATUS
1838 EFIAPI
1839 XhcSyncTrsRing (
1840 IN USB_XHCI_INSTANCE *Xhc,
1841 IN TRANSFER_RING *TrsRing
1842 )
1843 {
1844 UINTN Index;
1845 TRB_TEMPLATE *TrsTrb;
1846
1847 ASSERT (TrsRing != NULL);
1848 //
1849 // Calculate the latest RingEnqueue and RingPCS
1850 //
1851 TrsTrb = TrsRing->RingEnqueue;
1852 ASSERT (TrsTrb != NULL);
1853
1854 for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
1855 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
1856 break;
1857 }
1858 TrsTrb++;
1859 if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
1860 ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
1861 //
1862 // set cycle bit in Link TRB as normal
1863 //
1864 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
1865 //
1866 // Toggle PCS maintained by software
1867 //
1868 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
1869 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
1870 }
1871 }
1872
1873 ASSERT (Index != TrsRing->TrbNumber);
1874
1875 if (TrsTrb != TrsRing->RingEnqueue) {
1876 TrsRing->RingEnqueue = TrsTrb;
1877 }
1878
1879 //
1880 // Clear the Trb context for enqueue, but reserve the PCS bit
1881 //
1882 TrsTrb->Parameter1 = 0;
1883 TrsTrb->Parameter2 = 0;
1884 TrsTrb->Status = 0;
1885 TrsTrb->RsvdZ1 = 0;
1886 TrsTrb->Type = 0;
1887 TrsTrb->Control = 0;
1888
1889 return EFI_SUCCESS;
1890 }
1891
1892 /**
1893 Check if there is a new generated event.
1894
1895 @param Xhc The XHCI Instance.
1896 @param EvtRing The event ring to check.
1897 @param NewEvtTrb The new event TRB found.
1898
1899 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1900 @retval EFI_NOT_READY The event ring has no new event.
1901
1902 **/
1903 EFI_STATUS
1904 EFIAPI
1905 XhcCheckNewEvent (
1906 IN USB_XHCI_INSTANCE *Xhc,
1907 IN EVENT_RING *EvtRing,
1908 OUT TRB_TEMPLATE **NewEvtTrb
1909 )
1910 {
1911 ASSERT (EvtRing != NULL);
1912
1913 *NewEvtTrb = EvtRing->EventRingDequeue;
1914
1915 if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
1916 return EFI_NOT_READY;
1917 }
1918
1919 EvtRing->EventRingDequeue++;
1920 //
1921 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1922 //
1923 if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
1924 EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
1925 }
1926
1927 return EFI_SUCCESS;
1928 }
1929
1930 /**
1931 Ring the door bell to notify XHCI there is a transaction to be executed.
1932
1933 @param Xhc The XHCI Instance.
1934 @param SlotId The slot id of the target device.
1935 @param Dci The device context index of the target slot or endpoint.
1936
1937 @retval EFI_SUCCESS Successfully ring the door bell.
1938
1939 **/
1940 EFI_STATUS
1941 EFIAPI
1942 XhcRingDoorBell (
1943 IN USB_XHCI_INSTANCE *Xhc,
1944 IN UINT8 SlotId,
1945 IN UINT8 Dci
1946 )
1947 {
1948 if (SlotId == 0) {
1949 XhcWriteDoorBellReg (Xhc, 0, 0);
1950 } else {
1951 XhcWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);
1952 }
1953
1954 return EFI_SUCCESS;
1955 }
1956
1957 /**
1958 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1959
1960 @param Xhc The XHCI Instance.
1961 @param Urb The URB to be rung.
1962
1963 @retval EFI_SUCCESS Successfully ring the door bell.
1964
1965 **/
1966 EFI_STATUS
1967 RingIntTransferDoorBell (
1968 IN USB_XHCI_INSTANCE *Xhc,
1969 IN URB *Urb
1970 )
1971 {
1972 UINT8 SlotId;
1973 UINT8 Dci;
1974
1975 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1976 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1977 XhcRingDoorBell (Xhc, SlotId, Dci);
1978 return EFI_SUCCESS;
1979 }
1980
1981 /**
1982 Assign and initialize the device slot for a new device.
1983
1984 @param Xhc The XHCI Instance.
1985 @param ParentRouteChart The route string pointed to the parent device.
1986 @param ParentPort The port at which the device is located.
1987 @param RouteChart The route string pointed to the device.
1988 @param DeviceSpeed The device speed.
1989
1990 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1991
1992 **/
1993 EFI_STATUS
1994 EFIAPI
1995 XhcInitializeDeviceSlot (
1996 IN USB_XHCI_INSTANCE *Xhc,
1997 IN USB_DEV_ROUTE ParentRouteChart,
1998 IN UINT16 ParentPort,
1999 IN USB_DEV_ROUTE RouteChart,
2000 IN UINT8 DeviceSpeed
2001 )
2002 {
2003 EFI_STATUS Status;
2004 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2005 INPUT_CONTEXT *InputContext;
2006 DEVICE_CONTEXT *OutputContext;
2007 TRANSFER_RING *EndpointTransferRing;
2008 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
2009 UINT8 DeviceAddress;
2010 CMD_TRB_ENABLE_SLOT CmdTrb;
2011 UINT8 SlotId;
2012 UINT8 ParentSlotId;
2013 DEVICE_CONTEXT *ParentDeviceContext;
2014 EFI_PHYSICAL_ADDRESS PhyAddr;
2015
2016 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
2017 CmdTrb.CycleBit = 1;
2018 CmdTrb.Type = TRB_TYPE_EN_SLOT;
2019
2020 Status = XhcCmdTransfer (
2021 Xhc,
2022 (TRB_TEMPLATE *) (UINTN) &CmdTrb,
2023 XHC_GENERIC_TIMEOUT,
2024 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2025 );
2026 if (EFI_ERROR (Status)) {
2027 DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
2028 return Status;
2029 }
2030 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
2031 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
2032 SlotId = (UINT8)EvtTrb->SlotId;
2033 ASSERT (SlotId != 0);
2034
2035 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
2036 Xhc->UsbDevContext[SlotId].Enabled = TRUE;
2037 Xhc->UsbDevContext[SlotId].SlotId = SlotId;
2038 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
2039 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
2040
2041 //
2042 // 4.3.3 Device Slot Initialization
2043 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2044 //
2045 InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
2046 ASSERT (InputContext != NULL);
2047 ASSERT (((UINTN) InputContext & 0x3F) == 0);
2048 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2049
2050 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
2051
2052 //
2053 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2054 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2055 // Context are affected by the command.
2056 //
2057 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
2058
2059 //
2060 // 3) Initialize the Input Slot Context data structure
2061 //
2062 InputContext->Slot.RouteString = RouteChart.Route.RouteString;
2063 InputContext->Slot.Speed = DeviceSpeed + 1;
2064 InputContext->Slot.ContextEntries = 1;
2065 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;
2066
2067 if (RouteChart.Route.RouteString) {
2068 //
2069 // The device is behind of hub device.
2070 //
2071 ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
2072 ASSERT (ParentSlotId != 0);
2073 //
2074 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2075 //
2076 ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
2077 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
2078 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
2079 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
2080 //
2081 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2082 // environment from Full/Low speed signaling environment for a device
2083 //
2084 InputContext->Slot.TTPortNum = ParentPort;
2085 InputContext->Slot.TTHubSlotId = ParentSlotId;
2086 }
2087 } else {
2088 //
2089 // Inherit the TT parameters from parent device.
2090 //
2091 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
2092 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
2093 //
2094 // If the device is a High speed device then down the speed to be the same as its parent Hub
2095 //
2096 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2097 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
2098 }
2099 }
2100 }
2101
2102 //
2103 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2104 //
2105 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
2106 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
2107 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
2108 //
2109 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2110 //
2111 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
2112
2113 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2114 InputContext->EP[0].MaxPacketSize = 512;
2115 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2116 InputContext->EP[0].MaxPacketSize = 64;
2117 } else {
2118 InputContext->EP[0].MaxPacketSize = 8;
2119 }
2120 //
2121 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2122 // 1KB, and Bulk and Isoch endpoints 3KB.
2123 //
2124 InputContext->EP[0].AverageTRBLength = 8;
2125 InputContext->EP[0].MaxBurstSize = 0;
2126 InputContext->EP[0].Interval = 0;
2127 InputContext->EP[0].MaxPStreams = 0;
2128 InputContext->EP[0].Mult = 0;
2129 InputContext->EP[0].CErr = 3;
2130
2131 //
2132 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2133 //
2134 PhyAddr = UsbHcGetPciAddrForHostAddr (
2135 Xhc->MemPool,
2136 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
2137 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2138 );
2139 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
2140 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2141
2142 //
2143 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2144 //
2145 OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
2146 ASSERT (OutputContext != NULL);
2147 ASSERT (((UINTN) OutputContext & 0x3F) == 0);
2148 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
2149
2150 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
2151 //
2152 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2153 // a pointer to the Output Device Context data structure (6.2.1).
2154 //
2155 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));
2156 //
2157 // Fill DCBAA with PCI device address
2158 //
2159 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
2160
2161 //
2162 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2163 // Context data structure described above.
2164 //
2165 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2166 // to device.
2167 //
2168 gBS->Stall (XHC_RESET_RECOVERY_DELAY);
2169 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
2170 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
2171 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
2172 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2173 CmdTrbAddr.CycleBit = 1;
2174 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
2175 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2176 Status = XhcCmdTransfer (
2177 Xhc,
2178 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
2179 XHC_GENERIC_TIMEOUT,
2180 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2181 );
2182 if (!EFI_ERROR (Status)) {
2183 DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
2184 DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
2185 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
2186 }
2187
2188 return Status;
2189 }
2190
2191 /**
2192 Assign and initialize the device slot for a new device.
2193
2194 @param Xhc The XHCI Instance.
2195 @param ParentRouteChart The route string pointed to the parent device.
2196 @param ParentPort The port at which the device is located.
2197 @param RouteChart The route string pointed to the device.
2198 @param DeviceSpeed The device speed.
2199
2200 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
2201
2202 **/
2203 EFI_STATUS
2204 EFIAPI
2205 XhcInitializeDeviceSlot64 (
2206 IN USB_XHCI_INSTANCE *Xhc,
2207 IN USB_DEV_ROUTE ParentRouteChart,
2208 IN UINT16 ParentPort,
2209 IN USB_DEV_ROUTE RouteChart,
2210 IN UINT8 DeviceSpeed
2211 )
2212 {
2213 EFI_STATUS Status;
2214 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2215 INPUT_CONTEXT_64 *InputContext;
2216 DEVICE_CONTEXT_64 *OutputContext;
2217 TRANSFER_RING *EndpointTransferRing;
2218 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
2219 UINT8 DeviceAddress;
2220 CMD_TRB_ENABLE_SLOT CmdTrb;
2221 UINT8 SlotId;
2222 UINT8 ParentSlotId;
2223 DEVICE_CONTEXT_64 *ParentDeviceContext;
2224 EFI_PHYSICAL_ADDRESS PhyAddr;
2225
2226 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
2227 CmdTrb.CycleBit = 1;
2228 CmdTrb.Type = TRB_TYPE_EN_SLOT;
2229
2230 Status = XhcCmdTransfer (
2231 Xhc,
2232 (TRB_TEMPLATE *) (UINTN) &CmdTrb,
2233 XHC_GENERIC_TIMEOUT,
2234 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2235 );
2236 if (EFI_ERROR (Status)) {
2237 DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
2238 return Status;
2239 }
2240 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
2241 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
2242 SlotId = (UINT8)EvtTrb->SlotId;
2243 ASSERT (SlotId != 0);
2244
2245 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
2246 Xhc->UsbDevContext[SlotId].Enabled = TRUE;
2247 Xhc->UsbDevContext[SlotId].SlotId = SlotId;
2248 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
2249 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
2250
2251 //
2252 // 4.3.3 Device Slot Initialization
2253 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2254 //
2255 InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
2256 ASSERT (InputContext != NULL);
2257 ASSERT (((UINTN) InputContext & 0x3F) == 0);
2258 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
2259
2260 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
2261
2262 //
2263 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2264 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2265 // Context are affected by the command.
2266 //
2267 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
2268
2269 //
2270 // 3) Initialize the Input Slot Context data structure
2271 //
2272 InputContext->Slot.RouteString = RouteChart.Route.RouteString;
2273 InputContext->Slot.Speed = DeviceSpeed + 1;
2274 InputContext->Slot.ContextEntries = 1;
2275 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;
2276
2277 if (RouteChart.Route.RouteString) {
2278 //
2279 // The device is behind of hub device.
2280 //
2281 ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
2282 ASSERT (ParentSlotId != 0);
2283 //
2284 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2285 //
2286 ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
2287 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
2288 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
2289 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
2290 //
2291 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2292 // environment from Full/Low speed signaling environment for a device
2293 //
2294 InputContext->Slot.TTPortNum = ParentPort;
2295 InputContext->Slot.TTHubSlotId = ParentSlotId;
2296 }
2297 } else {
2298 //
2299 // Inherit the TT parameters from parent device.
2300 //
2301 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
2302 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
2303 //
2304 // If the device is a High speed device then down the speed to be the same as its parent Hub
2305 //
2306 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2307 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
2308 }
2309 }
2310 }
2311
2312 //
2313 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2314 //
2315 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
2316 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
2317 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
2318 //
2319 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2320 //
2321 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
2322
2323 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2324 InputContext->EP[0].MaxPacketSize = 512;
2325 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2326 InputContext->EP[0].MaxPacketSize = 64;
2327 } else {
2328 InputContext->EP[0].MaxPacketSize = 8;
2329 }
2330 //
2331 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2332 // 1KB, and Bulk and Isoch endpoints 3KB.
2333 //
2334 InputContext->EP[0].AverageTRBLength = 8;
2335 InputContext->EP[0].MaxBurstSize = 0;
2336 InputContext->EP[0].Interval = 0;
2337 InputContext->EP[0].MaxPStreams = 0;
2338 InputContext->EP[0].Mult = 0;
2339 InputContext->EP[0].CErr = 3;
2340
2341 //
2342 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2343 //
2344 PhyAddr = UsbHcGetPciAddrForHostAddr (
2345 Xhc->MemPool,
2346 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
2347 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2348 );
2349 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
2350 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2351
2352 //
2353 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2354 //
2355 OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
2356 ASSERT (OutputContext != NULL);
2357 ASSERT (((UINTN) OutputContext & 0x3F) == 0);
2358 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
2359
2360 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
2361 //
2362 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2363 // a pointer to the Output Device Context data structure (6.2.1).
2364 //
2365 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));
2366 //
2367 // Fill DCBAA with PCI device address
2368 //
2369 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
2370
2371 //
2372 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2373 // Context data structure described above.
2374 //
2375 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2376 // to device.
2377 //
2378 gBS->Stall (XHC_RESET_RECOVERY_DELAY);
2379 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
2380 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
2381 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
2382 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2383 CmdTrbAddr.CycleBit = 1;
2384 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
2385 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2386 Status = XhcCmdTransfer (
2387 Xhc,
2388 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
2389 XHC_GENERIC_TIMEOUT,
2390 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2391 );
2392 if (!EFI_ERROR (Status)) {
2393 DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
2394 DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
2395 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
2396 }
2397 return Status;
2398 }
2399
2400
2401 /**
2402 Disable the specified device slot.
2403
2404 @param Xhc The XHCI Instance.
2405 @param SlotId The slot id to be disabled.
2406
2407 @retval EFI_SUCCESS Successfully disable the device slot.
2408
2409 **/
2410 EFI_STATUS
2411 EFIAPI
2412 XhcDisableSlotCmd (
2413 IN USB_XHCI_INSTANCE *Xhc,
2414 IN UINT8 SlotId
2415 )
2416 {
2417 EFI_STATUS Status;
2418 TRB_TEMPLATE *EvtTrb;
2419 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;
2420 UINT8 Index;
2421 VOID *RingSeg;
2422
2423 //
2424 // Disable the device slots occupied by these devices on its downstream ports.
2425 // Entry 0 is reserved.
2426 //
2427 for (Index = 0; Index < 255; Index++) {
2428 if (!Xhc->UsbDevContext[Index + 1].Enabled ||
2429 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
2430 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
2431 continue;
2432 }
2433
2434 Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
2435
2436 if (EFI_ERROR (Status)) {
2437 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2438 Xhc->UsbDevContext[Index + 1].SlotId = 0;
2439 }
2440 }
2441
2442 //
2443 // Construct the disable slot command
2444 //
2445 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
2446
2447 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
2448 CmdTrbDisSlot.CycleBit = 1;
2449 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
2450 CmdTrbDisSlot.SlotId = SlotId;
2451 Status = XhcCmdTransfer (
2452 Xhc,
2453 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
2454 XHC_GENERIC_TIMEOUT,
2455 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2456 );
2457 if (EFI_ERROR (Status)) {
2458 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
2459 return Status;
2460 }
2461 //
2462 // Free the slot's device context entry
2463 //
2464 Xhc->DCBAA[SlotId] = 0;
2465
2466 //
2467 // Free the slot related data structure
2468 //
2469 for (Index = 0; Index < 31; Index++) {
2470 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
2471 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
2472 if (RingSeg != NULL) {
2473 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
2474 }
2475 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
2476 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
2477 }
2478 }
2479
2480 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
2481 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
2482 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
2483 }
2484 }
2485
2486 if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
2487 FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
2488 }
2489
2490 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
2491 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
2492 }
2493
2494 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
2495 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
2496 }
2497 //
2498 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2499 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2500 // remove urb from XHCI's asynchronous transfer list.
2501 //
2502 Xhc->UsbDevContext[SlotId].Enabled = FALSE;
2503 Xhc->UsbDevContext[SlotId].SlotId = 0;
2504
2505 return Status;
2506 }
2507
2508 /**
2509 Disable the specified device slot.
2510
2511 @param Xhc The XHCI Instance.
2512 @param SlotId The slot id to be disabled.
2513
2514 @retval EFI_SUCCESS Successfully disable the device slot.
2515
2516 **/
2517 EFI_STATUS
2518 EFIAPI
2519 XhcDisableSlotCmd64 (
2520 IN USB_XHCI_INSTANCE *Xhc,
2521 IN UINT8 SlotId
2522 )
2523 {
2524 EFI_STATUS Status;
2525 TRB_TEMPLATE *EvtTrb;
2526 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;
2527 UINT8 Index;
2528 VOID *RingSeg;
2529
2530 //
2531 // Disable the device slots occupied by these devices on its downstream ports.
2532 // Entry 0 is reserved.
2533 //
2534 for (Index = 0; Index < 255; Index++) {
2535 if (!Xhc->UsbDevContext[Index + 1].Enabled ||
2536 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
2537 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
2538 continue;
2539 }
2540
2541 Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
2542
2543 if (EFI_ERROR (Status)) {
2544 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2545 Xhc->UsbDevContext[Index + 1].SlotId = 0;
2546 }
2547 }
2548
2549 //
2550 // Construct the disable slot command
2551 //
2552 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
2553
2554 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
2555 CmdTrbDisSlot.CycleBit = 1;
2556 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
2557 CmdTrbDisSlot.SlotId = SlotId;
2558 Status = XhcCmdTransfer (
2559 Xhc,
2560 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
2561 XHC_GENERIC_TIMEOUT,
2562 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2563 );
2564 if (EFI_ERROR (Status)) {
2565 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
2566 return Status;
2567 }
2568 //
2569 // Free the slot's device context entry
2570 //
2571 Xhc->DCBAA[SlotId] = 0;
2572
2573 //
2574 // Free the slot related data structure
2575 //
2576 for (Index = 0; Index < 31; Index++) {
2577 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
2578 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
2579 if (RingSeg != NULL) {
2580 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
2581 }
2582 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
2583 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
2584 }
2585 }
2586
2587 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
2588 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
2589 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
2590 }
2591 }
2592
2593 if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
2594 FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
2595 }
2596
2597 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
2598 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
2599 }
2600
2601 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
2602 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
2603 }
2604 //
2605 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2606 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2607 // remove urb from XHCI's asynchronous transfer list.
2608 //
2609 Xhc->UsbDevContext[SlotId].Enabled = FALSE;
2610 Xhc->UsbDevContext[SlotId].SlotId = 0;
2611
2612 return Status;
2613 }
2614
2615 /**
2616 Initialize endpoint context in input context.
2617
2618 @param Xhc The XHCI Instance.
2619 @param SlotId The slot id to be configured.
2620 @param DeviceSpeed The device's speed.
2621 @param InputContext The pointer to the input context.
2622 @param IfDesc The pointer to the usb device interface descriptor.
2623
2624 @return The maximum device context index of endpoint.
2625
2626 **/
2627 UINT8
2628 EFIAPI
2629 XhcInitializeEndpointContext (
2630 IN USB_XHCI_INSTANCE *Xhc,
2631 IN UINT8 SlotId,
2632 IN UINT8 DeviceSpeed,
2633 IN INPUT_CONTEXT *InputContext,
2634 IN USB_INTERFACE_DESCRIPTOR *IfDesc
2635 )
2636 {
2637 USB_ENDPOINT_DESCRIPTOR *EpDesc;
2638 UINTN NumEp;
2639 UINTN EpIndex;
2640 UINT8 EpAddr;
2641 UINT8 Direction;
2642 UINT8 Dci;
2643 UINT8 MaxDci;
2644 EFI_PHYSICAL_ADDRESS PhyAddr;
2645 UINT8 Interval;
2646 TRANSFER_RING *EndpointTransferRing;
2647
2648 MaxDci = 0;
2649
2650 NumEp = IfDesc->NumEndpoints;
2651
2652 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
2653 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
2654 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
2655 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2656 }
2657
2658 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
2659 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2660 continue;
2661 }
2662
2663 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
2664 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
2665
2666 Dci = XhcEndpointToDci (EpAddr, Direction);
2667 ASSERT (Dci < 32);
2668 if (Dci > MaxDci) {
2669 MaxDci = Dci;
2670 }
2671
2672 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
2673 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
2674
2675 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2676 //
2677 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2678 //
2679 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2680 } else {
2681 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2682 }
2683
2684 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
2685 case USB_ENDPOINT_BULK:
2686 if (Direction == EfiUsbDataIn) {
2687 InputContext->EP[Dci-1].CErr = 3;
2688 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
2689 } else {
2690 InputContext->EP[Dci-1].CErr = 3;
2691 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
2692 }
2693
2694 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2695 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2696 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2697 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2698 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2699 DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",
2700 EpDesc->EndpointAddress,
2701 EndpointTransferRing->RingSeg0,
2702 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2703 ));
2704 }
2705
2706 break;
2707 case USB_ENDPOINT_ISO:
2708 if (Direction == EfiUsbDataIn) {
2709 InputContext->EP[Dci-1].CErr = 0;
2710 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
2711 } else {
2712 InputContext->EP[Dci-1].CErr = 0;
2713 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
2714 }
2715 //
2716 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2717 // Refer to XHCI 1.1 spec section 6.2.3.6.
2718 //
2719 if (DeviceSpeed == EFI_USB_SPEED_FULL) {
2720 Interval = EpDesc->Interval;
2721 ASSERT (Interval >= 1 && Interval <= 16);
2722 InputContext->EP[Dci-1].Interval = Interval + 2;
2723 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2724 Interval = EpDesc->Interval;
2725 ASSERT (Interval >= 1 && Interval <= 16);
2726 InputContext->EP[Dci-1].Interval = Interval - 1;
2727 }
2728
2729 //
2730 // Do not support isochronous transfer now.
2731 //
2732 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2733 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2734 continue;
2735 case USB_ENDPOINT_INTERRUPT:
2736 if (Direction == EfiUsbDataIn) {
2737 InputContext->EP[Dci-1].CErr = 3;
2738 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2739 } else {
2740 InputContext->EP[Dci-1].CErr = 3;
2741 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2742 }
2743 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2744 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2745 //
2746 // Get the bInterval from descriptor and init the the interval field of endpoint context
2747 //
2748 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2749 Interval = EpDesc->Interval;
2750 //
2751 // Calculate through the bInterval field of Endpoint descriptor.
2752 //
2753 ASSERT (Interval != 0);
2754 InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
2755 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2756 Interval = EpDesc->Interval;
2757 ASSERT (Interval >= 1 && Interval <= 16);
2758 //
2759 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2760 //
2761 InputContext->EP[Dci-1].Interval = Interval - 1;
2762 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2763 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;
2764 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2765 InputContext->EP[Dci-1].CErr = 3;
2766 }
2767
2768 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2769 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2770 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2771 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2772 DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",
2773 EpDesc->EndpointAddress,
2774 EndpointTransferRing->RingSeg0,
2775 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2776 ));
2777 }
2778 break;
2779
2780 case USB_ENDPOINT_CONTROL:
2781 //
2782 // Do not support control transfer now.
2783 //
2784 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2785 default:
2786 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
2787 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2788 continue;
2789 }
2790
2791 PhyAddr = UsbHcGetPciAddrForHostAddr (
2792 Xhc->MemPool,
2793 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
2794 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2795 );
2796 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
2797 PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2798 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
2799 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2800
2801 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2802 }
2803
2804 return MaxDci;
2805 }
2806
2807 /**
2808 Initialize endpoint context in input context.
2809
2810 @param Xhc The XHCI Instance.
2811 @param SlotId The slot id to be configured.
2812 @param DeviceSpeed The device's speed.
2813 @param InputContext The pointer to the input context.
2814 @param IfDesc The pointer to the usb device interface descriptor.
2815
2816 @return The maximum device context index of endpoint.
2817
2818 **/
2819 UINT8
2820 EFIAPI
2821 XhcInitializeEndpointContext64 (
2822 IN USB_XHCI_INSTANCE *Xhc,
2823 IN UINT8 SlotId,
2824 IN UINT8 DeviceSpeed,
2825 IN INPUT_CONTEXT_64 *InputContext,
2826 IN USB_INTERFACE_DESCRIPTOR *IfDesc
2827 )
2828 {
2829 USB_ENDPOINT_DESCRIPTOR *EpDesc;
2830 UINTN NumEp;
2831 UINTN EpIndex;
2832 UINT8 EpAddr;
2833 UINT8 Direction;
2834 UINT8 Dci;
2835 UINT8 MaxDci;
2836 EFI_PHYSICAL_ADDRESS PhyAddr;
2837 UINT8 Interval;
2838 TRANSFER_RING *EndpointTransferRing;
2839
2840 MaxDci = 0;
2841
2842 NumEp = IfDesc->NumEndpoints;
2843
2844 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
2845 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
2846 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
2847 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2848 }
2849
2850 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
2851 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2852 continue;
2853 }
2854
2855 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
2856 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
2857
2858 Dci = XhcEndpointToDci (EpAddr, Direction);
2859 ASSERT (Dci < 32);
2860 if (Dci > MaxDci) {
2861 MaxDci = Dci;
2862 }
2863
2864 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
2865 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
2866
2867 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2868 //
2869 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2870 //
2871 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2872 } else {
2873 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2874 }
2875
2876 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
2877 case USB_ENDPOINT_BULK:
2878 if (Direction == EfiUsbDataIn) {
2879 InputContext->EP[Dci-1].CErr = 3;
2880 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
2881 } else {
2882 InputContext->EP[Dci-1].CErr = 3;
2883 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
2884 }
2885
2886 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2887 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2888 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2889 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2890 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2891 DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
2892 EpDesc->EndpointAddress,
2893 EndpointTransferRing->RingSeg0,
2894 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2895 ));
2896 }
2897
2898 break;
2899 case USB_ENDPOINT_ISO:
2900 if (Direction == EfiUsbDataIn) {
2901 InputContext->EP[Dci-1].CErr = 0;
2902 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
2903 } else {
2904 InputContext->EP[Dci-1].CErr = 0;
2905 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
2906 }
2907 //
2908 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2909 // Refer to XHCI 1.1 spec section 6.2.3.6.
2910 //
2911 if (DeviceSpeed == EFI_USB_SPEED_FULL) {
2912 Interval = EpDesc->Interval;
2913 ASSERT (Interval >= 1 && Interval <= 16);
2914 InputContext->EP[Dci-1].Interval = Interval + 2;
2915 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2916 Interval = EpDesc->Interval;
2917 ASSERT (Interval >= 1 && Interval <= 16);
2918 InputContext->EP[Dci-1].Interval = Interval - 1;
2919 }
2920
2921 //
2922 // Do not support isochronous transfer now.
2923 //
2924 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2925 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2926 continue;
2927 case USB_ENDPOINT_INTERRUPT:
2928 if (Direction == EfiUsbDataIn) {
2929 InputContext->EP[Dci-1].CErr = 3;
2930 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2931 } else {
2932 InputContext->EP[Dci-1].CErr = 3;
2933 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2934 }
2935 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2936 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2937 //
2938 // Get the bInterval from descriptor and init the the interval field of endpoint context
2939 //
2940 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2941 Interval = EpDesc->Interval;
2942 //
2943 // Calculate through the bInterval field of Endpoint descriptor.
2944 //
2945 ASSERT (Interval != 0);
2946 InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
2947 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2948 Interval = EpDesc->Interval;
2949 ASSERT (Interval >= 1 && Interval <= 16);
2950 //
2951 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2952 //
2953 InputContext->EP[Dci-1].Interval = Interval - 1;
2954 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2955 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;
2956 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2957 InputContext->EP[Dci-1].CErr = 3;
2958 }
2959
2960 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2961 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2962 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2963 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2964 DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",
2965 EpDesc->EndpointAddress,
2966 EndpointTransferRing->RingSeg0,
2967 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2968 ));
2969 }
2970 break;
2971
2972 case USB_ENDPOINT_CONTROL:
2973 //
2974 // Do not support control transfer now.
2975 //
2976 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2977 default:
2978 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
2979 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2980 continue;
2981 }
2982
2983 PhyAddr = UsbHcGetPciAddrForHostAddr (
2984 Xhc->MemPool,
2985 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
2986 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2987 );
2988 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
2989 PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2990 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
2991 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2992
2993 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2994 }
2995
2996 return MaxDci;
2997 }
2998
2999 /**
3000 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
3001
3002 @param Xhc The XHCI Instance.
3003 @param SlotId The slot id to be configured.
3004 @param DeviceSpeed The device's speed.
3005 @param ConfigDesc The pointer to the usb device configuration descriptor.
3006
3007 @retval EFI_SUCCESS Successfully configure all the device endpoints.
3008
3009 **/
3010 EFI_STATUS
3011 EFIAPI
3012 XhcSetConfigCmd (
3013 IN USB_XHCI_INSTANCE *Xhc,
3014 IN UINT8 SlotId,
3015 IN UINT8 DeviceSpeed,
3016 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
3017 )
3018 {
3019 EFI_STATUS Status;
3020 USB_INTERFACE_DESCRIPTOR *IfDesc;
3021 UINT8 Index;
3022 UINT8 Dci;
3023 UINT8 MaxDci;
3024 EFI_PHYSICAL_ADDRESS PhyAddr;
3025
3026 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3027 INPUT_CONTEXT *InputContext;
3028 DEVICE_CONTEXT *OutputContext;
3029 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3030 //
3031 // 4.6.6 Configure Endpoint
3032 //
3033 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3034 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3035 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3036 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
3037
3038 ASSERT (ConfigDesc != NULL);
3039
3040 MaxDci = 0;
3041
3042 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3043 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
3044 while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
3045 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3046 }
3047
3048 if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {
3049 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3050 continue;
3051 }
3052
3053 Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);
3054 if (Dci > MaxDci) {
3055 MaxDci = Dci;
3056 }
3057
3058 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3059 }
3060
3061 InputContext->InputControlContext.Dword2 |= BIT0;
3062 InputContext->Slot.ContextEntries = MaxDci;
3063 //
3064 // configure endpoint
3065 //
3066 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3067 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3068 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3069 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3070 CmdTrbCfgEP.CycleBit = 1;
3071 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3072 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3073 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
3074 Status = XhcCmdTransfer (
3075 Xhc,
3076 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3077 XHC_GENERIC_TIMEOUT,
3078 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3079 );
3080 if (EFI_ERROR (Status)) {
3081 DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
3082 } else {
3083 Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
3084 }
3085
3086 return Status;
3087 }
3088
3089 /**
3090 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
3091
3092 @param Xhc The XHCI Instance.
3093 @param SlotId The slot id to be configured.
3094 @param DeviceSpeed The device's speed.
3095 @param ConfigDesc The pointer to the usb device configuration descriptor.
3096
3097 @retval EFI_SUCCESS Successfully configure all the device endpoints.
3098
3099 **/
3100 EFI_STATUS
3101 EFIAPI
3102 XhcSetConfigCmd64 (
3103 IN USB_XHCI_INSTANCE *Xhc,
3104 IN UINT8 SlotId,
3105 IN UINT8 DeviceSpeed,
3106 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
3107 )
3108 {
3109 EFI_STATUS Status;
3110 USB_INTERFACE_DESCRIPTOR *IfDesc;
3111 UINT8 Index;
3112 UINT8 Dci;
3113 UINT8 MaxDci;
3114 EFI_PHYSICAL_ADDRESS PhyAddr;
3115
3116 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3117 INPUT_CONTEXT_64 *InputContext;
3118 DEVICE_CONTEXT_64 *OutputContext;
3119 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3120 //
3121 // 4.6.6 Configure Endpoint
3122 //
3123 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3124 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3125 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
3126 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
3127
3128 ASSERT (ConfigDesc != NULL);
3129
3130 MaxDci = 0;
3131
3132 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3133 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
3134 while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
3135 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3136 }
3137
3138 if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {
3139 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3140 continue;
3141 }
3142
3143 Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);
3144 if (Dci > MaxDci) {
3145 MaxDci = Dci;
3146 }
3147
3148 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3149 }
3150
3151 InputContext->InputControlContext.Dword2 |= BIT0;
3152 InputContext->Slot.ContextEntries = MaxDci;
3153 //
3154 // configure endpoint
3155 //
3156 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3157 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
3158 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3159 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3160 CmdTrbCfgEP.CycleBit = 1;
3161 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3162 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3163 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
3164 Status = XhcCmdTransfer (
3165 Xhc,
3166 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3167 XHC_GENERIC_TIMEOUT,
3168 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3169 );
3170 if (EFI_ERROR (Status)) {
3171 DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
3172 } else {
3173 Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
3174 }
3175
3176 return Status;
3177 }
3178
3179 /**
3180 Stop endpoint through XHCI's Stop_Endpoint cmd.
3181
3182 @param Xhc The XHCI Instance.
3183 @param SlotId The slot id to be configured.
3184 @param Dci The device context index of endpoint.
3185 @param PendingUrb The pending URB to check completion status when stopping the end point.
3186
3187 @retval EFI_SUCCESS Stop endpoint successfully.
3188 @retval Others Failed to stop endpoint.
3189
3190 **/
3191 EFI_STATUS
3192 EFIAPI
3193 XhcStopEndpoint (
3194 IN USB_XHCI_INSTANCE *Xhc,
3195 IN UINT8 SlotId,
3196 IN UINT8 Dci,
3197 IN URB *PendingUrb OPTIONAL
3198 )
3199 {
3200 EFI_STATUS Status;
3201 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3202 CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
3203
3204 DEBUG ((EFI_D_INFO, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
3205
3206 //
3207 // When XhcCheckUrbResult waits for the Stop_Endpoint completion, it also checks
3208 // the PendingUrb completion status, because it's possible that the PendingUrb is
3209 // finished just before stopping the end point, but after the looping check.
3210 //
3211 // The PendingUrb could be passed to XhcCmdTransfer to XhcExecTransfer to XhcCheckUrbResult
3212 // through function parameter, but That will cause every consumer of XhcCmdTransfer,
3213 // XhcExecTransfer and XhcCheckUrbResult pass a NULL PendingUrb.
3214 // But actually only XhcCheckUrbResult is aware of the PendingUrb.
3215 // So we choose to save the PendingUrb into the USB_XHCI_INSTANCE and use it in XhcCheckUrbResult.
3216 //
3217 ASSERT (Xhc->PendingUrb == NULL);
3218 Xhc->PendingUrb = PendingUrb;
3219 //
3220 // Reset the URB result from Timeout to NoError.
3221 // The USB result will be:
3222 // changed to Timeout when Stop/StopInvalidLength Transfer Event is received, or
3223 // remain NoError when Success/ShortPacket Transfer Event is received.
3224 //
3225 if (PendingUrb != NULL) {
3226 PendingUrb->Result = EFI_USB_NOERROR;
3227 }
3228
3229 //
3230 // Send stop endpoint command to transit Endpoint from running to stop state
3231 //
3232 ZeroMem (&CmdTrbStopED, sizeof (CmdTrbStopED));
3233 CmdTrbStopED.CycleBit = 1;
3234 CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;
3235 CmdTrbStopED.EDID = Dci;
3236 CmdTrbStopED.SlotId = SlotId;
3237 Status = XhcCmdTransfer (
3238 Xhc,
3239 (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
3240 XHC_GENERIC_TIMEOUT,
3241 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3242 );
3243 if (EFI_ERROR(Status)) {
3244 DEBUG ((EFI_D_ERROR, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
3245 }
3246
3247 Xhc->PendingUrb = NULL;
3248
3249 return Status;
3250 }
3251
3252 /**
3253 Reset endpoint through XHCI's Reset_Endpoint cmd.
3254
3255 @param Xhc The XHCI Instance.
3256 @param SlotId The slot id to be configured.
3257 @param Dci The device context index of endpoint.
3258
3259 @retval EFI_SUCCESS Reset endpoint successfully.
3260 @retval Others Failed to reset endpoint.
3261
3262 **/
3263 EFI_STATUS
3264 EFIAPI
3265 XhcResetEndpoint (
3266 IN USB_XHCI_INSTANCE *Xhc,
3267 IN UINT8 SlotId,
3268 IN UINT8 Dci
3269 )
3270 {
3271 EFI_STATUS Status;
3272 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3273 CMD_TRB_RESET_ENDPOINT CmdTrbResetED;
3274
3275 DEBUG ((EFI_D_INFO, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
3276
3277 //
3278 // Send stop endpoint command to transit Endpoint from running to stop state
3279 //
3280 ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));
3281 CmdTrbResetED.CycleBit = 1;
3282 CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
3283 CmdTrbResetED.EDID = Dci;
3284 CmdTrbResetED.SlotId = SlotId;
3285 Status = XhcCmdTransfer (
3286 Xhc,
3287 (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,
3288 XHC_GENERIC_TIMEOUT,
3289 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3290 );
3291 if (EFI_ERROR(Status)) {
3292 DEBUG ((EFI_D_ERROR, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
3293 }
3294
3295 return Status;
3296 }
3297
3298 /**
3299 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
3300
3301 @param Xhc The XHCI Instance.
3302 @param SlotId The slot id to be configured.
3303 @param Dci The device context index of endpoint.
3304 @param Urb The dequeue pointer of the transfer ring specified
3305 by the urb to be updated.
3306
3307 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
3308 @retval Others Failed to set transfer ring dequeue pointer.
3309
3310 **/
3311 EFI_STATUS
3312 EFIAPI
3313 XhcSetTrDequeuePointer (
3314 IN USB_XHCI_INSTANCE *Xhc,
3315 IN UINT8 SlotId,
3316 IN UINT8 Dci,
3317 IN URB *Urb
3318 )
3319 {
3320 EFI_STATUS Status;
3321 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3322 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;
3323 EFI_PHYSICAL_ADDRESS PhyAddr;
3324
3325 DEBUG ((EFI_D_INFO, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
3326
3327 //
3328 // Send stop endpoint command to transit Endpoint from running to stop state
3329 //
3330 ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
3331 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
3332 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
3333 CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3334 CmdSetTRDeq.CycleBit = 1;
3335 CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
3336 CmdSetTRDeq.Endpoint = Dci;
3337 CmdSetTRDeq.SlotId = SlotId;
3338 Status = XhcCmdTransfer (
3339 Xhc,
3340 (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,
3341 XHC_GENERIC_TIMEOUT,
3342 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3343 );
3344 if (EFI_ERROR(Status)) {
3345 DEBUG ((EFI_D_ERROR, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
3346 }
3347
3348 return Status;
3349 }
3350
3351 /**
3352 Set interface through XHCI's Configure_Endpoint cmd.
3353
3354 @param Xhc The XHCI Instance.
3355 @param SlotId The slot id to be configured.
3356 @param DeviceSpeed The device's speed.
3357 @param ConfigDesc The pointer to the usb device configuration descriptor.
3358 @param Request USB device request to send.
3359
3360 @retval EFI_SUCCESS Successfully set interface.
3361
3362 **/
3363 EFI_STATUS
3364 EFIAPI
3365 XhcSetInterface (
3366 IN USB_XHCI_INSTANCE *Xhc,
3367 IN UINT8 SlotId,
3368 IN UINT8 DeviceSpeed,
3369 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
3370 IN EFI_USB_DEVICE_REQUEST *Request
3371 )
3372 {
3373 EFI_STATUS Status;
3374 USB_INTERFACE_DESCRIPTOR *IfDescActive;
3375 USB_INTERFACE_DESCRIPTOR *IfDescSet;
3376 USB_INTERFACE_DESCRIPTOR *IfDesc;
3377 USB_ENDPOINT_DESCRIPTOR *EpDesc;
3378 UINTN NumEp;
3379 UINTN EpIndex;
3380 UINT8 EpAddr;
3381 UINT8 Direction;
3382 UINT8 Dci;
3383 UINT8 MaxDci;
3384 EFI_PHYSICAL_ADDRESS PhyAddr;
3385 VOID *RingSeg;
3386
3387 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3388 INPUT_CONTEXT *InputContext;
3389 DEVICE_CONTEXT *OutputContext;
3390 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3391
3392 Status = EFI_SUCCESS;
3393
3394 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3395 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3396 //
3397 // XHCI 4.6.6 Configure Endpoint
3398 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3399 // Context and Add Context flags as follows:
3400 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3401 // Context and Add Context flags to '0'.
3402 //
3403 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3404 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3405 //
3406 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3407 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
3408
3409 ASSERT (ConfigDesc != NULL);
3410
3411 MaxDci = 0;
3412
3413 IfDescActive = NULL;
3414 IfDescSet = NULL;
3415
3416 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3417 while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
3418 if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
3419 if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
3420 if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
3421 //
3422 // Find out the active interface descriptor.
3423 //
3424 IfDescActive = IfDesc;
3425 } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
3426 //
3427 // Find out the interface descriptor to set.
3428 //
3429 IfDescSet = IfDesc;
3430 }
3431 }
3432 }
3433 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3434 }
3435
3436 //
3437 // XHCI 4.6.6 Configure Endpoint
3438 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3439 // Context and Add Context flags as follows:
3440 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3441 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3442 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3443 // the Drop Context flag to '1' and Add Context flag to '0'.
3444 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3445 // and Add Context flags shall be set to '1'.
3446 //
3447 // Below codes are to cover 2), 3) and 4).
3448 //
3449
3450 if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
3451 NumEp = IfDescActive->NumEndpoints;
3452 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
3453 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
3454 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
3455 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3456 }
3457
3458 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
3459 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3460 continue;
3461 }
3462
3463 EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
3464 Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
3465
3466 Dci = XhcEndpointToDci (EpAddr, Direction);
3467 ASSERT (Dci < 32);
3468 if (Dci > MaxDci) {
3469 MaxDci = Dci;
3470 }
3471 //
3472 // XHCI 4.3.6 - Setting Alternate Interfaces
3473 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3474 //
3475 Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);
3476 if (EFI_ERROR (Status)) {
3477 return Status;
3478 }
3479 //
3480 // XHCI 4.3.6 - Setting Alternate Interfaces
3481 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3482 //
3483 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {
3484 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;
3485 if (RingSeg != NULL) {
3486 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
3487 }
3488 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
3489 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
3490 }
3491
3492 //
3493 // Set the Drop Context flag to '1'.
3494 //
3495 InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);
3496
3497 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3498 }
3499
3500 //
3501 // XHCI 4.3.6 - Setting Alternate Interfaces
3502 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3503 // Interface setting, to '0'.
3504 //
3505 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3506 //
3507
3508 //
3509 // XHCI 4.3.6 - Setting Alternate Interfaces
3510 // 4) For each endpoint enabled by the Configure Endpoint Command:
3511 // a. Allocate a Transfer Ring.
3512 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3513 // c. Initialize the Endpoint Context data structure.
3514 //
3515 Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);
3516 if (Dci > MaxDci) {
3517 MaxDci = Dci;
3518 }
3519
3520 InputContext->InputControlContext.Dword2 |= BIT0;
3521 InputContext->Slot.ContextEntries = MaxDci;
3522 //
3523 // XHCI 4.3.6 - Setting Alternate Interfaces
3524 // 5) Issue and successfully complete a Configure Endpoint Command.
3525 //
3526 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3527 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3528 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3529 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3530 CmdTrbCfgEP.CycleBit = 1;
3531 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3532 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3533 DEBUG ((EFI_D_INFO, "SetInterface: Configure Endpoint\n"));
3534 Status = XhcCmdTransfer (
3535 Xhc,
3536 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3537 XHC_GENERIC_TIMEOUT,
3538 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3539 );
3540 if (EFI_ERROR (Status)) {
3541 DEBUG ((EFI_D_ERROR, "SetInterface: Config Endpoint Failed, Status = %r\n", Status));
3542 } else {
3543 //
3544 // Update the active AlternateSetting.
3545 //
3546 Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
3547 }
3548 }
3549
3550 return Status;
3551 }
3552
3553 /**
3554 Set interface through XHCI's Configure_Endpoint cmd.
3555
3556 @param Xhc The XHCI Instance.
3557 @param SlotId The slot id to be configured.
3558 @param DeviceSpeed The device's speed.
3559 @param ConfigDesc The pointer to the usb device configuration descriptor.
3560 @param Request USB device request to send.
3561
3562 @retval EFI_SUCCESS Successfully set interface.
3563
3564 **/
3565 EFI_STATUS
3566 EFIAPI
3567 XhcSetInterface64 (
3568 IN USB_XHCI_INSTANCE *Xhc,
3569 IN UINT8 SlotId,
3570 IN UINT8 DeviceSpeed,
3571 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
3572 IN EFI_USB_DEVICE_REQUEST *Request
3573 )
3574 {
3575 EFI_STATUS Status;
3576 USB_INTERFACE_DESCRIPTOR *IfDescActive;
3577 USB_INTERFACE_DESCRIPTOR *IfDescSet;
3578 USB_INTERFACE_DESCRIPTOR *IfDesc;
3579 USB_ENDPOINT_DESCRIPTOR *EpDesc;
3580 UINTN NumEp;
3581 UINTN EpIndex;
3582 UINT8 EpAddr;
3583 UINT8 Direction;
3584 UINT8 Dci;
3585 UINT8 MaxDci;
3586 EFI_PHYSICAL_ADDRESS PhyAddr;
3587 VOID *RingSeg;
3588
3589 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3590 INPUT_CONTEXT_64 *InputContext;
3591 DEVICE_CONTEXT_64 *OutputContext;
3592 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3593
3594 Status = EFI_SUCCESS;
3595
3596 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3597 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3598 //
3599 // XHCI 4.6.6 Configure Endpoint
3600 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3601 // Context and Add Context flags as follows:
3602 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3603 // Context and Add Context flags to '0'.
3604 //
3605 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3606 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3607 //
3608 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
3609 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
3610
3611 ASSERT (ConfigDesc != NULL);
3612
3613 MaxDci = 0;
3614
3615 IfDescActive = NULL;
3616 IfDescSet = NULL;
3617
3618 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3619 while ((UINTN) IfDesc < ((UINTN) ConfigDesc + ConfigDesc->TotalLength)) {
3620 if ((IfDesc->DescriptorType == USB_DESC_TYPE_INTERFACE) && (IfDesc->Length >= sizeof (USB_INTERFACE_DESCRIPTOR))) {
3621 if (IfDesc->InterfaceNumber == (UINT8) Request->Index) {
3622 if (IfDesc->AlternateSetting == Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[IfDesc->InterfaceNumber]) {
3623 //
3624 // Find out the active interface descriptor.
3625 //
3626 IfDescActive = IfDesc;
3627 } else if (IfDesc->AlternateSetting == (UINT8) Request->Value) {
3628 //
3629 // Find out the interface descriptor to set.
3630 //
3631 IfDescSet = IfDesc;
3632 }
3633 }
3634 }
3635 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3636 }
3637
3638 //
3639 // XHCI 4.6.6 Configure Endpoint
3640 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3641 // Context and Add Context flags as follows:
3642 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3643 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3644 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3645 // the Drop Context flag to '1' and Add Context flag to '0'.
3646 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3647 // and Add Context flags shall be set to '1'.
3648 //
3649 // Below codes are to cover 2), 3) and 4).
3650 //
3651
3652 if ((IfDescActive != NULL) && (IfDescSet != NULL)) {
3653 NumEp = IfDescActive->NumEndpoints;
3654 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDescActive + 1);
3655 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
3656 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
3657 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3658 }
3659
3660 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
3661 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3662 continue;
3663 }
3664
3665 EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
3666 Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
3667
3668 Dci = XhcEndpointToDci (EpAddr, Direction);
3669 ASSERT (Dci < 32);
3670 if (Dci > MaxDci) {
3671 MaxDci = Dci;
3672 }
3673 //
3674 // XHCI 4.3.6 - Setting Alternate Interfaces
3675 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3676 //
3677 Status = XhcStopEndpoint (Xhc, SlotId, Dci, NULL);
3678 if (EFI_ERROR (Status)) {
3679 return Status;
3680 }
3681 //
3682 // XHCI 4.3.6 - Setting Alternate Interfaces
3683 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3684 //
3685 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] != NULL) {
3686 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1])->RingSeg0;
3687 if (RingSeg != NULL) {
3688 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
3689 }
3690 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1]);
3691 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci - 1] = NULL;
3692 }
3693
3694 //
3695 // Set the Drop Context flag to '1'.
3696 //
3697 InputContext->InputControlContext.Dword1 |= (BIT0 << Dci);
3698
3699 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
3700 }
3701
3702 //
3703 // XHCI 4.3.6 - Setting Alternate Interfaces
3704 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3705 // Interface setting, to '0'.
3706 //
3707 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3708 //
3709
3710 //
3711 // XHCI 4.3.6 - Setting Alternate Interfaces
3712 // 4) For each endpoint enabled by the Configure Endpoint Command:
3713 // a. Allocate a Transfer Ring.
3714 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3715 // c. Initialize the Endpoint Context data structure.
3716 //
3717 Dci = XhcInitializeEndpointContext64 (Xhc, SlotId, DeviceSpeed, InputContext, IfDescSet);
3718 if (Dci > MaxDci) {
3719 MaxDci = Dci;
3720 }
3721
3722 InputContext->InputControlContext.Dword2 |= BIT0;
3723 InputContext->Slot.ContextEntries = MaxDci;
3724 //
3725 // XHCI 4.3.6 - Setting Alternate Interfaces
3726 // 5) Issue and successfully complete a Configure Endpoint Command.
3727 //
3728 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3729 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
3730 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3731 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3732 CmdTrbCfgEP.CycleBit = 1;
3733 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3734 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3735 DEBUG ((EFI_D_INFO, "SetInterface64: Configure Endpoint\n"));
3736 Status = XhcCmdTransfer (
3737 Xhc,
3738 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3739 XHC_GENERIC_TIMEOUT,
3740 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3741 );
3742 if (EFI_ERROR (Status)) {
3743 DEBUG ((EFI_D_ERROR, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status));
3744 } else {
3745 //
3746 // Update the active AlternateSetting.
3747 //
3748 Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] = (UINT8) Request->Value;
3749 }
3750 }
3751
3752 return Status;
3753 }
3754
3755 /**
3756 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3757
3758 @param Xhc The XHCI Instance.
3759 @param SlotId The slot id to be evaluated.
3760 @param MaxPacketSize The max packet size supported by the device control transfer.
3761
3762 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3763
3764 **/
3765 EFI_STATUS
3766 EFIAPI
3767 XhcEvaluateContext (
3768 IN USB_XHCI_INSTANCE *Xhc,
3769 IN UINT8 SlotId,
3770 IN UINT32 MaxPacketSize
3771 )
3772 {
3773 EFI_STATUS Status;
3774 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
3775 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3776 INPUT_CONTEXT *InputContext;
3777 EFI_PHYSICAL_ADDRESS PhyAddr;
3778
3779 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
3780
3781 //
3782 // 4.6.7 Evaluate Context
3783 //
3784 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3785 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3786
3787 InputContext->InputControlContext.Dword2 |= BIT1;
3788 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
3789
3790 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
3791 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3792 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
3793 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3794 CmdTrbEvalu.CycleBit = 1;
3795 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
3796 CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3797 DEBUG ((EFI_D_INFO, "Evaluate context\n"));
3798 Status = XhcCmdTransfer (
3799 Xhc,
3800 (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
3801 XHC_GENERIC_TIMEOUT,
3802 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3803 );
3804 if (EFI_ERROR (Status)) {
3805 DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
3806 }
3807 return Status;
3808 }
3809
3810 /**
3811 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3812
3813 @param Xhc The XHCI Instance.
3814 @param SlotId The slot id to be evaluated.
3815 @param MaxPacketSize The max packet size supported by the device control transfer.
3816
3817 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3818
3819 **/
3820 EFI_STATUS
3821 EFIAPI
3822 XhcEvaluateContext64 (
3823 IN USB_XHCI_INSTANCE *Xhc,
3824 IN UINT8 SlotId,
3825 IN UINT32 MaxPacketSize
3826 )
3827 {
3828 EFI_STATUS Status;
3829 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
3830 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3831 INPUT_CONTEXT_64 *InputContext;
3832 EFI_PHYSICAL_ADDRESS PhyAddr;
3833
3834 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
3835
3836 //
3837 // 4.6.7 Evaluate Context
3838 //
3839 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3840 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
3841
3842 InputContext->InputControlContext.Dword2 |= BIT1;
3843 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
3844
3845 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
3846 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
3847 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
3848 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3849 CmdTrbEvalu.CycleBit = 1;
3850 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
3851 CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3852 DEBUG ((EFI_D_INFO, "Evaluate context\n"));
3853 Status = XhcCmdTransfer (
3854 Xhc,
3855 (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
3856 XHC_GENERIC_TIMEOUT,
3857 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3858 );
3859 if (EFI_ERROR (Status)) {
3860 DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
3861 }
3862 return Status;
3863 }
3864
3865
3866 /**
3867 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3868
3869 @param Xhc The XHCI Instance.
3870 @param SlotId The slot id to be configured.
3871 @param PortNum The total number of downstream port supported by the hub.
3872 @param TTT The TT think time of the hub device.
3873 @param MTT The multi-TT of the hub device.
3874
3875 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3876
3877 **/
3878 EFI_STATUS
3879 XhcConfigHubContext (
3880 IN USB_XHCI_INSTANCE *Xhc,
3881 IN UINT8 SlotId,
3882 IN UINT8 PortNum,
3883 IN UINT8 TTT,
3884 IN UINT8 MTT
3885 )
3886 {
3887 EFI_STATUS Status;
3888 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3889 INPUT_CONTEXT *InputContext;
3890 DEVICE_CONTEXT *OutputContext;
3891 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3892 EFI_PHYSICAL_ADDRESS PhyAddr;
3893
3894 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
3895 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3896 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3897
3898 //
3899 // 4.6.7 Evaluate Context
3900 //
3901 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3902
3903 InputContext->InputControlContext.Dword2 |= BIT0;
3904
3905 //
3906 // Copy the slot context from OutputContext to Input context
3907 //
3908 CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
3909 InputContext->Slot.Hub = 1;
3910 InputContext->Slot.PortNum = PortNum;
3911 InputContext->Slot.TTT = TTT;
3912 InputContext->Slot.MTT = MTT;
3913
3914 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3915 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3916 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3917 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3918 CmdTrbCfgEP.CycleBit = 1;
3919 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3920 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3921 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
3922 Status = XhcCmdTransfer (
3923 Xhc,
3924 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3925 XHC_GENERIC_TIMEOUT,
3926 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3927 );
3928 if (EFI_ERROR (Status)) {
3929 DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
3930 }
3931 return Status;
3932 }
3933
3934 /**
3935 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3936
3937 @param Xhc The XHCI Instance.
3938 @param SlotId The slot id to be configured.
3939 @param PortNum The total number of downstream port supported by the hub.
3940 @param TTT The TT think time of the hub device.
3941 @param MTT The multi-TT of the hub device.
3942
3943 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3944
3945 **/
3946 EFI_STATUS
3947 XhcConfigHubContext64 (
3948 IN USB_XHCI_INSTANCE *Xhc,
3949 IN UINT8 SlotId,
3950 IN UINT8 PortNum,
3951 IN UINT8 TTT,
3952 IN UINT8 MTT
3953 )
3954 {
3955 EFI_STATUS Status;
3956 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3957 INPUT_CONTEXT_64 *InputContext;
3958 DEVICE_CONTEXT_64 *OutputContext;
3959 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3960 EFI_PHYSICAL_ADDRESS PhyAddr;
3961
3962 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
3963 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3964 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3965
3966 //
3967 // 4.6.7 Evaluate Context
3968 //
3969 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
3970
3971 InputContext->InputControlContext.Dword2 |= BIT0;
3972
3973 //
3974 // Copy the slot context from OutputContext to Input context
3975 //
3976 CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
3977 InputContext->Slot.Hub = 1;
3978 InputContext->Slot.PortNum = PortNum;
3979 InputContext->Slot.TTT = TTT;
3980 InputContext->Slot.MTT = MTT;
3981
3982 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3983 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
3984 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3985 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3986 CmdTrbCfgEP.CycleBit = 1;
3987 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3988 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3989 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
3990 Status = XhcCmdTransfer (
3991 Xhc,
3992 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3993 XHC_GENERIC_TIMEOUT,
3994 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3995 );
3996 if (EFI_ERROR (Status)) {
3997 DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
3998 }
3999 return Status;
4000 }
4001
4002
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