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MdeModulePkg: Replace BSD License with BSD+Patent License
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h
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92870c98 1/** @file\r
2\r
3 This file contains the definition for XHCI host controller schedule routines.\r
4\r
d1102dba 5Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
9d510e61 6SPDX-License-Identifier: BSD-2-Clause-Patent\r
92870c98 7\r
8**/\r
9\r
10#ifndef _EFI_XHCI_SCHED_H_\r
11#define _EFI_XHCI_SCHED_H_\r
12\r
13#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
14\r
15//\r
16// Transfer types, used in URB to identify the transfer type\r
17//\r
18#define XHC_CTRL_TRANSFER 0x01\r
19#define XHC_BULK_TRANSFER 0x02\r
20#define XHC_INT_TRANSFER_SYNC 0x04\r
21#define XHC_INT_TRANSFER_ASYNC 0x08\r
22#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
23\r
24//\r
25// 6.4.6 TRB Types\r
26//\r
27#define TRB_TYPE_NORMAL 1\r
28#define TRB_TYPE_SETUP_STAGE 2\r
29#define TRB_TYPE_DATA_STAGE 3\r
30#define TRB_TYPE_STATUS_STAGE 4\r
31#define TRB_TYPE_ISOCH 5\r
32#define TRB_TYPE_LINK 6\r
33#define TRB_TYPE_EVENT_DATA 7\r
34#define TRB_TYPE_NO_OP 8\r
35#define TRB_TYPE_EN_SLOT 9\r
36#define TRB_TYPE_DIS_SLOT 10\r
37#define TRB_TYPE_ADDRESS_DEV 11\r
38#define TRB_TYPE_CON_ENDPOINT 12\r
39#define TRB_TYPE_EVALU_CONTXT 13\r
40#define TRB_TYPE_RESET_ENDPOINT 14\r
41#define TRB_TYPE_STOP_ENDPOINT 15\r
42#define TRB_TYPE_SET_TR_DEQUE 16\r
43#define TRB_TYPE_RESET_DEV 17\r
44#define TRB_TYPE_GET_PORT_BANW 21\r
45#define TRB_TYPE_FORCE_HEADER 22\r
46#define TRB_TYPE_NO_OP_COMMAND 23\r
47#define TRB_TYPE_TRANS_EVENT 32\r
48#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
49#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
50#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
51#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
52#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
53\r
54//\r
55// Endpoint Type (EP Type).\r
56//\r
57#define ED_NOT_VALID 0\r
58#define ED_ISOCH_OUT 1\r
59#define ED_BULK_OUT 2\r
60#define ED_INTERRUPT_OUT 3\r
61#define ED_CONTROL_BIDIR 4\r
62#define ED_ISOCH_IN 5\r
63#define ED_BULK_IN 6\r
64#define ED_INTERRUPT_IN 7\r
65\r
66//\r
67// 6.4.5 TRB Completion Codes\r
68//\r
69#define TRB_COMPLETION_INVALID 0\r
70#define TRB_COMPLETION_SUCCESS 1\r
71#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
72#define TRB_COMPLETION_BABBLE_ERROR 3\r
73#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
74#define TRB_COMPLETION_TRB_ERROR 5\r
75#define TRB_COMPLETION_STALL_ERROR 6\r
76#define TRB_COMPLETION_SHORT_PACKET 13\r
49be9c3c
RN		 77#define TRB_COMPLETION_STOPPED 26\r
78#define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27\r
92870c98 79\r
80//\r
a9292c13 81// The topology string used to present usb device location\r
92870c98 82//\r
a9292c13 83typedef struct _USB_DEV_TOPOLOGY {\r
84 //\r
85 // The tier concatenation of down stream port.\r
86 //\r
87 UINT32 RouteString:20;\r
88 //\r
89 // The root port number of the chain.\r
90 //\r
91 UINT32 RootPortNum:8;\r
92 //\r
93 // The Tier the device reside.\r
94 //\r
95 UINT32 TierNum:4;\r
96} USB_DEV_TOPOLOGY;\r
97\r
98//\r
99// USB Device's RouteChart\r
100//\r
101typedef union _USB_DEV_ROUTE {\r
102 UINT32 Dword;\r
103 USB_DEV_TOPOLOGY Route;\r
92870c98 104} USB_DEV_ROUTE;\r
105\r
106//\r
107// Endpoint address and its capabilities\r
108//\r
109typedef struct _USB_ENDPOINT {\r
6b4483cd 110 //\r
111 // Store logical device address assigned by UsbBus\r
112 // It's because some XHCI host controllers may assign the same physcial device\r
113 // address for those devices inserted at different root port.\r
114 //\r
115 UINT8 BusAddr;\r
92870c98 116 UINT8 DevAddr;\r
117 UINT8 EpAddr;\r
118 EFI_USB_DATA_DIRECTION Direction;\r
119 UINT8 DevSpeed;\r
120 UINTN MaxPacket;\r
121 UINTN Type;\r
122} USB_ENDPOINT;\r
123\r
124//\r
a9292c13 125// TRB Template\r
92870c98 126//\r
a9292c13 127typedef struct _TRB_TEMPLATE {\r
128 UINT32 Parameter1;\r
129\r
130 UINT32 Parameter2;\r
131\r
132 UINT32 Status;\r
133\r
92870c98 134 UINT32 CycleBit:1;\r
135 UINT32 RsvdZ1:9;\r
136 UINT32 Type:6;\r
a9292c13 137 UINT32 Control:16;\r
138} TRB_TEMPLATE;\r
92870c98 139\r
140typedef struct _TRANSFER_RING {\r
141 VOID *RingSeg0;\r
142 UINTN TrbNumber;\r
a9292c13 143 TRB_TEMPLATE *RingEnqueue;\r
144 TRB_TEMPLATE *RingDequeue;\r
92870c98 145 UINT32 RingPCS;\r
146} TRANSFER_RING;\r
147\r
148typedef struct _EVENT_RING {\r
92870c98 149 VOID *ERSTBase;\r
150 VOID *EventRingSeg0;\r
151 UINTN TrbNumber;\r
a9292c13 152 TRB_TEMPLATE *EventRingEnqueue;\r
153 TRB_TEMPLATE *EventRingDequeue;\r
92870c98 154 UINT32 EventRingCCS;\r
155} EVENT_RING;\r
156\r
157//\r
158// URB (Usb Request Block) contains information for all kinds of\r
159// usb requests.\r
160//\r
161typedef struct _URB {\r
162 UINT32 Signature;\r
163 LIST_ENTRY UrbList;\r
164 //\r
165 // Usb Device URB related information\r
166 //\r
167 USB_ENDPOINT Ep;\r
168 EFI_USB_DEVICE_REQUEST *Request;\r
169 VOID *Data;\r
170 UINTN DataLen;\r
1847ed0b
EL		 171 VOID *DataPhy;\r
172 VOID *DataMap;\r
92870c98 173 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
174 VOID *Context;\r
175 //\r
176 // Execute result\r
177 //\r
178 UINT32 Result;\r
179 //\r
180 // completed data length\r
181 //\r
182 UINTN Completed;\r
183 //\r
184 // Command/Tranfer Ring info\r
185 //\r
186 TRANSFER_RING *Ring;\r
a9292c13 187 TRB_TEMPLATE *TrbStart;\r
188 TRB_TEMPLATE *TrbEnd;\r
92870c98 189 UINTN TrbNum;\r
a50f7c4c 190 BOOLEAN StartDone;\r
191 BOOLEAN EndDone;\r
192 BOOLEAN Finished;\r
193\r
194 TRB_TEMPLATE *EvtTrb;\r
92870c98 195} URB;\r
196\r
92870c98 197//\r
198// 6.5 Event Ring Segment Table\r
199// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r
200// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r
201// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r
202// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r
203//\r
204typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
205 UINT32 PtrLo;\r
206 UINT32 PtrHi;\r
207 UINT32 RingTrbSize:16;\r
208 UINT32 RsvdZ1:16;\r
209 UINT32 RsvdZ2;\r
210} EVENT_RING_SEG_TABLE_ENTRY;\r
211\r
212//\r
213// 6.4.1.1 Normal TRB\r
214// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
215// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
216// Rings, and to define the Data stage information for Control Transfer Rings.\r
217//\r
218typedef struct _TRANSFER_TRB_NORMAL {\r
219 UINT32 TRBPtrLo;\r
a9292c13 220\r
92870c98 221 UINT32 TRBPtrHi;\r
a9292c13 222\r
39e97c39 223 UINT32 Length:17;\r
92870c98 224 UINT32 TDSize:5;\r
225 UINT32 IntTarget:10;\r
a9292c13 226\r
92870c98 227 UINT32 CycleBit:1;\r
228 UINT32 ENT:1;\r
229 UINT32 ISP:1;\r
230 UINT32 NS:1;\r
231 UINT32 CH:1;\r
232 UINT32 IOC:1;\r
233 UINT32 IDT:1;\r
234 UINT32 RsvdZ1:2;\r
235 UINT32 BEI:1;\r
236 UINT32 Type:6;\r
237 UINT32 RsvdZ2:16;\r
238} TRANSFER_TRB_NORMAL;\r
239\r
240//\r
241// 6.4.1.2.1 Setup Stage TRB\r
242// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r
243//\r
a9292c13 244typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r
92870c98 245 UINT32 bmRequestType:8;\r
246 UINT32 bRequest:8;\r
247 UINT32 wValue:16;\r
248\r
249 UINT32 wIndex:16;\r
250 UINT32 wLength:16;\r
251\r
39e97c39 252 UINT32 Length:17;\r
92870c98 253 UINT32 RsvdZ1:5;\r
254 UINT32 IntTarget:10;\r
255\r
256 UINT32 CycleBit:1;\r
257 UINT32 RsvdZ2:4;\r
258 UINT32 IOC:1;\r
259 UINT32 IDT:1;\r
260 UINT32 RsvdZ3:3;\r
261 UINT32 Type:6;\r
262 UINT32 TRT:2;\r
263 UINT32 RsvdZ4:14;\r
264} TRANSFER_TRB_CONTROL_SETUP;\r
265\r
266//\r
267// 6.4.1.2.2 Data Stage TRB\r
268// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
269//\r
270typedef struct _TRANSFER_TRB_CONTROL_DATA {\r
271 UINT32 TRBPtrLo;\r
a9292c13 272\r
92870c98 273 UINT32 TRBPtrHi;\r
a9292c13 274\r
39e97c39 275 UINT32 Length:17;\r
92870c98 276 UINT32 TDSize:5;\r
277 UINT32 IntTarget:10;\r
a9292c13 278\r
92870c98 279 UINT32 CycleBit:1;\r
280 UINT32 ENT:1;\r
281 UINT32 ISP:1;\r
282 UINT32 NS:1;\r
283 UINT32 CH:1;\r
284 UINT32 IOC:1;\r
285 UINT32 IDT:1;\r
286 UINT32 RsvdZ1:3;\r
287 UINT32 Type:6;\r
288 UINT32 DIR:1;\r
289 UINT32 RsvdZ2:15;\r
290} TRANSFER_TRB_CONTROL_DATA;\r
291\r
292//\r
293// 6.4.1.2.2 Data Stage TRB\r
294// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
295//\r
296typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r
297 UINT32 RsvdZ1;\r
298 UINT32 RsvdZ2;\r
a9292c13 299\r
92870c98 300 UINT32 RsvdZ3:22;\r
301 UINT32 IntTarget:10;\r
a9292c13 302\r
92870c98 303 UINT32 CycleBit:1;\r
304 UINT32 ENT:1;\r
305 UINT32 RsvdZ4:2;\r
306 UINT32 CH:1;\r
307 UINT32 IOC:1;\r
308 UINT32 RsvdZ5:4;\r
309 UINT32 Type:6;\r
310 UINT32 DIR:1;\r
311 UINT32 RsvdZ6:15;\r
312} TRANSFER_TRB_CONTROL_STATUS;\r
313\r
314//\r
315// 6.4.2.1 Transfer Event TRB\r
316// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
317// for more information on the use and operation of Transfer Events.\r
318//\r
319typedef struct _EVT_TRB_TRANSFER {\r
320 UINT32 TRBPtrLo;\r
a9292c13 321\r
92870c98 322 UINT32 TRBPtrHi;\r
a9292c13 323\r
39e97c39 324 UINT32 Length:24;\r
a9292c13 325 UINT32 Completecode:8;\r
326\r
92870c98 327 UINT32 CycleBit:1;\r
328 UINT32 RsvdZ1:1;\r
329 UINT32 ED:1;\r
330 UINT32 RsvdZ2:7;\r
331 UINT32 Type:6;\r
a9292c13 332 UINT32 EndpointId:5;\r
92870c98 333 UINT32 RsvdZ3:3;\r
334 UINT32 SlotId:8;\r
335} EVT_TRB_TRANSFER;\r
336\r
337//\r
338// 6.4.2.2 Command Completion Event TRB\r
339// A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r
340// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r
341//\r
a9292c13 342typedef struct _EVT_TRB_COMMAND_COMPLETION {\r
92870c98 343 UINT32 TRBPtrLo;\r
a9292c13 344\r
92870c98 345 UINT32 TRBPtrHi;\r
a9292c13 346\r
92870c98 347 UINT32 RsvdZ2:24;\r
a9292c13 348 UINT32 Completecode:8;\r
349\r
92870c98 350 UINT32 CycleBit:1;\r
351 UINT32 RsvdZ3:9;\r
352 UINT32 Type:6;\r
353 UINT32 VFID:8;\r
354 UINT32 SlotId:8;\r
a9292c13 355} EVT_TRB_COMMAND_COMPLETION;\r
356\r
357typedef union _TRB {\r
358 TRB_TEMPLATE TrbTemplate;\r
359 TRANSFER_TRB_NORMAL TrbNormal;\r
360 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r
361 TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r
362 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r
363} TRB;\r
92870c98 364\r
365//\r
366// 6.4.3.1 No Op Command TRB\r
367// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r
a9292c13 368// mechanisms offered by the xHCI.\r
92870c98 369//\r
370typedef struct _CMD_TRB_NO_OP {\r
371 UINT32 RsvdZ0;\r
372 UINT32 RsvdZ1;\r
373 UINT32 RsvdZ2;\r
a9292c13 374\r
92870c98 375 UINT32 CycleBit:1;\r
376 UINT32 RsvdZ3:9;\r
377 UINT32 Type:6;\r
378 UINT32 RsvdZ4:16;\r
379} CMD_TRB_NO_OP;\r
380\r
381//\r
382// 6.4.3.2 Enable Slot Command TRB\r
383// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r
384// selected slot to the host in a Command Completion Event.\r
385//\r
a9292c13 386typedef struct _CMD_TRB_ENABLE_SLOT {\r
92870c98 387 UINT32 RsvdZ0;\r
388 UINT32 RsvdZ1;\r
389 UINT32 RsvdZ2;\r
a9292c13 390\r
92870c98 391 UINT32 CycleBit:1;\r
392 UINT32 RsvdZ3:9;\r
393 UINT32 Type:6;\r
394 UINT32 RsvdZ4:16;\r
a9292c13 395} CMD_TRB_ENABLE_SLOT;\r
92870c98 396\r
397//\r
398// 6.4.3.3 Disable Slot Command TRB\r
399// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r
400// internal xHC resources assigned to the slot.\r
401//\r
a9292c13 402typedef struct _CMD_TRB_DISABLE_SLOT {\r
92870c98 403 UINT32 RsvdZ0;\r
404 UINT32 RsvdZ1;\r
405 UINT32 RsvdZ2;\r
a9292c13 406\r
92870c98 407 UINT32 CycleBit:1;\r
408 UINT32 RsvdZ3:9;\r
409 UINT32 Type:6;\r
410 UINT32 RsvdZ4:8;\r
411 UINT32 SlotId:8;\r
a9292c13 412} CMD_TRB_DISABLE_SLOT;\r
92870c98 413\r
414//\r
415// 6.4.3.4 Address Device Command TRB\r
416// The Address Device Command TRB transitions the selected Device Context from the Default to the\r
417// Addressed state and causes the xHC to select an address for the USB device in the Default State and\r
418// issue a SET_ADDRESS request to the USB device.\r
419//\r
a9292c13 420typedef struct _CMD_TRB_ADDRESS_DEVICE {\r
92870c98 421 UINT32 PtrLo;\r
a9292c13 422\r
92870c98 423 UINT32 PtrHi;\r
a9292c13 424\r
92870c98 425 UINT32 RsvdZ1;\r
a9292c13 426\r
92870c98 427 UINT32 CycleBit:1;\r
428 UINT32 RsvdZ2:8;\r
429 UINT32 BSR:1;\r
430 UINT32 Type:6;\r
431 UINT32 RsvdZ3:8;\r
432 UINT32 SlotId:8;\r
a9292c13 433} CMD_TRB_ADDRESS_DEVICE;\r
92870c98 434\r
435//\r
436// 6.4.3.5 Configure Endpoint Command TRB\r
437// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r
438// endpoints selected by the command.\r
439//\r
a9292c13 440typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r
92870c98 441 UINT32 PtrLo;\r
a9292c13 442\r
92870c98 443 UINT32 PtrHi;\r
a9292c13 444\r
92870c98 445 UINT32 RsvdZ1;\r
a9292c13 446\r
92870c98 447 UINT32 CycleBit:1;\r
448 UINT32 RsvdZ2:8;\r
449 UINT32 DC:1;\r
450 UINT32 Type:6;\r
451 UINT32 RsvdZ3:8;\r
452 UINT32 SlotId:8;\r
a9292c13 453} CMD_TRB_CONFIG_ENDPOINT;\r
92870c98 454\r
455//\r
456// 6.4.3.6 Evaluate Context Command TRB\r
457// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r
458// Context data structures in the Device Context have been modified by system software and that the xHC\r
459// shall evaluate any changes\r
460//\r
a9292c13 461typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r
92870c98 462 UINT32 PtrLo;\r
a9292c13 463\r
92870c98 464 UINT32 PtrHi;\r
a9292c13 465\r
92870c98 466 UINT32 RsvdZ1;\r
a9292c13 467\r
92870c98 468 UINT32 CycleBit:1;\r
469 UINT32 RsvdZ2:9;\r
470 UINT32 Type:6;\r
471 UINT32 RsvdZ3:8;\r
472 UINT32 SlotId:8;\r
a9292c13 473} CMD_TRB_EVALUATE_CONTEXT;\r
92870c98 474\r
475//\r
476// 6.4.3.7 Reset Endpoint Command TRB\r
477// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r
478//\r
a9292c13 479typedef struct _CMD_TRB_RESET_ENDPOINT {\r
92870c98 480 UINT32 RsvdZ0;\r
481 UINT32 RsvdZ1;\r
482 UINT32 RsvdZ2;\r
a9292c13 483\r
92870c98 484 UINT32 CycleBit:1;\r
485 UINT32 RsvdZ3:8;\r
486 UINT32 TSP:1;\r
487 UINT32 Type:6;\r
488 UINT32 EDID:5;\r
489 UINT32 RsvdZ4:3;\r
490 UINT32 SlotId:8;\r
a9292c13 491} CMD_TRB_RESET_ENDPOINT;\r
92870c98 492\r
493//\r
494// 6.4.3.8 Stop Endpoint Command TRB\r
495// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r
496// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r
497//\r
a9292c13 498typedef struct _CMD_TRB_STOP_ENDPOINT {\r
92870c98 499 UINT32 RsvdZ0;\r
500 UINT32 RsvdZ1;\r
501 UINT32 RsvdZ2;\r
a9292c13 502\r
92870c98 503 UINT32 CycleBit:1;\r
504 UINT32 RsvdZ3:9;\r
505 UINT32 Type:6;\r
506 UINT32 EDID:5;\r
507 UINT32 RsvdZ4:2;\r
508 UINT32 SP:1;\r
509 UINT32 SlotId:8;\r
a9292c13 510} CMD_TRB_STOP_ENDPOINT;\r
92870c98 511\r
512//\r
513// 6.4.3.9 Set TR Dequeue Pointer Command TRB\r
514// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r
515// Pointer and DCS fields of an Endpoint or Stream Context.\r
516//\r
a9292c13 517typedef struct _CMD_SET_TR_DEQ_POINTER {\r
92870c98 518 UINT32 PtrLo;\r
a9292c13 519\r
92870c98 520 UINT32 PtrHi;\r
a9292c13 521\r
92870c98 522 UINT32 RsvdZ1:16;\r
523 UINT32 StreamID:16;\r
a9292c13 524\r
92870c98 525 UINT32 CycleBit:1;\r
526 UINT32 RsvdZ2:9;\r
527 UINT32 Type:6;\r
528 UINT32 Endpoint:5;\r
529 UINT32 RsvdZ3:3;\r
530 UINT32 SlotId:8;\r
a9292c13 531} CMD_SET_TR_DEQ_POINTER;\r
92870c98 532\r
533//\r
a9292c13 534// 6.4.4.1 Link TRB\r
92870c98 535// A Link TRB provides support for non-contiguous TRB Rings.\r
536//\r
a9292c13 537typedef struct _LINK_TRB {\r
92870c98 538 UINT32 PtrLo;\r
a9292c13 539\r
92870c98 540 UINT32 PtrHi;\r
a9292c13 541\r
92870c98 542 UINT32 RsvdZ1:22;\r
543 UINT32 InterTarget:10;\r
a9292c13 544\r
92870c98 545 UINT32 CycleBit:1;\r
546 UINT32 TC:1;\r
547 UINT32 RsvdZ2:2;\r
548 UINT32 CH:1;\r
549 UINT32 IOC:1;\r
550 UINT32 RsvdZ3:4;\r
551 UINT32 Type:6;\r
552 UINT32 RsvdZ4:16;\r
a9292c13 553} LINK_TRB;\r
92870c98 554\r
555//\r
556// 6.2.2 Slot Context\r
557//\r
558typedef struct _SLOT_CONTEXT {\r
a9292c13 559 UINT32 RouteString:20;\r
92870c98 560 UINT32 Speed:4;\r
561 UINT32 RsvdZ1:1;\r
562 UINT32 MTT:1;\r
563 UINT32 Hub:1;\r
564 UINT32 ContextEntries:5;\r
565\r
566 UINT32 MaxExitLatency:16;\r
567 UINT32 RootHubPortNum:8;\r
568 UINT32 PortNum:8;\r
569\r
570 UINT32 TTHubSlotId:8;\r
571 UINT32 TTPortNum:8;\r
572 UINT32 TTT:2;\r
573 UINT32 RsvdZ2:4;\r
574 UINT32 InterTarget:10;\r
575\r
576 UINT32 DeviceAddress:8;\r
577 UINT32 RsvdZ3:19;\r
578 UINT32 SlotState:5;\r
579\r
580 UINT32 RsvdZ4;\r
581 UINT32 RsvdZ5;\r
582 UINT32 RsvdZ6;\r
583 UINT32 RsvdZ7;\r
584} SLOT_CONTEXT;\r
585\r
6b4483cd 586typedef struct _SLOT_CONTEXT_64 {\r
587 UINT32 RouteString:20;\r
588 UINT32 Speed:4;\r
589 UINT32 RsvdZ1:1;\r
590 UINT32 MTT:1;\r
591 UINT32 Hub:1;\r
592 UINT32 ContextEntries:5;\r
593\r
594 UINT32 MaxExitLatency:16;\r
595 UINT32 RootHubPortNum:8;\r
596 UINT32 PortNum:8;\r
597\r
598 UINT32 TTHubSlotId:8;\r
599 UINT32 TTPortNum:8;\r
600 UINT32 TTT:2;\r
601 UINT32 RsvdZ2:4;\r
602 UINT32 InterTarget:10;\r
603\r
604 UINT32 DeviceAddress:8;\r
605 UINT32 RsvdZ3:19;\r
606 UINT32 SlotState:5;\r
607\r
608 UINT32 RsvdZ4;\r
609 UINT32 RsvdZ5;\r
610 UINT32 RsvdZ6;\r
611 UINT32 RsvdZ7;\r
612\r
613 UINT32 RsvdZ8;\r
614 UINT32 RsvdZ9;\r
615 UINT32 RsvdZ10;\r
616 UINT32 RsvdZ11;\r
d1102dba 617\r
6b4483cd 618 UINT32 RsvdZ12;\r
619 UINT32 RsvdZ13;\r
620 UINT32 RsvdZ14;\r
621 UINT32 RsvdZ15;\r
622\r
623} SLOT_CONTEXT_64;\r
624\r
625\r
92870c98 626//\r
627// 6.2.3 Endpoint Context\r
628//\r
629typedef struct _ENDPOINT_CONTEXT {\r
630 UINT32 EPState:3;\r
631 UINT32 RsvdZ1:5;\r
632 UINT32 Mult:2;\r
633 UINT32 MaxPStreams:5;\r
634 UINT32 LSA:1;\r
635 UINT32 Interval:8;\r
636 UINT32 RsvdZ2:8;\r
637\r
638 UINT32 RsvdZ3:1;\r
639 UINT32 CErr:2;\r
640 UINT32 EPType:3;\r
641 UINT32 RsvdZ4:1;\r
642 UINT32 HID:1;\r
643 UINT32 MaxBurstSize:8;\r
644 UINT32 MaxPacketSize:16;\r
645\r
646 UINT32 PtrLo;\r
647\r
648 UINT32 PtrHi;\r
649\r
650 UINT32 AverageTRBLength:16;\r
651 UINT32 MaxESITPayload:16;\r
652\r
653 UINT32 RsvdZ5;\r
654 UINT32 RsvdZ6;\r
655 UINT32 RsvdZ7;\r
656} ENDPOINT_CONTEXT;\r
657\r
6b4483cd 658typedef struct _ENDPOINT_CONTEXT_64 {\r
659 UINT32 EPState:3;\r
660 UINT32 RsvdZ1:5;\r
661 UINT32 Mult:2;\r
662 UINT32 MaxPStreams:5;\r
663 UINT32 LSA:1;\r
664 UINT32 Interval:8;\r
665 UINT32 RsvdZ2:8;\r
666\r
667 UINT32 RsvdZ3:1;\r
668 UINT32 CErr:2;\r
669 UINT32 EPType:3;\r
670 UINT32 RsvdZ4:1;\r
671 UINT32 HID:1;\r
672 UINT32 MaxBurstSize:8;\r
673 UINT32 MaxPacketSize:16;\r
674\r
675 UINT32 PtrLo;\r
676\r
677 UINT32 PtrHi;\r
678\r
679 UINT32 AverageTRBLength:16;\r
680 UINT32 MaxESITPayload:16;\r
681\r
682 UINT32 RsvdZ5;\r
683 UINT32 RsvdZ6;\r
684 UINT32 RsvdZ7;\r
d1102dba 685\r
6b4483cd 686 UINT32 RsvdZ8;\r
687 UINT32 RsvdZ9;\r
688 UINT32 RsvdZ10;\r
689 UINT32 RsvdZ11;\r
d1102dba 690\r
6b4483cd 691 UINT32 RsvdZ12;\r
692 UINT32 RsvdZ13;\r
693 UINT32 RsvdZ14;\r
694 UINT32 RsvdZ15;\r
695\r
696} ENDPOINT_CONTEXT_64;\r
697\r
698\r
92870c98 699//\r
700// 6.2.5.1 Input Control Context\r
701//\r
702typedef struct _INPUT_CONTRL_CONTEXT {\r
703 UINT32 Dword1;\r
704 UINT32 Dword2;\r
705 UINT32 RsvdZ1;\r
706 UINT32 RsvdZ2;\r
707 UINT32 RsvdZ3;\r
708 UINT32 RsvdZ4;\r
709 UINT32 RsvdZ5;\r
710 UINT32 RsvdZ6;\r
711} INPUT_CONTRL_CONTEXT;\r
712\r
6b4483cd 713typedef struct _INPUT_CONTRL_CONTEXT_64 {\r
714 UINT32 Dword1;\r
715 UINT32 Dword2;\r
716 UINT32 RsvdZ1;\r
717 UINT32 RsvdZ2;\r
718 UINT32 RsvdZ3;\r
719 UINT32 RsvdZ4;\r
720 UINT32 RsvdZ5;\r
721 UINT32 RsvdZ6;\r
722 UINT32 RsvdZ7;\r
723 UINT32 RsvdZ8;\r
724 UINT32 RsvdZ9;\r
725 UINT32 RsvdZ10;\r
726 UINT32 RsvdZ11;\r
727 UINT32 RsvdZ12;\r
728 UINT32 RsvdZ13;\r
729 UINT32 RsvdZ14;\r
730} INPUT_CONTRL_CONTEXT_64;\r
731\r
92870c98 732//\r
733// 6.2.1 Device Context\r
734//\r
735typedef struct _DEVICE_CONTEXT {\r
736 SLOT_CONTEXT Slot;\r
737 ENDPOINT_CONTEXT EP[31];\r
738} DEVICE_CONTEXT;\r
739\r
6b4483cd 740typedef struct _DEVICE_CONTEXT_64 {\r
741 SLOT_CONTEXT_64 Slot;\r
742 ENDPOINT_CONTEXT_64 EP[31];\r
743} DEVICE_CONTEXT_64;\r
744\r
92870c98 745//\r
746// 6.2.5 Input Context\r
747//\r
748typedef struct _INPUT_CONTEXT {\r
749 INPUT_CONTRL_CONTEXT InputControlContext;\r
750 SLOT_CONTEXT Slot;\r
751 ENDPOINT_CONTEXT EP[31];\r
752} INPUT_CONTEXT;\r
753\r
6b4483cd 754typedef struct _INPUT_CONTEXT_64 {\r
755 INPUT_CONTRL_CONTEXT_64 InputControlContext;\r
756 SLOT_CONTEXT_64 Slot;\r
757 ENDPOINT_CONTEXT_64 EP[31];\r
758} INPUT_CONTEXT_64;\r
759\r
760\r
92870c98 761/**\r
762 Initialize the XHCI host controller for schedule.\r
763\r
a9292c13 764 @param Xhc The XHCI Instance to be initialized.\r
92870c98 765\r
766**/\r
767VOID\r
768XhcInitSched (\r
a9292c13 769 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 770 );\r
771\r
772/**\r
773 Free the resouce allocated at initializing schedule.\r
774\r
a9292c13 775 @param Xhc The XHCI Instance.\r
92870c98 776\r
777**/\r
778VOID\r
779XhcFreeSched (\r
a9292c13 780 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 781 );\r
782\r
783/**\r
784 Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r
785\r
a9292c13 786 @param Xhc The XHCI Instance.\r
92870c98 787 @param Urb The URB to be rung.\r
788\r
789 @retval EFI_SUCCESS Successfully ring the door bell.\r
790\r
791**/\r
792EFI_STATUS\r
793RingIntTransferDoorBell (\r
a9292c13 794 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 795 IN URB *Urb\r
796 );\r
797\r
798/**\r
799 Execute the transfer by polling the URB. This is a synchronous operation.\r
800\r
a9292c13 801 @param Xhc The XHCI Instance.\r
92870c98 802 @param CmdTransfer The executed URB is for cmd transfer or not.\r
803 @param Urb The URB to execute.\r
a9292c13 804 @param Timeout The time to wait before abort, in millisecond.\r
92870c98 805\r
806 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
807 @return EFI_TIMEOUT The transfer failed due to time out.\r
808 @return EFI_SUCCESS The transfer finished OK.\r
809\r
810**/\r
811EFI_STATUS\r
812XhcExecTransfer (\r
a9292c13 813 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 814 IN BOOLEAN CmdTransfer,\r
815 IN URB *Urb,\r
a9292c13 816 IN UINTN Timeout\r
92870c98 817 );\r
818\r
819/**\r
820 Delete a single asynchronous interrupt transfer for\r
821 the device and endpoint.\r
822\r
a9292c13 823 @param Xhc The XHCI Instance.\r
6b4483cd 824 @param BusAddr The logical device address assigned by UsbBus driver.\r
92870c98 825 @param EpNum The endpoint of the target.\r
826\r
827 @retval EFI_SUCCESS An asynchronous transfer is removed.\r
828 @retval EFI_NOT_FOUND No transfer for the device is found.\r
829\r
830**/\r
831EFI_STATUS\r
832XhciDelAsyncIntTransfer (\r
a9292c13 833 IN USB_XHCI_INSTANCE *Xhc,\r
6b4483cd 834 IN UINT8 BusAddr,\r
92870c98 835 IN UINT8 EpNum\r
836 );\r
837\r
838/**\r
839 Remove all the asynchronous interrupt transfers.\r
840\r
a9292c13 841 @param Xhc The XHCI Instance.\r
92870c98 842\r
843**/\r
844VOID\r
845XhciDelAllAsyncIntTransfers (\r
a9292c13 846 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 847 );\r
848\r
6681582d
SZ		 849/**\r
850 Insert a single asynchronous interrupt transfer for\r
851 the device and endpoint.\r
852\r
853 @param Xhc The XHCI Instance\r
854 @param BusAddr The logical device address assigned by UsbBus driver\r
855 @param EpAddr Endpoint addrress\r
856 @param DevSpeed The device speed\r
857 @param MaxPacket The max packet length of the endpoint\r
858 @param DataLen The length of data buffer\r
859 @param Callback The function to call when data is transferred\r
860 @param Context The context to the callback\r
861\r
862 @return Created URB or NULL\r
863\r
864**/\r
865URB *\r
866XhciInsertAsyncIntTransfer (\r
867 IN USB_XHCI_INSTANCE *Xhc,\r
868 IN UINT8 BusAddr,\r
869 IN UINT8 EpAddr,\r
870 IN UINT8 DevSpeed,\r
871 IN UINTN MaxPacket,\r
872 IN UINTN DataLen,\r
873 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
874 IN VOID *Context\r
875 );\r
876\r
92870c98 877/**\r
878 Set Bios Ownership\r
879\r
a9292c13 880 @param Xhc The XHCI Instance.\r
92870c98 881\r
882**/\r
883VOID\r
884XhcSetBiosOwnership (\r
a9292c13 885 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 886 );\r
887\r
888/**\r
889 Clear Bios Ownership\r
890\r
a9292c13 891 @param Xhc The XHCI Instance.\r
92870c98 892\r
893**/\r
894VOID\r
895XhcClearBiosOwnership (\r
a9292c13 896 IN USB_XHCI_INSTANCE *Xhc\r
92870c98 897 );\r
898\r
92870c98 899/**\r
900 Find out the slot id according to the device's route string.\r
901\r
a9292c13 902 @param Xhc The XHCI Instance.\r
903 @param RouteString The route string described the device location.\r
92870c98 904\r
905 @return The slot id used by the device.\r
906\r
907**/\r
908UINT8\r
909EFIAPI\r
910XhcRouteStringToSlotId (\r
a9292c13 911 IN USB_XHCI_INSTANCE *Xhc,\r
912 IN USB_DEV_ROUTE RouteString\r
92870c98 913 );\r
914\r
915/**\r
916 Calculate the device context index by endpoint address and direction.\r
917\r
918 @param EpAddr The target endpoint number.\r
919 @param Direction The direction of the target endpoint.\r
920\r
921 @return The device context index of endpoint.\r
922\r
923**/\r
924UINT8\r
925XhcEndpointToDci (\r
926 IN UINT8 EpAddr,\r
927 IN UINT8 Direction\r
928 );\r
929\r
930/**\r
931 Ring the door bell to notify XHCI there is a transaction to be executed.\r
932\r
a9292c13 933 @param Xhc The XHCI Instance.\r
92870c98 934 @param SlotId The slot id of the target device.\r
935 @param Dci The device context index of the target slot or endpoint.\r
936\r
937 @retval EFI_SUCCESS Successfully ring the door bell.\r
938\r
939**/\r
940EFI_STATUS\r
941EFIAPI\r
942XhcRingDoorBell (\r
a9292c13 943 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 944 IN UINT8 SlotId,\r
945 IN UINT8 Dci\r
946 );\r
947\r
948/**\r
949 Interrupt transfer periodic check handler.\r
950\r
951 @param Event Interrupt event.\r
a9292c13 952 @param Context Pointer to USB_XHCI_INSTANCE.\r
92870c98 953\r
954**/\r
955VOID\r
956EFIAPI\r
957XhcMonitorAsyncRequests (\r
958 IN EFI_EVENT Event,\r
959 IN VOID *Context\r
960 );\r
961\r
962/**\r
963 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
964\r
a9292c13 965 @param Xhc The XHCI Instance.\r
92870c98 966 @param ParentRouteChart The route string pointed to the parent device if it exists.\r
967 @param Port The port to be polled.\r
968 @param PortState The port state.\r
969\r
970 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r
971 @retval Others Should not appear.\r
972\r
973**/\r
974EFI_STATUS\r
975EFIAPI\r
976XhcPollPortStatusChange (\r
a9292c13 977 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 978 IN USB_DEV_ROUTE ParentRouteChart,\r
979 IN UINT8 Port,\r
980 IN EFI_USB_PORT_STATUS *PortState\r
981 );\r
982\r
983/**\r
984 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
985\r
a9292c13 986 @param Xhc The XHCI Instance.\r
92870c98 987 @param SlotId The slot id to be configured.\r
988 @param PortNum The total number of downstream port supported by the hub.\r
989 @param TTT The TT think time of the hub device.\r
990 @param MTT The multi-TT of the hub device.\r
991\r
992 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
993\r
994**/\r
995EFI_STATUS\r
996XhcConfigHubContext (\r
a9292c13 997 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 998 IN UINT8 SlotId,\r
999 IN UINT8 PortNum,\r
1000 IN UINT8 TTT,\r
1001 IN UINT8 MTT\r
1002 );\r
1003\r
6b4483cd 1004\r
1005/**\r
1006 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
1007\r
1008 @param Xhc The XHCI Instance.\r
1009 @param SlotId The slot id to be configured.\r
1010 @param PortNum The total number of downstream port supported by the hub.\r
1011 @param TTT The TT think time of the hub device.\r
1012 @param MTT The multi-TT of the hub device.\r
1013\r
1014 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
1015\r
1016**/\r
1017EFI_STATUS\r
1018XhcConfigHubContext64 (\r
1019 IN USB_XHCI_INSTANCE *Xhc,\r
1020 IN UINT8 SlotId,\r
1021 IN UINT8 PortNum,\r
1022 IN UINT8 TTT,\r
1023 IN UINT8 MTT\r
1024 );\r
1025\r
1026\r
92870c98 1027/**\r
1028 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
1029\r
a9292c13 1030 @param Xhc The XHCI Instance.\r
92870c98 1031 @param SlotId The slot id to be configured.\r
1032 @param DeviceSpeed The device's speed.\r
1033 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1034\r
1035 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
1036\r
1037**/\r
1038EFI_STATUS\r
1039EFIAPI\r
1040XhcSetConfigCmd (\r
a9292c13 1041 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1042 IN UINT8 SlotId,\r
1043 IN UINT8 DeviceSpeed,\r
1044 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
1045 );\r
1046\r
6b4483cd 1047\r
1048/**\r
1049 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
1050\r
1051 @param Xhc The XHCI Instance.\r
1052 @param SlotId The slot id to be configured.\r
1053 @param DeviceSpeed The device's speed.\r
1054 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1055\r
1056 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
1057\r
1058**/\r
1059EFI_STATUS\r
1060EFIAPI\r
1061XhcSetConfigCmd64 (\r
1062 IN USB_XHCI_INSTANCE *Xhc,\r
1063 IN UINT8 SlotId,\r
1064 IN UINT8 DeviceSpeed,\r
1065 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
1066 );\r
1067\r
e1f2dfec
SZ		 1068/**\r
1069 Set interface through XHCI's Configure_Endpoint cmd.\r
1070\r
1071 @param Xhc The XHCI Instance.\r
1072 @param SlotId The slot id to be configured.\r
1073 @param DeviceSpeed The device's speed.\r
1074 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1075 @param Request USB device request to send.\r
1076\r
1077 @retval EFI_SUCCESS Successfully set interface.\r
1078\r
1079**/\r
1080EFI_STATUS\r
1081EFIAPI\r
1082XhcSetInterface (\r
1083 IN USB_XHCI_INSTANCE *Xhc,\r
1084 IN UINT8 SlotId,\r
1085 IN UINT8 DeviceSpeed,\r
1086 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
1087 IN EFI_USB_DEVICE_REQUEST *Request\r
1088 );\r
1089\r
1090/**\r
1091 Set interface through XHCI's Configure_Endpoint cmd.\r
1092\r
1093 @param Xhc The XHCI Instance.\r
1094 @param SlotId The slot id to be configured.\r
1095 @param DeviceSpeed The device's speed.\r
1096 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
1097 @param Request USB device request to send.\r
1098\r
1099 @retval EFI_SUCCESS Successfully set interface.\r
1100\r
1101**/\r
1102EFI_STATUS\r
1103EFIAPI\r
1104XhcSetInterface64 (\r
1105 IN USB_XHCI_INSTANCE *Xhc,\r
1106 IN UINT8 SlotId,\r
1107 IN UINT8 DeviceSpeed,\r
1108 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r
1109 IN EFI_USB_DEVICE_REQUEST *Request\r
1110 );\r
6b4483cd 1111\r
92870c98 1112/**\r
1113 Find out the actual device address according to the requested device address from UsbBus.\r
1114\r
a9292c13 1115 @param Xhc The XHCI Instance.\r
1116 @param BusDevAddr The requested device address by UsbBus upper driver.\r
92870c98 1117\r
1118 @return The actual device address assigned to the device.\r
1119\r
1120**/\r
1121UINT8\r
1122EFIAPI\r
1123XhcBusDevAddrToSlotId (\r
a9292c13 1124 IN USB_XHCI_INSTANCE *Xhc,\r
1125 IN UINT8 BusDevAddr\r
92870c98 1126 );\r
1127\r
1128/**\r
1129 Assign and initialize the device slot for a new device.\r
1130\r
a9292c13 1131 @param Xhc The XHCI Instance.\r
92870c98 1132 @param ParentRouteChart The route string pointed to the parent device.\r
1133 @param ParentPort The port at which the device is located.\r
1134 @param RouteChart The route string pointed to the device.\r
1135 @param DeviceSpeed The device speed.\r
1136\r
1137 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1138\r
1139**/\r
1140EFI_STATUS\r
1141EFIAPI\r
1142XhcInitializeDeviceSlot (\r
a9292c13 1143 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1144 IN USB_DEV_ROUTE ParentRouteChart,\r
1145 IN UINT16 ParentPort,\r
1146 IN USB_DEV_ROUTE RouteChart,\r
1147 IN UINT8 DeviceSpeed\r
1148 );\r
1149\r
6b4483cd 1150/**\r
1151 Assign and initialize the device slot for a new device.\r
1152\r
1153 @param Xhc The XHCI Instance.\r
1154 @param ParentRouteChart The route string pointed to the parent device.\r
1155 @param ParentPort The port at which the device is located.\r
1156 @param RouteChart The route string pointed to the device.\r
1157 @param DeviceSpeed The device speed.\r
1158\r
1159 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1160\r
1161**/\r
1162EFI_STATUS\r
1163EFIAPI\r
1164XhcInitializeDeviceSlot64 (\r
1165 IN USB_XHCI_INSTANCE *Xhc,\r
1166 IN USB_DEV_ROUTE ParentRouteChart,\r
1167 IN UINT16 ParentPort,\r
1168 IN USB_DEV_ROUTE RouteChart,\r
1169 IN UINT8 DeviceSpeed\r
1170 );\r
1171\r
92870c98 1172/**\r
1173 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
1174\r
a9292c13 1175 @param Xhc The XHCI Instance.\r
92870c98 1176 @param SlotId The slot id to be evaluated.\r
1177 @param MaxPacketSize The max packet size supported by the device control transfer.\r
1178\r
1179 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
1180\r
1181**/\r
1182EFI_STATUS\r
1183EFIAPI\r
1184XhcEvaluateContext (\r
a9292c13 1185 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1186 IN UINT8 SlotId,\r
1187 IN UINT32 MaxPacketSize\r
1188 );\r
1189\r
6b4483cd 1190\r
1191/**\r
1192 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
1193\r
1194 @param Xhc The XHCI Instance.\r
1195 @param SlotId The slot id to be evaluated.\r
1196 @param MaxPacketSize The max packet size supported by the device control transfer.\r
1197\r
1198 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
1199\r
1200**/\r
1201EFI_STATUS\r
1202EFIAPI\r
1203XhcEvaluateContext64 (\r
1204 IN USB_XHCI_INSTANCE *Xhc,\r
1205 IN UINT8 SlotId,\r
1206 IN UINT32 MaxPacketSize\r
1207 );\r
1208\r
1209\r
92870c98 1210/**\r
1211 Disable the specified device slot.\r
1212\r
a9292c13 1213 @param Xhc The XHCI Instance.\r
92870c98 1214 @param SlotId The slot id to be disabled.\r
1215\r
1216 @retval EFI_SUCCESS Successfully disable the device slot.\r
1217\r
1218**/\r
1219EFI_STATUS\r
1220EFIAPI\r
1221XhcDisableSlotCmd (\r
a9292c13 1222 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1223 IN UINT8 SlotId\r
1224 );\r
1225\r
6b4483cd 1226\r
1227/**\r
1228 Disable the specified device slot.\r
1229\r
1230 @param Xhc The XHCI Instance.\r
1231 @param SlotId The slot id to be disabled.\r
1232\r
1233 @retval EFI_SUCCESS Successfully disable the device slot.\r
1234\r
1235**/\r
1236EFI_STATUS\r
1237EFIAPI\r
1238XhcDisableSlotCmd64 (\r
1239 IN USB_XHCI_INSTANCE *Xhc,\r
1240 IN UINT8 SlotId\r
1241 );\r
1242\r
1243\r
92870c98 1244/**\r
1245 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
1246\r
a9292c13 1247 @param Xhc The XHCI Instance.\r
92870c98 1248 @param TrsRing The transfer ring to sync.\r
1249\r
1250 @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
1251\r
1252**/\r
1253EFI_STATUS\r
1254EFIAPI\r
1255XhcSyncTrsRing (\r
a9292c13 1256 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1257 TRANSFER_RING *TrsRing\r
1258 );\r
1259\r
1260/**\r
1261 Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
1262\r
a9292c13 1263 @param Xhc The XHCI Instance.\r
92870c98 1264 @param EvtRing The event ring to sync.\r
1265\r
1266 @retval EFI_SUCCESS The event ring is synchronized successfully.\r
1267\r
1268**/\r
1269EFI_STATUS\r
1270EFIAPI\r
1271XhcSyncEventRing (\r
a9292c13 1272 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1273 EVENT_RING *EvtRing\r
1274 );\r
1275\r
1276/**\r
1277 Check if there is a new generated event.\r
1278\r
a9292c13 1279 @param Xhc The XHCI Instance.\r
92870c98 1280 @param EvtRing The event ring to check.\r
1281 @param NewEvtTrb The new event TRB found.\r
1282\r
1283 @retval EFI_SUCCESS Found a new event TRB at the event ring.\r
1284 @retval EFI_NOT_READY The event ring has no new event.\r
1285\r
1286**/\r
1287EFI_STATUS\r
1288EFIAPI\r
1289XhcCheckNewEvent (\r
a9292c13 1290 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1291 IN EVENT_RING *EvtRing,\r
a9292c13 1292 OUT TRB_TEMPLATE **NewEvtTrb\r
92870c98 1293 );\r
1294\r
1295/**\r
1296 Create XHCI transfer ring.\r
1297\r
a9292c13 1298 @param Xhc The XHCI Instance.\r
92870c98 1299 @param TrbNum The number of TRB in the ring.\r
1300 @param TransferRing The created transfer ring.\r
1301\r
1302**/\r
1303VOID\r
1304CreateTransferRing (\r
a9292c13 1305 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1306 IN UINTN TrbNum,\r
1307 OUT TRANSFER_RING *TransferRing\r
1308 );\r
1309\r
1310/**\r
1311 Create XHCI event ring.\r
1312\r
a9292c13 1313 @param Xhc The XHCI Instance.\r
92870c98 1314 @param EventRing The created event ring.\r
1315\r
1316**/\r
1317VOID\r
1318CreateEventRing (\r
a9292c13 1319 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1320 OUT EVENT_RING *EventRing\r
1321 );\r
1322\r
1323/**\r
1324 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
1325 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
1326 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
1327 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
1328 Stopped to the Running state.\r
1329\r
a9292c13 1330 @param Xhc The XHCI Instance.\r
92870c98 1331 @param Urb The urb which makes the endpoint halted.\r
1332\r
1333 @retval EFI_SUCCESS The recovery is successful.\r
1334 @retval Others Failed to recovery halted endpoint.\r
1335\r
1336**/\r
1337EFI_STATUS\r
1338EFIAPI\r
1339XhcRecoverHaltedEndpoint (\r
a9292c13 1340 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1341 IN URB *Urb\r
1342 );\r
1343\r
12e6c738
FT		 1344/**\r
1345 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r
1346 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r
1347 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r
1348 state.\r
1349\r
1350 @param Xhc The XHCI Instance.\r
1351 @param Urb The urb which doesn't get completed in a specified timeout range.\r
1352\r
1353 @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r
1354 @retval Others Failed to stop the endpoint and dequeue the TDs.\r
1355\r
1356**/\r
1357EFI_STATUS\r
1358EFIAPI\r
1359XhcDequeueTrbFromEndpoint (\r
1360 IN USB_XHCI_INSTANCE *Xhc,\r
1361 IN URB *Urb\r
1362 );\r
1363\r
1364/**\r
1365 Stop endpoint through XHCI's Stop_Endpoint cmd.\r
1366\r
1367 @param Xhc The XHCI Instance.\r
1368 @param SlotId The slot id to be configured.\r
1369 @param Dci The device context index of endpoint.\r
49be9c3c 1370 @param PendingUrb The pending URB to check completion status when stopping the end point.\r
12e6c738
FT		 1371\r
1372 @retval EFI_SUCCESS Stop endpoint successfully.\r
1373 @retval Others Failed to stop endpoint.\r
1374\r
1375**/\r
1376EFI_STATUS\r
1377EFIAPI\r
1378XhcStopEndpoint (\r
1379 IN USB_XHCI_INSTANCE *Xhc,\r
1380 IN UINT8 SlotId,\r
49be9c3c
RN		 1381 IN UINT8 Dci,\r
1382 IN URB *PendingUrb OPTIONAL\r
12e6c738
FT		 1383 );\r
1384\r
1385/**\r
1386 Reset endpoint through XHCI's Reset_Endpoint cmd.\r
1387\r
1388 @param Xhc The XHCI Instance.\r
1389 @param SlotId The slot id to be configured.\r
1390 @param Dci The device context index of endpoint.\r
1391\r
1392 @retval EFI_SUCCESS Reset endpoint successfully.\r
1393 @retval Others Failed to reset endpoint.\r
1394\r
1395**/\r
1396EFI_STATUS\r
1397EFIAPI\r
1398XhcResetEndpoint (\r
1399 IN USB_XHCI_INSTANCE *Xhc,\r
1400 IN UINT8 SlotId,\r
1401 IN UINT8 Dci\r
1402 );\r
1403\r
1404/**\r
1405 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r
1406\r
1407 @param Xhc The XHCI Instance.\r
1408 @param SlotId The slot id to be configured.\r
1409 @param Dci The device context index of endpoint.\r
1410 @param Urb The dequeue pointer of the transfer ring specified\r
1411 by the urb to be updated.\r
1412\r
1413 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r
1414 @retval Others Failed to set transfer ring dequeue pointer.\r
1415\r
1416**/\r
1417EFI_STATUS\r
1418EFIAPI\r
1419XhcSetTrDequeuePointer (\r
1420 IN USB_XHCI_INSTANCE *Xhc,\r
1421 IN UINT8 SlotId,\r
1422 IN UINT8 Dci,\r
1423 IN URB *Urb\r
1424 );\r
1425\r
92870c98 1426/**\r
1427 Create a new URB for a new transaction.\r
1428\r
d98fc9ad
SZ		 1429 @param Xhc The XHCI Instance\r
1430 @param DevAddr The device address\r
1431 @param EpAddr Endpoint addrress\r
1432 @param DevSpeed The device speed\r
1433 @param MaxPacket The max packet length of the endpoint\r
1434 @param Type The transaction type\r
1435 @param Request The standard USB request for control transfer\r
1436 @param Data The user data to transfer\r
1437 @param DataLen The length of data buffer\r
1438 @param Callback The function to call when data is transferred\r
1439 @param Context The context to the callback\r
92870c98 1440\r
1441 @return Created URB or NULL\r
1442\r
1443**/\r
1444URB*\r
1445XhcCreateUrb (\r
a9292c13 1446 IN USB_XHCI_INSTANCE *Xhc,\r
d98fc9ad 1447 IN UINT8 DevAddr,\r
92870c98 1448 IN UINT8 EpAddr,\r
1449 IN UINT8 DevSpeed,\r
1450 IN UINTN MaxPacket,\r
1451 IN UINTN Type,\r
1452 IN EFI_USB_DEVICE_REQUEST *Request,\r
1453 IN VOID *Data,\r
1454 IN UINTN DataLen,\r
1455 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
1456 IN VOID *Context\r
1457 );\r
1458\r
1847ed0b
EL		 1459/**\r
1460 Free an allocated URB.\r
1461\r
1462 @param Xhc The XHCI device.\r
1463 @param Urb The URB to free.\r
1464\r
1465**/\r
1466VOID\r
1467XhcFreeUrb (\r
1468 IN USB_XHCI_INSTANCE *Xhc,\r
1469 IN URB *Urb\r
1470 );\r
1471\r
92870c98 1472/**\r
1473 Create a transfer TRB.\r
1474\r
a9292c13 1475 @param Xhc The XHCI Instance\r
92870c98 1476 @param Urb The urb used to construct the transfer TRB.\r
1477\r
1478 @return Created TRB or NULL\r
1479\r
1480**/\r
1481EFI_STATUS\r
1482XhcCreateTransferTrb (\r
a9292c13 1483 IN USB_XHCI_INSTANCE *Xhc,\r
92870c98 1484 IN URB *Urb\r
1485 );\r
1486\r
1487#endif\r
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