Omap35xxPkg/MMCHSDxe: fix device path initializer
[mirror_edk2.git] / Omap35xxPkg / MMCHSDxe / MMCHS.h
CommitLineData
a3f98646 1/** @file\r
2\r
3d70643b 3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
a3f98646 4\r
3d70643b 5 This program and the accompanying materials\r
a3f98646 6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef _MMCHS_H_\r
16#define _MMCHS_H_\r
17\r
1e57a462 18#include <Uefi.h>\r
19\r
20#include <Library/BaseLib.h>\r
21#include <Library/MemoryAllocationLib.h>\r
22#include <Library/DebugLib.h>\r
23#include <Library/IoLib.h>\r
24#include <Library/PcdLib.h>\r
25#include <Library/UefiBootServicesTableLib.h>\r
26#include <Library/BaseMemoryLib.h>\r
27#include <Library/OmapLib.h>\r
28#include <Library/OmapDmaLib.h>\r
29#include <Library/DmaLib.h>\r
30\r
a3f98646 31#include <Protocol/EmbeddedExternalDevice.h>\r
1e57a462 32#include <Protocol/BlockIo.h>\r
33#include <Protocol/DevicePath.h>\r
34\r
a3f98646 35#include <Omap3530/Omap3530.h>\r
36#include <TPS65950.h>\r
37\r
1e57a462 38#define MAX_RETRY_COUNT (100*5)\r
39\r
43263288 40#define HCS BIT30 //Host capacity support/1 = Supporting high capacity\r
41#define CCS BIT30 //Card capacity status/1 = High capacity card\r
a3f98646 42typedef struct {\r
3402aac7 43 UINT32 Reserved0: 7; // 0\r
a3f98646 44 UINT32 V170_V195: 1; // 1.70V - 1.95V\r
45 UINT32 V200_V260: 7; // 2.00V - 2.60V\r
46 UINT32 V270_V360: 9; // 2.70V - 3.60V\r
47 UINT32 RESERVED_1: 5; // Reserved\r
3402aac7 48 UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)\r
a3f98646 49 UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine\r
50}OCR;\r
51\r
52typedef struct {\r
53 UINT32 NOT_USED; // 1 [0:0]\r
54 UINT32 CRC; // CRC7 checksum [7:1]\r
55 UINT32 MDT; // Manufacturing date [19:8]\r
56 UINT32 RESERVED_1; // Reserved [23:20]\r
57 UINT32 PSN; // Product serial number [55:24]\r
58 UINT8 PRV; // Product revision [63:56]\r
59 UINT8 PNM[5]; // Product name [64:103]\r
60 UINT16 OID; // OEM/Application ID [119:104]\r
61 UINT8 MID; // Manufacturer ID [127:120]\r
62}CID;\r
63\r
64typedef struct {\r
65 UINT8 NOT_USED: 1; // Not used, always 1 [0:0]\r
66 UINT8 CRC: 7; // CRC [7:1]\r
8c6151f2 67\r
a3f98646 68 UINT8 RESERVED_1: 2; // Reserved [9:8]\r
69 UINT8 FILE_FORMAT: 2; // File format [11:10]\r
70 UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]\r
71 UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r
72 UINT8 COPY: 1; // Copy flag (OTP) [14:14]\r
73 UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]\r
3402aac7 74\r
a3f98646 75 UINT16 RESERVED_2: 5; // Reserved [20:16]\r
76 UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]\r
77 UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]\r
78 UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]\r
79 UINT16 RESERVED_3: 2; // Reserved [30:29]\r
80 UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]\r
3402aac7 81\r
a3f98646 82 UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]\r
83 UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]\r
84 UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]\r
85 UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]\r
86 UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]\r
87 UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]\r
88 UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]\r
89 UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]\r
8c6151f2 90 UINT32 C_SIZELow2: 2; // Device size [63:62]\r
3402aac7 91\r
8c6151f2 92 UINT32 C_SIZEHigh10: 10;// Device size [73:64]\r
a3f98646 93 UINT32 RESERVED_4: 2; // Reserved [75:74]\r
94 UINT32 DSR_IMP: 1; // DSR implemented [76:76]\r
95 UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]\r
96 UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]\r
97 UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]\r
98 UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]\r
99 UINT32 CCC: 12;// Card command classes [95:84]\r
8c6151f2 100\r
a3f98646 101 UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]\r
102 UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
103 UINT8 TAAC ; // Data read access-time 1 [119:112]\r
3402aac7 104\r
a3f98646 105 UINT8 RESERVED_5: 6; // Reserved [125:120]\r
106 UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]\r
107}CSD;\r
108\r
109typedef struct {\r
110 UINT8 NOT_USED: 1; // Not used, always 1 [0:0]\r
111 UINT8 CRC: 7; // CRC [7:1]\r
112 UINT8 RESERVED_1: 2; // Reserved [9:8]\r
113 UINT8 FILE_FORMAT: 2; // File format [11:10]\r
114 UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]\r
115 UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r
116 UINT8 COPY: 1; // Copy flag (OTP) [14:14]\r
117 UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]\r
118 UINT16 RESERVED_2: 5; // Reserved [20:16]\r
119 UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]\r
120 UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]\r
121 UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]\r
122 UINT16 RESERVED_3: 2; // Reserved [30:29]\r
123 UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]\r
124 UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]\r
125 UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]\r
126 UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]\r
127 UINT16 RESERVED_4: 1; // Reserved [47:47]\r
128 UINT32 C_SIZELow16: 16;// Device size [69:48]\r
129 UINT32 C_SIZEHigh6: 6; // Device size [69:48]\r
130 UINT32 RESERVED_5: 6; // Reserved [75:70]\r
131 UINT32 DSR_IMP: 1; // DSR implemented [76:76]\r
132 UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]\r
133 UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]\r
134 UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]\r
135 UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]\r
136 UINT16 CCC: 12;// Card command classes [95:84]\r
137 UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]\r
138 UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
139 UINT8 TAAC ; // Data read access-time 1 [119:112]\r
140 UINT8 RESERVED_6: 6; // 0 [125:120]\r
141 UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]\r
142}CSD_SDV2;\r
143\r
1e57a462 144typedef enum {\r
145 UNKNOWN_CARD,\r
146 MMC_CARD, //MMC card\r
147 SD_CARD, //SD 1.1 card\r
148 SD_CARD_2, //SD 2.0 or above standard card\r
149 SD_CARD_2_HIGH //SD 2.0 or above high capacity card\r
a3f98646 150} CARD_TYPE;\r
151\r
152typedef enum {\r
153 READ,\r
154 WRITE\r
155} OPERATION_TYPE;\r
156\r
8c6151f2 157typedef struct {\r
a3f98646 158 UINT16 RCA;\r
159 UINTN BlockSize;\r
160 UINTN NumBlocks;\r
161 UINTN ClockFrequencySelect;\r
162 CARD_TYPE CardType;\r
163 OCR OCRData;\r
164 CID CIDData;\r
165 CSD CSDData;\r
166} CARD_INFO;\r
167\r
1e57a462 168EFI_STATUS\r
169DetectCard (\r
170 VOID\r
8c6151f2 171 );\r
172\r
173extern EFI_BLOCK_IO_PROTOCOL gBlockIo;\r
174\r
a3f98646 175#endif\r