OvmfPkg/Microvm/pcie: mPhysMemAddressWidth tweak

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

/**@file\r
  Platform PEI driver\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/QemuFwCfgS3Lib.h>\r
#include <Library/QemuFwCfgSimpleParserLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/I440FxPiix4.h>\r
#include <IndustryStandard/Microvm.h>\r
#include <IndustryStandard/Pci22.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <IndustryStandard/QemuCpuHotplug.h>\r
#include <Library/MemEncryptSevLib.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
\r
EFI_HOB_PLATFORM_INFO  mPlatformInfoHob = { 0 };\r
\r
EFI_PEI_PPI_DESCRIPTOR  mPpiBootMode[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gEfiPeiMasterBootModePpiGuid,\r
    NULL\r
  }\r
};\r
\r
VOID\r
MemMapInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  RETURN_STATUS  PcdStatus;\r
\r
  PlatformMemMapInitialization (PlatformInfoHob);\r
\r
  if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {\r
    return;\r
  }\r
\r
  PcdStatus = PcdSet64S (PcdPciMmio32Base, PlatformInfoHob->PcdPciMmio32Base);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  PcdStatus = PcdSet64S (PcdPciMmio32Size, PlatformInfoHob->PcdPciMmio32Size);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
\r
  PcdStatus = PcdSet64S (PcdPciIoBase, PlatformInfoHob->PcdPciIoBase);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  PcdStatus = PcdSet64S (PcdPciIoSize, PlatformInfoHob->PcdPciIoSize);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
VOID\r
NoexecDxeInitialization (\r
  VOID\r
  )\r
{\r
  RETURN_STATUS  Status;\r
\r
  Status = PlatformNoexecDxeInitialization (&mPlatformInfoHob);\r
  if (!RETURN_ERROR (Status)) {\r
    Status = PcdSetBoolS (PcdSetNxForStack, mPlatformInfoHob.PcdSetNxForStack);\r
    ASSERT_RETURN_ERROR (Status);\r
  }\r
}\r
\r
static const UINT8  EmptyFdt[] = {\r
  0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x00, 0x48,\r
  0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x48,\r
  0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,\r
  0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,\r
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,\r
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,\r
  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09,\r
};\r
\r
VOID\r
MicrovmInitialization (\r
  VOID\r
  )\r
{\r
  FIRMWARE_CONFIG_ITEM  FdtItem;\r
  UINTN                 FdtSize;\r
  UINTN                 FdtPages;\r
  EFI_STATUS            Status;\r
  UINT64                *FdtHobData;\r
  VOID                  *NewBase;\r
\r
  Status = QemuFwCfgFindFile ("etc/fdt", &FdtItem, &FdtSize);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_INFO, "%a: no etc/fdt found in fw_cfg, using dummy\n", __FUNCTION__));\r
    FdtItem = 0;\r
    FdtSize = sizeof (EmptyFdt);\r
  }\r
\r
  FdtPages = EFI_SIZE_TO_PAGES (FdtSize);\r
  NewBase  = AllocatePages (FdtPages);\r
  if (NewBase == NULL) {\r
    DEBUG ((DEBUG_INFO, "%a: AllocatePages failed\n", __FUNCTION__));\r
    return;\r
  }\r
\r
  if (FdtItem) {\r
    QemuFwCfgSelectItem (FdtItem);\r
    QemuFwCfgReadBytes (FdtSize, NewBase);\r
  } else {\r
    CopyMem (NewBase, EmptyFdt, FdtSize);\r
  }\r
\r
  FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof (*FdtHobData));\r
  if (FdtHobData == NULL) {\r
    DEBUG ((DEBUG_INFO, "%a: BuildGuidHob failed\n", __FUNCTION__));\r
    return;\r
  }\r
\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "%a: fdt at 0x%x (size %d)\n",\r
    __FUNCTION__,\r
    NewBase,\r
    FdtSize\r
    ));\r
  *FdtHobData = (UINTN)NewBase;\r
}\r
\r
VOID\r
MiscInitializationForMicrovm (\r
  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  RETURN_STATUS  PcdStatus;\r
\r
  ASSERT (PlatformInfoHob->HostBridgeDevId == 0xffff);\r
\r
  DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__));\r
  //\r
  // Disable A20 Mask\r
  //\r
  IoOr8 (0x92, BIT1);\r
\r
  //\r
  // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
  // S3 resume as well, so we build it unconditionally.)\r
  //\r
  BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);\r
\r
  MicrovmInitialization ();\r
  PcdStatus = PcdSet16S (\r
                PcdOvmfHostBridgePciDevId,\r
                MICROVM_PSEUDO_DEVICE_ID\r
                );\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
VOID\r
MiscInitialization (\r
  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  RETURN_STATUS  PcdStatus;\r
\r
  PlatformMiscInitialization (PlatformInfoHob);\r
\r
  PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->HostBridgeDevId);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
VOID\r
BootModeInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  if (PlatformCmosRead8 (0xF) == 0xFE) {\r
    PlatformInfoHob->BootMode = BOOT_ON_S3_RESUME;\r
  }\r
\r
  PlatformCmosWrite8 (0xF, 0x00);\r
\r
  Status = PeiServicesSetBootMode (PlatformInfoHob->BootMode);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = PeiServicesInstallPpi (mPpiBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
VOID\r
ReserveEmuVariableNvStore (\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS  VariableStore;\r
  RETURN_STATUS         PcdStatus;\r
\r
  //\r
  // Allocate storage for NV variables early on so it will be\r
  // at a consistent address.  Since VM memory is preserved\r
  // across reboots, this allows the NV variable storage to survive\r
  // a VM reboot.\r
  //\r
  VariableStore =\r
    (EFI_PHYSICAL_ADDRESS)(UINTN)\r
    AllocateRuntimePages (\r
      EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
      );\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
    VariableStore,\r
    (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
    ));\r
  PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
VOID\r
S3Verification (\r
  VOID\r
  )\r
{\r
 #if defined (MDE_CPU_X64)\r
  if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.S3Supported) {\r
    DEBUG ((\r
      DEBUG_ERROR,\r
      "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",\r
      __FUNCTION__\r
      ));\r
    DEBUG ((\r
      DEBUG_ERROR,\r
      "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
      __FUNCTION__\r
      ));\r
    DEBUG ((\r
      DEBUG_ERROR,\r
      "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",\r
      __FUNCTION__\r
      ));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
\r
 #endif\r
}\r
\r
VOID\r
Q35BoardVerification (\r
  VOID\r
  )\r
{\r
  if (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    return;\r
  }\r
\r
  DEBUG ((\r
    DEBUG_ERROR,\r
    "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
    "only DID=0x%04x (Q35) is supported\n",\r
    __FUNCTION__,\r
    mPlatformInfoHob.HostBridgeDevId,\r
    INTEL_Q35_MCH_DEVICE_ID\r
    ));\r
  ASSERT (FALSE);\r
  CpuDeadLoop ();\r
}\r
\r
/**\r
  Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
  them to UefiCpuPkg modules. Set the MaxCpuCount field in PlatformInfoHob.\r
**/\r
VOID\r
MaxCpuCountInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  RETURN_STATUS  PcdStatus;\r
\r
  PlatformMaxCpuCountInitialization (PlatformInfoHob);\r
\r
  PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, PlatformInfoHob->PcdCpuBootLogicalProcessorNumber);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
/**\r
 * @brief Builds PlatformInfo Hob\r
 */\r
VOID\r
BuildPlatformInfoHob (\r
  VOID\r
  )\r
{\r
  BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, &mPlatformInfoHob, sizeof (EFI_HOB_PLATFORM_INFO));\r
}\r
\r
/**\r
  Perform Platform PEI initialization.\r
\r
  @param  FileHandle      Handle of the file being invoked.\r
  @param  PeiServices     Describes the list of possible PEI Services.\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializePlatform (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
\r
  mPlatformInfoHob.SmmSmramRequire     = FeaturePcdGet (PcdSmmSmramRequire);\r
  mPlatformInfoHob.SevEsIsEnabled      = MemEncryptSevEsIsEnabled ();\r
  mPlatformInfoHob.PcdPciMmio64Size    = PcdGet64 (PcdPciMmio64Size);\r
  mPlatformInfoHob.DefaultMaxCpuNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
\r
  PlatformDebugDumpCmos ();\r
\r
  if (QemuFwCfgS3Enabled ()) {\r
    DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));\r
    mPlatformInfoHob.S3Supported = TRUE;\r
    Status                       = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
\r
  S3Verification ();\r
  BootModeInitialization (&mPlatformInfoHob);\r
\r
  //\r
  // Query Host Bridge DID\r
  //\r
  mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
  AddressWidthInitialization (&mPlatformInfoHob);\r
\r
  MaxCpuCountInitialization (&mPlatformInfoHob);\r
\r
  if (mPlatformInfoHob.SmmSmramRequire) {\r
    Q35BoardVerification ();\r
    Q35TsegMbytesInitialization ();\r
    Q35SmramAtDefaultSmbaseInitialization ();\r
  }\r
\r
  PublishPeiMemory ();\r
\r
  PlatformQemuUc32BaseInitialization (&mPlatformInfoHob);\r
\r
  InitializeRamRegions (&mPlatformInfoHob);\r
\r
  if (mPlatformInfoHob.BootMode != BOOT_ON_S3_RESUME) {\r
    if (!mPlatformInfoHob.SmmSmramRequire) {\r
      ReserveEmuVariableNvStore ();\r
    }\r
\r
    PeiFvInitialization ();\r
    MemTypeInfoInitialization ();\r
    MemMapInitialization (&mPlatformInfoHob);\r
    NoexecDxeInitialization ();\r
  }\r
\r
  InstallClearCacheCallback ();\r
  AmdSevInitialize ();\r
  if (mPlatformInfoHob.HostBridgeDevId == 0xffff) {\r
    MiscInitializationForMicrovm (&mPlatformInfoHob);\r
  } else {\r
    MiscInitialization (&mPlatformInfoHob);\r
  }\r
\r
  IntelTdxInitialize ();\r
  InstallFeatureControlCallback ();\r
  BuildPlatformInfoHob ();\r
\r
  return EFI_SUCCESS;\r
}\r