[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

/**@file\r
  Platform PEI driver\r
\r
  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
  { EfiACPIMemoryNVS,       0x004 },\r
  { EfiACPIReclaimMemory,   0x008 },\r
  { EfiReservedMemoryType,  0x004 },\r
  { EfiRuntimeServicesData, 0x024 },\r
  { EfiRuntimeServicesCode, 0x030 },\r
  { EfiBootServicesCode,    0x180 },\r
  { EfiBootServicesData,    0xF00 },\r
  { EfiMaxMemoryType,       0x000 }\r
};\r
\r
\r
EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gEfiPeiMasterBootModePpiGuid,\r
    NULL\r
  }\r
};\r
\r
\r
UINT16 mHostBridgeDevId;\r
\r
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
\r
BOOLEAN mS3Supported = FALSE;\r
\r
\r
VOID\r
AddIoMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddReservedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize,\r
  BOOLEAN                     Cacheable\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_RESERVED,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      (Cacheable ?\r
       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
       0\r
       ) |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddIoMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddUntestedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddUntestedMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
VOID\r
MemMapInitialization (\r
  VOID\r
  )\r
{\r
  //\r
  // Create Memory Type Information HOB\r
  //\r
  BuildGuidDataHob (\r
    &gEfiMemoryTypeInformationGuid,\r
    mDefaultMemoryTypeInformation,\r
    sizeof(mDefaultMemoryTypeInformation)\r
    );\r
\r
  //\r
  // Add PCI IO Port space available for PCI resource allocations.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_IO,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
    0xC000,\r
    0x4000\r
    );\r
\r
  //\r
  // Video memory + Legacy BIOS region\r
  //\r
  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
  if (!mXen) {\r
    UINT32  TopOfLowRam;\r
    UINT32  PciBase;\r
\r
    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
      //\r
      // A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r
      // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r
      // the RAM below 4 GB exceed it.\r
      //\r
      PciBase = BASE_2GB + BASE_1GB;\r
      ASSERT (TopOfLowRam <= PciBase);\r
    } else {\r
      PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
    }\r
\r
    //\r
    // address       purpose   size\r
    // ------------  --------  -------------------------\r
    // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
    // 0xFC000000    gap                           44 MB\r
    // 0xFEC00000    IO-APIC                        4 KB\r
    // 0xFEC01000    gap                         1020 KB\r
    // 0xFED00000    HPET                           1 KB\r
    // 0xFED00400    gap                          111 KB\r
    // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
    // 0xFED20000    gap                          896 KB\r
    // 0xFEE00000    LAPIC                          1 MB\r
    //\r
    AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
    AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
    AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
      AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
    }\r
    AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
  }\r
}\r
\r
EFI_STATUS\r
GetNamedFwCfgBoolean (\r
  IN  CHAR8   *FwCfgFileName,\r
  OUT BOOLEAN *Setting\r
  )\r
{\r
  EFI_STATUS           Status;\r
  FIRMWARE_CONFIG_ITEM FwCfgItem;\r
  UINTN                FwCfgSize;\r
  UINT8                Value[3];\r
\r
  Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  if (FwCfgSize > sizeof Value) {\r
    return EFI_BAD_BUFFER_SIZE;\r
  }\r
  QemuFwCfgSelectItem (FwCfgItem);\r
  QemuFwCfgReadBytes (FwCfgSize, Value);\r
\r
  if ((FwCfgSize == 1) ||\r
      (FwCfgSize == 2 && Value[1] == '\n') ||\r
      (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
    switch (Value[0]) {\r
      case '0':\r
      case 'n':\r
      case 'N':\r
        *Setting = FALSE;\r
        return EFI_SUCCESS;\r
\r
      case '1':\r
      case 'y':\r
      case 'Y':\r
        *Setting = TRUE;\r
        return EFI_SUCCESS;\r
\r
      default:\r
        break;\r
    }\r
  }\r
  return EFI_PROTOCOL_ERROR;\r
}\r
\r
#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \\r
          do {                                                      \\r
            BOOLEAN Setting;                                        \\r
                                                                    \\r
            if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \\r
                              "opt/ovmf/" #TokenName, &Setting))) { \\r
              PcdSetBool (TokenName, Setting);                      \\r
            }                                                       \\r
          } while (0)\r
\r
VOID\r
NoexecDxeInitialization (\r
  VOID\r
  )\r
{\r
  UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
  UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
}\r
\r
VOID\r
MiscInitialization (\r
  VOID\r
  )\r
{\r
  UINTN  PmCmd;\r
  UINTN  Pmba;\r
  UINTN  AcpiCtlReg;\r
  UINT8  AcpiEnBit;\r
\r
  //\r
  // Disable A20 Mask\r
  //\r
  IoOr8 (0x92, BIT1);\r
\r
  //\r
  // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
  // S3 resume as well, so we build it unconditionally.)\r
  //\r
  BuildCpuHob (mPhysMemAddressWidth, 16);\r
\r
  //\r
  // Determine platform type and save Host Bridge DID to PCD\r
  //\r
  switch (mHostBridgeDevId) {\r
    case INTEL_82441_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
      break;\r
    case INTEL_Q35_MCH_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
      break;\r
    default:\r
      DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
        __FUNCTION__, mHostBridgeDevId));\r
      ASSERT (FALSE);\r
      return;\r
  }\r
  PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
\r
  //\r
  // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
  // has been configured (e.g., by Xen) and skip the setup here.\r
  // This matches the logic in AcpiTimerLibConstructor ().\r
  //\r
  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
    //\r
    // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
    // 1. set PMBA\r
    //\r
    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
\r
    //\r
    // 2. set PCICMD/IOSE\r
    //\r
    PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
\r
    //\r
    // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
    //\r
    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
  }\r
\r
  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    //\r
    // Set Root Complex Register Block BAR\r
    //\r
    PciWrite32 (\r
      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
      );\r
  }\r
}\r
\r
\r
VOID\r
BootModeInitialization (\r
  VOID\r
  )\r
{\r
  EFI_STATUS    Status;\r
\r
  if (CmosRead8 (0xF) == 0xFE) {\r
    mBootMode = BOOT_ON_S3_RESUME;\r
  }\r
  CmosWrite8 (0xF, 0x00);\r
\r
  Status = PeiServicesSetBootMode (mBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = PeiServicesInstallPpi (mPpiBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
VOID\r
ReserveEmuVariableNvStore (\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS VariableStore;\r
\r
  //\r
  // Allocate storage for NV variables early on so it will be\r
  // at a consistent address.  Since VM memory is preserved\r
  // across reboots, this allows the NV variable storage to survive\r
  // a VM reboot.\r
  //\r
  VariableStore =\r
    (EFI_PHYSICAL_ADDRESS)(UINTN)\r
      AllocateAlignedRuntimePages (\r
        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
        PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
        );\r
  DEBUG ((EFI_D_INFO,\r
          "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
          VariableStore,\r
          (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
        ));\r
  PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
}\r
\r
\r
VOID\r
DebugDumpCmos (\r
  VOID\r
  )\r
{\r
  UINT32 Loop;\r
\r
  DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
  for (Loop = 0; Loop < 0x80; Loop++) {\r
    if ((Loop % 0x10) == 0) {\r
      DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
    }\r
    DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
    if ((Loop % 0x10) == 0xf) {\r
      DEBUG ((EFI_D_INFO, "\n"));\r
    }\r
  }\r
}\r
\r
\r
/**\r
  Perform Platform PEI initialization.\r
\r
  @param  FileHandle      Handle of the file being invoked.\r
  @param  PeiServices     Describes the list of possible PEI Services.\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializePlatform (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
  DebugDumpCmos ();\r
\r
  XenDetect ();\r
\r
  if (QemuFwCfgS3Enabled ()) {\r
    DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
    mS3Supported = TRUE;\r
  }\r
\r
  BootModeInitialization ();\r
  AddressWidthInitialization ();\r
\r
  PublishPeiMemory ();\r
\r
  InitializeRamRegions ();\r
\r
  if (mXen) {\r
    DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
    InitializeXen ();\r
  }\r
\r
  //\r
  // Query Host Bridge DID\r
  //\r
  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
  if (mBootMode != BOOT_ON_S3_RESUME) {\r
    ReserveEmuVariableNvStore ();\r
    PeiFvInitialization ();\r
    MemMapInitialization ();\r
    NoexecDxeInitialization ();\r
  }\r
\r
  MiscInitialization ();\r
\r
  return EFI_SUCCESS;\r
}\r
Commit	Line	Data
49ba9447	1	/**@file\r
	2	Platform PEI driver\r
	3	\r
869b17cc	4	Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
eec7d420	5	Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
eec7d420	6	\r
56d7640a	7	This program and the accompanying materials\r
49ba9447	8	are licensed and made available under the terms and conditions of the BSD License\r
	9	which accompanies this distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	//\r
	18	// The package level header files this module uses\r
	19	//\r
	20	#include <PiPei.h>\r
	21	\r
	22	//\r
	23	// The Library classes this module consumes\r
	24	//\r
	25	#include <Library/DebugLib.h>\r
	26	#include <Library/HobLib.h>\r
	27	#include <Library/IoLib.h>\r
77ba993c	28	#include <Library/MemoryAllocationLib.h>\r
77ba993c	29	#include <Library/PcdLib.h>\r
49ba9447	30	#include <Library/PciLib.h>\r
49ba9447	31	#include <Library/PeimEntryPoint.h>\r
9ed65b10	32	#include <Library/PeiServicesLib.h>\r
7cdba634	33	#include <Library/QemuFwCfgLib.h>\r
49ba9447	34	#include <Library/ResourcePublicationLib.h>\r
49ba9447	35	#include <Guid/MemoryTypeInformation.h>\r
9ed65b10	36	#include <Ppi/MasterBootMode.h>\r
931a0c74	37	#include <IndustryStandard/Pci22.h>\r
97380beb	38	#include <OvmfPlatforms.h>\r
49ba9447	39	\r
49ba9447	40	#include "Platform.h"\r
3ca15914	41	#include "Cmos.h"\r
49ba9447	42	\r
	43	EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
	44	{ EfiACPIMemoryNVS, 0x004 },\r
991d9563	45	{ EfiACPIReclaimMemory, 0x008 },\r
55cdb67a	46	{ EfiReservedMemoryType, 0x004 },\r
991d9563	47	{ EfiRuntimeServicesData, 0x024 },\r
	48	{ EfiRuntimeServicesCode, 0x030 },\r
	49	{ EfiBootServicesCode, 0x180 },\r
	50	{ EfiBootServicesData, 0xF00 },\r
49ba9447	51	{ EfiMaxMemoryType, 0x000 }\r
	52	};\r
	53	\r
	54	\r
9ed65b10	55	EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
	56	{\r
	57	EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
	58	&gEfiPeiMasterBootModePpiGuid,\r
	59	NULL\r
	60	}\r
	61	};\r
	62	\r
	63	\r
589756c7 PA	64	UINT16 mHostBridgeDevId;\r
589756c7 PA	65	\r
979420df JJ	66	EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
979420df JJ	67	\r
7cdba634 JJ	68	BOOLEAN mS3Supported = FALSE;\r
7cdba634 JJ	69	\r
979420df	70	\r
49ba9447	71	VOID\r
	72	AddIoMemoryBaseSizeHob (\r
	73	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	74	UINT64 MemorySize\r
	75	)\r
	76	{\r
991d9563	77	BuildResourceDescriptorHob (\r
991d9563	78	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
49ba9447	79	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	80	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	81	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
991d9563	82	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447	83	MemoryBase,\r
	84	MemorySize\r
	85	);\r
	86	}\r
	87	\r
eec7d420	88	VOID\r
	89	AddReservedMemoryBaseSizeHob (\r
	90	EFI_PHYSICAL_ADDRESS MemoryBase,\r
cdef34ec LE	91	UINT64 MemorySize,\r
cdef34ec LE	92	BOOLEAN Cacheable\r
eec7d420	93	)\r
	94	{\r
	95	BuildResourceDescriptorHob (\r
	96	EFI_RESOURCE_MEMORY_RESERVED,\r
	97	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	98	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	99	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
cdef34ec LE	100	(Cacheable ?\r
	101	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	102	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	103	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
	104	0\r
	105	) \|\r
eec7d420	106	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
	107	MemoryBase,\r
	108	MemorySize\r
	109	);\r
	110	}\r
49ba9447	111	\r
	112	VOID\r
	113	AddIoMemoryRangeHob (\r
	114	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	115	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	116	)\r
	117	{\r
	118	AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	119	}\r
	120	\r
	121	\r
	122	VOID\r
	123	AddMemoryBaseSizeHob (\r
	124	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	125	UINT64 MemorySize\r
	126	)\r
	127	{\r
991d9563	128	BuildResourceDescriptorHob (\r
991d9563	129	EFI_RESOURCE_SYSTEM_MEMORY,\r
49ba9447	130	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	131	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	132	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	133	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	134	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	135	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE \|\r
991d9563	136	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447	137	MemoryBase,\r
	138	MemorySize\r
	139	);\r
	140	}\r
	141	\r
	142	\r
	143	VOID\r
	144	AddMemoryRangeHob (\r
	145	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	146	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	147	)\r
	148	{\r
	149	AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	150	}\r
	151	\r
c0e10976	152	\r
	153	VOID\r
	154	AddUntestedMemoryBaseSizeHob (\r
	155	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	156	UINT64 MemorySize\r
	157	)\r
	158	{\r
	159	BuildResourceDescriptorHob (\r
	160	EFI_RESOURCE_SYSTEM_MEMORY,\r
	161	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	162	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	163	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	164	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	165	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	166	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
	167	MemoryBase,\r
	168	MemorySize\r
	169	);\r
	170	}\r
	171	\r
	172	\r
	173	VOID\r
	174	AddUntestedMemoryRangeHob (\r
	175	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	176	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	177	)\r
	178	{\r
	179	AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	180	}\r
	181	\r
bb6a9a93	182	VOID\r
4b455f7b	183	MemMapInitialization (\r
bb6a9a93 WL	184	VOID\r
	185	)\r
	186	{\r
bb6a9a93 WL	187	//\r
	188	// Create Memory Type Information HOB\r
	189	//\r
	190	BuildGuidDataHob (\r
	191	&gEfiMemoryTypeInformationGuid,\r
	192	mDefaultMemoryTypeInformation,\r
	193	sizeof(mDefaultMemoryTypeInformation)\r
	194	);\r
	195	\r
	196	//\r
	197	// Add PCI IO Port space available for PCI resource allocations.\r
	198	//\r
	199	BuildResourceDescriptorHob (\r
	200	EFI_RESOURCE_IO,\r
	201	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	202	EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
	203	0xC000,\r
	204	0x4000\r
	205	);\r
	206	\r
	207	//\r
	208	// Video memory + Legacy BIOS region\r
	209	//\r
	210	AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
	211	\r
4b455f7b JJ	212	if (!mXen) {\r
4b455f7b JJ	213	UINT32 TopOfLowRam;\r
c68d3a69 LE	214	UINT32 PciBase;\r
c68d3a69 LE	215	\r
4b455f7b	216	TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
c68d3a69 LE	217	if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
	218	//\r
	219	// A 3GB base will always fall into Q35's 32-bit PCI host aperture,\r
	220	// regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets\r
	221	// the RAM below 4 GB exceed it.\r
	222	//\r
	223	PciBase = BASE_2GB + BASE_1GB;\r
	224	ASSERT (TopOfLowRam <= PciBase);\r
	225	} else {\r
	226	PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
	227	}\r
49ba9447	228	\r
4b455f7b JJ	229	//\r
	230	// address purpose size\r
	231	// ------------ -------- -------------------------\r
	232	// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
	233	// 0xFC000000 gap 44 MB\r
	234	// 0xFEC00000 IO-APIC 4 KB\r
	235	// 0xFEC01000 gap 1020 KB\r
	236	// 0xFED00000 HPET 1 KB\r
90721ba5 PA	237	// 0xFED00400 gap 111 KB\r
	238	// 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
	239	// 0xFED20000 gap 896 KB\r
4b455f7b JJ	240	// 0xFEE00000 LAPIC 1 MB\r
4b455f7b JJ	241	//\r
c68d3a69	242	AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
4b455f7b JJ	243	AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
4b455f7b JJ	244	AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
90721ba5 PA	245	if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
	246	AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
	247	}\r
4b455f7b	248	AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
4b455f7b	249	}\r
49ba9447	250	}\r
49ba9447	251	\r
ab081a50 LE	252	EFI_STATUS\r
	253	GetNamedFwCfgBoolean (\r
	254	IN CHAR8 *FwCfgFileName,\r
	255	OUT BOOLEAN *Setting\r
	256	)\r
	257	{\r
	258	EFI_STATUS Status;\r
	259	FIRMWARE_CONFIG_ITEM FwCfgItem;\r
	260	UINTN FwCfgSize;\r
	261	UINT8 Value[3];\r
	262	\r
	263	Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
	264	if (EFI_ERROR (Status)) {\r
	265	return Status;\r
	266	}\r
	267	if (FwCfgSize > sizeof Value) {\r
	268	return EFI_BAD_BUFFER_SIZE;\r
	269	}\r
	270	QemuFwCfgSelectItem (FwCfgItem);\r
	271	QemuFwCfgReadBytes (FwCfgSize, Value);\r
	272	\r
	273	if ((FwCfgSize == 1) \|\|\r
	274	(FwCfgSize == 2 && Value[1] == '\n') \|\|\r
	275	(FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
	276	switch (Value[0]) {\r
	277	case '0':\r
	278	case 'n':\r
	279	case 'N':\r
	280	*Setting = FALSE;\r
	281	return EFI_SUCCESS;\r
	282	\r
	283	case '1':\r
	284	case 'y':\r
	285	case 'Y':\r
	286	*Setting = TRUE;\r
	287	return EFI_SUCCESS;\r
	288	\r
	289	default:\r
	290	break;\r
	291	}\r
	292	}\r
	293	return EFI_PROTOCOL_ERROR;\r
	294	}\r
	295	\r
	296	#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
	297	do { \\r
	298	BOOLEAN Setting; \\r
	299	\\r
	300	if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
	301	"opt/ovmf/" #TokenName, &Setting))) { \\r
	302	PcdSetBool (TokenName, Setting); \\r
	303	} \\r
	304	} while (0)\r
	305	\r
	306	VOID\r
	307	NoexecDxeInitialization (\r
	308	VOID\r
	309	)\r
	310	{\r
	311	UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
	312	UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
	313	}\r
49ba9447	314	\r
	315	VOID\r
	316	MiscInitialization (\r
0e20a186	317	VOID\r
49ba9447	318	)\r
49ba9447	319	{\r
97380beb GS	320	UINTN PmCmd;\r
97380beb GS	321	UINTN Pmba;\r
e2ab3f81 GS	322	UINTN AcpiCtlReg;\r
e2ab3f81 GS	323	UINT8 AcpiEnBit;\r
97380beb	324	\r
49ba9447	325	//\r
	326	// Disable A20 Mask\r
	327	//\r
55cdb67a	328	IoOr8 (0x92, BIT1);\r
49ba9447	329	\r
49ba9447	330	//\r
86a14b0a LE	331	// Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
	332	// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
	333	// S3 resume as well, so we build it unconditionally.)\r
49ba9447	334	//\r
86a14b0a	335	BuildCpuHob (mPhysMemAddressWidth, 16);\r
c756b2ab	336	\r
97380beb	337	//\r
589756c7	338	// Determine platform type and save Host Bridge DID to PCD\r
97380beb	339	//\r
589756c7	340	switch (mHostBridgeDevId) {\r
97380beb	341	case INTEL_82441_DEVICE_ID:\r
e2ab3f81	342	PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
da372167 LE	343	Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
	344	AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
	345	AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
97380beb GS	346	break;\r
97380beb GS	347	case INTEL_Q35_MCH_DEVICE_ID:\r
e2ab3f81	348	PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
bc9d05d6 LE	349	Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
	350	AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
	351	AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
97380beb GS	352	break;\r
	353	default:\r
	354	DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
589756c7	355	__FUNCTION__, mHostBridgeDevId));\r
97380beb GS	356	ASSERT (FALSE);\r
	357	return;\r
	358	}\r
589756c7	359	PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
97380beb	360	\r
0e20a186	361	//\r
e2ab3f81 GS	362	// If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
	363	// has been configured (e.g., by Xen) and skip the setup here.\r
	364	// This matches the logic in AcpiTimerLibConstructor ().\r
0e20a186	365	//\r
e2ab3f81	366	if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
eec7d420	367	//\r
e2ab3f81	368	// The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
931a0c74	369	// 1. set PMBA\r
eec7d420	370	//\r
97380beb	371	PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
931a0c74	372	\r
	373	//\r
	374	// 2. set PCICMD/IOSE\r
	375	//\r
97380beb	376	PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
931a0c74	377	\r
931a0c74	378	//\r
e2ab3f81	379	// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
931a0c74	380	//\r
e2ab3f81	381	PciOr8 (AcpiCtlReg, AcpiEnBit);\r
eec7d420	382	}\r
90721ba5 PA	383	\r
	384	if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
	385	//\r
	386	// Set Root Complex Register Block BAR\r
	387	//\r
	388	PciWrite32 (\r
	389	POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
	390	ICH9_ROOT_COMPLEX_BASE \| ICH9_RCBA_EN\r
	391	);\r
	392	}\r
49ba9447	393	}\r
	394	\r
	395	\r
9ed65b10	396	VOID\r
9ed65b10	397	BootModeInitialization (\r
8f5ca05b	398	VOID\r
9ed65b10	399	)\r
9ed65b10	400	{\r
8f5ca05b LE	401	EFI_STATUS Status;\r
	402	\r
	403	if (CmosRead8 (0xF) == 0xFE) {\r
979420df	404	mBootMode = BOOT_ON_S3_RESUME;\r
8f5ca05b	405	}\r
9be75189	406	CmosWrite8 (0xF, 0x00);\r
667bf1e4	407	\r
979420df	408	Status = PeiServicesSetBootMode (mBootMode);\r
667bf1e4	409	ASSERT_EFI_ERROR (Status);\r
	410	\r
	411	Status = PeiServicesInstallPpi (mPpiBootMode);\r
	412	ASSERT_EFI_ERROR (Status);\r
9ed65b10	413	}\r
	414	\r
	415	\r
77ba993c	416	VOID\r
	417	ReserveEmuVariableNvStore (\r
	418	)\r
	419	{\r
	420	EFI_PHYSICAL_ADDRESS VariableStore;\r
	421	\r
	422	//\r
	423	// Allocate storage for NV variables early on so it will be\r
	424	// at a consistent address. Since VM memory is preserved\r
	425	// across reboots, this allows the NV variable storage to survive\r
	426	// a VM reboot.\r
	427	//\r
	428	VariableStore =\r
	429	(EFI_PHYSICAL_ADDRESS)(UINTN)\r
9edb2933	430	AllocateAlignedRuntimePages (\r
cce992ac WL	431	EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
cce992ac WL	432	PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
27f58ea1	433	);\r
77ba993c	434	DEBUG ((EFI_D_INFO,\r
	435	"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
	436	VariableStore,\r
29a3f139	437	(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
77ba993c	438	));\r
	439	PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
	440	}\r
	441	\r
	442	\r
3ca15914	443	VOID\r
	444	DebugDumpCmos (\r
	445	VOID\r
	446	)\r
	447	{\r
6394c35a	448	UINT32 Loop;\r
3ca15914	449	\r
	450	DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
	451	\r
	452	for (Loop = 0; Loop < 0x80; Loop++) {\r
	453	if ((Loop % 0x10) == 0) {\r
	454	DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
	455	}\r
	456	DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
	457	if ((Loop % 0x10) == 0xf) {\r
	458	DEBUG ((EFI_D_INFO, "\n"));\r
	459	}\r
	460	}\r
	461	}\r
	462	\r
	463	\r
49ba9447	464	/**\r
	465	Perform Platform PEI initialization.\r
	466	\r
	467	@param FileHandle Handle of the file being invoked.\r
	468	@param PeiServices Describes the list of possible PEI Services.\r
	469	\r
	470	@return EFI_SUCCESS The PEIM initialized successfully.\r
	471	\r
	472	**/\r
	473	EFI_STATUS\r
	474	EFIAPI\r
	475	InitializePlatform (\r
	476	IN EFI_PEI_FILE_HANDLE FileHandle,\r
	477	IN CONST EFI_PEI_SERVICES **PeiServices\r
	478	)\r
	479	{\r
	480	DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
	481	\r
3ca15914	482	DebugDumpCmos ();\r
3ca15914	483	\r
b98b4941	484	XenDetect ();\r
c7ea55b9	485	\r
7cdba634 JJ	486	if (QemuFwCfgS3Enabled ()) {\r
	487	DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
	488	mS3Supported = TRUE;\r
	489	}\r
	490	\r
869b17cc	491	BootModeInitialization ();\r
bc89fe48	492	AddressWidthInitialization ();\r
869b17cc	493	\r
f76e9eba JJ	494	PublishPeiMemory ();\r
f76e9eba JJ	495	\r
2818c158	496	InitializeRamRegions ();\r
49ba9447	497	\r
b621bb0a	498	if (mXen) {\r
c7ea55b9	499	DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
b98b4941	500	InitializeXen ();\r
c7ea55b9	501	}\r
eec7d420	502	\r
589756c7 PA	503	//\r
	504	// Query Host Bridge DID\r
	505	//\r
	506	mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
	507	\r
bd386eaf JJ	508	if (mBootMode != BOOT_ON_S3_RESUME) {\r
bd386eaf JJ	509	ReserveEmuVariableNvStore ();\r
bd386eaf	510	PeiFvInitialization ();\r
bd386eaf	511	MemMapInitialization ();\r
ab081a50	512	NoexecDxeInitialization ();\r
bd386eaf	513	}\r
49ba9447	514	\r
0e20a186	515	MiscInitialization ();\r
49ba9447	516	\r
	517	return EFI_SUCCESS;\r
	518	}\r