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49ba9447 | 1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
869b17cc | 4 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r |
eec7d420 | 5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r |
6 | \r | |
56d7640a | 7 | This program and the accompanying materials\r |
49ba9447 | 8 | are licensed and made available under the terms and conditions of the BSD License\r |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // The package level header files this module uses\r | |
19 | //\r | |
20 | #include <PiPei.h>\r | |
21 | \r | |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/HobLib.h>\r | |
27 | #include <Library/IoLib.h>\r | |
77ba993c | 28 | #include <Library/MemoryAllocationLib.h>\r |
29 | #include <Library/PcdLib.h>\r | |
49ba9447 | 30 | #include <Library/PciLib.h>\r |
31 | #include <Library/PeimEntryPoint.h>\r | |
9ed65b10 | 32 | #include <Library/PeiServicesLib.h>\r |
7cdba634 | 33 | #include <Library/QemuFwCfgLib.h>\r |
49ba9447 | 34 | #include <Library/ResourcePublicationLib.h>\r |
35 | #include <Guid/MemoryTypeInformation.h>\r | |
9ed65b10 | 36 | #include <Ppi/MasterBootMode.h>\r |
931a0c74 | 37 | #include <IndustryStandard/Pci22.h>\r |
97380beb | 38 | #include <OvmfPlatforms.h>\r |
49ba9447 | 39 | \r |
40 | #include "Platform.h"\r | |
3ca15914 | 41 | #include "Cmos.h"\r |
49ba9447 | 42 | \r |
43 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
44 | { EfiACPIMemoryNVS, 0x004 },\r | |
991d9563 | 45 | { EfiACPIReclaimMemory, 0x008 },\r |
55cdb67a | 46 | { EfiReservedMemoryType, 0x004 },\r |
991d9563 | 47 | { EfiRuntimeServicesData, 0x024 },\r |
48 | { EfiRuntimeServicesCode, 0x030 },\r | |
49 | { EfiBootServicesCode, 0x180 },\r | |
50 | { EfiBootServicesData, 0xF00 },\r | |
49ba9447 | 51 | { EfiMaxMemoryType, 0x000 }\r |
52 | };\r | |
53 | \r | |
54 | \r | |
9ed65b10 | 55 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r |
56 | {\r | |
57 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
58 | &gEfiPeiMasterBootModePpiGuid,\r | |
59 | NULL\r | |
60 | }\r | |
61 | };\r | |
62 | \r | |
63 | \r | |
979420df JJ |
64 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r |
65 | \r | |
7cdba634 JJ |
66 | BOOLEAN mS3Supported = FALSE;\r |
67 | \r | |
979420df | 68 | \r |
49ba9447 | 69 | VOID\r |
70 | AddIoMemoryBaseSizeHob (\r | |
71 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
72 | UINT64 MemorySize\r | |
73 | )\r | |
74 | {\r | |
991d9563 | 75 | BuildResourceDescriptorHob (\r |
76 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
49ba9447 | 77 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
78 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
79 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
991d9563 | 80 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 81 | MemoryBase,\r |
82 | MemorySize\r | |
83 | );\r | |
84 | }\r | |
85 | \r | |
eec7d420 | 86 | VOID\r |
87 | AddReservedMemoryBaseSizeHob (\r | |
88 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
89 | UINT64 MemorySize\r | |
90 | )\r | |
91 | {\r | |
92 | BuildResourceDescriptorHob (\r | |
93 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
94 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
95 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
96 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
97 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
98 | MemoryBase,\r | |
99 | MemorySize\r | |
100 | );\r | |
101 | }\r | |
49ba9447 | 102 | \r |
103 | VOID\r | |
104 | AddIoMemoryRangeHob (\r | |
105 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
106 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
107 | )\r | |
108 | {\r | |
109 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
110 | }\r | |
111 | \r | |
112 | \r | |
113 | VOID\r | |
114 | AddMemoryBaseSizeHob (\r | |
115 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
116 | UINT64 MemorySize\r | |
117 | )\r | |
118 | {\r | |
991d9563 | 119 | BuildResourceDescriptorHob (\r |
120 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
49ba9447 | 121 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r |
122 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
123 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
124 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
125 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
126 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
991d9563 | 127 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r |
49ba9447 | 128 | MemoryBase,\r |
129 | MemorySize\r | |
130 | );\r | |
131 | }\r | |
132 | \r | |
133 | \r | |
134 | VOID\r | |
135 | AddMemoryRangeHob (\r | |
136 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
137 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
138 | )\r | |
139 | {\r | |
140 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
141 | }\r | |
142 | \r | |
c0e10976 | 143 | \r |
144 | VOID\r | |
145 | AddUntestedMemoryBaseSizeHob (\r | |
146 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
147 | UINT64 MemorySize\r | |
148 | )\r | |
149 | {\r | |
150 | BuildResourceDescriptorHob (\r | |
151 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
152 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
153 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
154 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
155 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
156 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
157 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r | |
158 | MemoryBase,\r | |
159 | MemorySize\r | |
160 | );\r | |
161 | }\r | |
162 | \r | |
163 | \r | |
164 | VOID\r | |
165 | AddUntestedMemoryRangeHob (\r | |
166 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
167 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
168 | )\r | |
169 | {\r | |
170 | AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
171 | }\r | |
172 | \r | |
bb6a9a93 | 173 | VOID\r |
4b455f7b | 174 | MemMapInitialization (\r |
bb6a9a93 WL |
175 | VOID\r |
176 | )\r | |
177 | {\r | |
bb6a9a93 WL |
178 | //\r |
179 | // Create Memory Type Information HOB\r | |
180 | //\r | |
181 | BuildGuidDataHob (\r | |
182 | &gEfiMemoryTypeInformationGuid,\r | |
183 | mDefaultMemoryTypeInformation,\r | |
184 | sizeof(mDefaultMemoryTypeInformation)\r | |
185 | );\r | |
186 | \r | |
187 | //\r | |
188 | // Add PCI IO Port space available for PCI resource allocations.\r | |
189 | //\r | |
190 | BuildResourceDescriptorHob (\r | |
191 | EFI_RESOURCE_IO,\r | |
192 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
193 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
194 | 0xC000,\r | |
195 | 0x4000\r | |
196 | );\r | |
197 | \r | |
198 | //\r | |
199 | // Video memory + Legacy BIOS region\r | |
200 | //\r | |
201 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
202 | \r | |
4b455f7b JJ |
203 | if (!mXen) {\r |
204 | UINT32 TopOfLowRam;\r | |
205 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r | |
49ba9447 | 206 | \r |
4b455f7b JJ |
207 | //\r |
208 | // address purpose size\r | |
209 | // ------------ -------- -------------------------\r | |
210 | // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r | |
211 | // 0xFC000000 gap 44 MB\r | |
212 | // 0xFEC00000 IO-APIC 4 KB\r | |
213 | // 0xFEC01000 gap 1020 KB\r | |
214 | // 0xFED00000 HPET 1 KB\r | |
215 | // 0xFED00400 gap 1023 KB\r | |
216 | // 0xFEE00000 LAPIC 1 MB\r | |
217 | //\r | |
218 | AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r | |
219 | BASE_2GB : TopOfLowRam, 0xFC000000);\r | |
220 | AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r | |
221 | AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r | |
222 | AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r | |
4b455f7b | 223 | }\r |
49ba9447 | 224 | }\r |
225 | \r | |
226 | \r | |
227 | VOID\r | |
228 | MiscInitialization (\r | |
0e20a186 | 229 | VOID\r |
49ba9447 | 230 | )\r |
231 | {\r | |
97380beb GS |
232 | UINT16 HostBridgeDevId;\r |
233 | UINTN PmCmd;\r | |
234 | UINTN Pmba;\r | |
235 | UINTN PmRegMisc;\r | |
236 | \r | |
49ba9447 | 237 | //\r |
238 | // Disable A20 Mask\r | |
239 | //\r | |
55cdb67a | 240 | IoOr8 (0x92, BIT1);\r |
49ba9447 | 241 | \r |
242 | //\r | |
243 | // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r | |
244 | //\r | |
245 | BuildCpuHob (36, 16);\r | |
c756b2ab | 246 | \r |
97380beb | 247 | //\r |
d55004da | 248 | // Query Host Bridge DID to determine platform type and save to PCD\r |
97380beb GS |
249 | //\r |
250 | HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
251 | switch (HostBridgeDevId) {\r | |
252 | case INTEL_82441_DEVICE_ID:\r | |
253 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r | |
254 | Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r | |
255 | PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r | |
256 | break;\r | |
257 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
258 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r | |
259 | Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r | |
260 | PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r | |
261 | break;\r | |
262 | default:\r | |
263 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
264 | __FUNCTION__, HostBridgeDevId));\r | |
265 | ASSERT (FALSE);\r | |
266 | return;\r | |
267 | }\r | |
d55004da | 268 | PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId);\r |
97380beb | 269 | \r |
0e20a186 | 270 | //\r |
271 | // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for\r | |
272 | // example by Xen) and skip the setup here. This matches the logic in\r | |
273 | // AcpiTimerLibConstructor ().\r | |
274 | //\r | |
97380beb | 275 | if ((PciRead8 (PmRegMisc) & 0x01) == 0) {\r |
eec7d420 | 276 | //\r |
931a0c74 | 277 | // The PEI phase should be exited with fully accessibe PIIX4 IO space:\r |
278 | // 1. set PMBA\r | |
eec7d420 | 279 | //\r |
97380beb | 280 | PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r |
931a0c74 | 281 | \r |
282 | //\r | |
283 | // 2. set PCICMD/IOSE\r | |
284 | //\r | |
97380beb | 285 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r |
931a0c74 | 286 | \r |
287 | //\r | |
288 | // 3. set PMREGMISC/PMIOSE\r | |
289 | //\r | |
97380beb | 290 | PciOr8 (PmRegMisc, 0x01);\r |
eec7d420 | 291 | }\r |
49ba9447 | 292 | }\r |
293 | \r | |
294 | \r | |
9ed65b10 | 295 | VOID\r |
296 | BootModeInitialization (\r | |
8f5ca05b | 297 | VOID\r |
9ed65b10 | 298 | )\r |
299 | {\r | |
8f5ca05b LE |
300 | EFI_STATUS Status;\r |
301 | \r | |
302 | if (CmosRead8 (0xF) == 0xFE) {\r | |
979420df | 303 | mBootMode = BOOT_ON_S3_RESUME;\r |
8f5ca05b | 304 | }\r |
667bf1e4 | 305 | \r |
979420df | 306 | Status = PeiServicesSetBootMode (mBootMode);\r |
667bf1e4 | 307 | ASSERT_EFI_ERROR (Status);\r |
308 | \r | |
309 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
310 | ASSERT_EFI_ERROR (Status);\r | |
9ed65b10 | 311 | }\r |
312 | \r | |
313 | \r | |
77ba993c | 314 | VOID\r |
315 | ReserveEmuVariableNvStore (\r | |
316 | )\r | |
317 | {\r | |
318 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
319 | \r | |
320 | //\r | |
321 | // Allocate storage for NV variables early on so it will be\r | |
322 | // at a consistent address. Since VM memory is preserved\r | |
323 | // across reboots, this allows the NV variable storage to survive\r | |
324 | // a VM reboot.\r | |
325 | //\r | |
326 | VariableStore =\r | |
327 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
9edb2933 | 328 | AllocateAlignedRuntimePages (\r |
cce992ac WL |
329 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r |
330 | PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r | |
27f58ea1 | 331 | );\r |
77ba993c | 332 | DEBUG ((EFI_D_INFO,\r |
333 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
334 | VariableStore,\r | |
29a3f139 | 335 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r |
77ba993c | 336 | ));\r |
337 | PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r | |
338 | }\r | |
339 | \r | |
340 | \r | |
3ca15914 | 341 | VOID\r |
342 | DebugDumpCmos (\r | |
343 | VOID\r | |
344 | )\r | |
345 | {\r | |
346 | UINTN Loop;\r | |
347 | \r | |
348 | DEBUG ((EFI_D_INFO, "CMOS:\n"));\r | |
349 | \r | |
350 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
351 | if ((Loop % 0x10) == 0) {\r | |
352 | DEBUG ((EFI_D_INFO, "%02x:", Loop));\r | |
353 | }\r | |
354 | DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r | |
355 | if ((Loop % 0x10) == 0xf) {\r | |
356 | DEBUG ((EFI_D_INFO, "\n"));\r | |
357 | }\r | |
358 | }\r | |
359 | }\r | |
360 | \r | |
361 | \r | |
49ba9447 | 362 | /**\r |
363 | Perform Platform PEI initialization.\r | |
364 | \r | |
365 | @param FileHandle Handle of the file being invoked.\r | |
366 | @param PeiServices Describes the list of possible PEI Services.\r | |
367 | \r | |
368 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
369 | \r | |
370 | **/\r | |
371 | EFI_STATUS\r | |
372 | EFIAPI\r | |
373 | InitializePlatform (\r | |
374 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
375 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
376 | )\r | |
377 | {\r | |
378 | DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r | |
379 | \r | |
3ca15914 | 380 | DebugDumpCmos ();\r |
381 | \r | |
b98b4941 | 382 | XenDetect ();\r |
c7ea55b9 | 383 | \r |
7cdba634 JJ |
384 | if (QemuFwCfgS3Enabled ()) {\r |
385 | DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r | |
386 | mS3Supported = TRUE;\r | |
387 | }\r | |
388 | \r | |
869b17cc JJ |
389 | BootModeInitialization ();\r |
390 | \r | |
f76e9eba JJ |
391 | PublishPeiMemory ();\r |
392 | \r | |
2818c158 | 393 | InitializeRamRegions ();\r |
49ba9447 | 394 | \r |
b621bb0a | 395 | if (mXen) {\r |
c7ea55b9 | 396 | DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r |
b98b4941 | 397 | InitializeXen ();\r |
c7ea55b9 | 398 | }\r |
eec7d420 | 399 | \r |
bd386eaf JJ |
400 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
401 | ReserveEmuVariableNvStore ();\r | |
77ba993c | 402 | \r |
bd386eaf | 403 | PeiFvInitialization ();\r |
49ba9447 | 404 | \r |
bd386eaf JJ |
405 | MemMapInitialization ();\r |
406 | }\r | |
49ba9447 | 407 | \r |
0e20a186 | 408 | MiscInitialization ();\r |
49ba9447 | 409 | \r |
410 | return EFI_SUCCESS;\r | |
411 | }\r |