[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

/**@file\r
  Platform PEI driver\r
\r
  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
  { EfiACPIMemoryNVS,       0x004 },\r
  { EfiACPIReclaimMemory,   0x008 },\r
  { EfiReservedMemoryType,  0x004 },\r
  { EfiRuntimeServicesData, 0x024 },\r
  { EfiRuntimeServicesCode, 0x030 },\r
  { EfiBootServicesCode,    0x180 },\r
  { EfiBootServicesData,    0xF00 },\r
  { EfiMaxMemoryType,       0x000 }\r
};\r
\r
\r
EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gEfiPeiMasterBootModePpiGuid,\r
    NULL\r
  }\r
};\r
\r
\r
UINT16 mHostBridgeDevId;\r
\r
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
\r
BOOLEAN mS3Supported = FALSE;\r
\r
\r
VOID\r
AddIoMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddReservedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_RESERVED,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddIoMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddUntestedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddUntestedMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
VOID\r
MemMapInitialization (\r
  VOID\r
  )\r
{\r
  //\r
  // Create Memory Type Information HOB\r
  //\r
  BuildGuidDataHob (\r
    &gEfiMemoryTypeInformationGuid,\r
    mDefaultMemoryTypeInformation,\r
    sizeof(mDefaultMemoryTypeInformation)\r
    );\r
\r
  //\r
  // Add PCI IO Port space available for PCI resource allocations.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_IO,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
    0xC000,\r
    0x4000\r
    );\r
\r
  //\r
  // Video memory + Legacy BIOS region\r
  //\r
  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
  if (!mXen) {\r
    UINT32  TopOfLowRam;\r
    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
\r
    //\r
    // address       purpose   size\r
    // ------------  --------  -------------------------\r
    // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
    // 0xFC000000    gap                           44 MB\r
    // 0xFEC00000    IO-APIC                        4 KB\r
    // 0xFEC01000    gap                         1020 KB\r
    // 0xFED00000    HPET                           1 KB\r
    // 0xFED00400    gap                          111 KB\r
    // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
    // 0xFED20000    gap                          896 KB\r
    // 0xFEE00000    LAPIC                          1 MB\r
    //\r
    AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
                         BASE_2GB : TopOfLowRam, 0xFC000000);\r
    AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
    AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
      AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
    }\r
    AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
  }\r
}\r
\r
\r
VOID\r
MiscInitialization (\r
  VOID\r
  )\r
{\r
  UINTN  PmCmd;\r
  UINTN  Pmba;\r
  UINTN  AcpiCtlReg;\r
  UINT8  AcpiEnBit;\r
\r
  //\r
  // Disable A20 Mask\r
  //\r
  IoOr8 (0x92, BIT1);\r
\r
  //\r
  // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
  // S3 resume as well, so we build it unconditionally.)\r
  //\r
  BuildCpuHob (mPhysMemAddressWidth, 16);\r
\r
  //\r
  // Determine platform type and save Host Bridge DID to PCD\r
  //\r
  switch (mHostBridgeDevId) {\r
    case INTEL_82441_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
      break;\r
    case INTEL_Q35_MCH_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
      break;\r
    default:\r
      DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
        __FUNCTION__, mHostBridgeDevId));\r
      ASSERT (FALSE);\r
      return;\r
  }\r
  PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
\r
  //\r
  // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
  // has been configured (e.g., by Xen) and skip the setup here.\r
  // This matches the logic in AcpiTimerLibConstructor ().\r
  //\r
  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
    //\r
    // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
    // 1. set PMBA\r
    //\r
    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
\r
    //\r
    // 2. set PCICMD/IOSE\r
    //\r
    PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
\r
    //\r
    // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
    //\r
    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
  }\r
\r
  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    //\r
    // Set Root Complex Register Block BAR\r
    //\r
    PciWrite32 (\r
      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
      );\r
  }\r
}\r
\r
\r
VOID\r
BootModeInitialization (\r
  VOID\r
  )\r
{\r
  EFI_STATUS    Status;\r
\r
  if (CmosRead8 (0xF) == 0xFE) {\r
    mBootMode = BOOT_ON_S3_RESUME;\r
  }\r
  CmosWrite8 (0xF, 0x00);\r
\r
  Status = PeiServicesSetBootMode (mBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = PeiServicesInstallPpi (mPpiBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
VOID\r
ReserveEmuVariableNvStore (\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS VariableStore;\r
\r
  //\r
  // Allocate storage for NV variables early on so it will be\r
  // at a consistent address.  Since VM memory is preserved\r
  // across reboots, this allows the NV variable storage to survive\r
  // a VM reboot.\r
  //\r
  VariableStore =\r
    (EFI_PHYSICAL_ADDRESS)(UINTN)\r
      AllocateAlignedRuntimePages (\r
        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
        PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
        );\r
  DEBUG ((EFI_D_INFO,\r
          "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
          VariableStore,\r
          (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
        ));\r
  PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
}\r
\r
\r
VOID\r
DebugDumpCmos (\r
  VOID\r
  )\r
{\r
  UINT32 Loop;\r
\r
  DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
  for (Loop = 0; Loop < 0x80; Loop++) {\r
    if ((Loop % 0x10) == 0) {\r
      DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
    }\r
    DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
    if ((Loop % 0x10) == 0xf) {\r
      DEBUG ((EFI_D_INFO, "\n"));\r
    }\r
  }\r
}\r
\r
\r
/**\r
  Perform Platform PEI initialization.\r
\r
  @param  FileHandle      Handle of the file being invoked.\r
  @param  PeiServices     Describes the list of possible PEI Services.\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializePlatform (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
  DebugDumpCmos ();\r
\r
  XenDetect ();\r
\r
  if (QemuFwCfgS3Enabled ()) {\r
    DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
    mS3Supported = TRUE;\r
  }\r
\r
  BootModeInitialization ();\r
  AddressWidthInitialization ();\r
\r
  PublishPeiMemory ();\r
\r
  InitializeRamRegions ();\r
\r
  if (mXen) {\r
    DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
    InitializeXen ();\r
  }\r
\r
  //\r
  // Query Host Bridge DID\r
  //\r
  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
  if (mBootMode != BOOT_ON_S3_RESUME) {\r
    ReserveEmuVariableNvStore ();\r
\r
    PeiFvInitialization ();\r
\r
    MemMapInitialization ();\r
  }\r
\r
  MiscInitialization ();\r
\r
  return EFI_SUCCESS;\r
}\r
Commit	Line	Data
49ba9447	1	/**@file\r
	2	Platform PEI driver\r
	3	\r
869b17cc	4	Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
eec7d420	5	Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
eec7d420	6	\r
56d7640a	7	This program and the accompanying materials\r
49ba9447	8	are licensed and made available under the terms and conditions of the BSD License\r
	9	which accompanies this distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	//\r
	18	// The package level header files this module uses\r
	19	//\r
	20	#include <PiPei.h>\r
	21	\r
	22	//\r
	23	// The Library classes this module consumes\r
	24	//\r
	25	#include <Library/DebugLib.h>\r
	26	#include <Library/HobLib.h>\r
	27	#include <Library/IoLib.h>\r
77ba993c	28	#include <Library/MemoryAllocationLib.h>\r
77ba993c	29	#include <Library/PcdLib.h>\r
49ba9447	30	#include <Library/PciLib.h>\r
49ba9447	31	#include <Library/PeimEntryPoint.h>\r
9ed65b10	32	#include <Library/PeiServicesLib.h>\r
7cdba634	33	#include <Library/QemuFwCfgLib.h>\r
49ba9447	34	#include <Library/ResourcePublicationLib.h>\r
49ba9447	35	#include <Guid/MemoryTypeInformation.h>\r
9ed65b10	36	#include <Ppi/MasterBootMode.h>\r
931a0c74	37	#include <IndustryStandard/Pci22.h>\r
97380beb	38	#include <OvmfPlatforms.h>\r
49ba9447	39	\r
49ba9447	40	#include "Platform.h"\r
3ca15914	41	#include "Cmos.h"\r
49ba9447	42	\r
	43	EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
	44	{ EfiACPIMemoryNVS, 0x004 },\r
991d9563	45	{ EfiACPIReclaimMemory, 0x008 },\r
55cdb67a	46	{ EfiReservedMemoryType, 0x004 },\r
991d9563	47	{ EfiRuntimeServicesData, 0x024 },\r
	48	{ EfiRuntimeServicesCode, 0x030 },\r
	49	{ EfiBootServicesCode, 0x180 },\r
	50	{ EfiBootServicesData, 0xF00 },\r
49ba9447	51	{ EfiMaxMemoryType, 0x000 }\r
	52	};\r
	53	\r
	54	\r
9ed65b10	55	EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
	56	{\r
	57	EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
	58	&gEfiPeiMasterBootModePpiGuid,\r
	59	NULL\r
	60	}\r
	61	};\r
	62	\r
	63	\r
589756c7 PA	64	UINT16 mHostBridgeDevId;\r
589756c7 PA	65	\r
979420df JJ	66	EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
979420df JJ	67	\r
7cdba634 JJ	68	BOOLEAN mS3Supported = FALSE;\r
7cdba634 JJ	69	\r
979420df	70	\r
49ba9447	71	VOID\r
	72	AddIoMemoryBaseSizeHob (\r
	73	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	74	UINT64 MemorySize\r
	75	)\r
	76	{\r
991d9563	77	BuildResourceDescriptorHob (\r
991d9563	78	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
49ba9447	79	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	80	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	81	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
991d9563	82	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447	83	MemoryBase,\r
	84	MemorySize\r
	85	);\r
	86	}\r
	87	\r
eec7d420	88	VOID\r
	89	AddReservedMemoryBaseSizeHob (\r
	90	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	91	UINT64 MemorySize\r
	92	)\r
	93	{\r
	94	BuildResourceDescriptorHob (\r
	95	EFI_RESOURCE_MEMORY_RESERVED,\r
	96	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	97	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	98	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	99	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
	100	MemoryBase,\r
	101	MemorySize\r
	102	);\r
	103	}\r
49ba9447	104	\r
	105	VOID\r
	106	AddIoMemoryRangeHob (\r
	107	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	108	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	109	)\r
	110	{\r
	111	AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	112	}\r
	113	\r
	114	\r
	115	VOID\r
	116	AddMemoryBaseSizeHob (\r
	117	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	118	UINT64 MemorySize\r
	119	)\r
	120	{\r
991d9563	121	BuildResourceDescriptorHob (\r
991d9563	122	EFI_RESOURCE_SYSTEM_MEMORY,\r
49ba9447	123	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	124	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	125	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	126	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	127	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	128	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE \|\r
991d9563	129	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447	130	MemoryBase,\r
	131	MemorySize\r
	132	);\r
	133	}\r
	134	\r
	135	\r
	136	VOID\r
	137	AddMemoryRangeHob (\r
	138	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	139	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	140	)\r
	141	{\r
	142	AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	143	}\r
	144	\r
c0e10976	145	\r
	146	VOID\r
	147	AddUntestedMemoryBaseSizeHob (\r
	148	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	149	UINT64 MemorySize\r
	150	)\r
	151	{\r
	152	BuildResourceDescriptorHob (\r
	153	EFI_RESOURCE_SYSTEM_MEMORY,\r
	154	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	155	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	156	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	157	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	158	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	159	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
	160	MemoryBase,\r
	161	MemorySize\r
	162	);\r
	163	}\r
	164	\r
	165	\r
	166	VOID\r
	167	AddUntestedMemoryRangeHob (\r
	168	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	169	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	170	)\r
	171	{\r
	172	AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	173	}\r
	174	\r
bb6a9a93	175	VOID\r
4b455f7b	176	MemMapInitialization (\r
bb6a9a93 WL	177	VOID\r
	178	)\r
	179	{\r
bb6a9a93 WL	180	//\r
	181	// Create Memory Type Information HOB\r
	182	//\r
	183	BuildGuidDataHob (\r
	184	&gEfiMemoryTypeInformationGuid,\r
	185	mDefaultMemoryTypeInformation,\r
	186	sizeof(mDefaultMemoryTypeInformation)\r
	187	);\r
	188	\r
	189	//\r
	190	// Add PCI IO Port space available for PCI resource allocations.\r
	191	//\r
	192	BuildResourceDescriptorHob (\r
	193	EFI_RESOURCE_IO,\r
	194	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	195	EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
	196	0xC000,\r
	197	0x4000\r
	198	);\r
	199	\r
	200	//\r
	201	// Video memory + Legacy BIOS region\r
	202	//\r
	203	AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
	204	\r
4b455f7b JJ	205	if (!mXen) {\r
	206	UINT32 TopOfLowRam;\r
	207	TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
49ba9447	208	\r
4b455f7b JJ	209	//\r
	210	// address purpose size\r
	211	// ------------ -------- -------------------------\r
	212	// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
	213	// 0xFC000000 gap 44 MB\r
	214	// 0xFEC00000 IO-APIC 4 KB\r
	215	// 0xFEC01000 gap 1020 KB\r
	216	// 0xFED00000 HPET 1 KB\r
90721ba5 PA	217	// 0xFED00400 gap 111 KB\r
	218	// 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
	219	// 0xFED20000 gap 896 KB\r
4b455f7b JJ	220	// 0xFEE00000 LAPIC 1 MB\r
	221	//\r
	222	AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
	223	BASE_2GB : TopOfLowRam, 0xFC000000);\r
	224	AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
	225	AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
90721ba5 PA	226	if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
	227	AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
	228	}\r
4b455f7b	229	AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
4b455f7b	230	}\r
49ba9447	231	}\r
	232	\r
	233	\r
	234	VOID\r
	235	MiscInitialization (\r
0e20a186	236	VOID\r
49ba9447	237	)\r
49ba9447	238	{\r
97380beb GS	239	UINTN PmCmd;\r
97380beb GS	240	UINTN Pmba;\r
e2ab3f81 GS	241	UINTN AcpiCtlReg;\r
e2ab3f81 GS	242	UINT8 AcpiEnBit;\r
97380beb	243	\r
49ba9447	244	//\r
	245	// Disable A20 Mask\r
	246	//\r
55cdb67a	247	IoOr8 (0x92, BIT1);\r
49ba9447	248	\r
49ba9447	249	//\r
86a14b0a LE	250	// Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
	251	// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
	252	// S3 resume as well, so we build it unconditionally.)\r
49ba9447	253	//\r
86a14b0a	254	BuildCpuHob (mPhysMemAddressWidth, 16);\r
c756b2ab	255	\r
97380beb	256	//\r
589756c7	257	// Determine platform type and save Host Bridge DID to PCD\r
97380beb	258	//\r
589756c7	259	switch (mHostBridgeDevId) {\r
97380beb	260	case INTEL_82441_DEVICE_ID:\r
e2ab3f81	261	PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
da372167 LE	262	Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
	263	AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
	264	AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
97380beb GS	265	break;\r
97380beb GS	266	case INTEL_Q35_MCH_DEVICE_ID:\r
e2ab3f81	267	PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
bc9d05d6 LE	268	Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
	269	AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
	270	AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
97380beb GS	271	break;\r
	272	default:\r
	273	DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
589756c7	274	__FUNCTION__, mHostBridgeDevId));\r
97380beb GS	275	ASSERT (FALSE);\r
	276	return;\r
	277	}\r
589756c7	278	PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
97380beb	279	\r
0e20a186	280	//\r
e2ab3f81 GS	281	// If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
	282	// has been configured (e.g., by Xen) and skip the setup here.\r
	283	// This matches the logic in AcpiTimerLibConstructor ().\r
0e20a186	284	//\r
e2ab3f81	285	if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
eec7d420	286	//\r
e2ab3f81	287	// The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
931a0c74	288	// 1. set PMBA\r
eec7d420	289	//\r
97380beb	290	PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
931a0c74	291	\r
	292	//\r
	293	// 2. set PCICMD/IOSE\r
	294	//\r
97380beb	295	PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
931a0c74	296	\r
931a0c74	297	//\r
e2ab3f81	298	// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
931a0c74	299	//\r
e2ab3f81	300	PciOr8 (AcpiCtlReg, AcpiEnBit);\r
eec7d420	301	}\r
90721ba5 PA	302	\r
	303	if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
	304	//\r
	305	// Set Root Complex Register Block BAR\r
	306	//\r
	307	PciWrite32 (\r
	308	POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
	309	ICH9_ROOT_COMPLEX_BASE \| ICH9_RCBA_EN\r
	310	);\r
	311	}\r
49ba9447	312	}\r
	313	\r
	314	\r
9ed65b10	315	VOID\r
9ed65b10	316	BootModeInitialization (\r
8f5ca05b	317	VOID\r
9ed65b10	318	)\r
9ed65b10	319	{\r
8f5ca05b LE	320	EFI_STATUS Status;\r
	321	\r
	322	if (CmosRead8 (0xF) == 0xFE) {\r
979420df	323	mBootMode = BOOT_ON_S3_RESUME;\r
8f5ca05b	324	}\r
9be75189	325	CmosWrite8 (0xF, 0x00);\r
667bf1e4	326	\r
979420df	327	Status = PeiServicesSetBootMode (mBootMode);\r
667bf1e4	328	ASSERT_EFI_ERROR (Status);\r
	329	\r
	330	Status = PeiServicesInstallPpi (mPpiBootMode);\r
	331	ASSERT_EFI_ERROR (Status);\r
9ed65b10	332	}\r
	333	\r
	334	\r
77ba993c	335	VOID\r
	336	ReserveEmuVariableNvStore (\r
	337	)\r
	338	{\r
	339	EFI_PHYSICAL_ADDRESS VariableStore;\r
	340	\r
	341	//\r
	342	// Allocate storage for NV variables early on so it will be\r
	343	// at a consistent address. Since VM memory is preserved\r
	344	// across reboots, this allows the NV variable storage to survive\r
	345	// a VM reboot.\r
	346	//\r
	347	VariableStore =\r
	348	(EFI_PHYSICAL_ADDRESS)(UINTN)\r
9edb2933	349	AllocateAlignedRuntimePages (\r
cce992ac WL	350	EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
cce992ac WL	351	PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
27f58ea1	352	);\r
77ba993c	353	DEBUG ((EFI_D_INFO,\r
	354	"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
	355	VariableStore,\r
29a3f139	356	(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
77ba993c	357	));\r
	358	PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
	359	}\r
	360	\r
	361	\r
3ca15914	362	VOID\r
	363	DebugDumpCmos (\r
	364	VOID\r
	365	)\r
	366	{\r
6394c35a	367	UINT32 Loop;\r
3ca15914	368	\r
	369	DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
	370	\r
	371	for (Loop = 0; Loop < 0x80; Loop++) {\r
	372	if ((Loop % 0x10) == 0) {\r
	373	DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
	374	}\r
	375	DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
	376	if ((Loop % 0x10) == 0xf) {\r
	377	DEBUG ((EFI_D_INFO, "\n"));\r
	378	}\r
	379	}\r
	380	}\r
	381	\r
	382	\r
49ba9447	383	/**\r
	384	Perform Platform PEI initialization.\r
	385	\r
	386	@param FileHandle Handle of the file being invoked.\r
	387	@param PeiServices Describes the list of possible PEI Services.\r
	388	\r
	389	@return EFI_SUCCESS The PEIM initialized successfully.\r
	390	\r
	391	**/\r
	392	EFI_STATUS\r
	393	EFIAPI\r
	394	InitializePlatform (\r
	395	IN EFI_PEI_FILE_HANDLE FileHandle,\r
	396	IN CONST EFI_PEI_SERVICES **PeiServices\r
	397	)\r
	398	{\r
	399	DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
	400	\r
3ca15914	401	DebugDumpCmos ();\r
3ca15914	402	\r
b98b4941	403	XenDetect ();\r
c7ea55b9	404	\r
7cdba634 JJ	405	if (QemuFwCfgS3Enabled ()) {\r
	406	DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
	407	mS3Supported = TRUE;\r
	408	}\r
	409	\r
869b17cc	410	BootModeInitialization ();\r
bc89fe48	411	AddressWidthInitialization ();\r
869b17cc	412	\r
f76e9eba JJ	413	PublishPeiMemory ();\r
f76e9eba JJ	414	\r
2818c158	415	InitializeRamRegions ();\r
49ba9447	416	\r
b621bb0a	417	if (mXen) {\r
c7ea55b9	418	DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
b98b4941	419	InitializeXen ();\r
c7ea55b9	420	}\r
eec7d420	421	\r
589756c7 PA	422	//\r
	423	// Query Host Bridge DID\r
	424	//\r
	425	mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
	426	\r
bd386eaf JJ	427	if (mBootMode != BOOT_ON_S3_RESUME) {\r
bd386eaf JJ	428	ReserveEmuVariableNvStore ();\r
77ba993c	429	\r
bd386eaf	430	PeiFvInitialization ();\r
49ba9447	431	\r
bd386eaf JJ	432	MemMapInitialization ();\r
bd386eaf JJ	433	}\r
49ba9447	434	\r
0e20a186	435	MiscInitialization ();\r
49ba9447	436	\r
	437	return EFI_SUCCESS;\r
	438	}\r