[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

/**@file\r
  Platform PEI driver\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/QemuFwCfgS3Lib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
  { EfiACPIMemoryNVS,       0x004 },\r
  { EfiACPIReclaimMemory,   0x008 },\r
  { EfiReservedMemoryType,  0x004 },\r
  { EfiRuntimeServicesData, 0x024 },\r
  { EfiRuntimeServicesCode, 0x030 },\r
  { EfiBootServicesCode,    0x180 },\r
  { EfiBootServicesData,    0xF00 },\r
  { EfiMaxMemoryType,       0x000 }\r
};\r
\r
\r
EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gEfiPeiMasterBootModePpiGuid,\r
    NULL\r
  }\r
};\r
\r
\r
UINT16 mHostBridgeDevId;\r
\r
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
\r
BOOLEAN mS3Supported = FALSE;\r
\r
UINT32 mMaxCpuCount;\r
\r
VOID\r
AddIoMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddReservedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize,\r
  BOOLEAN                     Cacheable\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_RESERVED,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      (Cacheable ?\r
       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
       0\r
       ) |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddIoMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
MemMapInitialization (\r
  VOID\r
  )\r
{\r
  UINT64        PciIoBase;\r
  UINT64        PciIoSize;\r
  RETURN_STATUS PcdStatus;\r
\r
  PciIoBase = 0xC000;\r
  PciIoSize = 0x4000;\r
\r
  //\r
  // Create Memory Type Information HOB\r
  //\r
  BuildGuidDataHob (\r
    &gEfiMemoryTypeInformationGuid,\r
    mDefaultMemoryTypeInformation,\r
    sizeof(mDefaultMemoryTypeInformation)\r
    );\r
\r
  //\r
  // Video memory + Legacy BIOS region\r
  //\r
  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
  if (!mXen) {\r
    UINT32  TopOfLowRam;\r
    UINT64  PciExBarBase;\r
    UINT32  PciBase;\r
    UINT32  PciSize;\r
\r
    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
    PciExBarBase = 0;\r
    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
      //\r
      // The MMCONFIG area is expected to fall between the top of low RAM and\r
      // the base of the 32-bit PCI host aperture.\r
      //\r
      PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
      ASSERT (TopOfLowRam <= PciExBarBase);\r
      ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
      PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
    } else {\r
      PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
    }\r
\r
    //\r
    // address       purpose   size\r
    // ------------  --------  -------------------------\r
    // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
    // 0xFC000000    gap                           44 MB\r
    // 0xFEC00000    IO-APIC                        4 KB\r
    // 0xFEC01000    gap                         1020 KB\r
    // 0xFED00000    HPET                           1 KB\r
    // 0xFED00400    gap                          111 KB\r
    // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
    // 0xFED20000    gap                          896 KB\r
    // 0xFEE00000    LAPIC                          1 MB\r
    //\r
    PciSize = 0xFC000000 - PciBase;\r
    AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
    PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
    ASSERT_RETURN_ERROR (PcdStatus);\r
    PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
    ASSERT_RETURN_ERROR (PcdStatus);\r
\r
    AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
    AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
      AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
      //\r
      // Note: there should be an\r
      //\r
      //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
      //\r
      // call below, just like the one above for RCBA. However, Linux insists\r
      // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
      // "reserved memory" -- Linux does not content itself with a simple gap\r
      // in the memory map wherever the MCFG ACPI table points to.\r
      //\r
      // This appears to be a safety measure. The PCI Firmware Specification\r
      // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
      // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
      // [...]". (Emphasis added here.)\r
      //\r
      // Normally we add memory resource descriptor HOBs in\r
      // QemuInitializeRam(), and pre-allocate from those with memory\r
      // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
      // is most definitely not RAM; so, as an exception, cover it with\r
      // uncacheable reserved memory right here.\r
      //\r
      AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
      BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,\r
        EfiReservedMemoryType);\r
    }\r
    AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
\r
    //\r
    // On Q35, the IO Port space is available for PCI resource allocations from\r
    // 0x6000 up.\r
    //\r
    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
      PciIoBase = 0x6000;\r
      PciIoSize = 0xA000;\r
      ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
    }\r
  }\r
\r
  //\r
  // Add PCI IO Port space available for PCI resource allocations.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_IO,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
    PciIoBase,\r
    PciIoSize\r
    );\r
  PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
EFI_STATUS\r
GetNamedFwCfgBoolean (\r
  IN  CHAR8   *FwCfgFileName,\r
  OUT BOOLEAN *Setting\r
  )\r
{\r
  EFI_STATUS           Status;\r
  FIRMWARE_CONFIG_ITEM FwCfgItem;\r
  UINTN                FwCfgSize;\r
  UINT8                Value[3];\r
\r
  Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  if (FwCfgSize > sizeof Value) {\r
    return EFI_BAD_BUFFER_SIZE;\r
  }\r
  QemuFwCfgSelectItem (FwCfgItem);\r
  QemuFwCfgReadBytes (FwCfgSize, Value);\r
\r
  if ((FwCfgSize == 1) ||\r
      (FwCfgSize == 2 && Value[1] == '\n') ||\r
      (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
    switch (Value[0]) {\r
      case '0':\r
      case 'n':\r
      case 'N':\r
        *Setting = FALSE;\r
        return EFI_SUCCESS;\r
\r
      case '1':\r
      case 'y':\r
      case 'Y':\r
        *Setting = TRUE;\r
        return EFI_SUCCESS;\r
\r
      default:\r
        break;\r
    }\r
  }\r
  return EFI_PROTOCOL_ERROR;\r
}\r
\r
#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \\r
          do {                                                      \\r
            BOOLEAN       Setting;                                  \\r
            RETURN_STATUS PcdStatus;                                \\r
                                                                    \\r
            if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \\r
                              "opt/ovmf/" #TokenName, &Setting))) { \\r
              PcdStatus = PcdSetBoolS (TokenName, Setting);         \\r
              ASSERT_RETURN_ERROR (PcdStatus);                      \\r
            }                                                       \\r
          } while (0)\r
\r
VOID\r
NoexecDxeInitialization (\r
  VOID\r
  )\r
{\r
  UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
  UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
}\r
\r
VOID\r
PciExBarInitialization (\r
  VOID\r
  )\r
{\r
  union {\r
    UINT64 Uint64;\r
    UINT32 Uint32[2];\r
  } PciExBarBase;\r
\r
  //\r
  // We only support the 256MB size for the MMCONFIG area:\r
  // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r
  //\r
  // The masks used below enforce the Q35 requirements that the MMCONFIG area\r
  // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r
  //\r
  // Note that (b) also ensures that the minimum address width we have\r
  // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
  // for DXE's page tables to cover the MMCONFIG area.\r
  //\r
  PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
  ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
  ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
\r
  //\r
  // Clear the PCIEXBAREN bit first, before programming the high register.\r
  //\r
  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r
\r
  //\r
  // Program the high register. Then program the low register, setting the\r
  // MMCONFIG area size and enabling decoding at once.\r
  //\r
  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r
  PciWrite32 (\r
    DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r
    PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r
    );\r
}\r
\r
VOID\r
MiscInitialization (\r
  VOID\r
  )\r
{\r
  UINTN         PmCmd;\r
  UINTN         Pmba;\r
  UINT32        PmbaAndVal;\r
  UINT32        PmbaOrVal;\r
  UINTN         AcpiCtlReg;\r
  UINT8         AcpiEnBit;\r
  RETURN_STATUS PcdStatus;\r
\r
  //\r
  // Disable A20 Mask\r
  //\r
  IoOr8 (0x92, BIT1);\r
\r
  //\r
  // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
  // S3 resume as well, so we build it unconditionally.)\r
  //\r
  BuildCpuHob (mPhysMemAddressWidth, 16);\r
\r
  //\r
  // Determine platform type and save Host Bridge DID to PCD\r
  //\r
  switch (mHostBridgeDevId) {\r
    case INTEL_82441_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
      PmbaOrVal  = PIIX4_PMBA_VALUE;\r
      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
      break;\r
    case INTEL_Q35_MCH_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
      PmbaOrVal  = ICH9_PMBASE_VALUE;\r
      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
      break;\r
    default:\r
      DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
        __FUNCTION__, mHostBridgeDevId));\r
      ASSERT (FALSE);\r
      return;\r
  }\r
  PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
\r
  //\r
  // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
  // has been configured (e.g., by Xen) and skip the setup here.\r
  // This matches the logic in AcpiTimerLibConstructor ().\r
  //\r
  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
    //\r
    // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
    // 1. set PMBA\r
    //\r
    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
\r
    //\r
    // 2. set PCICMD/IOSE\r
    //\r
    PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
\r
    //\r
    // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
    //\r
    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
  }\r
\r
  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    //\r
    // Set Root Complex Register Block BAR\r
    //\r
    PciWrite32 (\r
      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
      );\r
\r
    //\r
    // Set PCI Express Register Range Base Address\r
    //\r
    PciExBarInitialization ();\r
  }\r
}\r
\r
\r
VOID\r
BootModeInitialization (\r
  VOID\r
  )\r
{\r
  EFI_STATUS    Status;\r
\r
  if (CmosRead8 (0xF) == 0xFE) {\r
    mBootMode = BOOT_ON_S3_RESUME;\r
  }\r
  CmosWrite8 (0xF, 0x00);\r
\r
  Status = PeiServicesSetBootMode (mBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = PeiServicesInstallPpi (mPpiBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
VOID\r
ReserveEmuVariableNvStore (\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS VariableStore;\r
  RETURN_STATUS        PcdStatus;\r
\r
  //\r
  // Allocate storage for NV variables early on so it will be\r
  // at a consistent address.  Since VM memory is preserved\r
  // across reboots, this allows the NV variable storage to survive\r
  // a VM reboot.\r
  //\r
  VariableStore =\r
    (EFI_PHYSICAL_ADDRESS)(UINTN)\r
      AllocateRuntimePages (\r
        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
        );\r
  DEBUG ((EFI_D_INFO,\r
          "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
          VariableStore,\r
          (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
        ));\r
  PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
\r
VOID\r
DebugDumpCmos (\r
  VOID\r
  )\r
{\r
  UINT32 Loop;\r
\r
  DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
  for (Loop = 0; Loop < 0x80; Loop++) {\r
    if ((Loop % 0x10) == 0) {\r
      DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
    }\r
    DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
    if ((Loop % 0x10) == 0xf) {\r
      DEBUG ((EFI_D_INFO, "\n"));\r
    }\r
  }\r
}\r
\r
\r
VOID\r
S3Verification (\r
  VOID\r
  )\r
{\r
#if defined (MDE_CPU_X64)\r
  if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
    DEBUG ((EFI_D_ERROR,\r
      "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
    DEBUG ((EFI_D_ERROR,\r
      "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
      __FUNCTION__));\r
    DEBUG ((EFI_D_ERROR,\r
      "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
#endif\r
}\r
\r
\r
/**\r
  Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r
  Set the mMaxCpuCount variable.\r
**/\r
VOID\r
MaxCpuCountInitialization (\r
  VOID\r
  )\r
{\r
  UINT16        ProcessorCount;\r
  RETURN_STATUS PcdStatus;\r
\r
  QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
  ProcessorCount = QemuFwCfgRead16 ();\r
  //\r
  // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r
  // from the PCD default. No change to PCDs.\r
  //\r
  if (ProcessorCount == 0) {\r
    mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
    return;\r
  }\r
  //\r
  // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r
  //\r
  mMaxCpuCount = ProcessorCount;\r
  //\r
  // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r
  // to wait, in the initial AP bringup, exactly as long as it takes for all of\r
  // the APs to report in. For this, we set the longest representable timeout\r
  // (approx. 71 minutes).\r
  //\r
  PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r
    ProcessorCount));\r
}\r
\r
\r
/**\r
  Perform Platform PEI initialization.\r
\r
  @param  FileHandle      Handle of the file being invoked.\r
  @param  PeiServices     Describes the list of possible PEI Services.\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializePlatform (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  EFI_STATUS    Status;\r
\r
  DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
\r
  DebugDumpCmos ();\r
\r
  XenDetect ();\r
\r
  if (QemuFwCfgS3Enabled ()) {\r
    DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
    mS3Supported = TRUE;\r
    Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
\r
  S3Verification ();\r
  BootModeInitialization ();\r
  AddressWidthInitialization ();\r
  MaxCpuCountInitialization ();\r
\r
  //\r
  // Query Host Bridge DID\r
  //\r
  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
  if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
    Q35TsegMbytesInitialization ();\r
  }\r
\r
  PublishPeiMemory ();\r
\r
  InitializeRamRegions ();\r
\r
  if (mXen) {\r
    DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
    InitializeXen ();\r
  }\r
\r
  if (mBootMode != BOOT_ON_S3_RESUME) {\r
    if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
      ReserveEmuVariableNvStore ();\r
    }\r
    PeiFvInitialization ();\r
    MemMapInitialization ();\r
    NoexecDxeInitialization ();\r
  }\r
\r
  InstallClearCacheCallback ();\r
  AmdSevInitialize ();\r
  MiscInitialization ();\r
  InstallFeatureControlCallback ();\r
\r
  return EFI_SUCCESS;\r
}\r