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OvmfPkg: PlatformPei: lower the 32-bit PCI MMIO base to 2GB on Q35
[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c
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49ba9447 1/**@file\r
2 Platform PEI driver\r
3\r
869b17cc 4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
eec7d420 5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6\r
56d7640a 7 This program and the accompanying materials\r
49ba9447 8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17//\r
18// The package level header files this module uses\r
19//\r
20#include <PiPei.h>\r
21\r
22//\r
23// The Library classes this module consumes\r
24//\r
5133d1f1 25#include <Library/BaseLib.h>\r
49ba9447 26#include <Library/DebugLib.h>\r
27#include <Library/HobLib.h>\r
28#include <Library/IoLib.h>\r
77ba993c 29#include <Library/MemoryAllocationLib.h>\r
30#include <Library/PcdLib.h>\r
49ba9447 31#include <Library/PciLib.h>\r
32#include <Library/PeimEntryPoint.h>\r
9ed65b10 33#include <Library/PeiServicesLib.h>\r
7cdba634 34#include <Library/QemuFwCfgLib.h>\r
49ba9447 35#include <Library/ResourcePublicationLib.h>\r
36#include <Guid/MemoryTypeInformation.h>\r
9ed65b10 37#include <Ppi/MasterBootMode.h>\r
931a0c74 38#include <IndustryStandard/Pci22.h>\r
97380beb 39#include <OvmfPlatforms.h>\r
49ba9447 40\r
41#include "Platform.h"\r
3ca15914 42#include "Cmos.h"\r
49ba9447 43\r
44EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
45 { EfiACPIMemoryNVS, 0x004 },\r
991d9563 46 { EfiACPIReclaimMemory, 0x008 },\r
55cdb67a 47 { EfiReservedMemoryType, 0x004 },\r
991d9563 48 { EfiRuntimeServicesData, 0x024 },\r
49 { EfiRuntimeServicesCode, 0x030 },\r
50 { EfiBootServicesCode, 0x180 },\r
51 { EfiBootServicesData, 0xF00 },\r
49ba9447 52 { EfiMaxMemoryType, 0x000 }\r
53};\r
54\r
55\r
9ed65b10 56EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
57 {\r
58 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
59 &gEfiPeiMasterBootModePpiGuid,\r
60 NULL\r
61 }\r
62};\r
63\r
64\r
589756c7
PA		 65UINT16 mHostBridgeDevId;\r
66\r
979420df
JJ		 67EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
68\r
7cdba634
JJ		 69BOOLEAN mS3Supported = FALSE;\r
70\r
979420df 71\r
49ba9447 72VOID\r
73AddIoMemoryBaseSizeHob (\r
74 EFI_PHYSICAL_ADDRESS MemoryBase,\r
75 UINT64 MemorySize\r
76 )\r
77{\r
991d9563 78 BuildResourceDescriptorHob (\r
79 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
49ba9447 80 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
81 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
82 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
991d9563 83 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447 84 MemoryBase,\r
85 MemorySize\r
86 );\r
87}\r
88\r
eec7d420 89VOID\r
90AddReservedMemoryBaseSizeHob (\r
91 EFI_PHYSICAL_ADDRESS MemoryBase,\r
cdef34ec
LE		 92 UINT64 MemorySize,\r
93 BOOLEAN Cacheable\r
eec7d420 94 )\r
95{\r
96 BuildResourceDescriptorHob (\r
97 EFI_RESOURCE_MEMORY_RESERVED,\r
98 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
99 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
100 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
cdef34ec
LE		 101 (Cacheable ?\r
102 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
103 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
104 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
105 0\r
106 ) |\r
eec7d420 107 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
108 MemoryBase,\r
109 MemorySize\r
110 );\r
111}\r
49ba9447 112\r
113VOID\r
114AddIoMemoryRangeHob (\r
115 EFI_PHYSICAL_ADDRESS MemoryBase,\r
116 EFI_PHYSICAL_ADDRESS MemoryLimit\r
117 )\r
118{\r
119 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
120}\r
121\r
122\r
123VOID\r
124AddMemoryBaseSizeHob (\r
125 EFI_PHYSICAL_ADDRESS MemoryBase,\r
126 UINT64 MemorySize\r
127 )\r
128{\r
991d9563 129 BuildResourceDescriptorHob (\r
130 EFI_RESOURCE_SYSTEM_MEMORY,\r
49ba9447 131 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
132 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
133 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
134 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
135 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
136 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
991d9563 137 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447 138 MemoryBase,\r
139 MemorySize\r
140 );\r
141}\r
142\r
143\r
144VOID\r
145AddMemoryRangeHob (\r
146 EFI_PHYSICAL_ADDRESS MemoryBase,\r
147 EFI_PHYSICAL_ADDRESS MemoryLimit\r
148 )\r
149{\r
150 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
151}\r
152\r
c0e10976 153\r
154VOID\r
155AddUntestedMemoryBaseSizeHob (\r
156 EFI_PHYSICAL_ADDRESS MemoryBase,\r
157 UINT64 MemorySize\r
158 )\r
159{\r
160 BuildResourceDescriptorHob (\r
161 EFI_RESOURCE_SYSTEM_MEMORY,\r
162 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
163 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
164 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
165 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
166 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
167 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
168 MemoryBase,\r
169 MemorySize\r
170 );\r
171}\r
172\r
173\r
174VOID\r
175AddUntestedMemoryRangeHob (\r
176 EFI_PHYSICAL_ADDRESS MemoryBase,\r
177 EFI_PHYSICAL_ADDRESS MemoryLimit\r
178 )\r
179{\r
180 AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
181}\r
182\r
bb6a9a93 183VOID\r
4b455f7b 184MemMapInitialization (\r
bb6a9a93
WL		 185 VOID\r
186 )\r
187{\r
bb6a9a93
WL		 188 //\r
189 // Create Memory Type Information HOB\r
190 //\r
191 BuildGuidDataHob (\r
192 &gEfiMemoryTypeInformationGuid,\r
193 mDefaultMemoryTypeInformation,\r
194 sizeof(mDefaultMemoryTypeInformation)\r
195 );\r
196\r
197 //\r
198 // Add PCI IO Port space available for PCI resource allocations.\r
199 //\r
200 BuildResourceDescriptorHob (\r
201 EFI_RESOURCE_IO,\r
202 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
203 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
e705f899
LE		 204 PcdGet64 (PcdPciIoBase),\r
205 PcdGet64 (PcdPciIoSize)\r
bb6a9a93
WL		 206 );\r
207\r
208 //\r
209 // Video memory + Legacy BIOS region\r
210 //\r
211 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
212\r
4b455f7b
JJ		 213 if (!mXen) {\r
214 UINT32 TopOfLowRam;\r
c68d3a69 215 UINT32 PciBase;\r
03845e90 216 UINT32 PciSize;\r
c68d3a69 217\r
4b455f7b 218 TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
c68d3a69
LE		 219 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
220 //\r
b01acf6e
LE		 221 // On Q35 machine types that QEMU intends to support in the long term,\r
222 // QEMU never lets the RAM below 4 GB exceed 2 GB.\r
c68d3a69 223 //\r
b01acf6e 224 PciBase = BASE_2GB;\r
c68d3a69
LE		 225 ASSERT (TopOfLowRam <= PciBase);\r
226 } else {\r
227 PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
228 }\r
49ba9447 229\r
4b455f7b
JJ		 230 //\r
231 // address purpose size\r
232 // ------------ -------- -------------------------\r
233 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
234 // 0xFC000000 gap 44 MB\r
235 // 0xFEC00000 IO-APIC 4 KB\r
236 // 0xFEC01000 gap 1020 KB\r
237 // 0xFED00000 HPET 1 KB\r
90721ba5
PA		 238 // 0xFED00400 gap 111 KB\r
239 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
240 // 0xFED20000 gap 896 KB\r
4b455f7b
JJ		 241 // 0xFEE00000 LAPIC 1 MB\r
242 //\r
03845e90
LE		 243 PciSize = 0xFC000000 - PciBase;\r
244 AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
245 PcdSet64 (PcdPciMmio32Base, PciBase);\r
246 PcdSet64 (PcdPciMmio32Size, PciSize);\r
4b455f7b
JJ		 247 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
248 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
90721ba5
PA		 249 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
250 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
251 }\r
4b455f7b 252 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
4b455f7b 253 }\r
49ba9447 254}\r
255\r
ab081a50
LE		 256EFI_STATUS\r
257GetNamedFwCfgBoolean (\r
258 IN CHAR8 *FwCfgFileName,\r
259 OUT BOOLEAN *Setting\r
260 )\r
261{\r
262 EFI_STATUS Status;\r
263 FIRMWARE_CONFIG_ITEM FwCfgItem;\r
264 UINTN FwCfgSize;\r
265 UINT8 Value[3];\r
266\r
267 Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
268 if (EFI_ERROR (Status)) {\r
269 return Status;\r
270 }\r
271 if (FwCfgSize > sizeof Value) {\r
272 return EFI_BAD_BUFFER_SIZE;\r
273 }\r
274 QemuFwCfgSelectItem (FwCfgItem);\r
275 QemuFwCfgReadBytes (FwCfgSize, Value);\r
276\r
277 if ((FwCfgSize == 1) ||\r
278 (FwCfgSize == 2 && Value[1] == '\n') ||\r
279 (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
280 switch (Value[0]) {\r
281 case '0':\r
282 case 'n':\r
283 case 'N':\r
284 *Setting = FALSE;\r
285 return EFI_SUCCESS;\r
286\r
287 case '1':\r
288 case 'y':\r
289 case 'Y':\r
290 *Setting = TRUE;\r
291 return EFI_SUCCESS;\r
292\r
293 default:\r
294 break;\r
295 }\r
296 }\r
297 return EFI_PROTOCOL_ERROR;\r
298}\r
299\r
300#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
301 do { \\r
302 BOOLEAN Setting; \\r
303 \\r
304 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
305 "opt/ovmf/" #TokenName, &Setting))) { \\r
306 PcdSetBool (TokenName, Setting); \\r
307 } \\r
308 } while (0)\r
309\r
310VOID\r
311NoexecDxeInitialization (\r
312 VOID\r
313 )\r
314{\r
315 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
316 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
317}\r
49ba9447 318\r
319VOID\r
320MiscInitialization (\r
0e20a186 321 VOID\r
49ba9447 322 )\r
323{\r
97380beb
GS		 324 UINTN PmCmd;\r
325 UINTN Pmba;\r
e2ab3f81
GS		 326 UINTN AcpiCtlReg;\r
327 UINT8 AcpiEnBit;\r
97380beb 328\r
49ba9447 329 //\r
330 // Disable A20 Mask\r
331 //\r
55cdb67a 332 IoOr8 (0x92, BIT1);\r
49ba9447 333\r
334 //\r
86a14b0a
LE		 335 // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
336 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
337 // S3 resume as well, so we build it unconditionally.)\r
49ba9447 338 //\r
86a14b0a 339 BuildCpuHob (mPhysMemAddressWidth, 16);\r
c756b2ab 340\r
97380beb 341 //\r
589756c7 342 // Determine platform type and save Host Bridge DID to PCD\r
97380beb 343 //\r
589756c7 344 switch (mHostBridgeDevId) {\r
97380beb 345 case INTEL_82441_DEVICE_ID:\r
e2ab3f81 346 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
da372167
LE		 347 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
348 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
349 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
97380beb
GS		 350 break;\r
351 case INTEL_Q35_MCH_DEVICE_ID:\r
e2ab3f81 352 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
bc9d05d6
LE		 353 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
354 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
355 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
97380beb
GS		 356 break;\r
357 default:\r
358 DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
589756c7 359 __FUNCTION__, mHostBridgeDevId));\r
97380beb
GS		 360 ASSERT (FALSE);\r
361 return;\r
362 }\r
589756c7 363 PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
97380beb 364\r
0e20a186 365 //\r
e2ab3f81
GS		 366 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
367 // has been configured (e.g., by Xen) and skip the setup here.\r
368 // This matches the logic in AcpiTimerLibConstructor ().\r
0e20a186 369 //\r
e2ab3f81 370 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
eec7d420 371 //\r
e2ab3f81 372 // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
931a0c74 373 // 1. set PMBA\r
eec7d420 374 //\r
97380beb 375 PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
931a0c74 376\r
377 //\r
378 // 2. set PCICMD/IOSE\r
379 //\r
97380beb 380 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
931a0c74 381\r
382 //\r
e2ab3f81 383 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
931a0c74 384 //\r
e2ab3f81 385 PciOr8 (AcpiCtlReg, AcpiEnBit);\r
eec7d420 386 }\r
90721ba5
PA		 387\r
388 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
389 //\r
390 // Set Root Complex Register Block BAR\r
391 //\r
392 PciWrite32 (\r
393 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
394 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
395 );\r
396 }\r
49ba9447 397}\r
398\r
399\r
9ed65b10 400VOID\r
401BootModeInitialization (\r
8f5ca05b 402 VOID\r
9ed65b10 403 )\r
404{\r
8f5ca05b
LE		 405 EFI_STATUS Status;\r
406\r
407 if (CmosRead8 (0xF) == 0xFE) {\r
979420df 408 mBootMode = BOOT_ON_S3_RESUME;\r
8f5ca05b 409 }\r
9be75189 410 CmosWrite8 (0xF, 0x00);\r
667bf1e4 411\r
979420df 412 Status = PeiServicesSetBootMode (mBootMode);\r
667bf1e4 413 ASSERT_EFI_ERROR (Status);\r
414\r
415 Status = PeiServicesInstallPpi (mPpiBootMode);\r
416 ASSERT_EFI_ERROR (Status);\r
9ed65b10 417}\r
418\r
419\r
77ba993c 420VOID\r
421ReserveEmuVariableNvStore (\r
422 )\r
423{\r
424 EFI_PHYSICAL_ADDRESS VariableStore;\r
425\r
426 //\r
427 // Allocate storage for NV variables early on so it will be\r
428 // at a consistent address. Since VM memory is preserved\r
429 // across reboots, this allows the NV variable storage to survive\r
430 // a VM reboot.\r
431 //\r
432 VariableStore =\r
433 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
9edb2933 434 AllocateAlignedRuntimePages (\r
cce992ac
WL		 435 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
436 PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
27f58ea1 437 );\r
77ba993c 438 DEBUG ((EFI_D_INFO,\r
439 "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
440 VariableStore,\r
29a3f139 441 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
77ba993c 442 ));\r
443 PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
444}\r
445\r
446\r
3ca15914 447VOID\r
448DebugDumpCmos (\r
449 VOID\r
450 )\r
451{\r
6394c35a 452 UINT32 Loop;\r
3ca15914 453\r
454 DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
455\r
456 for (Loop = 0; Loop < 0x80; Loop++) {\r
457 if ((Loop % 0x10) == 0) {\r
458 DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
459 }\r
460 DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
461 if ((Loop % 0x10) == 0xf) {\r
462 DEBUG ((EFI_D_INFO, "\n"));\r
463 }\r
464 }\r
465}\r
466\r
467\r
5133d1f1
LE		 468VOID\r
469S3Verification (\r
470 VOID\r
471 )\r
472{\r
473#if defined (MDE_CPU_X64)\r
474 if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
475 DEBUG ((EFI_D_ERROR,\r
476 "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
477 DEBUG ((EFI_D_ERROR,\r
478 "%a: Please disable S3 on the QEMU command line (see the README),\n",\r
479 __FUNCTION__));\r
480 DEBUG ((EFI_D_ERROR,\r
481 "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
482 ASSERT (FALSE);\r
483 CpuDeadLoop ();\r
484 }\r
485#endif\r
486}\r
487\r
488\r
49ba9447 489/**\r
490 Perform Platform PEI initialization.\r
491\r
492 @param FileHandle Handle of the file being invoked.\r
493 @param PeiServices Describes the list of possible PEI Services.\r
494\r
495 @return EFI_SUCCESS The PEIM initialized successfully.\r
496\r
497**/\r
498EFI_STATUS\r
499EFIAPI\r
500InitializePlatform (\r
501 IN EFI_PEI_FILE_HANDLE FileHandle,\r
502 IN CONST EFI_PEI_SERVICES **PeiServices\r
503 )\r
504{\r
505 DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
506\r
3ca15914 507 DebugDumpCmos ();\r
508\r
b98b4941 509 XenDetect ();\r
c7ea55b9 510\r
7cdba634
JJ		 511 if (QemuFwCfgS3Enabled ()) {\r
512 DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
513 mS3Supported = TRUE;\r
514 }\r
515\r
5133d1f1 516 S3Verification ();\r
869b17cc 517 BootModeInitialization ();\r
bc89fe48 518 AddressWidthInitialization ();\r
869b17cc 519\r
f76e9eba
JJ		 520 PublishPeiMemory ();\r
521\r
2818c158 522 InitializeRamRegions ();\r
49ba9447 523\r
b621bb0a 524 if (mXen) {\r
c7ea55b9 525 DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
b98b4941 526 InitializeXen ();\r
c7ea55b9 527 }\r
eec7d420 528\r
589756c7
PA		 529 //\r
530 // Query Host Bridge DID\r
531 //\r
532 mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
533\r
bd386eaf
JJ		 534 if (mBootMode != BOOT_ON_S3_RESUME) {\r
535 ReserveEmuVariableNvStore ();\r
bd386eaf 536 PeiFvInitialization ();\r
bd386eaf 537 MemMapInitialization ();\r
ab081a50 538 NoexecDxeInitialization ();\r
bd386eaf 539 }\r
49ba9447 540\r
0e20a186 541 MiscInitialization ();\r
49ba9447 542\r
543 return EFI_SUCCESS;\r
544}\r
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