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pointer verification (not NULL) and buffer overrun fixes.
[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c
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5d73d92f 1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
3737ac2b 4 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
5d73d92f 5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "UefiShellDebug1CommandsLib.h"\r
16#include <Protocol/PciRootBridgeIo.h>\r
17#include <Library/ShellLib.h>\r
18#include <IndustryStandard/Pci.h>\r
19#include <IndustryStandard/Acpi.h>\r
20#include "Pci.h"\r
21\r
22#define PCI_CLASS_STRING_LIMIT 54\r
23//\r
24// Printable strings for Pci class code\r
25//\r
26typedef struct {\r
27 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
28 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
29 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
30} PCI_CLASS_STRINGS;\r
31\r
32//\r
33// a structure holding a single entry, which also points to its lower level\r
34// class\r
35//\r
36typedef struct PCI_CLASS_ENTRY_TAG {\r
37 UINT8 Code; // Class, subclass or I/F code\r
38 CHAR16 *DescText; // Description string\r
39 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
40} PCI_CLASS_ENTRY;\r
41\r
42//\r
43// Declarations of entries which contain printable strings for class codes\r
44// in PCI configuration space\r
45//\r
46PCI_CLASS_ENTRY PCIBlankEntry[];\r
47PCI_CLASS_ENTRY PCISubClass_00[];\r
48PCI_CLASS_ENTRY PCISubClass_01[];\r
49PCI_CLASS_ENTRY PCISubClass_02[];\r
50PCI_CLASS_ENTRY PCISubClass_03[];\r
51PCI_CLASS_ENTRY PCISubClass_04[];\r
52PCI_CLASS_ENTRY PCISubClass_05[];\r
53PCI_CLASS_ENTRY PCISubClass_06[];\r
54PCI_CLASS_ENTRY PCISubClass_07[];\r
55PCI_CLASS_ENTRY PCISubClass_08[];\r
56PCI_CLASS_ENTRY PCISubClass_09[];\r
57PCI_CLASS_ENTRY PCISubClass_0a[];\r
58PCI_CLASS_ENTRY PCISubClass_0b[];\r
59PCI_CLASS_ENTRY PCISubClass_0c[];\r
60PCI_CLASS_ENTRY PCISubClass_0d[];\r
61PCI_CLASS_ENTRY PCISubClass_0e[];\r
62PCI_CLASS_ENTRY PCISubClass_0f[];\r
63PCI_CLASS_ENTRY PCISubClass_10[];\r
64PCI_CLASS_ENTRY PCISubClass_11[];\r
65PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
66PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
67PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
69PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
70PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
75PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
77PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
78PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
79\r
80//\r
81// Base class strings entries\r
82//\r
83PCI_CLASS_ENTRY gClassStringList[] = {\r
84 {\r
85 0x00,\r
86 L"Pre 2.0 device",\r
87 PCISubClass_00\r
88 },\r
89 {\r
90 0x01,\r
91 L"Mass Storage Controller",\r
92 PCISubClass_01\r
93 },\r
94 {\r
95 0x02,\r
96 L"Network Controller",\r
97 PCISubClass_02\r
98 },\r
99 {\r
100 0x03,\r
101 L"Display Controller",\r
102 PCISubClass_03\r
103 },\r
104 {\r
105 0x04,\r
106 L"Multimedia Device",\r
107 PCISubClass_04\r
108 },\r
109 {\r
110 0x05,\r
111 L"Memory Controller",\r
112 PCISubClass_05\r
113 },\r
114 {\r
115 0x06,\r
116 L"Bridge Device",\r
117 PCISubClass_06\r
118 },\r
119 {\r
120 0x07,\r
121 L"Simple Communications Controllers",\r
122 PCISubClass_07\r
123 },\r
124 {\r
125 0x08,\r
126 L"Base System Peripherals",\r
127 PCISubClass_08\r
128 },\r
129 {\r
130 0x09,\r
131 L"Input Devices",\r
132 PCISubClass_09\r
133 },\r
134 {\r
135 0x0a,\r
136 L"Docking Stations",\r
137 PCISubClass_0a\r
138 },\r
139 {\r
140 0x0b,\r
141 L"Processors",\r
142 PCISubClass_0b\r
143 },\r
144 {\r
145 0x0c,\r
146 L"Serial Bus Controllers",\r
147 PCISubClass_0c\r
148 },\r
149 {\r
150 0x0d,\r
151 L"Wireless Controllers",\r
152 PCISubClass_0d\r
153 },\r
154 {\r
155 0x0e,\r
156 L"Intelligent IO Controllers",\r
157 PCISubClass_0e\r
158 },\r
159 {\r
160 0x0f,\r
161 L"Satellite Communications Controllers",\r
162 PCISubClass_0f\r
163 },\r
164 {\r
165 0x10,\r
166 L"Encryption/Decryption Controllers",\r
167 PCISubClass_10\r
168 },\r
169 {\r
170 0x11,\r
171 L"Data Acquisition & Signal Processing Controllers",\r
172 PCISubClass_11\r
173 },\r
174 {\r
175 0xff,\r
176 L"Device does not fit in any defined classes",\r
177 PCIBlankEntry\r
178 },\r
179 {\r
180 0x00,\r
181 NULL,\r
182 /* null string ends the list */NULL\r
183 }\r
184};\r
185\r
186//\r
187// Subclass strings entries\r
188//\r
189PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
190 {\r
191 0x00,\r
192 L"",\r
193 PCIBlankEntry\r
194 },\r
195 {\r
196 0x00,\r
197 NULL,\r
198 /* null string ends the list */NULL\r
199 }\r
200};\r
201\r
202PCI_CLASS_ENTRY PCISubClass_00[] = {\r
203 {\r
204 0x00,\r
205 L"All devices other than VGA",\r
206 PCIBlankEntry\r
207 },\r
208 {\r
209 0x01,\r
210 L"VGA-compatible devices",\r
211 PCIBlankEntry\r
212 },\r
213 {\r
214 0x00,\r
215 NULL,\r
216 /* null string ends the list */NULL\r
217 }\r
218};\r
219\r
220PCI_CLASS_ENTRY PCISubClass_01[] = {\r
221 {\r
222 0x00,\r
223 L"SCSI controller",\r
224 PCIBlankEntry\r
225 },\r
226 {\r
227 0x01,\r
228 L"IDE controller",\r
229 PCIPIFClass_0101\r
230 },\r
231 {\r
232 0x02,\r
233 L"Floppy disk controller",\r
234 PCIBlankEntry\r
235 },\r
236 {\r
237 0x03,\r
238 L"IPI controller",\r
239 PCIBlankEntry\r
240 },\r
241 {\r
242 0x04,\r
243 L"RAID controller",\r
244 PCIBlankEntry\r
245 },\r
246 {\r
247 0x80,\r
248 L"Other mass storage controller",\r
249 PCIBlankEntry\r
250 },\r
251 {\r
252 0x00,\r
253 NULL,\r
254 /* null string ends the list */NULL\r
255 }\r
256};\r
257\r
258PCI_CLASS_ENTRY PCISubClass_02[] = {\r
259 {\r
260 0x00,\r
261 L"Ethernet controller",\r
262 PCIBlankEntry\r
263 },\r
264 {\r
265 0x01,\r
266 L"Token ring controller",\r
267 PCIBlankEntry\r
268 },\r
269 {\r
270 0x02,\r
271 L"FDDI controller",\r
272 PCIBlankEntry\r
273 },\r
274 {\r
275 0x03,\r
276 L"ATM controller",\r
277 PCIBlankEntry\r
278 },\r
279 {\r
280 0x04,\r
281 L"ISDN controller",\r
282 PCIBlankEntry\r
283 },\r
284 {\r
285 0x80,\r
286 L"Other network controller",\r
287 PCIBlankEntry\r
288 },\r
289 {\r
290 0x00,\r
291 NULL,\r
292 /* null string ends the list */NULL\r
293 }\r
294};\r
295\r
296PCI_CLASS_ENTRY PCISubClass_03[] = {\r
297 {\r
298 0x00,\r
299 L"VGA/8514 controller",\r
300 PCIPIFClass_0300\r
301 },\r
302 {\r
303 0x01,\r
304 L"XGA controller",\r
305 PCIBlankEntry\r
306 },\r
307 {\r
308 0x02,\r
309 L"3D controller",\r
310 PCIBlankEntry\r
311 },\r
312 {\r
313 0x80,\r
314 L"Other display controller",\r
315 PCIBlankEntry\r
316 },\r
317 {\r
318 0x00,\r
319 NULL,\r
320 /* null string ends the list */PCIBlankEntry\r
321 }\r
322};\r
323\r
324PCI_CLASS_ENTRY PCISubClass_04[] = {\r
325 {\r
326 0x00,\r
327 L"Video device",\r
328 PCIBlankEntry\r
329 },\r
330 {\r
331 0x01,\r
332 L"Audio device",\r
333 PCIBlankEntry\r
334 },\r
335 {\r
336 0x02,\r
337 L"Computer Telephony device",\r
338 PCIBlankEntry\r
339 },\r
340 {\r
341 0x80,\r
342 L"Other multimedia device",\r
343 PCIBlankEntry\r
344 },\r
345 {\r
346 0x00,\r
347 NULL,\r
348 /* null string ends the list */NULL\r
349 }\r
350};\r
351\r
352PCI_CLASS_ENTRY PCISubClass_05[] = {\r
353 {\r
354 0x00,\r
355 L"RAM memory controller",\r
356 PCIBlankEntry\r
357 },\r
358 {\r
359 0x01,\r
360 L"Flash memory controller",\r
361 PCIBlankEntry\r
362 },\r
363 {\r
364 0x80,\r
365 L"Other memory controller",\r
366 PCIBlankEntry\r
367 },\r
368 {\r
369 0x00,\r
370 NULL,\r
371 /* null string ends the list */NULL\r
372 }\r
373};\r
374\r
375PCI_CLASS_ENTRY PCISubClass_06[] = {\r
376 {\r
377 0x00,\r
378 L"Host/PCI bridge",\r
379 PCIBlankEntry\r
380 },\r
381 {\r
382 0x01,\r
383 L"PCI/ISA bridge",\r
384 PCIBlankEntry\r
385 },\r
386 {\r
387 0x02,\r
388 L"PCI/EISA bridge",\r
389 PCIBlankEntry\r
390 },\r
391 {\r
392 0x03,\r
393 L"PCI/Micro Channel bridge",\r
394 PCIBlankEntry\r
395 },\r
396 {\r
397 0x04,\r
398 L"PCI/PCI bridge",\r
399 PCIPIFClass_0604\r
400 },\r
401 {\r
402 0x05,\r
403 L"PCI/PCMCIA bridge",\r
404 PCIBlankEntry\r
405 },\r
406 {\r
407 0x06,\r
408 L"NuBus bridge",\r
409 PCIBlankEntry\r
410 },\r
411 {\r
412 0x07,\r
413 L"CardBus bridge",\r
414 PCIBlankEntry\r
415 },\r
416 {\r
417 0x08,\r
418 L"RACEway bridge",\r
419 PCIBlankEntry\r
420 },\r
421 {\r
422 0x80,\r
423 L"Other bridge type",\r
424 PCIBlankEntry\r
425 },\r
426 {\r
427 0x00,\r
428 NULL,\r
429 /* null string ends the list */NULL\r
430 }\r
431};\r
432\r
433PCI_CLASS_ENTRY PCISubClass_07[] = {\r
434 {\r
435 0x00,\r
436 L"Serial controller",\r
437 PCIPIFClass_0700\r
438 },\r
439 {\r
440 0x01,\r
441 L"Parallel port",\r
442 PCIPIFClass_0701\r
443 },\r
444 {\r
445 0x02,\r
446 L"Multiport serial controller",\r
447 PCIBlankEntry\r
448 },\r
449 {\r
450 0x03,\r
451 L"Modem",\r
452 PCIPIFClass_0703\r
453 },\r
454 {\r
455 0x80,\r
456 L"Other communication device",\r
457 PCIBlankEntry\r
458 },\r
459 {\r
460 0x00,\r
461 NULL,\r
462 /* null string ends the list */NULL\r
463 }\r
464};\r
465\r
466PCI_CLASS_ENTRY PCISubClass_08[] = {\r
467 {\r
468 0x00,\r
469 L"PIC",\r
470 PCIPIFClass_0800\r
471 },\r
472 {\r
473 0x01,\r
474 L"DMA controller",\r
475 PCIPIFClass_0801\r
476 },\r
477 {\r
478 0x02,\r
479 L"System timer",\r
480 PCIPIFClass_0802\r
481 },\r
482 {\r
483 0x03,\r
484 L"RTC controller",\r
485 PCIPIFClass_0803\r
486 },\r
487 {\r
488 0x04,\r
489 L"Generic PCI Hot-Plug controller",\r
490 PCIBlankEntry\r
491 },\r
492 {\r
493 0x80,\r
494 L"Other system peripheral",\r
495 PCIBlankEntry\r
496 },\r
497 {\r
498 0x00,\r
499 NULL,\r
500 /* null string ends the list */NULL\r
501 }\r
502};\r
503\r
504PCI_CLASS_ENTRY PCISubClass_09[] = {\r
505 {\r
506 0x00,\r
507 L"Keyboard controller",\r
508 PCIBlankEntry\r
509 },\r
510 {\r
511 0x01,\r
512 L"Digitizer (pen)",\r
513 PCIBlankEntry\r
514 },\r
515 {\r
516 0x02,\r
517 L"Mouse controller",\r
518 PCIBlankEntry\r
519 },\r
520 {\r
521 0x03,\r
522 L"Scanner controller",\r
523 PCIBlankEntry\r
524 },\r
525 {\r
526 0x04,\r
527 L"Gameport controller",\r
528 PCIPIFClass_0904\r
529 },\r
530 {\r
531 0x80,\r
532 L"Other input controller",\r
533 PCIBlankEntry\r
534 },\r
535 {\r
536 0x00,\r
537 NULL,\r
538 /* null string ends the list */NULL\r
539 }\r
540};\r
541\r
542PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
543 {\r
544 0x00,\r
545 L"Generic docking station",\r
546 PCIBlankEntry\r
547 },\r
548 {\r
549 0x80,\r
550 L"Other type of docking station",\r
551 PCIBlankEntry\r
552 },\r
553 {\r
554 0x00,\r
555 NULL,\r
556 /* null string ends the list */NULL\r
557 }\r
558};\r
559\r
560PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
561 {\r
562 0x00,\r
563 L"386",\r
564 PCIBlankEntry\r
565 },\r
566 {\r
567 0x01,\r
568 L"486",\r
569 PCIBlankEntry\r
570 },\r
571 {\r
572 0x02,\r
573 L"Pentium",\r
574 PCIBlankEntry\r
575 },\r
576 {\r
577 0x10,\r
578 L"Alpha",\r
579 PCIBlankEntry\r
580 },\r
581 {\r
582 0x20,\r
583 L"PowerPC",\r
584 PCIBlankEntry\r
585 },\r
586 {\r
587 0x30,\r
588 L"MIPS",\r
589 PCIBlankEntry\r
590 },\r
591 {\r
592 0x40,\r
593 L"Co-processor",\r
594 PCIBlankEntry\r
595 },\r
596 {\r
597 0x80,\r
598 L"Other processor",\r
599 PCIBlankEntry\r
600 },\r
601 {\r
602 0x00,\r
603 NULL,\r
604 /* null string ends the list */NULL\r
605 }\r
606};\r
607\r
608PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
609 {\r
610 0x00,\r
611 L"Firewire(IEEE 1394)",\r
612 PCIPIFClass_0c03\r
613 },\r
614 {\r
615 0x01,\r
616 L"ACCESS.bus",\r
617 PCIBlankEntry\r
618 },\r
619 {\r
620 0x02,\r
621 L"SSA",\r
622 PCIBlankEntry\r
623 },\r
624 {\r
625 0x03,\r
626 L"USB",\r
627 PCIPIFClass_0c00\r
628 },\r
629 {\r
630 0x04,\r
631 L"Fibre Channel",\r
632 PCIBlankEntry\r
633 },\r
634 {\r
635 0x05,\r
636 L"System Management Bus",\r
637 PCIBlankEntry\r
638 },\r
639 {\r
640 0x80,\r
641 L"Other bus type",\r
642 PCIBlankEntry\r
643 },\r
644 {\r
645 0x00,\r
646 NULL,\r
647 /* null string ends the list */NULL\r
648 }\r
649};\r
650\r
651PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
652 {\r
653 0x00,\r
654 L"iRDA compatible controller",\r
655 PCIBlankEntry\r
656 },\r
657 {\r
658 0x01,\r
659 L"Consumer IR controller",\r
660 PCIBlankEntry\r
661 },\r
662 {\r
663 0x10,\r
664 L"RF controller",\r
665 PCIBlankEntry\r
666 },\r
667 {\r
668 0x80,\r
669 L"Other type of wireless controller",\r
670 PCIBlankEntry\r
671 },\r
672 {\r
673 0x00,\r
674 NULL,\r
675 /* null string ends the list */NULL\r
676 }\r
677};\r
678\r
679PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
680 {\r
681 0x00,\r
682 L"I2O Architecture",\r
683 PCIPIFClass_0e00\r
684 },\r
685 {\r
686 0x00,\r
687 NULL,\r
688 /* null string ends the list */NULL\r
689 }\r
690};\r
691\r
692PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
693 {\r
694 0x00,\r
695 L"TV",\r
696 PCIBlankEntry\r
697 },\r
698 {\r
699 0x01,\r
700 L"Audio",\r
701 PCIBlankEntry\r
702 },\r
703 {\r
704 0x02,\r
705 L"Voice",\r
706 PCIBlankEntry\r
707 },\r
708 {\r
709 0x03,\r
710 L"Data",\r
711 PCIBlankEntry\r
712 },\r
713 {\r
714 0x00,\r
715 NULL,\r
716 /* null string ends the list */NULL\r
717 }\r
718};\r
719\r
720PCI_CLASS_ENTRY PCISubClass_10[] = {\r
721 {\r
722 0x00,\r
723 L"Network & computing Encrypt/Decrypt",\r
724 PCIBlankEntry\r
725 },\r
726 {\r
727 0x01,\r
728 L"Entertainment Encrypt/Decrypt",\r
729 PCIBlankEntry\r
730 },\r
731 {\r
732 0x80,\r
733 L"Other Encrypt/Decrypt",\r
734 PCIBlankEntry\r
735 },\r
736 {\r
737 0x00,\r
738 NULL,\r
739 /* null string ends the list */NULL\r
740 }\r
741};\r
742\r
743PCI_CLASS_ENTRY PCISubClass_11[] = {\r
744 {\r
745 0x00,\r
746 L"DPIO modules",\r
747 PCIBlankEntry\r
748 },\r
749 {\r
750 0x80,\r
751 L"Other DAQ & SP controllers",\r
752 PCIBlankEntry\r
753 },\r
754 {\r
755 0x00,\r
756 NULL,\r
757 /* null string ends the list */NULL\r
758 }\r
759};\r
760\r
761//\r
762// Programming Interface entries\r
763//\r
764PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
765 {\r
766 0x00,\r
767 L"",\r
768 PCIBlankEntry\r
769 },\r
770 {\r
771 0x01,\r
772 L"OM-primary",\r
773 PCIBlankEntry\r
774 },\r
775 {\r
776 0x02,\r
777 L"PI-primary",\r
778 PCIBlankEntry\r
779 },\r
780 {\r
781 0x03,\r
782 L"OM/PI-primary",\r
783 PCIBlankEntry\r
784 },\r
785 {\r
786 0x04,\r
787 L"OM-secondary",\r
788 PCIBlankEntry\r
789 },\r
790 {\r
791 0x05,\r
792 L"OM-primary, OM-secondary",\r
793 PCIBlankEntry\r
794 },\r
795 {\r
796 0x06,\r
797 L"PI-primary, OM-secondary",\r
798 PCIBlankEntry\r
799 },\r
800 {\r
801 0x07,\r
802 L"OM/PI-primary, OM-secondary",\r
803 PCIBlankEntry\r
804 },\r
805 {\r
806 0x08,\r
807 L"OM-secondary",\r
808 PCIBlankEntry\r
809 },\r
810 {\r
811 0x09,\r
812 L"OM-primary, PI-secondary",\r
813 PCIBlankEntry\r
814 },\r
815 {\r
816 0x0a,\r
817 L"PI-primary, PI-secondary",\r
818 PCIBlankEntry\r
819 },\r
820 {\r
821 0x0b,\r
822 L"OM/PI-primary, PI-secondary",\r
823 PCIBlankEntry\r
824 },\r
825 {\r
826 0x0c,\r
827 L"OM-secondary",\r
828 PCIBlankEntry\r
829 },\r
830 {\r
831 0x0d,\r
832 L"OM-primary, OM/PI-secondary",\r
833 PCIBlankEntry\r
834 },\r
835 {\r
836 0x0e,\r
837 L"PI-primary, OM/PI-secondary",\r
838 PCIBlankEntry\r
839 },\r
840 {\r
841 0x0f,\r
842 L"OM/PI-primary, OM/PI-secondary",\r
843 PCIBlankEntry\r
844 },\r
845 {\r
846 0x80,\r
847 L"Master",\r
848 PCIBlankEntry\r
849 },\r
850 {\r
851 0x81,\r
852 L"Master, OM-primary",\r
853 PCIBlankEntry\r
854 },\r
855 {\r
856 0x82,\r
857 L"Master, PI-primary",\r
858 PCIBlankEntry\r
859 },\r
860 {\r
861 0x83,\r
862 L"Master, OM/PI-primary",\r
863 PCIBlankEntry\r
864 },\r
865 {\r
866 0x84,\r
867 L"Master, OM-secondary",\r
868 PCIBlankEntry\r
869 },\r
870 {\r
871 0x85,\r
872 L"Master, OM-primary, OM-secondary",\r
873 PCIBlankEntry\r
874 },\r
875 {\r
876 0x86,\r
877 L"Master, PI-primary, OM-secondary",\r
878 PCIBlankEntry\r
879 },\r
880 {\r
881 0x87,\r
882 L"Master, OM/PI-primary, OM-secondary",\r
883 PCIBlankEntry\r
884 },\r
885 {\r
886 0x88,\r
887 L"Master, OM-secondary",\r
888 PCIBlankEntry\r
889 },\r
890 {\r
891 0x89,\r
892 L"Master, OM-primary, PI-secondary",\r
893 PCIBlankEntry\r
894 },\r
895 {\r
896 0x8a,\r
897 L"Master, PI-primary, PI-secondary",\r
898 PCIBlankEntry\r
899 },\r
900 {\r
901 0x8b,\r
902 L"Master, OM/PI-primary, PI-secondary",\r
903 PCIBlankEntry\r
904 },\r
905 {\r
906 0x8c,\r
907 L"Master, OM-secondary",\r
908 PCIBlankEntry\r
909 },\r
910 {\r
911 0x8d,\r
912 L"Master, OM-primary, OM/PI-secondary",\r
913 PCIBlankEntry\r
914 },\r
915 {\r
916 0x8e,\r
917 L"Master, PI-primary, OM/PI-secondary",\r
918 PCIBlankEntry\r
919 },\r
920 {\r
921 0x8f,\r
922 L"Master, OM/PI-primary, OM/PI-secondary",\r
923 PCIBlankEntry\r
924 },\r
925 {\r
926 0x00,\r
927 NULL,\r
928 /* null string ends the list */NULL\r
929 }\r
930};\r
931\r
932PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
933 {\r
934 0x00,\r
935 L"VGA compatible",\r
936 PCIBlankEntry\r
937 },\r
938 {\r
939 0x01,\r
940 L"8514 compatible",\r
941 PCIBlankEntry\r
942 },\r
943 {\r
944 0x00,\r
945 NULL,\r
946 /* null string ends the list */NULL\r
947 }\r
948};\r
949\r
950PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
951 {\r
952 0x00,\r
953 L"",\r
954 PCIBlankEntry\r
955 },\r
956 {\r
957 0x01,\r
958 L"Subtractive decode",\r
959 PCIBlankEntry\r
960 },\r
961 {\r
962 0x00,\r
963 NULL,\r
964 /* null string ends the list */NULL\r
965 }\r
966};\r
967\r
968PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
969 {\r
970 0x00,\r
971 L"Generic XT-compatible",\r
972 PCIBlankEntry\r
973 },\r
974 {\r
975 0x01,\r
976 L"16450-compatible",\r
977 PCIBlankEntry\r
978 },\r
979 {\r
980 0x02,\r
981 L"16550-compatible",\r
982 PCIBlankEntry\r
983 },\r
984 {\r
985 0x03,\r
986 L"16650-compatible",\r
987 PCIBlankEntry\r
988 },\r
989 {\r
990 0x04,\r
991 L"16750-compatible",\r
992 PCIBlankEntry\r
993 },\r
994 {\r
995 0x05,\r
996 L"16850-compatible",\r
997 PCIBlankEntry\r
998 },\r
999 {\r
1000 0x06,\r
1001 L"16950-compatible",\r
1002 PCIBlankEntry\r
1003 },\r
1004 {\r
1005 0x00,\r
1006 NULL,\r
1007 /* null string ends the list */NULL\r
1008 }\r
1009};\r
1010\r
1011PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1012 {\r
1013 0x00,\r
1014 L"",\r
1015 PCIBlankEntry\r
1016 },\r
1017 {\r
1018 0x01,\r
1019 L"Bi-directional",\r
1020 PCIBlankEntry\r
1021 },\r
1022 {\r
1023 0x02,\r
1024 L"ECP 1.X-compliant",\r
1025 PCIBlankEntry\r
1026 },\r
1027 {\r
1028 0x03,\r
1029 L"IEEE 1284",\r
1030 PCIBlankEntry\r
1031 },\r
1032 {\r
1033 0xfe,\r
1034 L"IEEE 1284 target (not a controller)",\r
1035 PCIBlankEntry\r
1036 },\r
1037 {\r
1038 0x00,\r
1039 NULL,\r
1040 /* null string ends the list */NULL\r
1041 }\r
1042};\r
1043\r
1044PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1045 {\r
1046 0x00,\r
1047 L"Generic",\r
1048 PCIBlankEntry\r
1049 },\r
1050 {\r
1051 0x01,\r
1052 L"Hayes-compatible 16450",\r
1053 PCIBlankEntry\r
1054 },\r
1055 {\r
1056 0x02,\r
1057 L"Hayes-compatible 16550",\r
1058 PCIBlankEntry\r
1059 },\r
1060 {\r
1061 0x03,\r
1062 L"Hayes-compatible 16650",\r
1063 PCIBlankEntry\r
1064 },\r
1065 {\r
1066 0x04,\r
1067 L"Hayes-compatible 16750",\r
1068 PCIBlankEntry\r
1069 },\r
1070 {\r
1071 0x00,\r
1072 NULL,\r
1073 /* null string ends the list */NULL\r
1074 }\r
1075};\r
1076\r
1077PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1078 {\r
1079 0x00,\r
1080 L"Generic 8259",\r
1081 PCIBlankEntry\r
1082 },\r
1083 {\r
1084 0x01,\r
1085 L"ISA",\r
1086 PCIBlankEntry\r
1087 },\r
1088 {\r
1089 0x02,\r
1090 L"EISA",\r
1091 PCIBlankEntry\r
1092 },\r
1093 {\r
1094 0x10,\r
1095 L"IO APIC",\r
1096 PCIBlankEntry\r
1097 },\r
1098 {\r
1099 0x20,\r
1100 L"IO(x) APIC interrupt controller",\r
1101 PCIBlankEntry\r
1102 },\r
1103 {\r
1104 0x00,\r
1105 NULL,\r
1106 /* null string ends the list */NULL\r
1107 }\r
1108};\r
1109\r
1110PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1111 {\r
1112 0x00,\r
1113 L"Generic 8237",\r
1114 PCIBlankEntry\r
1115 },\r
1116 {\r
1117 0x01,\r
1118 L"ISA",\r
1119 PCIBlankEntry\r
1120 },\r
1121 {\r
1122 0x02,\r
1123 L"EISA",\r
1124 PCIBlankEntry\r
1125 },\r
1126 {\r
1127 0x00,\r
1128 NULL,\r
1129 /* null string ends the list */NULL\r
1130 }\r
1131};\r
1132\r
1133PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1134 {\r
1135 0x00,\r
1136 L"Generic 8254",\r
1137 PCIBlankEntry\r
1138 },\r
1139 {\r
1140 0x01,\r
1141 L"ISA",\r
1142 PCIBlankEntry\r
1143 },\r
1144 {\r
1145 0x02,\r
1146 L"EISA",\r
1147 PCIBlankEntry\r
1148 },\r
1149 {\r
1150 0x00,\r
1151 NULL,\r
1152 /* null string ends the list */NULL\r
1153 }\r
1154};\r
1155\r
1156PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1157 {\r
1158 0x00,\r
1159 L"Generic",\r
1160 PCIBlankEntry\r
1161 },\r
1162 {\r
1163 0x01,\r
1164 L"ISA",\r
1165 PCIBlankEntry\r
1166 },\r
1167 {\r
1168 0x02,\r
1169 L"EISA",\r
1170 PCIBlankEntry\r
1171 },\r
1172 {\r
1173 0x00,\r
1174 NULL,\r
1175 /* null string ends the list */NULL\r
1176 }\r
1177};\r
1178\r
1179PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1180 {\r
1181 0x00,\r
1182 L"Generic",\r
1183 PCIBlankEntry\r
1184 },\r
1185 {\r
1186 0x10,\r
1187 L"",\r
1188 PCIBlankEntry\r
1189 },\r
1190 {\r
1191 0x00,\r
1192 NULL,\r
1193 /* null string ends the list */NULL\r
1194 }\r
1195};\r
1196\r
1197PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1198 {\r
1199 0x00,\r
1200 L"Universal Host Controller spec",\r
1201 PCIBlankEntry\r
1202 },\r
1203 {\r
1204 0x10,\r
1205 L"Open Host Controller spec",\r
1206 PCIBlankEntry\r
1207 },\r
1208 {\r
1209 0x80,\r
1210 L"No specific programming interface",\r
1211 PCIBlankEntry\r
1212 },\r
1213 {\r
1214 0xfe,\r
1215 L"(Not Host Controller)",\r
1216 PCIBlankEntry\r
1217 },\r
1218 {\r
1219 0x00,\r
1220 NULL,\r
1221 /* null string ends the list */NULL\r
1222 }\r
1223};\r
1224\r
1225PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1226 {\r
1227 0x00,\r
1228 L"",\r
1229 PCIBlankEntry\r
1230 },\r
1231 {\r
1232 0x10,\r
1233 L"Using 1394 OpenHCI spec",\r
1234 PCIBlankEntry\r
1235 },\r
1236 {\r
1237 0x00,\r
1238 NULL,\r
1239 /* null string ends the list */NULL\r
1240 }\r
1241};\r
1242\r
1243PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1244 {\r
1245 0x00,\r
1246 L"Message FIFO at offset 40h",\r
1247 PCIBlankEntry\r
1248 },\r
1249 {\r
1250 0x01,\r
1251 L"",\r
1252 PCIBlankEntry\r
1253 },\r
1254 {\r
1255 0x00,\r
1256 NULL,\r
1257 /* null string ends the list */NULL\r
1258 }\r
1259};\r
1260\r
1261#define EFI_HEX_DISP_SIZE 32\r
1262BOOLEAN\r
1263PrivateDumpHex (\r
1264 IN UINTN Indent,\r
1265 IN UINTN Offset,\r
1266 IN UINTN DataSize,\r
1267 IN VOID *UserData\r
1268 )\r
1269/*++\r
1270\r
1271Routine Description:\r
1272\r
1273 Add page break feature to the DumpHex\r
1274\r
1275Arguments:\r
1276 Indent - The indent space\r
1277\r
1278 Offset - The offset\r
1279\r
1280 DataSize - The data size\r
1281\r
1282 UserData - The data\r
1283\r
1284Returns:\r
1285\r
1286 TRUE - The dump is broke\r
1287 FALSE - The dump is completed\r
1288\r
1289**/\r
1290{\r
1291 UINTN DispSize;\r
1292 UINT8 *DispData;\r
1293\r
1294 DispSize = EFI_HEX_DISP_SIZE;\r
1295 DispData = (UINT8 *) UserData;\r
1296\r
1297 while (DataSize!=0) {\r
1298 if (ShellGetExecutionBreakFlag ()) {\r
1299 return TRUE;\r
1300 }\r
1301\r
1302 if (DataSize > EFI_HEX_DISP_SIZE) {\r
1303 DataSize -= EFI_HEX_DISP_SIZE;\r
1304 } else {\r
1305 DispSize = DataSize;\r
1306 DataSize = 0;\r
1307 }\r
1308\r
1309 DumpHex (Indent, Offset + DispData - (UINT8 *) UserData, DispSize, DispData);\r
1310 DispData += DispSize;\r
1311 }\r
1312\r
1313 return FALSE;\r
1314}\r
1315\r
1316//\r
1317// Implemetations\r
1318//\r
1319VOID\r
1320PciGetClassStrings (\r
1321 IN UINT32 ClassCode,\r
1322 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1323 )\r
1324/*++\r
1325Routine Description:\r
1326\r
1327 Generates printable Unicode strings that represent PCI device class,\r
1328 subclass and programmed I/F based on a value passed to the function.\r
1329\r
1330Arguments:\r
1331\r
1332 ClassCode Value representing the PCI "Class Code" register read from a\r
1333 PCI device. The encodings are:\r
1334 bits 23:16 - Base Class Code\r
1335 bits 15:8 - Sub-Class Code\r
1336 bits 7:0 - Programming Interface\r
1337 ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
1338 printable class strings corresponding to ClassCode. The\r
1339 caller must not modify the strings that are pointed by\r
1340 the fields in ClassStrings.\r
1341Returns:\r
1342\r
1343 None\r
1344**/\r
1345{\r
1346 INTN Index;\r
1347 UINT8 Code;\r
1348 PCI_CLASS_ENTRY *CurrentClass;\r
1349\r
1350 //\r
1351 // Assume no strings found\r
1352 //\r
1353 ClassStrings->BaseClass = L"UNDEFINED";\r
1354 ClassStrings->SubClass = L"UNDEFINED";\r
1355 ClassStrings->PIFClass = L"UNDEFINED";\r
1356\r
1357 CurrentClass = gClassStringList;\r
1358 Code = (UINT8) (ClassCode >> 16);\r
1359 Index = 0;\r
1360\r
1361 //\r
1362 // Go through all entries of the base class, until the entry with a matching\r
1363 // base class code is found. If reaches an entry with a null description\r
1364 // text, the last entry is met, which means no text for the base class was\r
1365 // found, so no more action is needed.\r
1366 //\r
1367 while (Code != CurrentClass[Index].Code) {\r
1368 if (NULL == CurrentClass[Index].DescText) {\r
1369 return ;\r
1370 }\r
1371\r
1372 Index++;\r
1373 }\r
1374 //\r
1375 // A base class was found. Assign description, and check if this class has\r
1376 // sub-class defined. If sub-class defined, no more action is needed,\r
1377 // otherwise, continue to find description for the sub-class code.\r
1378 //\r
1379 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1380 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1381 return ;\r
1382 }\r
1383 //\r
1384 // find Subclass entry\r
1385 //\r
1386 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1387 Code = (UINT8) (ClassCode >> 8);\r
1388 Index = 0;\r
1389\r
1390 //\r
1391 // Go through all entries of the sub-class, until the entry with a matching\r
1392 // sub-class code is found. If reaches an entry with a null description\r
1393 // text, the last entry is met, which means no text for the sub-class was\r
1394 // found, so no more action is needed.\r
1395 //\r
1396 while (Code != CurrentClass[Index].Code) {\r
1397 if (NULL == CurrentClass[Index].DescText) {\r
1398 return ;\r
1399 }\r
1400\r
1401 Index++;\r
1402 }\r
1403 //\r
1404 // A class was found for the sub-class code. Assign description, and check if\r
1405 // this sub-class has programming interface defined. If no, no more action is\r
1406 // needed, otherwise, continue to find description for the programming\r
1407 // interface.\r
1408 //\r
1409 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1410 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1411 return ;\r
1412 }\r
1413 //\r
1414 // Find programming interface entry\r
1415 //\r
1416 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1417 Code = (UINT8) ClassCode;\r
1418 Index = 0;\r
1419\r
1420 //\r
1421 // Go through all entries of the I/F entries, until the entry with a\r
1422 // matching I/F code is found. If reaches an entry with a null description\r
1423 // text, the last entry is met, which means no text was found, so no more\r
1424 // action is needed.\r
1425 //\r
1426 while (Code != CurrentClass[Index].Code) {\r
1427 if (NULL == CurrentClass[Index].DescText) {\r
1428 return ;\r
1429 }\r
1430\r
1431 Index++;\r
1432 }\r
1433 //\r
1434 // A class was found for the I/F code. Assign description, done!\r
1435 //\r
1436 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1437 return ;\r
1438}\r
1439\r
1440VOID\r
1441PciPrintClassCode (\r
1442 IN UINT8 *ClassCodePtr,\r
1443 IN BOOLEAN IncludePIF\r
1444 )\r
1445/*++\r
1446Routine Description:\r
1447\r
1448 Print strings that represent PCI device class, subclass and programmed I/F\r
1449\r
1450Arguments:\r
1451\r
1452 ClassCodePtr Points to the memory which stores register Class Code in PCI\r
1453 configuation space.\r
1454 IncludePIF If the printed string should include the programming I/F part\r
1455Returns:\r
1456\r
1457 None\r
1458**/\r
1459{\r
1460 UINT32 ClassCode;\r
1461 PCI_CLASS_STRINGS ClassStrings;\r
1462 CHAR16 OutputString[PCI_CLASS_STRING_LIMIT + 1];\r
1463\r
1464 ClassCode = 0;\r
1465 ClassCode |= ClassCodePtr[0];\r
1466 ClassCode |= (ClassCodePtr[1] << 8);\r
1467 ClassCode |= (ClassCodePtr[2] << 16);\r
1468\r
1469 //\r
1470 // Get name from class code\r
1471 //\r
1472 PciGetClassStrings (ClassCode, &ClassStrings);\r
1473\r
1474 if (IncludePIF) {\r
1475 //\r
1476 // Only print base class and sub class name\r
1477 //\r
1478 ShellPrintEx(-1,-1, L"%s - %s - %s",\r
1479 ClassStrings.BaseClass,\r
1480 ClassStrings.SubClass,\r
1481 ClassStrings.PIFClass\r
1482 );\r
1483\r
1484 } else {\r
1485 //\r
1486 // Print base class, sub class, and programming inferface name\r
1487 //\r
1488 UnicodeSPrint (\r
1489 OutputString,\r
1490 PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),\r
1491 L"%s - %s",\r
1492 ClassStrings.BaseClass,\r
1493 ClassStrings.SubClass\r
1494 );\r
1495\r
1496 OutputString[PCI_CLASS_STRING_LIMIT] = 0;\r
1497 ShellPrintEx(-1,-1, L"%s", OutputString);\r
1498 }\r
1499}\r
1500\r
1501EFI_STATUS\r
1502PciDump (\r
1503 IN EFI_HANDLE ImageHandle,\r
1504 IN EFI_SYSTEM_TABLE *SystemTable\r
1505 );\r
1506\r
1507EFI_STATUS\r
1508PciFindProtocolInterface (\r
1509 IN EFI_HANDLE *HandleBuf,\r
1510 IN UINTN HandleCount,\r
1511 IN UINT16 Segment,\r
1512 IN UINT16 Bus,\r
1513 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1514 );\r
1515\r
1516EFI_STATUS\r
1517PciGetProtocolAndResource (\r
1518 IN EFI_HANDLE Handle,\r
1519 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1520 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1521 );\r
1522\r
1523EFI_STATUS\r
1524PciGetNextBusRange (\r
1525 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1526 OUT UINT16 *MinBus,\r
1527 OUT UINT16 *MaxBus,\r
1528 OUT BOOLEAN *IsEnd\r
1529 );\r
1530\r
1531EFI_STATUS\r
1532PciExplainData (\r
1533 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1534 IN UINT64 Address,\r
1535 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1536 );\r
1537\r
1538EFI_STATUS\r
1539PciExplainDeviceData (\r
1540 IN PCI_DEVICE_HEADER *Device,\r
1541 IN UINT64 Address,\r
1542 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1543 );\r
1544\r
1545EFI_STATUS\r
1546PciExplainBridgeData (\r
1547 IN PCI_BRIDGE_HEADER *Bridge,\r
1548 IN UINT64 Address,\r
1549 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1550 );\r
1551\r
1552EFI_STATUS\r
1553PciExplainBar (\r
1554 IN UINT32 *Bar,\r
1555 IN UINT16 *Command,\r
1556 IN UINT64 Address,\r
1557 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1558 IN OUT UINTN *Index\r
1559 );\r
1560\r
1561EFI_STATUS\r
1562PciExplainCardBusData (\r
1563 IN PCI_CARDBUS_HEADER *CardBus,\r
1564 IN UINT64 Address,\r
1565 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1566 );\r
1567\r
1568EFI_STATUS\r
1569PciExplainStatus (\r
1570 IN UINT16 *Status,\r
1571 IN BOOLEAN MainStatus,\r
1572 IN PCI_HEADER_TYPE HeaderType\r
1573 );\r
1574\r
1575EFI_STATUS\r
1576PciExplainCommand (\r
1577 IN UINT16 *Command\r
1578 );\r
1579\r
1580EFI_STATUS\r
1581PciExplainBridgeControl (\r
1582 IN UINT16 *BridgeControl,\r
1583 IN PCI_HEADER_TYPE HeaderType\r
1584 );\r
1585\r
1586EFI_STATUS\r
1587PciExplainCapabilityStruct (\r
1588 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1589 IN UINT64 Address,\r
1590 IN UINT8 CapPtr\r
1591 );\r
1592\r
1593EFI_STATUS\r
1594PciExplainPciExpress (\r
1595 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1596 IN UINT64 Address,\r
1597 IN UINT8 CapabilityPtr\r
1598 );\r
1599\r
1600EFI_STATUS\r
1601ExplainPcieCapReg (\r
1602 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1603);\r
1604\r
1605EFI_STATUS\r
1606ExplainPcieDeviceCap (\r
1607 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1608);\r
1609\r
1610EFI_STATUS\r
1611ExplainPcieDeviceControl (\r
1612 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1613);\r
1614\r
1615EFI_STATUS\r
1616ExplainPcieDeviceStatus (\r
1617 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1618);\r
1619\r
1620EFI_STATUS\r
1621ExplainPcieLinkCap (\r
1622 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1623);\r
1624\r
1625EFI_STATUS\r
1626ExplainPcieLinkControl (\r
1627 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1628);\r
1629\r
1630EFI_STATUS\r
1631ExplainPcieLinkStatus (\r
1632 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1633);\r
1634\r
1635EFI_STATUS\r
1636ExplainPcieSlotCap (\r
1637 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1638);\r
1639\r
1640EFI_STATUS\r
1641ExplainPcieSlotControl (\r
1642 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1643);\r
1644\r
1645EFI_STATUS\r
1646ExplainPcieSlotStatus (\r
1647 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1648);\r
1649\r
1650EFI_STATUS\r
1651ExplainPcieRootControl (\r
1652 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1653);\r
1654\r
1655EFI_STATUS\r
1656ExplainPcieRootCap (\r
1657 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1658);\r
1659\r
1660EFI_STATUS\r
1661ExplainPcieRootStatus (\r
1662 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1663);\r
1664\r
1665typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
1666\r
1667typedef enum {\r
1668 FieldWidthUINT8,\r
1669 FieldWidthUINT16,\r
1670 FieldWidthUINT32\r
1671} PCIE_CAPREG_FIELD_WIDTH;\r
1672\r
1673typedef enum {\r
1674 PcieExplainTypeCommon,\r
1675 PcieExplainTypeDevice,\r
1676 PcieExplainTypeLink,\r
1677 PcieExplainTypeSlot,\r
1678 PcieExplainTypeRoot,\r
1679 PcieExplainTypeMax\r
1680} PCIE_EXPLAIN_TYPE;\r
1681\r
1682typedef struct\r
1683{\r
1684 UINT16 Token;\r
1685 UINTN Offset;\r
1686 PCIE_CAPREG_FIELD_WIDTH Width;\r
1687 PCIE_EXPLAIN_FUNCTION Func;\r
1688 PCIE_EXPLAIN_TYPE Type;\r
1689} PCIE_EXPLAIN_STRUCT;\r
1690\r
1691PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
1692 {\r
1693 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
1694 0x00,\r
1695 FieldWidthUINT8,\r
1696 NULL,\r
1697 PcieExplainTypeCommon\r
1698 },\r
1699 {\r
1700 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
1701 0x01,\r
1702 FieldWidthUINT8,\r
1703 NULL,\r
1704 PcieExplainTypeCommon\r
1705 },\r
1706 {\r
1707 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
1708 0x02,\r
1709 FieldWidthUINT16,\r
1710 ExplainPcieCapReg,\r
1711 PcieExplainTypeCommon\r
1712 },\r
1713 {\r
1714 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
1715 0x04,\r
1716 FieldWidthUINT32,\r
1717 ExplainPcieDeviceCap,\r
1718 PcieExplainTypeDevice\r
1719 },\r
1720 {\r
1721 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
1722 0x08,\r
1723 FieldWidthUINT16,\r
1724 ExplainPcieDeviceControl,\r
1725 PcieExplainTypeDevice\r
1726 },\r
1727 {\r
1728 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
1729 0x0a,\r
1730 FieldWidthUINT16,\r
1731 ExplainPcieDeviceStatus,\r
1732 PcieExplainTypeDevice\r
1733 },\r
1734 {\r
1735 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
1736 0x0c,\r
1737 FieldWidthUINT32,\r
1738 ExplainPcieLinkCap,\r
1739 PcieExplainTypeLink\r
1740 },\r
1741 {\r
1742 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
1743 0x10,\r
1744 FieldWidthUINT16,\r
1745 ExplainPcieLinkControl,\r
1746 PcieExplainTypeLink\r
1747 },\r
1748 {\r
1749 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
1750 0x12,\r
1751 FieldWidthUINT16,\r
1752 ExplainPcieLinkStatus,\r
1753 PcieExplainTypeLink\r
1754 },\r
1755 {\r
1756 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
1757 0x14,\r
1758 FieldWidthUINT32,\r
1759 ExplainPcieSlotCap,\r
1760 PcieExplainTypeSlot\r
1761 },\r
1762 {\r
1763 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
1764 0x18,\r
1765 FieldWidthUINT16,\r
1766 ExplainPcieSlotControl,\r
1767 PcieExplainTypeSlot\r
1768 },\r
1769 {\r
1770 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
1771 0x1a,\r
1772 FieldWidthUINT16,\r
1773 ExplainPcieSlotStatus,\r
1774 PcieExplainTypeSlot\r
1775 },\r
1776 {\r
1777 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
1778 0x1c,\r
1779 FieldWidthUINT16,\r
1780 ExplainPcieRootControl,\r
1781 PcieExplainTypeRoot\r
1782 },\r
1783 {\r
1784 STRING_TOKEN (STR_PCIEX_RSVDP),\r
1785 0x1e,\r
1786 FieldWidthUINT16,\r
1787 ExplainPcieRootCap,\r
1788 PcieExplainTypeRoot\r
1789 },\r
1790 {\r
1791 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
1792 0x20,\r
1793 FieldWidthUINT32,\r
1794 ExplainPcieRootStatus,\r
1795 PcieExplainTypeRoot\r
1796 },\r
1797 {\r
1798 0,\r
1799 0,\r
1800 (PCIE_CAPREG_FIELD_WIDTH)0,\r
1801 NULL,\r
1802 PcieExplainTypeMax\r
1803 }\r
1804};\r
1805\r
1806//\r
1807// Global Variables\r
1808//\r
1809PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
1810STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
1811 {L"-s", TypeValue},\r
1812 {L"-i", TypeFlag},\r
1813 {NULL, TypeMax}\r
1814 };\r
1815\r
1816CHAR16 *DevicePortTypeTable[] = {\r
1817 L"PCI Express Endpoint",\r
1818 L"Legacy PCI Express Endpoint",\r
1819 L"Unknown Type",\r
1820 L"Unknonw Type",\r
1821 L"Root Port of PCI Express Root Complex",\r
1822 L"Upstream Port of PCI Express Switch",\r
1823 L"Downstream Port of PCI Express Switch",\r
1824 L"PCI Express to PCI/PCI-X Bridge",\r
1825 L"PCI/PCI-X to PCI Express Bridge",\r
1826 L"Root Complex Integrated Endpoint",\r
1827 L"Root Complex Event Collector"\r
1828};\r
1829\r
1830CHAR16 *L0sLatencyStrTable[] = {\r
1831 L"Less than 64ns",\r
1832 L"64ns to less than 128ns",\r
1833 L"128ns to less than 256ns",\r
1834 L"256ns to less than 512ns",\r
1835 L"512ns to less than 1us",\r
1836 L"1us to less than 2us",\r
1837 L"2us-4us",\r
1838 L"More than 4us"\r
1839};\r
1840\r
1841CHAR16 *L1LatencyStrTable[] = {\r
1842 L"Less than 1us",\r
1843 L"1us to less than 2us",\r
1844 L"2us to less than 4us",\r
1845 L"4us to less than 8us",\r
1846 L"8us to less than 16us",\r
1847 L"16us to less than 32us",\r
1848 L"32us-64us",\r
1849 L"More than 64us"\r
1850};\r
1851\r
1852CHAR16 *ASPMCtrlStrTable[] = {\r
1853 L"Disabled",\r
1854 L"L0s Entry Enabled",\r
1855 L"L1 Entry Enabled",\r
1856 L"L0s and L1 Entry Enabled"\r
1857};\r
1858\r
1859CHAR16 *SlotPwrLmtScaleTable[] = {\r
1860 L"1.0x",\r
1861 L"0.1x",\r
1862 L"0.01x",\r
1863 L"0.001x"\r
1864};\r
1865\r
1866CHAR16 *IndicatorTable[] = {\r
1867 L"Reserved",\r
1868 L"On",\r
1869 L"Blink",\r
1870 L"Off"\r
1871};\r
1872\r
1873\r
1874SHELL_STATUS\r
1875EFIAPI\r
1876ShellCommandRunPci (\r
1877 IN EFI_HANDLE ImageHandle,\r
1878 IN EFI_SYSTEM_TABLE *SystemTable\r
1879 )\r
1880{\r
1881 UINT16 Segment;\r
1882 UINT16 Bus;\r
1883 UINT16 Device;\r
1884 UINT16 Func;\r
1885 UINT64 Address;\r
1886 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
1887 EFI_STATUS Status;\r
1888 PCI_COMMON_HEADER PciHeader;\r
1889 PCI_CONFIG_SPACE ConfigSpace;\r
1890 UINTN ScreenCount;\r
1891 UINTN TempColumn;\r
1892 UINTN ScreenSize;\r
1893 BOOLEAN ExplainData;\r
1894 UINTN Index;\r
1895 UINTN SizeOfHeader;\r
1896 BOOLEAN PrintTitle;\r
1897 UINTN HandleBufSize;\r
1898 EFI_HANDLE *HandleBuf;\r
1899 UINTN HandleCount;\r
1900 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
1901 UINT16 MinBus;\r
1902 UINT16 MaxBus;\r
1903 BOOLEAN IsEnd;\r
1904 LIST_ENTRY *Package;\r
1905 CHAR16 *ProblemParam;\r
1906 SHELL_STATUS ShellStatus;\r
1907 UINTN Size;\r
1908 CONST CHAR16 *Temp;\r
1909\r
1910 ShellStatus = SHELL_SUCCESS;\r
1911 Status = EFI_SUCCESS;\r
1912 Address = 0;\r
1913 Size = 0;\r
1914 IoDev = NULL;\r
1915 HandleBuf = NULL;\r
1916 Package = NULL;\r
1917\r
1918 //\r
1919 // initialize the shell lib (we must be in non-auto-init...)\r
1920 //\r
1921 Status = ShellInitialize();\r
1922 ASSERT_EFI_ERROR(Status);\r
1923\r
1924 Status = CommandInit();\r
1925 ASSERT_EFI_ERROR(Status);\r
1926\r
1927 //\r
1928 // parse the command line\r
1929 //\r
1930 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
1931 if (EFI_ERROR(Status)) {\r
1932 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
1933 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
1934 FreePool(ProblemParam);\r
1935 ShellStatus = SHELL_INVALID_PARAMETER;\r
1936 } else {\r
1937 ASSERT(FALSE);\r
1938 }\r
1939 } else {\r
1940\r
3737ac2b 1941 if (ShellCommandLineGetCount(Package) == 2) {\r
1942 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
1943 ShellStatus = SHELL_INVALID_PARAMETER;\r
1944 goto Done;\r
1945 }\r
5d73d92f 1946\r
3737ac2b 1947 if (ShellCommandLineGetCount(Package) > 4) {\r
1948 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
1949 ShellStatus = SHELL_INVALID_PARAMETER;\r
1950 goto Done;\r
1951 }\r
1952 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
1953 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
1954 ShellStatus = SHELL_INVALID_PARAMETER;\r
1955 goto Done;\r
1956 }\r
5d73d92f 1957 //\r
1958 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
1959 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
1960 // space for handles and call it again.\r
1961 //\r
1962 HandleBufSize = sizeof (EFI_HANDLE);\r
3737ac2b 1963 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
5d73d92f 1964 if (HandleBuf == NULL) {\r
1965 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
1966 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
1967 goto Done;\r
1968 }\r
1969\r
1970 Status = gBS->LocateHandle (\r
1971 ByProtocol,\r
1972 &gEfiPciRootBridgeIoProtocolGuid,\r
1973 NULL,\r
1974 &HandleBufSize,\r
1975 HandleBuf\r
1976 );\r
1977\r
1978 if (Status == EFI_BUFFER_TOO_SMALL) {\r
1979 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
1980 if (HandleBuf == NULL) {\r
1981 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
1982 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
1983 goto Done;\r
1984 }\r
1985\r
1986 Status = gBS->LocateHandle (\r
1987 ByProtocol,\r
1988 &gEfiPciRootBridgeIoProtocolGuid,\r
1989 NULL,\r
1990 &HandleBufSize,\r
1991 HandleBuf\r
1992 );\r
1993 }\r
1994\r
1995 if (EFI_ERROR (Status)) {\r
1996 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
1997 ShellStatus = SHELL_NOT_FOUND;\r
1998 goto Done;\r
1999 }\r
2000\r
2001 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2002 //\r
2003 // Argument Count == 1(no other argument): enumerate all pci functions\r
2004 //\r
3737ac2b 2005 if (ShellCommandLineGetCount(Package) == 1) {\r
5d73d92f 2006 gST->ConOut->QueryMode (\r
2007 gST->ConOut,\r
2008 gST->ConOut->Mode->Mode,\r
2009 &TempColumn,\r
2010 &ScreenSize\r
2011 );\r
2012\r
2013 ScreenCount = 0;\r
2014 ScreenSize -= 4;\r
2015 if ((ScreenSize & 1) == 1) {\r
2016 ScreenSize -= 1;\r
2017 }\r
2018\r
2019 PrintTitle = TRUE;\r
2020\r
2021 //\r
2022 // For each handle, which decides a segment and a bus number range,\r
2023 // enumerate all devices on it.\r
2024 //\r
2025 for (Index = 0; Index < HandleCount; Index++) {\r
2026 Status = PciGetProtocolAndResource (\r
2027 HandleBuf[Index],\r
2028 &IoDev,\r
2029 &Descriptors\r
2030 );\r
2031 if (EFI_ERROR (Status)) {\r
2032 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
2033 ShellStatus = SHELL_NOT_FOUND;\r
2034 goto Done;\r
2035 }\r
2036 //\r
2037 // No document say it's impossible for a RootBridgeIo protocol handle\r
2038 // to have more than one address space descriptors, so find out every\r
2039 // bus range and for each of them do device enumeration.\r
2040 //\r
2041 while (TRUE) {\r
2042 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2043\r
2044 if (EFI_ERROR (Status)) {\r
2045 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
2046 ShellStatus = SHELL_NOT_FOUND;\r
2047 goto Done;\r
2048 }\r
2049\r
2050 if (IsEnd) {\r
2051 break;\r
2052 }\r
2053\r
2054 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2055 //\r
2056 // For each devices, enumerate all functions it contains\r
2057 //\r
2058 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2059 //\r
2060 // For each function, read its configuration space and print summary\r
2061 //\r
2062 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2063 if (ShellGetExecutionBreakFlag ()) {\r
2064 ShellStatus = SHELL_ABORTED;\r
2065 goto Done;\r
2066 }\r
2067 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2068 IoDev->Pci.Read (\r
2069 IoDev,\r
2070 EfiPciWidthUint16,\r
2071 Address,\r
2072 1,\r
2073 &PciHeader.VendorId\r
2074 );\r
2075\r
2076 //\r
2077 // If VendorId = 0xffff, there does not exist a device at this\r
2078 // location. For each device, if there is any function on it,\r
2079 // there must be 1 function at Function 0. So if Func = 0, there\r
2080 // will be no more functions in the same device, so we can break\r
2081 // loop to deal with the next device.\r
2082 //\r
2083 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2084 break;\r
2085 }\r
2086\r
2087 if (PciHeader.VendorId != 0xffff) {\r
2088\r
2089 if (PrintTitle) {\r
2090 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2091 PrintTitle = FALSE;\r
2092 }\r
2093\r
2094 IoDev->Pci.Read (\r
2095 IoDev,\r
2096 EfiPciWidthUint32,\r
2097 Address,\r
2098 sizeof (PciHeader) / sizeof (UINT32),\r
2099 &PciHeader\r
2100 );\r
2101\r
2102 ShellPrintHiiEx(\r
2103 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2104 IoDev->SegmentNumber,\r
2105 Bus,\r
2106 Device,\r
2107 Func\r
2108 );\r
2109\r
2110 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2111 ShellPrintHiiEx(\r
2112 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2113 PciHeader.VendorId,\r
2114 PciHeader.DeviceId,\r
2115 PciHeader.ClassCode[0]\r
2116 );\r
2117\r
2118 ScreenCount += 2;\r
2119 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2120 //\r
2121 // If ScreenSize == 0 we have the console redirected so don't\r
2122 // block updates\r
2123 //\r
2124 ScreenCount = 0;\r
2125 }\r
2126 //\r
2127 // If this is not a multi-function device, we can leave the loop\r
2128 // to deal with the next device.\r
2129 //\r
2130 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2131 break;\r
2132 }\r
2133 }\r
2134 }\r
2135 }\r
2136 }\r
2137 //\r
2138 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2139 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2140 // devices on all bus, we can leave loop.\r
2141 //\r
2142 if (Descriptors == NULL) {\r
2143 break;\r
2144 }\r
2145 }\r
2146 }\r
2147\r
2148 Status = EFI_SUCCESS;\r
2149 goto Done;\r
2150 }\r
2151\r
5d73d92f 2152 ExplainData = FALSE;\r
2153 Segment = 0;\r
2154 Bus = 0;\r
2155 Device = 0;\r
2156 Func = 0;\r
2157 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2158 ExplainData = TRUE;\r
2159 }\r
2160\r
2161 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2162 if (Temp != NULL) {\r
3737ac2b 2163 Segment = (UINT16) ShellStrToUintn (Temp);\r
5d73d92f 2164 }\r
2165\r
2166 //\r
2167 // The first Argument(except "-i") is assumed to be Bus number, second\r
2168 // to be Device number, and third to be Func number.\r
2169 //\r
2170 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2171 if (Temp != NULL) {\r
3737ac2b 2172 Bus = (UINT16)ShellStrToUintn(Temp);\r
5d73d92f 2173 if (Bus > MAX_BUS_NUMBER) {\r
2174 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2175 ShellStatus = SHELL_INVALID_PARAMETER;\r
2176 goto Done;\r
2177 }\r
2178 }\r
2179 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2180 if (Temp != NULL) {\r
3737ac2b 2181 Device = (UINT16) ShellStrToUintn(Temp);\r
5d73d92f 2182 if (Device > MAX_DEVICE_NUMBER){\r
2183 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2184 ShellStatus = SHELL_INVALID_PARAMETER;\r
2185 goto Done;\r
2186 }\r
2187 }\r
2188\r
2189 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2190 if (Temp != NULL) {\r
3737ac2b 2191 Func = (UINT16) ShellStrToUintn(Temp);\r
5d73d92f 2192 if (Func > MAX_FUNCTION_NUMBER){\r
2193 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2194 ShellStatus = SHELL_INVALID_PARAMETER;\r
2195 goto Done;\r
2196 }\r
2197 }\r
2198\r
2199 //\r
2200 // Find the protocol interface who's in charge of current segment, and its\r
2201 // bus range covers the current bus\r
2202 //\r
2203 Status = PciFindProtocolInterface (\r
2204 HandleBuf,\r
2205 HandleCount,\r
2206 Segment,\r
2207 Bus,\r
2208 &IoDev\r
2209 );\r
2210\r
2211 if (EFI_ERROR (Status)) {\r
2212 ShellPrintHiiEx(\r
2213 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
2214 gShellDebug1HiiHandle,\r
2215 Segment,\r
2216 Bus\r
2217 );\r
2218 ShellStatus = SHELL_NOT_FOUND;\r
2219 goto Done;\r
2220 }\r
2221\r
2222 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2223 Status = IoDev->Pci.Read (\r
2224 IoDev,\r
2225 EfiPciWidthUint8,\r
2226 Address,\r
2227 sizeof (ConfigSpace),\r
2228 &ConfigSpace\r
2229 );\r
2230\r
2231 if (EFI_ERROR (Status)) {\r
2232 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
2233 ShellStatus = SHELL_ACCESS_DENIED;\r
2234 goto Done;\r
2235 }\r
2236\r
2237 mConfigSpace = &ConfigSpace;\r
2238 ShellPrintHiiEx(\r
2239 -1,\r
2240 -1,\r
2241 NULL,\r
2242 STRING_TOKEN (STR_PCI_INFO),\r
2243 gShellDebug1HiiHandle,\r
2244 Segment,\r
2245 Bus,\r
2246 Device,\r
2247 Func,\r
2248 Segment,\r
2249 Bus,\r
2250 Device,\r
2251 Func\r
2252 );\r
2253\r
2254 //\r
2255 // Dump standard header of configuration space\r
2256 //\r
2257 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2258\r
2259 PrivateDumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
2260 ShellPrintEx(-1,-1, L"\r\n");\r
2261\r
2262 //\r
2263 // Dump device dependent Part of configuration space\r
2264 //\r
2265 PrivateDumpHex (\r
2266 2,\r
2267 SizeOfHeader,\r
2268 sizeof (ConfigSpace) - SizeOfHeader,\r
2269 ConfigSpace.Data\r
2270 );\r
2271\r
2272 //\r
2273 // If "-i" appears in command line, interpret data in configuration space\r
2274 //\r
2275 if (ExplainData) {\r
2276 Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
2277 }\r
2278 }\r
2279Done:\r
2280 if (HandleBuf != NULL) {\r
2281 FreePool (HandleBuf);\r
2282 }\r
2283 if (Package != NULL) {\r
2284 ShellCommandLineFreeVarList (Package);\r
2285 }\r
2286 mConfigSpace = NULL;\r
2287 return ShellStatus;\r
2288}\r
2289\r
2290EFI_STATUS\r
2291PciFindProtocolInterface (\r
2292 IN EFI_HANDLE *HandleBuf,\r
2293 IN UINTN HandleCount,\r
2294 IN UINT16 Segment,\r
2295 IN UINT16 Bus,\r
2296 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2297 )\r
2298/*++\r
2299\r
2300Routine Description:\r
2301\r
2302 This function finds out the protocol which is in charge of the given\r
2303 segment, and its bus range covers the current bus number. It lookes\r
2304 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2305 criteria is found.\r
2306\r
2307Arguments:\r
2308\r
2309 HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles\r
2310 HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles\r
2311 Segment Segment number of device we are dealing with\r
2312 Bus Bus number of device we are dealing with\r
2313 IoDev Handle used to access configuration space of PCI device\r
2314\r
2315Returns:\r
2316\r
2317 EFI_SUCCESS - The command completed successfully\r
2318 EFI_INVALID_PARAMETER - Invalid parameter\r
2319\r
2320**/\r
2321{\r
2322 UINTN Index;\r
2323 EFI_STATUS Status;\r
2324 BOOLEAN FoundInterface;\r
2325 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2326 UINT16 MinBus;\r
2327 UINT16 MaxBus;\r
2328 BOOLEAN IsEnd;\r
2329\r
2330 FoundInterface = FALSE;\r
2331 //\r
2332 // Go through all handles, until the one meets the criteria is found\r
2333 //\r
2334 for (Index = 0; Index < HandleCount; Index++) {\r
2335 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2336 if (EFI_ERROR (Status)) {\r
2337 return Status;\r
2338 }\r
2339 //\r
2340 // When Descriptors == NULL, the Configuration() is not implemented,\r
2341 // so we only check the Segment number\r
2342 //\r
2343 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2344 return EFI_SUCCESS;\r
2345 }\r
2346\r
2347 if ((*IoDev)->SegmentNumber != Segment) {\r
2348 continue;\r
2349 }\r
2350\r
2351 while (TRUE) {\r
2352 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2353 if (EFI_ERROR (Status)) {\r
2354 return Status;\r
2355 }\r
2356\r
2357 if (IsEnd) {\r
2358 break;\r
2359 }\r
2360\r
2361 if (MinBus <= Bus && MaxBus >= Bus) {\r
2362 FoundInterface = TRUE;\r
2363 break;\r
2364 }\r
2365 }\r
2366 }\r
2367\r
2368 if (FoundInterface) {\r
2369 return EFI_SUCCESS;\r
2370 } else {\r
2371 return EFI_INVALID_PARAMETER;\r
2372 }\r
2373}\r
2374\r
2375EFI_STATUS\r
2376PciGetProtocolAndResource (\r
2377 IN EFI_HANDLE Handle,\r
2378 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2379 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2380 )\r
2381/*++\r
2382\r
2383Routine Description:\r
2384\r
2385 This function gets the protocol interface from the given handle, and\r
2386 obtains its address space descriptors.\r
2387\r
2388Arguments:\r
2389\r
2390 Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle\r
2391 IoDev Handle used to access configuration space of PCI device\r
2392 Descriptors Points to the address space descriptors\r
2393\r
2394Returns:\r
2395\r
2396 EFI_SUCCESS The command completed successfully\r
2397\r
2398**/\r
2399{\r
2400 EFI_STATUS Status;\r
2401\r
2402 //\r
2403 // Get inferface from protocol\r
2404 //\r
2405 Status = gBS->HandleProtocol (\r
2406 Handle,\r
2407 &gEfiPciRootBridgeIoProtocolGuid,\r
2408 (VOID**)IoDev\r
2409 );\r
2410\r
2411 if (EFI_ERROR (Status)) {\r
2412 return Status;\r
2413 }\r
2414 //\r
2415 // Call Configuration() to get address space descriptors\r
2416 //\r
2417 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
2418 if (Status == EFI_UNSUPPORTED) {\r
2419 *Descriptors = NULL;\r
2420 return EFI_SUCCESS;\r
2421\r
2422 } else {\r
2423 return Status;\r
2424 }\r
2425}\r
2426\r
2427EFI_STATUS\r
2428PciGetNextBusRange (\r
2429 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
2430 OUT UINT16 *MinBus,\r
2431 OUT UINT16 *MaxBus,\r
2432 OUT BOOLEAN *IsEnd\r
2433 )\r
2434/*++\r
2435\r
2436Routine Description:\r
2437\r
2438 This function get the next bus range of given address space descriptors.\r
2439 It also moves the pointer backward a node, to get prepared to be called\r
2440 again.\r
2441\r
2442Arguments:\r
2443\r
2444 Descriptors points to current position of a serial of address space\r
2445 descriptors\r
2446 MinBus The lower range of bus number\r
2447 ManBus The upper range of bus number\r
2448 IsEnd Meet end of the serial of descriptors\r
2449\r
2450Returns:\r
2451\r
2452 EFI_SUCCESS The command completed successfully\r
2453\r
2454**/\r
2455{\r
2456 *IsEnd = FALSE;\r
2457\r
2458 //\r
2459 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
2460 // range is 0~PCI_MAX_BUS\r
2461 //\r
2462 if ((*Descriptors) == NULL) {\r
2463 *MinBus = 0;\r
2464 *MaxBus = PCI_MAX_BUS;\r
2465 return EFI_SUCCESS;\r
2466 }\r
2467 //\r
2468 // *Descriptors points to one or more address space descriptors, which\r
2469 // ends with a end tagged descriptor. Examine each of the descriptors,\r
2470 // if a bus typed one is found and its bus range covers bus, this handle\r
2471 // is the handle we are looking for.\r
2472 //\r
5d73d92f 2473\r
2474 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2475 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
2476 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
2477 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
2478 (*Descriptors)++;\r
3737ac2b 2479 return (EFI_SUCCESS);\r
5d73d92f 2480 }\r
2481\r
2482 (*Descriptors)++;\r
2483 }\r
2484\r
3737ac2b 2485 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
2486 *IsEnd = TRUE;\r
2487 }\r
2488\r
5d73d92f 2489 return EFI_SUCCESS;\r
2490}\r
2491\r
2492EFI_STATUS\r
2493PciExplainData (\r
2494 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2495 IN UINT64 Address,\r
2496 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2497 )\r
2498/*++\r
2499\r
2500Routine Description:\r
2501\r
2502 Explain the data in PCI configuration space. The part which is common for\r
2503 PCI device and bridge is interpreted in this function. It calls other\r
2504 functions to interpret data unique for device or bridge.\r
2505\r
2506Arguments:\r
2507\r
2508 ConfigSpace Data in PCI configuration space\r
2509 Address Address used to access configuration space of this PCI device\r
2510 IoDev Handle used to access configuration space of PCI device\r
2511\r
2512Returns:\r
2513\r
2514 EFI_SUCCESS The command completed successfully\r
2515\r
2516**/\r
2517{\r
2518 PCI_COMMON_HEADER *Common;\r
2519 PCI_HEADER_TYPE HeaderType;\r
2520 EFI_STATUS Status;\r
2521 UINT8 CapPtr;\r
2522\r
2523 Common = &(ConfigSpace->Common);\r
2524\r
2525 Print (L"\n");\r
2526\r
2527 //\r
2528 // Print Vendor Id and Device Id\r
2529 //\r
2530 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
2531 INDEX_OF (&(Common->VendorId)),\r
2532 Common->VendorId,\r
2533 INDEX_OF (&(Common->DeviceId)),\r
2534 Common->DeviceId\r
2535 );\r
2536\r
2537 //\r
2538 // Print register Command\r
2539 //\r
2540 PciExplainCommand (&(Common->Command));\r
2541\r
2542 //\r
2543 // Print register Status\r
2544 //\r
2545 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
2546\r
2547 //\r
2548 // Print register Revision ID\r
2549 //\r
2550 ShellPrintEx(-1, -1, L"/r/n");\r
2551 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
2552 INDEX_OF (&(Common->RevisionId)),\r
2553 Common->RevisionId\r
2554 );\r
2555\r
2556 //\r
2557 // Print register BIST\r
2558 //\r
2559 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r
2560 if ((Common->BIST & PCI_BIT_7) != 0) {\r
2561 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r
2562 } else {\r
2563 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
2564 }\r
2565 //\r
2566 // Print register Cache Line Size\r
2567 //\r
2568 ShellPrintHiiEx(-1, -1, NULL,\r
2569 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
2570 gShellDebug1HiiHandle,\r
2571 INDEX_OF (&(Common->CacheLineSize)),\r
2572 Common->CacheLineSize\r
2573 );\r
2574\r
2575 //\r
2576 // Print register Latency Timer\r
2577 //\r
2578 ShellPrintHiiEx(-1, -1, NULL,\r
2579 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
2580 gShellDebug1HiiHandle,\r
2581 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
2582 Common->PrimaryLatencyTimer\r
2583 );\r
2584\r
2585 //\r
2586 // Print register Header Type\r
2587 //\r
2588 ShellPrintHiiEx(-1, -1, NULL,\r
2589 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
2590 gShellDebug1HiiHandle,\r
2591 INDEX_OF (&(Common->HeaderType)),\r
2592 Common->HeaderType\r
2593 );\r
2594\r
2595 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
2596 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
2597\r
2598 } else {\r
2599 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
2600 }\r
2601\r
2602 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
2603 switch (HeaderType) {\r
2604 case PciDevice:\r
2605 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
2606 break;\r
2607\r
2608 case PciP2pBridge:\r
2609 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
2610 break;\r
2611\r
2612 case PciCardBusBridge:\r
2613 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
2614 break;\r
2615\r
2616 default:\r
2617 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
2618 HeaderType = PciUndefined;\r
2619 }\r
2620\r
2621 //\r
2622 // Print register Class Code\r
2623 //\r
2624 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
2625 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
2626 Print (L"\n");\r
2627\r
2628 if (ShellGetExecutionBreakFlag()) {\r
2629 return EFI_SUCCESS;\r
2630 }\r
2631\r
2632 //\r
2633 // Interpret remaining part of PCI configuration header depending on\r
2634 // HeaderType\r
2635 //\r
2636 CapPtr = 0;\r
2637 Status = EFI_SUCCESS;\r
2638 switch (HeaderType) {\r
2639 case PciDevice:\r
2640 Status = PciExplainDeviceData (\r
2641 &(ConfigSpace->NonCommon.Device),\r
2642 Address,\r
2643 IoDev\r
2644 );\r
2645 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
2646 break;\r
2647\r
2648 case PciP2pBridge:\r
2649 Status = PciExplainBridgeData (\r
2650 &(ConfigSpace->NonCommon.Bridge),\r
2651 Address,\r
2652 IoDev\r
2653 );\r
2654 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
2655 break;\r
2656\r
2657 case PciCardBusBridge:\r
2658 Status = PciExplainCardBusData (\r
2659 &(ConfigSpace->NonCommon.CardBus),\r
2660 Address,\r
2661 IoDev\r
2662 );\r
2663 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
2664 break;\r
2665 }\r
2666 //\r
2667 // If Status bit4 is 1, dump or explain capability structure\r
2668 //\r
2669 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
2670 PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
2671 }\r
2672\r
2673 return Status;\r
2674}\r
2675\r
2676EFI_STATUS\r
2677PciExplainDeviceData (\r
2678 IN PCI_DEVICE_HEADER *Device,\r
2679 IN UINT64 Address,\r
2680 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2681 )\r
2682/*++\r
2683\r
2684Routine Description:\r
2685\r
2686 Explain the device specific part of data in PCI configuration space.\r
2687\r
2688Arguments:\r
2689\r
2690 Device Data in PCI configuration space\r
2691 Address Address used to access configuration space of this PCI device\r
2692 IoDev Handle used to access configuration space of PCI device\r
2693\r
2694Returns:\r
2695\r
2696 EFI_SUCCESS The command completed successfully\r
2697\r
2698**/\r
2699{\r
2700 UINTN Index;\r
2701 BOOLEAN BarExist;\r
2702 EFI_STATUS Status;\r
2703 UINTN BarCount;\r
2704\r
2705 //\r
2706 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
2707 // exist. If these no Bar for this function, print "none", otherwise\r
2708 // list detail information about this Bar.\r
2709 //\r
2710 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
2711\r
2712 BarExist = FALSE;\r
2713 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
2714 for (Index = 0; Index < BarCount; Index++) {\r
2715 if (Device->Bar[Index] == 0) {\r
2716 continue;\r
2717 }\r
2718\r
2719 if (!BarExist) {\r
2720 BarExist = TRUE;\r
2721 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
2722 Print (L" --------------------------------------------------------------------------");\r
2723 }\r
2724\r
2725 Status = PciExplainBar (\r
2726 &(Device->Bar[Index]),\r
2727 &(mConfigSpace->Common.Command),\r
2728 Address,\r
2729 IoDev,\r
2730 &Index\r
2731 );\r
2732\r
2733 if (EFI_ERROR (Status)) {\r
2734 break;\r
2735 }\r
2736 }\r
2737\r
2738 if (!BarExist) {\r
2739 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2740\r
2741 } else {\r
2742 Print (L"\n --------------------------------------------------------------------------");\r
2743 }\r
2744\r
2745 //\r
2746 // Print register Expansion ROM Base Address\r
2747 //\r
2748 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
2749 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
2750\r
2751 } else {\r
2752 ShellPrintHiiEx(-1, -1, NULL,\r
2753 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
2754 gShellDebug1HiiHandle,\r
2755 INDEX_OF (&(Device->ROMBar)),\r
2756 Device->ROMBar\r
2757 );\r
2758 }\r
2759 //\r
2760 // Print register Cardbus CIS ptr\r
2761 //\r
2762 ShellPrintHiiEx(-1, -1, NULL,\r
2763 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
2764 gShellDebug1HiiHandle,\r
2765 INDEX_OF (&(Device->CardBusCISPtr)),\r
2766 Device->CardBusCISPtr\r
2767 );\r
2768\r
2769 //\r
2770 // Print register Sub-vendor ID and subsystem ID\r
2771 //\r
2772 ShellPrintHiiEx(-1, -1, NULL,\r
2773 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
2774 gShellDebug1HiiHandle,\r
2775 INDEX_OF (&(Device->SubVendorId)),\r
2776 Device->SubVendorId\r
2777 );\r
2778\r
2779 ShellPrintHiiEx(-1, -1, NULL,\r
2780 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
2781 gShellDebug1HiiHandle,\r
2782 INDEX_OF (&(Device->SubSystemId)),\r
2783 Device->SubSystemId\r
2784 );\r
2785\r
2786 //\r
2787 // Print register Capabilities Ptr\r
2788 //\r
2789 ShellPrintHiiEx(-1, -1, NULL,\r
2790 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
2791 gShellDebug1HiiHandle,\r
2792 INDEX_OF (&(Device->CapabilitiesPtr)),\r
2793 Device->CapabilitiesPtr\r
2794 );\r
2795\r
2796 //\r
2797 // Print register Interrupt Line and interrupt pin\r
2798 //\r
2799 ShellPrintHiiEx(-1, -1, NULL,\r
2800 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
2801 gShellDebug1HiiHandle,\r
2802 INDEX_OF (&(Device->InterruptLine)),\r
2803 Device->InterruptLine\r
2804 );\r
2805\r
2806 ShellPrintHiiEx(-1, -1, NULL,\r
2807 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
2808 gShellDebug1HiiHandle,\r
2809 INDEX_OF (&(Device->InterruptPin)),\r
2810 Device->InterruptPin\r
2811 );\r
2812\r
2813 //\r
2814 // Print register Min_Gnt and Max_Lat\r
2815 //\r
2816 ShellPrintHiiEx(-1, -1, NULL,\r
2817 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
2818 gShellDebug1HiiHandle,\r
2819 INDEX_OF (&(Device->MinGnt)),\r
2820 Device->MinGnt\r
2821 );\r
2822\r
2823 ShellPrintHiiEx(-1, -1, NULL,\r
2824 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
2825 gShellDebug1HiiHandle,\r
2826 INDEX_OF (&(Device->MaxLat)),\r
2827 Device->MaxLat\r
2828 );\r
2829\r
2830 return EFI_SUCCESS;\r
2831}\r
2832\r
2833EFI_STATUS\r
2834PciExplainBridgeData (\r
2835 IN PCI_BRIDGE_HEADER *Bridge,\r
2836 IN UINT64 Address,\r
2837 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2838 )\r
2839/*++\r
2840\r
2841Routine Description:\r
2842\r
2843 Explain the bridge specific part of data in PCI configuration space.\r
2844\r
2845Arguments:\r
2846\r
2847 Bridge Bridge specific data region in PCI configuration space\r
2848 Address Address used to access configuration space of this PCI device\r
2849 IoDev Handle used to access configuration space of PCI device\r
2850\r
2851Returns:\r
2852\r
2853 EFI_SUCCESS The command completed successfully\r
2854\r
2855**/\r
2856{\r
2857 UINTN Index;\r
2858 BOOLEAN BarExist;\r
2859 UINTN BarCount;\r
2860 UINT32 IoAddress32;\r
2861 EFI_STATUS Status;\r
2862\r
2863 //\r
2864 // Print Base Address Registers. When Bar = 0, this Bar does not\r
2865 // exist. If these no Bar for this function, print "none", otherwise\r
2866 // list detail information about this Bar.\r
2867 //\r
2868 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
2869\r
2870 BarExist = FALSE;\r
2871 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
2872\r
2873 for (Index = 0; Index < BarCount; Index++) {\r
2874 if (Bridge->Bar[Index] == 0) {\r
2875 continue;\r
2876 }\r
2877\r
2878 if (!BarExist) {\r
2879 BarExist = TRUE;\r
2880 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
2881 Print (L" --------------------------------------------------------------------------");\r
2882 }\r
2883\r
2884 Status = PciExplainBar (\r
2885 &(Bridge->Bar[Index]),\r
2886 &(mConfigSpace->Common.Command),\r
2887 Address,\r
2888 IoDev,\r
2889 &Index\r
2890 );\r
2891\r
2892 if (EFI_ERROR (Status)) {\r
2893 break;\r
2894 }\r
2895 }\r
2896\r
2897 if (!BarExist) {\r
2898 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2899 } else {\r
2900 Print (L"\n --------------------------------------------------------------------------");\r
2901 }\r
2902\r
2903 //\r
2904 // Expansion register ROM Base Address\r
2905 //\r
2906 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
2907 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
2908\r
2909 } else {\r
2910 ShellPrintHiiEx(-1, -1, NULL,\r
2911 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
2912 gShellDebug1HiiHandle,\r
2913 INDEX_OF (&(Bridge->ROMBar)),\r
2914 Bridge->ROMBar\r
2915 );\r
2916 }\r
2917 //\r
2918 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
2919 //\r
2920 ShellPrintHiiEx(-1, -1, NULL,\r
2921 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
2922 gShellDebug1HiiHandle,\r
2923 INDEX_OF (&(Bridge->PrimaryBus)),\r
2924 INDEX_OF (&(Bridge->SecondaryBus)),\r
2925 INDEX_OF (&(Bridge->SubordinateBus))\r
2926 );\r
2927\r
2928 Print (L" ------------------------------------------------------\n");\r
2929\r
2930 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
2931 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
2932 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
2933\r
2934 //\r
2935 // Print register Secondary Latency Timer\r
2936 //\r
2937 ShellPrintHiiEx(-1, -1, NULL,\r
2938 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
2939 gShellDebug1HiiHandle,\r
2940 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
2941 Bridge->SecondaryLatencyTimer\r
2942 );\r
2943\r
2944 //\r
2945 // Print register Secondary Status\r
2946 //\r
2947 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
2948\r
2949 //\r
2950 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
2951 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
2952 // base and limit address are listed.\r
2953 //\r
2954 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
2955 Print (L"----------------------------------------------------------------------\n");\r
2956\r
2957 //\r
2958 // IO Base & Limit\r
2959 //\r
2960 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
2961 IoAddress32 &= 0xfffff000;\r
2962 ShellPrintHiiEx(-1, -1, NULL,\r
2963 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
2964 gShellDebug1HiiHandle,\r
2965 INDEX_OF (&(Bridge->IoBase)),\r
2966 IoAddress32\r
2967 );\r
2968\r
2969 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
2970 IoAddress32 |= 0x00000fff;\r
2971 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
2972\r
2973 //\r
2974 // Memory Base & Limit\r
2975 //\r
2976 ShellPrintHiiEx(-1, -1, NULL,\r
2977 STRING_TOKEN (STR_PCI2_MEMORY),\r
2978 gShellDebug1HiiHandle,\r
2979 INDEX_OF (&(Bridge->MemoryBase)),\r
2980 (Bridge->MemoryBase << 16) & 0xfff00000\r
2981 );\r
2982\r
2983 ShellPrintHiiEx(-1, -1, NULL,\r
2984 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
2985 gShellDebug1HiiHandle,\r
2986 (Bridge->MemoryLimit << 16) | 0x000fffff\r
2987 );\r
2988\r
2989 //\r
2990 // Pre-fetch-able Memory Base & Limit\r
2991 //\r
2992 ShellPrintHiiEx(-1, -1, NULL,\r
2993 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
2994 gShellDebug1HiiHandle,\r
2995 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
2996 Bridge->PrefetchableBaseUpper,\r
2997 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
2998 );\r
2999\r
3000 ShellPrintHiiEx(-1, -1, NULL,\r
3001 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3002 gShellDebug1HiiHandle,\r
3003 Bridge->PrefetchableLimitUpper,\r
3004 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3005 );\r
3006\r
3007 //\r
3008 // Print register Capabilities Pointer\r
3009 //\r
3010 ShellPrintHiiEx(-1, -1, NULL,\r
3011 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3012 gShellDebug1HiiHandle,\r
3013 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3014 Bridge->CapabilitiesPtr\r
3015 );\r
3016\r
3017 //\r
3018 // Print register Bridge Control\r
3019 //\r
3020 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3021\r
3022 //\r
3023 // Print register Interrupt Line & PIN\r
3024 //\r
3025 ShellPrintHiiEx(-1, -1, NULL,\r
3026 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3027 gShellDebug1HiiHandle,\r
3028 INDEX_OF (&(Bridge->InterruptLine)),\r
3029 Bridge->InterruptLine\r
3030 );\r
3031\r
3032 ShellPrintHiiEx(-1, -1, NULL,\r
3033 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3034 gShellDebug1HiiHandle,\r
3035 INDEX_OF (&(Bridge->InterruptPin)),\r
3036 Bridge->InterruptPin\r
3037 );\r
3038\r
3039 return EFI_SUCCESS;\r
3040}\r
3041\r
3042EFI_STATUS\r
3043PciExplainBar (\r
3044 IN UINT32 *Bar,\r
3045 IN UINT16 *Command,\r
3046 IN UINT64 Address,\r
3047 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3048 IN OUT UINTN *Index\r
3049 )\r
3050/*++\r
3051\r
3052Routine Description:\r
3053\r
3054 Explain the Base Address Register(Bar) in PCI configuration space.\r
3055\r
3056Arguments:\r
3057\r
3058 Bar Points to the Base Address Register intended to interpret\r
3059 Command Points to the register Command\r
3060 Address Address used to access configuration space of this PCI device\r
3061 IoDev Handle used to access configuration space of PCI device\r
3062 Index The Index\r
3063\r
3064Returns:\r
3065\r
3066 EFI_SUCCESS The command completed successfully\r
3067\r
3068**/\r
3069{\r
3070 UINT16 OldCommand;\r
3071 UINT16 NewCommand;\r
3072 UINT64 Bar64;\r
3073 UINT32 OldBar32;\r
3074 UINT32 NewBar32;\r
3075 UINT64 OldBar64;\r
3076 UINT64 NewBar64;\r
3077 BOOLEAN IsMem;\r
3078 BOOLEAN IsBar32;\r
3079 UINT64 RegAddress;\r
3080\r
3081 IsBar32 = TRUE;\r
3082 Bar64 = 0;\r
3083 NewBar32 = 0;\r
3084 NewBar64 = 0;\r
3085\r
3086 //\r
3087 // According the bar type, list detail about this bar, for example: 32 or\r
3088 // 64 bits; pre-fetchable or not.\r
3089 //\r
3090 if ((*Bar & PCI_BIT_0) == 0) {\r
3091 //\r
3092 // This bar is of memory type\r
3093 //\r
3094 IsMem = TRUE;\r
3095\r
3096 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3097 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3098 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3099 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3100\r
3101 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3102 Bar64 = 0x0;\r
3103 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
3104 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0), 32));\r
3105 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0));\r
3106 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3107 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3108 IsBar32 = FALSE;\r
3109 *Index += 1;\r
3110\r
3111 } else {\r
3112 //\r
3113 // Reserved\r
3114 //\r
3115 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3116 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3117 }\r
3118\r
3119 if ((*Bar & PCI_BIT_3) == 0) {\r
3120 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3121\r
3122 } else {\r
3123 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3124 }\r
3125\r
3126 } else {\r
3127 //\r
3128 // This bar is of io type\r
3129 //\r
3130 IsMem = FALSE;\r
3131 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
3132 Print (L"I/O ");\r
3133 }\r
3134\r
3135 //\r
3136 // Get BAR length(or the amount of resource this bar demands for). To get\r
3137 // Bar length, first we should temporarily disable I/O and memory access\r
3138 // of this function(by set bits in the register Command), then write all\r
3139 // "1"s to this bar. The bar value read back is the amount of resource\r
3140 // this bar demands for.\r
3141 //\r
3142 //\r
3143 // Disable io & mem access\r
3144 //\r
3145 OldCommand = *Command;\r
3146 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3147 RegAddress = Address | INDEX_OF (Command);\r
3148 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3149\r
3150 RegAddress = Address | INDEX_OF (Bar);\r
3151\r
3152 //\r
3153 // Read after write the BAR to get the size\r
3154 //\r
3155 if (IsBar32) {\r
3156 OldBar32 = *Bar;\r
3157 NewBar32 = 0xffffffff;\r
3158\r
3159 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3160 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3161 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3162\r
3163 if (IsMem) {\r
3164 NewBar32 = NewBar32 & 0xfffffff0;\r
3165 NewBar32 = (~NewBar32) + 1;\r
3166\r
3167 } else {\r
3168 NewBar32 = NewBar32 & 0xfffffffc;\r
3169 NewBar32 = (~NewBar32) + 1;\r
3170 NewBar32 = NewBar32 & 0x0000ffff;\r
3171 }\r
3172 } else {\r
3173\r
3174 OldBar64 = 0x0;\r
3175 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
3176 NewBar64 = 0xffffffffffffffff;\r
3177\r
3178 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3179 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3180 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3181\r
3182 if (IsMem) {\r
3183 NewBar64 = NewBar64 & 0xfffffffffffffff0;\r
3184 NewBar64 = (~NewBar64) + 1;\r
3185\r
3186 } else {\r
3187 NewBar64 = NewBar64 & 0xfffffffffffffffc;\r
3188 NewBar64 = (~NewBar64) + 1;\r
3189 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3190 }\r
3191 }\r
3192 //\r
3193 // Enable io & mem access\r
3194 //\r
3195 RegAddress = Address | INDEX_OF (Command);\r
3196 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3197\r
3198 if (IsMem) {\r
3199 if (IsBar32) {\r
3200 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3201 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3202\r
3203 } else {\r
3204 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));\r
3205 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
3206 Print (L" ");\r
3207 ShellPrintHiiEx(-1, -1, NULL,\r
3208 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3209 gShellDebug1HiiHandle,\r
3210 RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1), 32)\r
3211 );\r
3212 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1));\r
3213\r
3214 }\r
3215 } else {\r
3216 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3217 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3218 }\r
3219\r
3220 return EFI_SUCCESS;\r
3221}\r
3222\r
3223EFI_STATUS\r
3224PciExplainCardBusData (\r
3225 IN PCI_CARDBUS_HEADER *CardBus,\r
3226 IN UINT64 Address,\r
3227 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3228 )\r
3229/*++\r
3230\r
3231Routine Description:\r
3232\r
3233 Explain the cardbus specific part of data in PCI configuration space.\r
3234\r
3235Arguments:\r
3236\r
3237 CardBus CardBus specific region of PCI configuration space\r
3238 Address Address used to access configuration space of this PCI device\r
3239 IoDev Handle used to access configuration space of PCI device\r
3240\r
3241Returns:\r
3242\r
3243 EFI_SUCCESS The command completed successfully\r
3244\r
3245**/\r
3246{\r
3247 BOOLEAN Io32Bit;\r
3248 PCI_CARDBUS_DATA *CardBusData;\r
3249\r
3250 ShellPrintHiiEx(-1, -1, NULL,\r
3251 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3252 gShellDebug1HiiHandle,\r
3253 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3254 CardBus->CardBusSocketReg\r
3255 );\r
3256\r
3257 //\r
3258 // Print Secondary Status\r
3259 //\r
3260 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3261\r
3262 //\r
3263 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3264 // Subordinate bus number\r
3265 //\r
3266 ShellPrintHiiEx(-1, -1, NULL,\r
3267 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3268 gShellDebug1HiiHandle,\r
3269 INDEX_OF (&(CardBus->PciBusNumber)),\r
3270 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3271 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3272 );\r
3273\r
3274 Print (L" ------------------------------------------------------\n");\r
3275\r
3276 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3277 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3278 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3279\r
3280 //\r
3281 // Print CardBus Latency Timer\r
3282 //\r
3283 ShellPrintHiiEx(-1, -1, NULL,\r
3284 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3285 gShellDebug1HiiHandle,\r
3286 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3287 CardBus->CardBusLatencyTimer\r
3288 );\r
3289\r
3290 //\r
3291 // Print Memory/Io ranges this cardbus bridge forwards\r
3292 //\r
3293 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
3294 Print (L"----------------------------------------------------------------------\n");\r
3295\r
3296 ShellPrintHiiEx(-1, -1, NULL,\r
3297 STRING_TOKEN (STR_PCI2_MEM_3),\r
3298 gShellDebug1HiiHandle,\r
3299 INDEX_OF (&(CardBus->MemoryBase0)),\r
3300 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3301 CardBus->MemoryBase0 & 0xfffff000,\r
3302 CardBus->MemoryLimit0 | 0x00000fff\r
3303 );\r
3304\r
3305 ShellPrintHiiEx(-1, -1, NULL,\r
3306 STRING_TOKEN (STR_PCI2_MEM_3),\r
3307 gShellDebug1HiiHandle,\r
3308 INDEX_OF (&(CardBus->MemoryBase1)),\r
3309 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3310 CardBus->MemoryBase1 & 0xfffff000,\r
3311 CardBus->MemoryLimit1 | 0x00000fff\r
3312 );\r
3313\r
3314 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3315 ShellPrintHiiEx(-1, -1, NULL,\r
3316 STRING_TOKEN (STR_PCI2_IO_2),\r
3317 gShellDebug1HiiHandle,\r
3318 INDEX_OF (&(CardBus->IoBase0)),\r
3319 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3320 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
3321 CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
3322 );\r
3323\r
3324 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3325 ShellPrintHiiEx(-1, -1, NULL,\r
3326 STRING_TOKEN (STR_PCI2_IO_2),\r
3327 gShellDebug1HiiHandle,\r
3328 INDEX_OF (&(CardBus->IoBase1)),\r
3329 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3330 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
3331 CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
3332 );\r
3333\r
3334 //\r
3335 // Print register Interrupt Line & PIN\r
3336 //\r
3337 ShellPrintHiiEx(-1, -1, NULL,\r
3338 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3339 gShellDebug1HiiHandle,\r
3340 INDEX_OF (&(CardBus->InterruptLine)),\r
3341 CardBus->InterruptLine,\r
3342 INDEX_OF (&(CardBus->InterruptPin)),\r
3343 CardBus->InterruptPin\r
3344 );\r
3345\r
3346 //\r
3347 // Print register Bridge Control\r
3348 //\r
3349 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3350\r
3351 //\r
3352 // Print some registers in data region of PCI configuration space for cardbus\r
3353 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3354 // Address.\r
3355 //\r
3356 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3357\r
3358 ShellPrintHiiEx(-1, -1, NULL,\r
3359 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3360 gShellDebug1HiiHandle,\r
3361 INDEX_OF (&(CardBusData->SubVendorId)),\r
3362 CardBusData->SubVendorId,\r
3363 INDEX_OF (&(CardBusData->SubSystemId)),\r
3364 CardBusData->SubSystemId\r
3365 );\r
3366\r
3367 ShellPrintHiiEx(-1, -1, NULL,\r
3368 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3369 gShellDebug1HiiHandle,\r
3370 INDEX_OF (&(CardBusData->LegacyBase)),\r
3371 CardBusData->LegacyBase\r
3372 );\r
3373\r
3374 return EFI_SUCCESS;\r
3375}\r
3376\r
3377EFI_STATUS\r
3378PciExplainStatus (\r
3379 IN UINT16 *Status,\r
3380 IN BOOLEAN MainStatus,\r
3381 IN PCI_HEADER_TYPE HeaderType\r
3382 )\r
3383/*++\r
3384\r
3385Routine Description:\r
3386\r
3387 Explain each meaningful bit of register Status. The definition of Status is\r
3388 slightly different depending on the PCI header type.\r
3389\r
3390Arguments:\r
3391\r
3392 Status Points to the content of register Status\r
3393 MainStatus Indicates if this register is main status(not secondary\r
3394 status)\r
3395 HeaderType Header type of this PCI device\r
3396\r
3397Returns:\r
3398\r
3399 EFI_SUCCESS The command completed successfully\r
3400\r
3401**/\r
3402{\r
3403 if (MainStatus) {\r
3404 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3405\r
3406 } else {\r
3407 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3408 }\r
3409\r
3410 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3411\r
3412 //\r
3413 // Bit 5 is meaningless for CardBus Bridge\r
3414 //\r
3415 if (HeaderType == PciCardBusBridge) {\r
3416 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3417\r
3418 } else {\r
3419 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3420 }\r
3421\r
3422 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3423\r
3424 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3425 //\r
3426 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3427 //\r
3428 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3429 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3430 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3431\r
3432 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3433 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3434\r
3435 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3436 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3437\r
3438 } else {\r
3439 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3440 }\r
3441\r
3442 ShellPrintHiiEx(-1, -1, NULL,\r
3443 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3444 gShellDebug1HiiHandle,\r
3445 (*Status & PCI_BIT_11) != 0\r
3446 );\r
3447\r
3448 ShellPrintHiiEx(-1, -1, NULL,\r
3449 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3450 gShellDebug1HiiHandle,\r
3451 (*Status & PCI_BIT_12) != 0\r
3452 );\r
3453\r
3454 ShellPrintHiiEx(-1, -1, NULL,\r
3455 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3456 gShellDebug1HiiHandle,\r
3457 (*Status & PCI_BIT_13) != 0\r
3458 );\r
3459\r
3460 if (MainStatus) {\r
3461 ShellPrintHiiEx(-1, -1, NULL,\r
3462 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3463 gShellDebug1HiiHandle,\r
3464 (*Status & PCI_BIT_14) != 0\r
3465 );\r
3466\r
3467 } else {\r
3468 ShellPrintHiiEx(-1, -1, NULL,\r
3469 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3470 gShellDebug1HiiHandle,\r
3471 (*Status & PCI_BIT_14) != 0\r
3472 );\r
3473 }\r
3474\r
3475 ShellPrintHiiEx(-1, -1, NULL,\r
3476 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
3477 gShellDebug1HiiHandle,\r
3478 (*Status & PCI_BIT_15) != 0\r
3479 );\r
3480\r
3481 return EFI_SUCCESS;\r
3482}\r
3483\r
3484EFI_STATUS\r
3485PciExplainCommand (\r
3486 IN UINT16 *Command\r
3487 )\r
3488/*++\r
3489\r
3490Routine Description:\r
3491\r
3492 Explain each meaningful bit of register Command.\r
3493\r
3494Arguments:\r
3495\r
3496 Command Points to the content of register Command\r
3497\r
3498Returns:\r
3499\r
3500 EFI_SUCCESS The command completed successfully\r
3501\r
3502**/\r
3503{\r
3504 //\r
3505 // Print the binary value of register Command\r
3506 //\r
3507 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
3508\r
3509 //\r
3510 // Explain register Command bit by bit\r
3511 //\r
3512 ShellPrintHiiEx(-1, -1, NULL,\r
3513 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
3514 gShellDebug1HiiHandle,\r
3515 (*Command & PCI_BIT_0) != 0\r
3516 );\r
3517\r
3518 ShellPrintHiiEx(-1, -1, NULL,\r
3519 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
3520 gShellDebug1HiiHandle,\r
3521 (*Command & PCI_BIT_1) != 0\r
3522 );\r
3523\r
3524 ShellPrintHiiEx(-1, -1, NULL,\r
3525 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
3526 gShellDebug1HiiHandle,\r
3527 (*Command & PCI_BIT_2) != 0\r
3528 );\r
3529\r
3530 ShellPrintHiiEx(-1, -1, NULL,\r
3531 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
3532 gShellDebug1HiiHandle,\r
3533 (*Command & PCI_BIT_3) != 0\r
3534 );\r
3535\r
3536 ShellPrintHiiEx(-1, -1, NULL,\r
3537 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
3538 gShellDebug1HiiHandle,\r
3539 (*Command & PCI_BIT_4) != 0\r
3540 );\r
3541\r
3542 ShellPrintHiiEx(-1, -1, NULL,\r
3543 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
3544 gShellDebug1HiiHandle,\r
3545 (*Command & PCI_BIT_5) != 0\r
3546 );\r
3547\r
3548 ShellPrintHiiEx(-1, -1, NULL,\r
3549 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
3550 gShellDebug1HiiHandle,\r
3551 (*Command & PCI_BIT_6) != 0\r
3552 );\r
3553\r
3554 ShellPrintHiiEx(-1, -1, NULL,\r
3555 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
3556 gShellDebug1HiiHandle,\r
3557 (*Command & PCI_BIT_7) != 0\r
3558 );\r
3559\r
3560 ShellPrintHiiEx(-1, -1, NULL,\r
3561 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
3562 gShellDebug1HiiHandle,\r
3563 (*Command & PCI_BIT_8) != 0\r
3564 );\r
3565\r
3566 ShellPrintHiiEx(-1, -1, NULL,\r
3567 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
3568 gShellDebug1HiiHandle,\r
3569 (*Command & PCI_BIT_9) != 0\r
3570 );\r
3571\r
3572 return EFI_SUCCESS;\r
3573}\r
3574\r
3575EFI_STATUS\r
3576PciExplainBridgeControl (\r
3577 IN UINT16 *BridgeControl,\r
3578 IN PCI_HEADER_TYPE HeaderType\r
3579 )\r
3580/*++\r
3581\r
3582Routine Description:\r
3583\r
3584 Explain each meaningful bit of register Bridge Control.\r
3585\r
3586Arguments:\r
3587\r
3588 BridgeControl Points to the content of register Bridge Control\r
3589 HeaderType The headertype\r
3590\r
3591Returns:\r
3592\r
3593 EFI_SUCCESS The command completed successfully\r
3594\r
3595**/\r
3596{\r
3597 ShellPrintHiiEx(-1, -1, NULL,\r
3598 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
3599 gShellDebug1HiiHandle,\r
3600 INDEX_OF (BridgeControl),\r
3601 *BridgeControl\r
3602 );\r
3603\r
3604 ShellPrintHiiEx(-1, -1, NULL,\r
3605 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
3606 gShellDebug1HiiHandle,\r
3607 (*BridgeControl & PCI_BIT_0) != 0\r
3608 );\r
3609 ShellPrintHiiEx(-1, -1, NULL,\r
3610 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
3611 gShellDebug1HiiHandle,\r
3612 (*BridgeControl & PCI_BIT_1) != 0\r
3613 );\r
3614 ShellPrintHiiEx(-1, -1, NULL,\r
3615 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
3616 gShellDebug1HiiHandle,\r
3617 (*BridgeControl & PCI_BIT_2) != 0\r
3618 );\r
3619 ShellPrintHiiEx(-1, -1, NULL,\r
3620 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
3621 gShellDebug1HiiHandle,\r
3622 (*BridgeControl & PCI_BIT_3) != 0\r
3623 );\r
3624 ShellPrintHiiEx(-1, -1, NULL,\r
3625 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
3626 gShellDebug1HiiHandle,\r
3627 (*BridgeControl & PCI_BIT_5) != 0\r
3628 );\r
3629\r
3630 //\r
3631 // Register Bridge Control has some slight differences between P2P bridge\r
3632 // and Cardbus bridge from bit 6 to bit 11.\r
3633 //\r
3634 if (HeaderType == PciP2pBridge) {\r
3635 ShellPrintHiiEx(-1, -1, NULL,\r
3636 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
3637 gShellDebug1HiiHandle,\r
3638 (*BridgeControl & PCI_BIT_6) != 0\r
3639 );\r
3640 ShellPrintHiiEx(-1, -1, NULL,\r
3641 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
3642 gShellDebug1HiiHandle,\r
3643 (*BridgeControl & PCI_BIT_7) != 0\r
3644 );\r
3645 ShellPrintHiiEx(-1, -1, NULL,\r
3646 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
3647 gShellDebug1HiiHandle,\r
3648 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
3649 );\r
3650 ShellPrintHiiEx(-1, -1, NULL,\r
3651 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
3652 gShellDebug1HiiHandle,\r
3653 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
3654 );\r
3655 ShellPrintHiiEx(-1, -1, NULL,\r
3656 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
3657 gShellDebug1HiiHandle,\r
3658 (*BridgeControl & PCI_BIT_10) != 0\r
3659 );\r
3660 ShellPrintHiiEx(-1, -1, NULL,\r
3661 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
3662 gShellDebug1HiiHandle,\r
3663 (*BridgeControl & PCI_BIT_11) != 0\r
3664 );\r
3665\r
3666 } else {\r
3667 ShellPrintHiiEx(-1, -1, NULL,\r
3668 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
3669 gShellDebug1HiiHandle,\r
3670 (*BridgeControl & PCI_BIT_6) != 0\r
3671 );\r
3672 ShellPrintHiiEx(-1, -1, NULL,\r
3673 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
3674 gShellDebug1HiiHandle,\r
3675 (*BridgeControl & PCI_BIT_7) != 0\r
3676 );\r
3677 ShellPrintHiiEx(-1, -1, NULL,\r
3678 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
3679 gShellDebug1HiiHandle,\r
3680 (*BridgeControl & PCI_BIT_10) != 0\r
3681 );\r
3682 }\r
3683\r
3684 return EFI_SUCCESS;\r
3685}\r
3686\r
3687EFI_STATUS\r
3688PciExplainCapabilityStruct (\r
3689 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3690 IN UINT64 Address,\r
3691 IN UINT8 CapPtr\r
3692 )\r
3693{\r
3694 UINT8 CapabilityPtr;\r
3695 UINT16 CapabilityEntry;\r
3696 UINT8 CapabilityID;\r
3697 UINT64 RegAddress;\r
3698\r
3699 CapabilityPtr = CapPtr;\r
3700\r
3701 //\r
3702 // Go through the Capability list\r
3703 //\r
3704 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
3705 RegAddress = Address + CapabilityPtr;\r
3706 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
3707\r
3708 CapabilityID = (UINT8) CapabilityEntry;\r
3709\r
3710 //\r
3711 // Explain PciExpress data\r
3712 //\r
3713 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
3714 PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
3715 return EFI_SUCCESS;\r
3716 }\r
3717 //\r
3718 // Explain other capabilities here\r
3719 //\r
3720 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
3721 }\r
3722\r
3723 return EFI_SUCCESS;\r
3724}\r
3725\r
3726EFI_STATUS\r
3727ExplainPcieCapReg (\r
3728 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3729)\r
3730{\r
3731 UINT16 PcieCapReg;\r
3732 CHAR16 *DevicePortType;\r
3733\r
3734 PcieCapReg = PciExpressCap->PcieCapReg;\r
3735 Print (\r
3736 L" Capability Version(3:0): %E0x%04x%N\n",\r
3737 PCIE_CAP_VERSION (PcieCapReg)\r
3738 );\r
3739 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
3740 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
3741 } else {\r
3742 DevicePortType = L"Unknown Type";\r
3743 }\r
3744 Print (\r
3745 L" Device/PortType(7:4): %E%s%N\n",\r
3746 DevicePortType\r
3747 );\r
3748 //\r
3749 // 'Slot Implemented' is only valid for:\r
3750 // a) Root Port of PCI Express Root Complex, or\r
3751 // b) Downstream Port of PCI Express Switch\r
3752 //\r
3753 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
3754 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
3755 Print (\r
3756 L" Slot Implemented(8): %E%d%N\n",\r
3757 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
3758 );\r
3759 }\r
3760 Print (\r
3761 L" Interrupt Message Number(13:9): %E0x%05x%N\n",\r
3762 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
3763 );\r
3764 return EFI_SUCCESS;\r
3765}\r
3766\r
3767EFI_STATUS\r
3768ExplainPcieDeviceCap (\r
3769 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3770)\r
3771{\r
3772 UINT16 PcieCapReg;\r
3773 UINT32 PcieDeviceCap;\r
3774 UINT8 DevicePortType;\r
3775 UINT8 L0sLatency;\r
3776 UINT8 L1Latency;\r
3777\r
3778 PcieCapReg = PciExpressCap->PcieCapReg;\r
3779 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
3780 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
3781 Print (L" Max_Payload_Size Supported(2:0): ");\r
3782 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
3783 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
3784 } else {\r
3785 Print (L"%EUnknown%N\n");\r
3786 }\r
3787 Print (\r
3788 L" Phantom Functions Supported(4:3): %E%d%N\n",\r
3789 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
3790 );\r
3791 Print (\r
3792 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",\r
3793 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
3794 );\r
3795 //\r
3796 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
3797 //\r
3798 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3799 L0sLatency = (UINT8) PCIE_CAP_L0sLatency (PcieDeviceCap);\r
3800 L1Latency = (UINT8) PCIE_CAP_L1Latency (PcieDeviceCap);\r
3801 Print (L" Endpoint L0s Acceptable Latency(8:6): ");\r
3802 if (L0sLatency < 4) {\r
3803 Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));\r
3804 } else {\r
3805 if (L0sLatency < 7) {\r
3806 Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));\r
3807 } else {\r
3808 Print (L"%ENo limit%N\n");\r
3809 }\r
3810 }\r
3811 Print (L" Endpoint L1 Acceptable Latency(11:9): ");\r
3812 if (L1Latency < 7) {\r
3813 Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));\r
3814 } else {\r
3815 Print (L"%ENo limit%N\n");\r
3816 }\r
3817 }\r
3818 Print (\r
3819 L" Role-based Error Reporting(15): %E%d%N\n",\r
3820 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
3821 );\r
3822 //\r
3823 // Only valid for Upstream Port:\r
3824 // a) Captured Slot Power Limit Value\r
3825 // b) Captured Slot Power Scale\r
3826 //\r
3827 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
3828 Print (\r
3829 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",\r
3830 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
3831 );\r
3832 Print (\r
3833 L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",\r
3834 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
3835 );\r
3836 }\r
3837 //\r
3838 // Function Level Reset Capability is only valid for Endpoint\r
3839 //\r
3840 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3841 Print (\r
3842 L" Function Level Reset Capability(28): %E%d%N\n",\r
3843 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
3844 );\r
3845 }\r
3846 return EFI_SUCCESS;\r
3847}\r
3848\r
3849EFI_STATUS\r
3850ExplainPcieDeviceControl (\r
3851 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3852)\r
3853{\r
3854 UINT16 PcieCapReg;\r
3855 UINT16 PcieDeviceControl;\r
3856\r
3857 PcieCapReg = PciExpressCap->PcieCapReg;\r
3858 PcieDeviceControl = PciExpressCap->DeviceControl;\r
3859 Print (\r
3860 L" Correctable Error Reporting Enable(0): %E%d%N\n",\r
3861 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3862 );\r
3863 Print (\r
3864 L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",\r
3865 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3866 );\r
3867 Print (\r
3868 L" Fatal Error Reporting Enable(2): %E%d%N\n",\r
3869 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3870 );\r
3871 Print (\r
3872 L" Unsupported Request Reporting Enable(3): %E%d%N\n",\r
3873 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
3874 );\r
3875 Print (\r
3876 L" Enable Relaxed Ordering(4): %E%d%N\n",\r
3877 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
3878 );\r
3879 Print (L" Max_Payload_Size(7:5): ");\r
3880 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
3881 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
3882 } else {\r
3883 Print (L"%EUnknown%N\n");\r
3884 }\r
3885 Print (\r
3886 L" Extended Tag Field Enable(8): %E%d%N\n",\r
3887 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
3888 );\r
3889 Print (\r
3890 L" Phantom Functions Enable(9): %E%d%N\n",\r
3891 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
3892 );\r
3893 Print (\r
3894 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",\r
3895 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
3896 );\r
3897 Print (\r
3898 L" Enable No Snoop(11): %E%d%N\n",\r
3899 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
3900 );\r
3901 Print (L" Max_Read_Request_Size(14:12): ");\r
3902 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
3903 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
3904 } else {\r
3905 Print (L"%EUnknown%N\n");\r
3906 }\r
3907 //\r
3908 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
3909 //\r
3910 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
3911 Print (\r
3912 L" Bridge Configuration Retry Enable(15): %E%d%N\n",\r
3913 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
3914 );\r
3915 }\r
3916 return EFI_SUCCESS;\r
3917}\r
3918\r
3919EFI_STATUS\r
3920ExplainPcieDeviceStatus (\r
3921 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3922)\r
3923{\r
3924 UINT16 PcieDeviceStatus;\r
3925\r
3926 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
3927 Print (\r
3928 L" Correctable Error Detected(0): %E%d%N\n",\r
3929 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
3930 );\r
3931 Print (\r
3932 L" Non-Fatal Error Detected(1): %E%d%N\n",\r
3933 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
3934 );\r
3935 Print (\r
3936 L" Fatal Error Detected(2): %E%d%N\n",\r
3937 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
3938 );\r
3939 Print (\r
3940 L" Unsupported Request Detected(3): %E%d%N\n",\r
3941 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
3942 );\r
3943 Print (\r
3944 L" AUX Power Detected(4): %E%d%N\n",\r
3945 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
3946 );\r
3947 Print (\r
3948 L" Transactions Pending(5): %E%d%N\n",\r
3949 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
3950 );\r
3951 return EFI_SUCCESS;\r
3952}\r
3953\r
3954EFI_STATUS\r
3955ExplainPcieLinkCap (\r
3956 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3957)\r
3958{\r
3959 UINT32 PcieLinkCap;\r
3960 CHAR16 *SupLinkSpeeds;\r
3961 CHAR16 *ASPM;\r
3962\r
3963 PcieLinkCap = PciExpressCap->LinkCap;\r
3964 switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
3965 case 1:\r
3966 SupLinkSpeeds = L"2.5 GT/s";\r
3967 break;\r
3968 case 2:\r
3969 SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
3970 break;\r
3971 default:\r
3972 SupLinkSpeeds = L"Unknown";\r
3973 break;\r
3974 }\r
3975 Print (\r
3976 L" Supported Link Speeds(3:0): %E%s supported%N\n",\r
3977 SupLinkSpeeds\r
3978 );\r
3979 Print (\r
3980 L" Maximum Link Width(9:4): %Ex%d%N\n",\r
3981 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
3982 );\r
3983 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
3984 case 1:\r
3985 ASPM = L"L0s Entry";\r
3986 break;\r
3987 case 3:\r
3988 ASPM = L"L0s and L1";\r
3989 break;\r
3990 default:\r
3991 ASPM = L"Reserved";\r
3992 break;\r
3993 }\r
3994 Print (\r
3995 L" Active State Power Management Support(11:10): %E%s Supported%N\n",\r
3996 ASPM\r
3997 );\r
3998 Print (\r
3999 L" L0s Exit Latency(14:12): %E%s%N\n",\r
4000 L0sLatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]\r
4001 );\r
4002 Print (\r
4003 L" L1 Exit Latency(17:15): %E%s%N\n",\r
4004 L1LatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]\r
4005 );\r
4006 Print (\r
4007 L" Clock Power Management(18): %E%d%N\n",\r
4008 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4009 );\r
4010 Print (\r
4011 L" Surprise Down Error Reporting Capable(19): %E%d%N\n",\r
4012 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4013 );\r
4014 Print (\r
4015 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",\r
4016 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4017 );\r
4018 Print (\r
4019 L" Link Bandwidth Notification Capability(21): %E%d%N\n",\r
4020 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4021 );\r
4022 Print (\r
4023 L" Port Number(31:24): %E0x%02x%N\n",\r
4024 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4025 );\r
4026 return EFI_SUCCESS;\r
4027}\r
4028\r
4029EFI_STATUS\r
4030ExplainPcieLinkControl (\r
4031 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4032)\r
4033{\r
4034 UINT16 PcieLinkControl;\r
4035 UINT8 DevicePortType;\r
4036\r
4037 PcieLinkControl = PciExpressCap->LinkControl;\r
4038 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
4039 Print (\r
4040 L" Active State Power Management Control(1:0): %E%s%N\n",\r
4041 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4042 );\r
4043 //\r
4044 // RCB is not applicable to switches\r
4045 //\r
4046 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
4047 Print (\r
4048 L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",\r
4049 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4050 );\r
4051 }\r
4052 //\r
4053 // Link Disable is reserved on\r
4054 // a) Endpoints\r
4055 // b) PCI Express to PCI/PCI-X bridges\r
4056 // c) Upstream Ports of Switches\r
4057 //\r
4058 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4059 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4060 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4061 Print (\r
4062 L" Link Disable(4): %E%d%N\n",\r
4063 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4064 );\r
4065 }\r
4066 Print (\r
4067 L" Common Clock Configuration(6): %E%d%N\n",\r
4068 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4069 );\r
4070 Print (\r
4071 L" Extended Synch(7): %E%d%N\n",\r
4072 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4073 );\r
4074 Print (\r
4075 L" Enable Clock Power Management(8): %E%d%N\n",\r
4076 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4077 );\r
4078 Print (\r
4079 L" Hardware Autonomous Width Disable(9): %E%d%N\n",\r
4080 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4081 );\r
4082 Print (\r
4083 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",\r
4084 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4085 );\r
4086 Print (\r
4087 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",\r
4088 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4089 );\r
4090 return EFI_SUCCESS;\r
4091}\r
4092\r
4093EFI_STATUS\r
4094ExplainPcieLinkStatus (\r
4095 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4096)\r
4097{\r
4098 UINT16 PcieLinkStatus;\r
4099 CHAR16 *SupLinkSpeeds;\r
4100\r
4101 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4102 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4103 case 1:\r
4104 SupLinkSpeeds = L"2.5 GT/s";\r
4105 break;\r
4106 case 2:\r
4107 SupLinkSpeeds = L"5.0 GT/s";\r
4108 break;\r
4109 default:\r
4110 SupLinkSpeeds = L"Reserved";\r
4111 break;\r
4112 }\r
4113 Print (\r
4114 L" Current Link Speed(3:0): %E%s%N\n",\r
4115 SupLinkSpeeds\r
4116 );\r
4117 Print (\r
4118 L" Negotiated Link Width(9:4): %Ex%d%N\n",\r
4119 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4120 );\r
4121 Print (\r
4122 L" Link Training(11): %E%d%N\n",\r
4123 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4124 );\r
4125 Print (\r
4126 L" Slot Clock Configuration(12): %E%d%N\n",\r
4127 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4128 );\r
4129 Print (\r
4130 L" Data Link Layer Link Active(13): %E%d%N\n",\r
4131 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4132 );\r
4133 Print (\r
4134 L" Link Bandwidth Management Status(14): %E%d%N\n",\r
4135 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4136 );\r
4137 Print (\r
4138 L" Link Autonomous Bandwidth Status(15): %E%d%N\n",\r
4139 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4140 );\r
4141 return EFI_SUCCESS;\r
4142}\r
4143\r
4144EFI_STATUS\r
4145ExplainPcieSlotCap (\r
4146 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4147)\r
4148{\r
4149 UINT32 PcieSlotCap;\r
4150\r
4151 PcieSlotCap = PciExpressCap->SlotCap;\r
4152\r
4153 Print (\r
4154 L" Attention Button Present(0): %E%d%N\n",\r
4155 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4156 );\r
4157 Print (\r
4158 L" Power Controller Present(1): %E%d%N\n",\r
4159 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4160 );\r
4161 Print (\r
4162 L" MRL Sensor Present(2): %E%d%N\n",\r
4163 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4164 );\r
4165 Print (\r
4166 L" Attention Indicator Present(3): %E%d%N\n",\r
4167 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4168 );\r
4169 Print (\r
4170 L" Power Indicator Present(4): %E%d%N\n",\r
4171 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4172 );\r
4173 Print (\r
4174 L" Hot-Plug Surprise(5): %E%d%N\n",\r
4175 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4176 );\r
4177 Print (\r
4178 L" Hot-Plug Capable(6): %E%d%N\n",\r
4179 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4180 );\r
4181 Print (\r
4182 L" Slot Power Limit Value(14:7): %E0x%02x%N\n",\r
4183 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4184 );\r
4185 Print (\r
4186 L" Slot Power Limit Scale(16:15): %E%s%N\n",\r
4187 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4188 );\r
4189 Print (\r
4190 L" Electromechanical Interlock Present(17): %E%d%N\n",\r
4191 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4192 );\r
4193 Print (\r
4194 L" No Command Completed Support(18): %E%d%N\n",\r
4195 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4196 );\r
4197 Print (\r
4198 L" Physical Slot Number(31:19): %E%d%N\n",\r
4199 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4200 );\r
4201\r
4202 return EFI_SUCCESS;\r
4203}\r
4204\r
4205EFI_STATUS\r
4206ExplainPcieSlotControl (\r
4207 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4208)\r
4209{\r
4210 UINT16 PcieSlotControl;\r
4211\r
4212 PcieSlotControl = PciExpressCap->SlotControl;\r
4213 Print (\r
4214 L" Attention Button Pressed Enable(0): %E%d%N\n",\r
4215 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4216 );\r
4217 Print (\r
4218 L" Power Fault Detected Enable(1): %E%d%N\n",\r
4219 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4220 );\r
4221 Print (\r
4222 L" MRL Sensor Changed Enable(2): %E%d%N\n",\r
4223 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4224 );\r
4225 Print (\r
4226 L" Presence Detect Changed Enable(3): %E%d%N\n",\r
4227 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4228 );\r
4229 Print (\r
4230 L" Command Completed Interrupt Enable(4): %E%d%N\n",\r
4231 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4232 );\r
4233 Print (\r
4234 L" Hot-Plug Interrupt Enable(5): %E%d%N\n",\r
4235 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4236 );\r
4237 Print (\r
4238 L" Attention Indicator Control(7:6): %E%s%N\n",\r
4239 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4240 );\r
4241 Print (\r
4242 L" Power Indicator Control(9:8): %E%s%N\n",\r
4243 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4244 );\r
4245 Print (L" Power Controller Control(10): %EPower ");\r
4246 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
4247 Print (L"Off%N\n");\r
4248 } else {\r
4249 Print (L"On%N\n");\r
4250 }\r
4251 Print (\r
4252 L" Electromechanical Interlock Control(11): %E%d%N\n",\r
4253 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4254 );\r
4255 Print (\r
4256 L" Data Link Layer State Changed Enable(12): %E%d%N\n",\r
4257 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4258 );\r
4259 return EFI_SUCCESS;\r
4260}\r
4261\r
4262EFI_STATUS\r
4263ExplainPcieSlotStatus (\r
4264 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4265)\r
4266{\r
4267 UINT16 PcieSlotStatus;\r
4268\r
4269 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4270\r
4271 Print (\r
4272 L" Attention Button Pressed(0): %E%d%N\n",\r
4273 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4274 );\r
4275 Print (\r
4276 L" Power Fault Detected(1): %E%d%N\n",\r
4277 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4278 );\r
4279 Print (\r
4280 L" MRL Sensor Changed(2): %E%d%N\n",\r
4281 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4282 );\r
4283 Print (\r
4284 L" Presence Detect Changed(3): %E%d%N\n",\r
4285 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4286 );\r
4287 Print (\r
4288 L" Command Completed(4): %E%d%N\n",\r
4289 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4290 );\r
4291 Print (L" MRL Sensor State(5): %EMRL ");\r
4292 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
4293 Print (L" Opened%N\n");\r
4294 } else {\r
4295 Print (L" Closed%N\n");\r
4296 }\r
4297 Print (L" Presence Detect State(6): ");\r
4298 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
4299 Print (L"%ECard Present in slot%N\n");\r
4300 } else {\r
4301 Print (L"%ESlot Empty%N\n");\r
4302 }\r
4303 Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
4304 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
4305 Print (L"Engaged%N\n");\r
4306 } else {\r
4307 Print (L"Disengaged%N\n");\r
4308 }\r
4309 Print (\r
4310 L" Data Link Layer State Changed(8): %E%d%N\n",\r
4311 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4312 );\r
4313 return EFI_SUCCESS;\r
4314}\r
4315\r
4316EFI_STATUS\r
4317ExplainPcieRootControl (\r
4318 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4319)\r
4320{\r
4321 UINT16 PcieRootControl;\r
4322\r
4323 PcieRootControl = PciExpressCap->RootControl;\r
4324\r
4325 Print (\r
4326 L" System Error on Correctable Error Enable(0): %E%d%N\n",\r
4327 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4328 );\r
4329 Print (\r
4330 L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",\r
4331 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4332 );\r
4333 Print (\r
4334 L" System Error on Fatal Error Enable(2): %E%d%N\n",\r
4335 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4336 );\r
4337 Print (\r
4338 L" PME Interrupt Enable(3): %E%d%N\n",\r
4339 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4340 );\r
4341 Print (\r
4342 L" CRS Software Visibility Enable(4): %E%d%N\n",\r
4343 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4344 );\r
4345\r
4346 return EFI_SUCCESS;\r
4347}\r
4348\r
4349EFI_STATUS\r
4350ExplainPcieRootCap (\r
4351 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4352)\r
4353{\r
4354 UINT16 PcieRootCap;\r
4355\r
4356 PcieRootCap = PciExpressCap->RsvdP;\r
4357\r
4358 Print (\r
4359 L" CRS Software Visibility(0): %E%d%N\n",\r
4360 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4361 );\r
4362\r
4363 return EFI_SUCCESS;\r
4364}\r
4365\r
4366EFI_STATUS\r
4367ExplainPcieRootStatus (\r
4368 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4369)\r
4370{\r
4371 UINT32 PcieRootStatus;\r
4372\r
4373 PcieRootStatus = PciExpressCap->RootStatus;\r
4374\r
4375 Print (\r
4376 L" PME Requester ID(15:0): %E0x%04x%N\n",\r
4377 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
4378 );\r
4379 Print (\r
4380 L" PME Status(16): %E%d%N\n",\r
4381 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
4382 );\r
4383 Print (\r
4384 L" PME Pending(17): %E%d%N\n",\r
4385 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
4386 );\r
4387 return EFI_SUCCESS;\r
4388}\r
4389\r
4390EFI_STATUS\r
4391PciExplainPciExpress (\r
4392 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
4393 IN UINT64 Address,\r
4394 IN UINT8 CapabilityPtr\r
4395 )\r
4396{\r
4397\r
4398 PCIE_CAP_STURCTURE PciExpressCap;\r
4399 EFI_STATUS Status;\r
4400 UINT64 CapRegAddress;\r
4401 UINT8 Bus;\r
4402 UINT8 Dev;\r
4403 UINT8 Func;\r
4404 UINT8 *ExRegBuffer;\r
4405 UINTN ExtendRegSize;\r
4406 UINT64 Pciex_Address;\r
4407 UINT8 DevicePortType;\r
4408 UINTN Index;\r
4409 UINT8 *RegAddr;\r
4410 UINTN RegValue;\r
4411\r
4412 CapRegAddress = Address + CapabilityPtr;\r
4413 IoDev->Pci.Read (\r
4414 IoDev,\r
4415 EfiPciWidthUint32,\r
4416 CapRegAddress,\r
4417 sizeof (PciExpressCap) / sizeof (UINT32),\r
4418 &PciExpressCap\r
4419 );\r
4420\r
4421 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
4422\r
4423 Print (L"\nPci Express device capability structure:\n");\r
4424\r
4425 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
4426 if (ShellGetExecutionBreakFlag()) {\r
4427 goto Done;\r
4428 }\r
4429 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
4430 switch (PcieExplainList[Index].Width) {\r
4431 case FieldWidthUINT8:\r
4432 RegValue = *(UINT8 *) RegAddr;\r
4433 break;\r
4434 case FieldWidthUINT16:\r
4435 RegValue = *(UINT16 *) RegAddr;\r
4436 break;\r
4437 case FieldWidthUINT32:\r
4438 RegValue = *(UINT32 *) RegAddr;\r
4439 break;\r
4440 default:\r
4441 RegValue = 0;\r
4442 break;\r
4443 }\r
4444 ShellPrintHiiEx(-1, -1, NULL,\r
4445 PcieExplainList[Index].Token,\r
4446 gShellDebug1HiiHandle,\r
4447 PcieExplainList[Index].Offset,\r
4448 RegValue\r
4449 );\r
4450 if (PcieExplainList[Index].Func == NULL) {\r
4451 continue;\r
4452 }\r
4453 switch (PcieExplainList[Index].Type) {\r
4454 case PcieExplainTypeLink:\r
4455 //\r
4456 // Link registers should not be used by\r
4457 // a) Root Complex Integrated Endpoint\r
4458 // b) Root Complex Event Collector\r
4459 //\r
4460 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
4461 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
4462 continue;\r
4463 }\r
4464 break;\r
4465 case PcieExplainTypeSlot:\r
4466 //\r
4467 // Slot registers are only valid for\r
4468 // a) Root Port of PCI Express Root Complex\r
4469 // b) Downstream Port of PCI Express Switch\r
4470 // and when SlotImplemented bit is set in PCIE cap register.\r
4471 //\r
4472 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
4473 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
4474 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
4475 continue;\r
4476 }\r
4477 break;\r
4478 case PcieExplainTypeRoot:\r
4479 //\r
4480 // Root registers are only valid for\r
4481 // Root Port of PCI Express Root Complex\r
4482 //\r
4483 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
4484 continue;\r
4485 }\r
4486 break;\r
4487 default:\r
4488 break;\r
4489 }\r
4490 PcieExplainList[Index].Func (&PciExpressCap);\r
4491 }\r
4492\r
4493 Bus = (UINT8) (RShiftU64 (Address, 24));\r
4494 Dev = (UINT8) (RShiftU64 (Address, 16));\r
4495 Func = (UINT8) (RShiftU64 (Address, 8));\r
4496\r
4497 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
4498\r
4499 ExtendRegSize = 0x1000 - 0x100;\r
4500\r
3737ac2b 4501 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
5d73d92f 4502\r
4503 //\r
4504 // PciRootBridgeIo protocol should support pci express extend space IO\r
4505 // (Begins at offset 0x100)\r
4506 //\r
4507 Status = IoDev->Pci.Read (\r
4508 IoDev,\r
4509 EfiPciWidthUint32,\r
4510 Pciex_Address,\r
4511 (ExtendRegSize) / sizeof (UINT32),\r
4512 (VOID *) (ExRegBuffer)\r
4513 );\r
4514 if (EFI_ERROR (Status)) {\r
4515 FreePool ((VOID *) ExRegBuffer);\r
4516 return EFI_UNSUPPORTED;\r
4517 }\r
4518 //\r
4519 // Start outputing PciEx extend space( 0xFF-0xFFF)\r
4520 //\r
4521 Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");\r
4522\r
4523 PrivateDumpHex (\r
4524 2,\r
4525 0x100,\r
4526 ExtendRegSize,\r
4527 (VOID *) (ExRegBuffer)\r
4528 );\r
4529\r
4530 FreePool ((VOID *) ExRegBuffer);\r
4531\r
4532Done:\r
4533 return EFI_SUCCESS;\r
4534}\r
EFI Development Kit II mirror for PVE