[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Internal.h

/** @file\r
  Debug Port Library implementation based on usb3 debug port.\r
\r
  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__\r
#define __USB3_DEBUG_PORT_LIB_INTERNAL__\r
\r
#include <Uefi.h>\r
#include <Base.h>\r
#include <IndustryStandard/Usb.h>\r
#include <Library/IoLib.h>\r
#include <IndustryStandard/Pci.h>\r
#include <Library/PcdLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/DebugCommunicationLib.h>\r
#include <Library/PciLib.h>\r
\r
//\r
// USB Debug GUID value\r
//\r
#define USB3_DBG_GUID \\r
    { \\r
      0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \\r
    }\r
\r
//\r
// The state machine of usb debug port\r
//\r
#define USB3DBG_NO_DBG_CAB    0   // The XHCI host controller does not support debug capability\r
#define USB3DBG_DBG_CAB       1   // The XHCI host controller supports debug capability\r
#define USB3DBG_ENABLED       2   // The XHCI debug device is enabled\r
#define USB3DBG_NOT_ENABLED   4   // The XHCI debug device is not enabled\r
#define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized\r
\r
#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08\r
\r
//\r
// MaxPacketSize for DbC Endpoint Descriptor IN and OUT\r
//\r
#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE    0x400\r
\r
#define XHCI_DEBUG_DEVICE_VENDOR_ID   0x0525\r
#define XHCI_DEBUG_DEVICE_PRODUCT_ID  0x127A\r
#define XHCI_DEBUG_DEVICE_PROTOCOL    0xFF\r
#define XHCI_DEBUG_DEVICE_REVISION    0x00\r
\r
#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
\r
#define PCI_CAPABILITY_ID_DEBUG_PORT  0x0A\r
#define XHC_HCCPARAMS_OFFSET          0x10\r
#define XHC_CAPABILITY_ID_MASK        0xFF\r
#define XHC_NEXT_CAPABILITY_MASK      0xFF00\r
\r
#define XHC_HCSPARAMS1_OFFSET         0x4    // Structural Parameters 1\r
#define XHC_USBCMD_OFFSET             0x0    // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET             0x4    // USB Status Register Offset\r
#define XHC_PORTSC_OFFSET             0x400  // Port Status and Control Register Offset\r
\r
#define XHC_USBCMD_RUN                BIT0  // Run/Stop\r
#define XHC_USBCMD_RESET              BIT1  // Host Controller Reset\r
\r
#define XHC_USBSTS_HALT               BIT0\r
\r
//\r
// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.\r
//\r
#define DATA_TRANSFER_WRITE_TIMEOUT      0\r
#define DATA_TRANSFER_READ_TIMEOUT       50000\r
#define DATA_TRANSFER_POLL_TIMEOUT       1000\r
#define XHC_DEBUG_PORT_1_MILLISECOND     1000\r
//\r
// XHCI port power off/on delay\r
//\r
#define XHC_DEBUG_PORT_ON_OFF_DELAY    100000\r
\r
//\r
// USB debug device string descritpor (header size + unicode string length)\r
//\r
#define STRING0_DESC_LEN      4\r
#define MANU_DESC_LEN         12\r
#define PRODUCT_DESC_LEN      40\r
#define SERIAL_DESC_LEN       4\r
\r
//\r
// Debug Capability Register Offset\r
//\r
#define XHC_DC_DCID                  0x0\r
#define XHC_DC_DCDB                  0x4\r
#define XHC_DC_DCERSTSZ              0x8\r
#define XHC_DC_DCERSTBA              0x10\r
#define XHC_DC_DCERDP                0x18\r
#define XHC_DC_DCCTRL                0x20\r
#define XHC_DC_DCST                  0x24\r
#define XHC_DC_DCPORTSC              0x28\r
#define XHC_DC_DCCP                  0x30\r
#define XHC_DC_DCDDI1                0x38\r
#define XHC_DC_DCDDI2                0x3C\r
\r
#define TRB_TYPE_LINK                6\r
\r
#define ERST_NUMBER                  0x01\r
#define TR_RING_TRB_NUMBER           0x100\r
#define EVENT_RING_TRB_NUMBER        0x200\r
\r
#define ED_BULK_OUT                  2\r
#define ED_BULK_IN                   6\r
\r
#define XHC_LOW_32BIT(Addr64)          ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
#define XHC_HIGH_32BIT(Addr64)         ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
#define XHC_BIT_IS_SET(Data, Bit)      ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
\r
//\r
// Endpoint Type (EP Type).\r
//\r
#define ED_NOT_VALID                          0\r
#define ED_ISOCH_OUT                          1\r
#define ED_BULK_OUT                           2\r
#define ED_INTERRUPT_OUT                      3\r
#define ED_CONTROL_BIDIR                      4\r
#define ED_ISOCH_IN                           5\r
#define ED_BULK_IN                            6\r
#define ED_INTERRUPT_IN                       7\r
\r
//\r
// 6.4.5 TRB Completion Codes\r
//\r
#define TRB_COMPLETION_INVALID                0\r
#define TRB_COMPLETION_SUCCESS                1\r
#define TRB_COMPLETION_DATA_BUFFER_ERROR      2\r
#define TRB_COMPLETION_BABBLE_ERROR           3\r
#define TRB_COMPLETION_USB_TRANSACTION_ERROR  4\r
#define TRB_COMPLETION_TRB_ERROR              5\r
#define TRB_COMPLETION_STALL_ERROR            6\r
#define TRB_COMPLETION_SHORT_PACKET           13\r
\r
//\r
// 6.4.6 TRB Types\r
//\r
#define TRB_TYPE_NORMAL                       1\r
#define TRB_TYPE_SETUP_STAGE                  2\r
#define TRB_TYPE_DATA_STAGE                   3\r
#define TRB_TYPE_STATUS_STAGE                 4\r
#define TRB_TYPE_ISOCH                        5\r
#define TRB_TYPE_LINK                         6\r
#define TRB_TYPE_EVENT_DATA                   7\r
#define TRB_TYPE_NO_OP                        8\r
#define TRB_TYPE_EN_SLOT                      9\r
#define TRB_TYPE_DIS_SLOT                     10\r
#define TRB_TYPE_ADDRESS_DEV                  11\r
#define TRB_TYPE_CON_ENDPOINT                 12\r
#define TRB_TYPE_EVALU_CONTXT                 13\r
#define TRB_TYPE_RESET_ENDPOINT               14\r
#define TRB_TYPE_STOP_ENDPOINT                15\r
#define TRB_TYPE_SET_TR_DEQUE                 16\r
#define TRB_TYPE_RESET_DEV                    17\r
#define TRB_TYPE_GET_PORT_BANW                21\r
#define TRB_TYPE_FORCE_HEADER                 22\r
#define TRB_TYPE_NO_OP_COMMAND                23\r
#define TRB_TYPE_TRANS_EVENT                  32\r
#define TRB_TYPE_COMMAND_COMPLT_EVENT         33\r
#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT     34\r
#define TRB_TYPE_HOST_CONTROLLER_EVENT        37\r
#define TRB_TYPE_DEVICE_NOTIFI_EVENT          38\r
#define TRB_TYPE_MFINDEX_WRAP_EVENT           39\r
\r
//\r
// Convert millisecond to microsecond.\r
//\r
#define XHC_1_MILLISECOND                     (1000)\r
#define XHC_POLL_DELAY                        (1000)\r
#define XHC_GENERIC_TIMEOUT                   (10 * 1000)\r
\r
#define EFI_USB_SPEED_FULL                    0x0000  ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
#define EFI_USB_SPEED_LOW                     0x0001  ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
#define EFI_USB_SPEED_HIGH                    0x0002  ///< 480 Mb/s, USB 2.0 EHCI HC.\r
#define EFI_USB_SPEED_SUPER                   0x0003  ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
\r
//\r
// Transfer types, used in URB to identify the transfer type\r
//\r
#define XHC_CTRL_TRANSFER                     0x01\r
#define XHC_BULK_TRANSFER                     0x02\r
#define XHC_INT_TRANSFER_SYNC                 0x04\r
#define XHC_INT_TRANSFER_ASYNC                0x08\r
#define XHC_INT_ONLY_TRANSFER_ASYNC           0x10\r
\r
//\r
// USB Transfer Results\r
//\r
#define EFI_USB_NOERROR             0x00\r
#define EFI_USB_ERR_NOTEXECUTE      0x01\r
#define EFI_USB_ERR_STALL           0x02\r
#define EFI_USB_ERR_BUFFER          0x04\r
#define EFI_USB_ERR_BABBLE          0x08\r
#define EFI_USB_ERR_NAK             0x10\r
#define EFI_USB_ERR_CRC             0x20\r
#define EFI_USB_ERR_TIMEOUT         0x40\r
#define EFI_USB_ERR_BITSTUFF        0x80\r
#define EFI_USB_ERR_SYSTEM          0x100\r
\r
#pragma pack(1)\r
\r
//\r
// 7.6.9 OUT/IN EP Context: 64 bytes\r
// 7.6.9.2 When used by the DbC it is always a 64 byte data structure\r
//\r
typedef struct _ENDPOINT_CONTEXT_64 {\r
  UINT32                  EPState:3;\r
  UINT32                  RsvdZ1:5;\r
  UINT32                  Mult:2;         // set to 0\r
  UINT32                  MaxPStreams:5;  // set to 0\r
  UINT32                  LSA:1;          // set to 0\r
  UINT32                  Interval:8;     // set to 0\r
  UINT32                  RsvdZ2:8;\r
\r
  UINT32                  RsvdZ3:1;\r
  UINT32                  CErr:2;\r
  UINT32                  EPType:3;\r
  UINT32                  RsvdZ4:1;\r
  UINT32                  HID:1;          // set to 0\r
  UINT32                  MaxBurstSize:8;\r
  UINT32                  MaxPacketSize:16;\r
\r
  UINT32                  PtrLo;\r
\r
  UINT32                  PtrHi;\r
\r
  UINT32                  AverageTRBLength:16;\r
  UINT32                  MaxESITPayload:16;  // set to 0\r
\r
  UINT32                  RsvdZ5;             // Reserved\r
  UINT32                  RsvdZ6;\r
  UINT32                  RsvdZ7;\r
\r
  UINT32                  RsvdZ8;\r
  UINT32                  RsvdZ9;\r
  UINT32                  RsvdZ10;\r
  UINT32                  RsvdZ11;\r
\r
  UINT32                  RsvdZ12;\r
  UINT32                  RsvdZ13;\r
  UINT32                  RsvdZ14;\r
  UINT32                  RsvdZ15;\r
} ENDPOINT_CONTEXT_64;\r
\r
//\r
// 6.4.1.1 Normal TRB: 16 bytes\r
// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
// Rings, and to define the Data stage information for Control Transfer Rings.\r
//\r
typedef struct _TRANSFER_TRB_NORMAL {\r
  UINT32                  TRBPtrLo;\r
\r
  UINT32                  TRBPtrHi;\r
\r
  UINT32                  Length:17;\r
  UINT32                  TDSize:5;\r
  UINT32                  IntTarget:10;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  ENT:1;\r
  UINT32                  ISP:1;\r
  UINT32                  NS:1;\r
  UINT32                  CH:1;\r
  UINT32                  IOC:1;\r
  UINT32                  IDT:1;\r
  UINT32                  RsvdZ1:2;\r
  UINT32                  BEI:1;\r
  UINT32                  Type:6;\r
  UINT32                  RsvdZ2:16;\r
} TRANSFER_TRB_NORMAL;\r
\r
//\r
// 6.4.2.1 Transfer Event TRB: 16 bytes\r
// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
// for more information on the use and operation of Transfer Events.\r
//\r
typedef struct _EVT_TRB_TRANSFER {\r
  UINT32                  TRBPtrLo;\r
\r
  UINT32                  TRBPtrHi;\r
\r
  UINT32                  Length:24;\r
  UINT32                  Completecode:8;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  RsvdZ1:1;\r
  UINT32                  ED:1;\r
  UINT32                  RsvdZ2:7;\r
  UINT32                  Type:6;\r
  UINT32                  EndpointId:5;\r
  UINT32                  RsvdZ3:3;\r
  UINT32                  SlotId:8;\r
} EVT_TRB_TRANSFER;\r
\r
//\r
// 6.4.4.1 Link TRB: 16 bytes\r
// A Link TRB provides support for non-contiguous TRB Rings.\r
//\r
typedef struct _LINK_TRB {\r
  UINT32                  PtrLo;\r
\r
  UINT32                  PtrHi;\r
\r
  UINT32                  RsvdZ1:22;\r
  UINT32                  InterTarget:10;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  TC:1;\r
  UINT32                  RsvdZ2:2;\r
  UINT32                  CH:1;\r
  UINT32                  IOC:1;\r
  UINT32                  RsvdZ3:4;\r
  UINT32                  Type:6;\r
  UINT32                  RsvdZ4:16;\r
} LINK_TRB;\r
\r
//\r
// TRB Template: 16 bytes\r
//\r
typedef struct _TRB_TEMPLATE {\r
  UINT32                    Parameter1;\r
\r
  UINT32                    Parameter2;\r
\r
  UINT32                    Status;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ1:9;\r
  UINT32                    Type:6;\r
  UINT32                    Control:16;\r
} TRB_TEMPLATE;\r
\r
//\r
// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes\r
//\r
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
  UINT32                  PtrLo;\r
  UINT32                  PtrHi;\r
  UINT32                  RingTrbSize:16;\r
  UINT32                  RsvdZ1:16;\r
  UINT32                  RsvdZ2;\r
} EVENT_RING_SEG_TABLE_ENTRY;\r
\r
//\r
// Size: 40 bytes\r
//\r
typedef struct _EVENT_RING {\r
  EFI_PHYSICAL_ADDRESS      ERSTBase;\r
  EFI_PHYSICAL_ADDRESS      EventRingSeg0;\r
  UINT32                    TrbNumber;\r
  EFI_PHYSICAL_ADDRESS      EventRingEnqueue;\r
  EFI_PHYSICAL_ADDRESS      EventRingDequeue;\r
  UINT32                    EventRingCCS;\r
} EVENT_RING;\r
\r
// Size: 32 bytes\r
typedef struct _TRANSFER_RING {\r
  EFI_PHYSICAL_ADDRESS      RingSeg0;\r
  UINT32                    TrbNumber;\r
  EFI_PHYSICAL_ADDRESS      RingEnqueue;\r
  EFI_PHYSICAL_ADDRESS      RingDequeue;\r
  UINT32                    RingPCS;\r
} TRANSFER_RING;\r
\r
//\r
// Size: 64 bytes\r
//\r
typedef struct _DBC_INFO_CONTEXT {\r
  UINT64        String0DescAddress;\r
  UINT64        ManufacturerStrDescAddress;\r
  UINT64        ProductStrDescAddress;\r
  UINT64        SerialNumberStrDescAddress;\r
  UINT64        String0Length:8;\r
  UINT64        ManufacturerStrLength:8;\r
  UINT64        ProductStrLength:8;\r
  UINT64        SerialNumberStrLength:8;\r
  UINT64        RsvdZ1:32;\r
  UINT64        RsvdZ2;\r
  UINT64        RsvdZ3;\r
  UINT64        RsvdZ4;\r
} DBC_INFO_CONTEXT;\r
\r
//\r
// Debug Capability Context Data Structure: 192 bytes\r
//\r
typedef struct _XHC_DC_CONTEXT {\r
  DBC_INFO_CONTEXT      DbcInfoContext;\r
  ENDPOINT_CONTEXT_64   EpOutContext;\r
  ENDPOINT_CONTEXT_64   EpInContext;\r
} XHC_DC_CONTEXT;\r
\r
//\r
// Size: 16 bytes\r
//\r
typedef union _TRB {\r
  TRB_TEMPLATE                TrbTemplate;\r
  TRANSFER_TRB_NORMAL         TrbNormal;\r
} TRB;\r
\r
///\r
/// USB data transfer direction\r
///\r
typedef enum {\r
  EfiUsbDataIn,\r
  EfiUsbDataOut,\r
  EfiUsbNoData\r
} EFI_USB_DATA_DIRECTION;\r
\r
//\r
// URB (Usb Request Block) contains information for all kinds of\r
// usb requests.\r
//\r
typedef struct _URB {\r
  //\r
  // Transfer data buffer\r
  //\r
  EFI_PHYSICAL_ADDRESS            Data;\r
  UINT32                          DataLen;\r
\r
  //\r
  // Execute result\r
  //\r
  UINT32                          Result;\r
  //\r
  // Completed data length\r
  //\r
  UINT32                          Completed;\r
  //\r
  // Tranfer Ring info\r
  //\r
  EFI_PHYSICAL_ADDRESS            Ring;\r
  EFI_PHYSICAL_ADDRESS            Trb;\r
  BOOLEAN                         Finished;\r
  EFI_USB_DATA_DIRECTION          Direction;\r
} URB;\r
\r
typedef struct _USB3_DEBUG_PORT_INSTANCE {\r
  UINT8                                   Initialized;\r
\r
  //\r
  // The flag indicates debug capability is supported\r
  //\r
  BOOLEAN                                 DebugSupport;\r
\r
  //\r
  // The flag indicates debug device is ready\r
  //\r
  BOOLEAN                                 Ready;\r
\r
  //\r
  // The flag indicates the instance is from HOB\r
  //\r
  BOOLEAN                                 FromHob;\r
\r
  //\r
  // Prevent notification being interrupted by debug timer\r
  //\r
  BOOLEAN                                 InNotify;\r
\r
  //\r
  // PciIo protocol event\r
  //\r
  EFI_PHYSICAL_ADDRESS                    PciIoEvent;\r
\r
  //\r
  // The flag indicates if USB 3.0 ports has been turn off/on power\r
  //\r
  BOOLEAN                                 ChangePortPower;\r
\r
  //\r
  // XHCI MMIO Base address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    XhciMmioBase;\r
\r
  //\r
  // XHCI OP RegisterBase address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    XhciOpRegister;\r
\r
  //\r
  // XHCI Debug Register Base Address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    DebugCapabilityBase;\r
\r
  //\r
  // XHCI Debug Capability offset\r
  //\r
  UINT64                                  DebugCapabilityOffset;\r
\r
  //\r
  // XHCI Debug Context Address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    DebugCapabilityContext;\r
\r
  //\r
  // Transfer Ring\r
  //\r
  TRANSFER_RING                           TransferRingOut;\r
  TRANSFER_RING                           TransferRingIn;\r
\r
  //\r
  // EventRing\r
  //\r
  EVENT_RING                              EventRing;\r
\r
  //\r
  // URB - Read\r
  //\r
  URB                                     UrbOut;\r
\r
  //\r
  // URB - Write\r
  //\r
  URB                                     UrbIn;\r
\r
  //\r
  // The available data length in the following data buffer.\r
  //\r
  UINT8                                   DataCount;\r
  //\r
  // The data buffer address for data read and poll.\r
  //\r
  EFI_PHYSICAL_ADDRESS                    Data;\r
} USB3_DEBUG_PORT_HANDLE;\r
\r
#pragma pack()\r
\r
/**\r
  Read XHCI debug register.\r
\r
 @param  Handle        Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadDebugReg (\r
  IN  USB3_DEBUG_PORT_HANDLE    *Handle,\r
  IN  UINT32                    Offset\r
  );\r
\r
/**\r
  Set one bit of the debug register while keeping other bits.\r
\r
  @param  Handle       Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetDebugRegBit (\r
  IN USB3_DEBUG_PORT_HANDLE  *Handle,\r
  IN UINT32                  Offset,\r
  IN UINT32                  Bit\r
  );\r
\r
/**\r
  Write the data to the debug register.\r
\r
  @param  Handle       Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteDebugReg (\r
  IN USB3_DEBUG_PORT_HANDLE     *Handle,\r
  IN UINT32                     Offset,\r
  IN UINT32                     Data\r
  );\r
\r
/**\r
  Verifies if the bit positions specified by a mask are set in a register.\r
\r
  @param[in, out] Register    UNITN register\r
  @param[in]      BitMask     32-bit mask\r
\r
  @return  BOOLEAN  - TRUE  if all bits specified by the mask are enabled.\r
                    - FALSE even if one of the bits specified by the mask\r
                            is not enabled.\r
**/\r
BOOLEAN\r
XhcIsBitSet(\r
  UINTN   Register,\r
  UINT32  BitMask\r
  );\r
\r
/**\r
  Sets bits as per the enabled bit positions in the mask.\r
\r
  @param[in, out] Register    UINTN register\r
  @param[in]      BitMask     32-bit mask\r
**/\r
VOID\r
XhcSetR32Bit(\r
  UINTN   Register,\r
  UINT32  BitMask\r
  );\r
\r
/**\r
  Clears bits as per the enabled bit positions in the mask.\r
\r
  @param[in, out] Register    UINTN register\r
  @param[in]      BitMask     32-bit mask\r
**/\r
VOID\r
XhcClearR32Bit(\r
  IN OUT  UINTN  Register,\r
  IN      UINT32 BitMask\r
  );\r
\r
/**\r
  Initialize USB3 debug port.\r
\r
  This method invokes various internal functions to facilitate\r
  detection and initialization of USB3 debug port.\r
\r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
USB3Initialize (\r
  VOID\r
  );\r
\r
/**\r
  Return command register value in XHCI controller.\r
\r
**/\r
UINT16\r
GetXhciPciCommand (\r
  VOID\r
  );\r
\r
/**\r
  Allocate aligned memory for XHC's usage.\r
\r
  @param  BufferSize      The size, in bytes, of the Buffer.\r
\r
  @return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
VOID*\r
AllocateAlignBuffer (\r
  IN UINTN                    BufferSize\r
  );\r
\r
/**\r
  The real function to initialize USB3 debug port.\r
\r
  This method invokes various internal functions to facilitate\r
  detection and initialization of USB3 debug port.\r
\r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
USB3InitializeReal (\r
  VOID\r
  );\r
\r
/**\r
  Submits bulk transfer to a bulk endpoint of a USB device.\r
\r
  @param  Handle                The instance of debug device.\r
  @param  Direction             The direction of data transfer.\r
  @param  Data                  Array of pointers to the buffers of data to transmit\r
                                from or receive into.\r
  @param  DataLength            The lenght of the data buffer.\r
  @param  Timeout               Indicates the maximum time, in millisecond, which\r
                                the transfer is allowed to complete.\r
\r
  @retval EFI_SUCCESS           The transfer was completed successfully.\r
  @retval EFI_OUT_OF_RESOURCES  The transfer failed due to lack of resource.\r
  @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
  @retval EFI_TIMEOUT           The transfer failed due to timeout.\r
  @retval EFI_DEVICE_ERROR      The transfer failed due to host controller error.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcDataTransfer (\r
  IN     USB3_DEBUG_PORT_HANDLE              *Handle,\r
  IN     EFI_USB_DATA_DIRECTION              Direction,\r
  IN OUT VOID                                *Data,\r
  IN OUT UINTN                               *DataLength,\r
  IN     UINTN                               Timeout\r
  );\r
\r
/**\r
  Initialize usb debug port hardware.\r
\r
  @param  Handle           Debug port handle.\r
\r
  @retval TRUE             The usb debug port hardware configuration is changed.\r
  @retval FALSE            The usb debug port hardware configuration is not changed.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
InitializeUsbDebugHardware (\r
  IN USB3_DEBUG_PORT_HANDLE *Handle\r
  );\r
\r
/**\r
  Return USB3 debug instance address pointer.\r
\r
**/\r
EFI_PHYSICAL_ADDRESS *\r
GetUsb3DebugPortInstanceAddrPtr (\r
  VOID\r
  );\r
\r
/**\r
  Return USB3 debug instance address.\r
\r
**/\r
USB3_DEBUG_PORT_HANDLE *\r
GetUsb3DebugPortInstance (\r
  VOID\r
  );\r
\r
#endif //__SERIAL_PORT_LIB_USB__\r
Commit	Line	Data
2cb6eabe EL	1	/** @file\r
	2	Debug Port Library implementation based on usb3 debug port.\r
	3	\r
f0c56276	4	Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
2cb6eabe EL	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php.\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__\r
	16	#define __USB3_DEBUG_PORT_LIB_INTERNAL__\r
	17	\r
	18	#include <Uefi.h>\r
	19	#include <Base.h>\r
	20	#include <IndustryStandard/Usb.h>\r
	21	#include <Library/IoLib.h>\r
	22	#include <IndustryStandard/Pci.h>\r
	23	#include <Library/PcdLib.h>\r
	24	#include <Library/UefiLib.h>\r
	25	#include <Library/UefiBootServicesTableLib.h>\r
	26	#include <Library/MemoryAllocationLib.h>\r
	27	#include <Library/DebugLib.h>\r
	28	#include <Library/BaseMemoryLib.h>\r
	29	#include <Library/BaseLib.h>\r
	30	#include <Library/TimerLib.h>\r
	31	#include <Library/DebugCommunicationLib.h>\r
	32	#include <Library/PciLib.h>\r
2cb6eabe EL	33	\r
	34	//\r
	35	// USB Debug GUID value\r
	36	//\r
	37	#define USB3_DBG_GUID \\r
	38	{ \\r
	39	0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \\r
	40	}\r
	41	\r
	42	//\r
	43	// The state machine of usb debug port\r
	44	//\r
	45	#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability\r
	46	#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability\r
	47	#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled\r
	48	#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled\r
75787f65	49	#define USB3DBG_UNINITIALIZED 255 // The XHCI debug device is uninitialized\r
2cb6eabe	50	\r
5d6507a1 EL	51	#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08\r
	52	\r
	53	//\r
	54	// MaxPacketSize for DbC Endpoint Descriptor IN and OUT\r
	55	//\r
	56	#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400\r
2cb6eabe EL	57	\r
	58	#define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525\r
	59	#define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A\r
	60	#define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF\r
	61	#define XHCI_DEBUG_DEVICE_REVISION 0x00\r
	62	\r
	63	#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
	64	#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
	65	\r
	66	#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A\r
	67	#define XHC_HCCPARAMS_OFFSET 0x10\r
	68	#define XHC_CAPABILITY_ID_MASK 0xFF\r
	69	#define XHC_NEXT_CAPABILITY_MASK 0xFF00\r
	70	\r
	71	#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1\r
	72	#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset\r
	73	#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset\r
	74	#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset\r
	75	\r
	76	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	77	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	78	\r
	79	#define XHC_USBSTS_HALT BIT0\r
	80	\r
2cb6eabe EL	81	//\r
	82	// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.\r
	83	//\r
	84	#define DATA_TRANSFER_WRITE_TIMEOUT 0\r
	85	#define DATA_TRANSFER_READ_TIMEOUT 50000\r
	86	#define DATA_TRANSFER_POLL_TIMEOUT 1000\r
08021523	87	#define XHC_DEBUG_PORT_1_MILLISECOND 1000\r
2cb6eabe EL	88	//\r
	89	// XHCI port power off/on delay\r
	90	//\r
	91	#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000\r
	92	\r
	93	//\r
	94	// USB debug device string descritpor (header size + unicode string length)\r
	95	//\r
	96	#define STRING0_DESC_LEN 4\r
	97	#define MANU_DESC_LEN 12\r
	98	#define PRODUCT_DESC_LEN 40\r
	99	#define SERIAL_DESC_LEN 4\r
	100	\r
	101	//\r
	102	// Debug Capability Register Offset\r
	103	//\r
	104	#define XHC_DC_DCID 0x0\r
	105	#define XHC_DC_DCDB 0x4\r
	106	#define XHC_DC_DCERSTSZ 0x8\r
	107	#define XHC_DC_DCERSTBA 0x10\r
	108	#define XHC_DC_DCERDP 0x18\r
	109	#define XHC_DC_DCCTRL 0x20\r
	110	#define XHC_DC_DCST 0x24\r
	111	#define XHC_DC_DCPORTSC 0x28\r
	112	#define XHC_DC_DCCP 0x30\r
	113	#define XHC_DC_DCDDI1 0x38\r
	114	#define XHC_DC_DCDDI2 0x3C\r
	115	\r
	116	#define TRB_TYPE_LINK 6\r
	117	\r
	118	#define ERST_NUMBER 0x01\r
	119	#define TR_RING_TRB_NUMBER 0x100\r
	120	#define EVENT_RING_TRB_NUMBER 0x200\r
	121	\r
	122	#define ED_BULK_OUT 2\r
	123	#define ED_BULK_IN 6\r
	124	\r
	125	#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
	126	#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
	127	#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
	128	\r
	129	//\r
	130	// Endpoint Type (EP Type).\r
	131	//\r
	132	#define ED_NOT_VALID 0\r
	133	#define ED_ISOCH_OUT 1\r
	134	#define ED_BULK_OUT 2\r
	135	#define ED_INTERRUPT_OUT 3\r
	136	#define ED_CONTROL_BIDIR 4\r
	137	#define ED_ISOCH_IN 5\r
	138	#define ED_BULK_IN 6\r
	139	#define ED_INTERRUPT_IN 7\r
	140	\r
	141	//\r
	142	// 6.4.5 TRB Completion Codes\r
	143	//\r
	144	#define TRB_COMPLETION_INVALID 0\r
	145	#define TRB_COMPLETION_SUCCESS 1\r
	146	#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
	147	#define TRB_COMPLETION_BABBLE_ERROR 3\r
	148	#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
	149	#define TRB_COMPLETION_TRB_ERROR 5\r
	150	#define TRB_COMPLETION_STALL_ERROR 6\r
	151	#define TRB_COMPLETION_SHORT_PACKET 13\r
152	\r
153	//\r
154	// 6.4.6 TRB Types\r
155	//\r
156	#define TRB_TYPE_NORMAL 1\r
157	#define TRB_TYPE_SETUP_STAGE 2\r
158	#define TRB_TYPE_DATA_STAGE 3\r
159	#define TRB_TYPE_STATUS_STAGE 4\r
160	#define TRB_TYPE_ISOCH 5\r
161	#define TRB_TYPE_LINK 6\r
162	#define TRB_TYPE_EVENT_DATA 7\r
163	#define TRB_TYPE_NO_OP 8\r
164	#define TRB_TYPE_EN_SLOT 9\r
165	#define TRB_TYPE_DIS_SLOT 10\r
166	#define TRB_TYPE_ADDRESS_DEV 11\r
167	#define TRB_TYPE_CON_ENDPOINT 12\r
168	#define TRB_TYPE_EVALU_CONTXT 13\r
169	#define TRB_TYPE_RESET_ENDPOINT 14\r
170	#define TRB_TYPE_STOP_ENDPOINT 15\r
171	#define TRB_TYPE_SET_TR_DEQUE 16\r
172	#define TRB_TYPE_RESET_DEV 17\r
173	#define TRB_TYPE_GET_PORT_BANW 21\r
174	#define TRB_TYPE_FORCE_HEADER 22\r
175	#define TRB_TYPE_NO_OP_COMMAND 23\r
176	#define TRB_TYPE_TRANS_EVENT 32\r
177	#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
178	#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
179	#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
180	#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
181	#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
182	\r
183	//\r
184	// Convert millisecond to microsecond.\r
185	//\r
186	#define XHC_1_MILLISECOND (1000)\r
187	#define XHC_POLL_DELAY (1000)\r
188	#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
189	\r
190	#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
191	#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
192	#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.\r
193	#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
194	\r
195	//\r
196	// Transfer types, used in URB to identify the transfer type\r
197	//\r
198	#define XHC_CTRL_TRANSFER 0x01\r
199	#define XHC_BULK_TRANSFER 0x02\r
200	#define XHC_INT_TRANSFER_SYNC 0x04\r
201	#define XHC_INT_TRANSFER_ASYNC 0x08\r
202	#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
203	\r
204	//\r
205	// USB Transfer Results\r
206	//\r
207	#define EFI_USB_NOERROR 0x00\r
208	#define EFI_USB_ERR_NOTEXECUTE 0x01\r
209	#define EFI_USB_ERR_STALL 0x02\r
210	#define EFI_USB_ERR_BUFFER 0x04\r
211	#define EFI_USB_ERR_BABBLE 0x08\r
212	#define EFI_USB_ERR_NAK 0x10\r
213	#define EFI_USB_ERR_CRC 0x20\r
214	#define EFI_USB_ERR_TIMEOUT 0x40\r
215	#define EFI_USB_ERR_BITSTUFF 0x80\r
216	#define EFI_USB_ERR_SYSTEM 0x100\r
217	\r
218	#pragma pack(1)\r
219	\r
220	//\r
221	// 7.6.9 OUT/IN EP Context: 64 bytes\r
222	// 7.6.9.2 When used by the DbC it is always a 64 byte data structure\r
223	//\r
224	typedef struct _ENDPOINT_CONTEXT_64 {\r
225	UINT32 EPState:3;\r
226	UINT32 RsvdZ1:5;\r
227	UINT32 Mult:2; // set to 0\r
228	UINT32 MaxPStreams:5; // set to 0\r
229	UINT32 LSA:1; // set to 0\r
230	UINT32 Interval:8; // set to 0\r
231	UINT32 RsvdZ2:8;\r
232	\r
233	UINT32 RsvdZ3:1;\r
234	UINT32 CErr:2;\r
235	UINT32 EPType:3;\r
236	UINT32 RsvdZ4:1;\r
237	UINT32 HID:1; // set to 0\r
238	UINT32 MaxBurstSize:8;\r
239	UINT32 MaxPacketSize:16;\r
240	\r
241	UINT32 PtrLo;\r
242	\r
243	UINT32 PtrHi;\r
244	\r
245	UINT32 AverageTRBLength:16;\r
246	UINT32 MaxESITPayload:16; // set to 0\r
247	\r
248	UINT32 RsvdZ5; // Reserved\r
249	UINT32 RsvdZ6;\r
250	UINT32 RsvdZ7;\r
77695f4d	251	\r
2cb6eabe EL	252	UINT32 RsvdZ8;\r
	253	UINT32 RsvdZ9;\r
	254	UINT32 RsvdZ10;\r
	255	UINT32 RsvdZ11;\r
77695f4d	256	\r
2cb6eabe EL	257	UINT32 RsvdZ12;\r
	258	UINT32 RsvdZ13;\r
	259	UINT32 RsvdZ14;\r
	260	UINT32 RsvdZ15;\r
	261	} ENDPOINT_CONTEXT_64;\r
	262	\r
	263	//\r
	264	// 6.4.1.1 Normal TRB: 16 bytes\r
	265	// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
	266	// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
	267	// Rings, and to define the Data stage information for Control Transfer Rings.\r
	268	//\r
	269	typedef struct _TRANSFER_TRB_NORMAL {\r
	270	UINT32 TRBPtrLo;\r
	271	\r
	272	UINT32 TRBPtrHi;\r
	273	\r
	274	UINT32 Length:17;\r
	275	UINT32 TDSize:5;\r
	276	UINT32 IntTarget:10;\r
	277	\r
	278	UINT32 CycleBit:1;\r
	279	UINT32 ENT:1;\r
	280	UINT32 ISP:1;\r
	281	UINT32 NS:1;\r
	282	UINT32 CH:1;\r
	283	UINT32 IOC:1;\r
	284	UINT32 IDT:1;\r
	285	UINT32 RsvdZ1:2;\r
	286	UINT32 BEI:1;\r
	287	UINT32 Type:6;\r
	288	UINT32 RsvdZ2:16;\r
	289	} TRANSFER_TRB_NORMAL;\r
	290	\r
	291	//\r
	292	// 6.4.2.1 Transfer Event TRB: 16 bytes\r
	293	// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
	294	// for more information on the use and operation of Transfer Events.\r
	295	//\r
	296	typedef struct _EVT_TRB_TRANSFER {\r
	297	UINT32 TRBPtrLo;\r
	298	\r
	299	UINT32 TRBPtrHi;\r
	300	\r
	301	UINT32 Length:24;\r
	302	UINT32 Completecode:8;\r
	303	\r
	304	UINT32 CycleBit:1;\r
	305	UINT32 RsvdZ1:1;\r
	306	UINT32 ED:1;\r
	307	UINT32 RsvdZ2:7;\r
	308	UINT32 Type:6;\r
	309	UINT32 EndpointId:5;\r
	310	UINT32 RsvdZ3:3;\r
	311	UINT32 SlotId:8;\r
	312	} EVT_TRB_TRANSFER;\r
	313	\r
	314	//\r
	315	// 6.4.4.1 Link TRB: 16 bytes\r
	316	// A Link TRB provides support for non-contiguous TRB Rings.\r
	317	//\r
	318	typedef struct _LINK_TRB {\r
	319	UINT32 PtrLo;\r
	320	\r
321	UINT32 PtrHi;\r
322	\r
323	UINT32 RsvdZ1:22;\r
324	UINT32 InterTarget:10;\r
325	\r
326	UINT32 CycleBit:1;\r
327	UINT32 TC:1;\r
328	UINT32 RsvdZ2:2;\r
329	UINT32 CH:1;\r
330	UINT32 IOC:1;\r
331	UINT32 RsvdZ3:4;\r
332	UINT32 Type:6;\r
333	UINT32 RsvdZ4:16;\r
334	} LINK_TRB;\r
335	\r
336	//\r
337	// TRB Template: 16 bytes\r
338	//\r
339	typedef struct _TRB_TEMPLATE {\r
340	UINT32 Parameter1;\r
341	\r
342	UINT32 Parameter2;\r
343	\r
344	UINT32 Status;\r
345	\r
346	UINT32 CycleBit:1;\r
347	UINT32 RsvdZ1:9;\r
348	UINT32 Type:6;\r
349	UINT32 Control:16;\r
350	} TRB_TEMPLATE;\r
351	\r
352	//\r
353	// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes\r
354	//\r
355	typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
356	UINT32 PtrLo;\r
357	UINT32 PtrHi;\r
358	UINT32 RingTrbSize:16;\r
359	UINT32 RsvdZ1:16;\r
360	UINT32 RsvdZ2;\r
361	} EVENT_RING_SEG_TABLE_ENTRY;\r
362	\r
363	//\r
364	// Size: 40 bytes\r
365	//\r
366	typedef struct _EVENT_RING {\r
367	EFI_PHYSICAL_ADDRESS ERSTBase;\r
368	EFI_PHYSICAL_ADDRESS EventRingSeg0;\r
369	UINT32 TrbNumber;\r
370	EFI_PHYSICAL_ADDRESS EventRingEnqueue;\r
371	EFI_PHYSICAL_ADDRESS EventRingDequeue;\r
372	UINT32 EventRingCCS;\r
373	} EVENT_RING;\r
374	\r
375	// Size: 32 bytes\r
376	typedef struct _TRANSFER_RING {\r
377	EFI_PHYSICAL_ADDRESS RingSeg0;\r
378	UINT32 TrbNumber;\r
379	EFI_PHYSICAL_ADDRESS RingEnqueue;\r
380	EFI_PHYSICAL_ADDRESS RingDequeue;\r
381	UINT32 RingPCS;\r
382	} TRANSFER_RING;\r
383	\r
384	//\r
385	// Size: 64 bytes\r
386	//\r
387	typedef struct _DBC_INFO_CONTEXT {\r
388	UINT64 String0DescAddress;\r
389	UINT64 ManufacturerStrDescAddress;\r
390	UINT64 ProductStrDescAddress;\r
391	UINT64 SerialNumberStrDescAddress;\r
392	UINT64 String0Length:8;\r
393	UINT64 ManufacturerStrLength:8;\r
394	UINT64 ProductStrLength:8;\r
395	UINT64 SerialNumberStrLength:8;\r
396	UINT64 RsvdZ1:32;\r
397	UINT64 RsvdZ2;\r
398	UINT64 RsvdZ3;\r
77695f4d	399	UINT64 RsvdZ4;\r
2cb6eabe EL	400	} DBC_INFO_CONTEXT;\r
	401	\r
	402	//\r
	403	// Debug Capability Context Data Structure: 192 bytes\r
	404	//\r
	405	typedef struct _XHC_DC_CONTEXT {\r
	406	DBC_INFO_CONTEXT DbcInfoContext;\r
	407	ENDPOINT_CONTEXT_64 EpOutContext;\r
	408	ENDPOINT_CONTEXT_64 EpInContext;\r
	409	} XHC_DC_CONTEXT;\r
	410	\r
	411	//\r
	412	// Size: 16 bytes\r
	413	//\r
	414	typedef union _TRB {\r
	415	TRB_TEMPLATE TrbTemplate;\r
	416	TRANSFER_TRB_NORMAL TrbNormal;\r
	417	} TRB;\r
	418	\r
	419	///\r
	420	/// USB data transfer direction\r
	421	///\r
	422	typedef enum {\r
	423	EfiUsbDataIn,\r
	424	EfiUsbDataOut,\r
	425	EfiUsbNoData\r
	426	} EFI_USB_DATA_DIRECTION;\r
	427	\r
	428	//\r
	429	// URB (Usb Request Block) contains information for all kinds of\r
	430	// usb requests.\r
	431	//\r
	432	typedef struct _URB {\r
	433	//\r
	434	// Transfer data buffer\r
	435	//\r
	436	EFI_PHYSICAL_ADDRESS Data;\r
	437	UINT32 DataLen;\r
	438	\r
	439	//\r
	440	// Execute result\r
	441	//\r
	442	UINT32 Result;\r
	443	//\r
	444	// Completed data length\r
	445	//\r
	446	UINT32 Completed;\r
	447	//\r
	448	// Tranfer Ring info\r
	449	//\r
	450	EFI_PHYSICAL_ADDRESS Ring;\r
	451	EFI_PHYSICAL_ADDRESS Trb;\r
	452	BOOLEAN Finished;\r
	453	EFI_USB_DATA_DIRECTION Direction;\r
	454	} URB;\r
	455	\r
	456	typedef struct _USB3_DEBUG_PORT_INSTANCE {\r
	457	UINT8 Initialized;\r
	458	\r
	459	//\r
75787f65	460	// The flag indicates debug capability is supported\r
2cb6eabe EL	461	//\r
2cb6eabe EL	462	BOOLEAN DebugSupport;\r
77695f4d	463	\r
2cb6eabe EL	464	//\r
	465	// The flag indicates debug device is ready\r
	466	//\r
	467	BOOLEAN Ready;\r
	468	\r
75787f65 SZ	469	//\r
	470	// The flag indicates the instance is from HOB\r
	471	//\r
	472	BOOLEAN FromHob;\r
	473	\r
	474	//\r
	475	// Prevent notification being interrupted by debug timer\r
	476	//\r
	477	BOOLEAN InNotify;\r
	478	\r
	479	//\r
	480	// PciIo protocol event\r
	481	//\r
	482	EFI_PHYSICAL_ADDRESS PciIoEvent;\r
	483	\r
2cb6eabe EL	484	//\r
2cb6eabe EL	485	// The flag indicates if USB 3.0 ports has been turn off/on power\r
77695f4d	486	//\r
2cb6eabe EL	487	BOOLEAN ChangePortPower;\r
	488	\r
	489	//\r
	490	// XHCI MMIO Base address\r
	491	//\r
	492	EFI_PHYSICAL_ADDRESS XhciMmioBase;\r
	493	\r
	494	//\r
	495	// XHCI OP RegisterBase address\r
77695f4d	496	//\r
2cb6eabe	497	EFI_PHYSICAL_ADDRESS XhciOpRegister;\r
77695f4d	498	\r
2cb6eabe EL	499	//\r
	500	// XHCI Debug Register Base Address\r
	501	//\r
	502	EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
77695f4d	503	\r
2cb6eabe EL	504	//\r
	505	// XHCI Debug Capability offset\r
	506	//\r
77695f4d LG	507	UINT64 DebugCapabilityOffset;\r
77695f4d LG	508	\r
2cb6eabe EL	509	//\r
	510	// XHCI Debug Context Address\r
	511	//\r
	512	EFI_PHYSICAL_ADDRESS DebugCapabilityContext;\r
77695f4d	513	\r
2cb6eabe EL	514	//\r
	515	// Transfer Ring\r
	516	//\r
	517	TRANSFER_RING TransferRingOut;\r
	518	TRANSFER_RING TransferRingIn;\r
	519	\r
	520	//\r
	521	// EventRing\r
	522	//\r
	523	EVENT_RING EventRing;\r
77695f4d	524	\r
2cb6eabe EL	525	//\r
	526	// URB - Read\r
	527	//\r
	528	URB UrbOut;\r
	529	\r
	530	//\r
	531	// URB - Write\r
	532	//\r
	533	URB UrbIn;\r
	534	\r
	535	//\r
	536	// The available data length in the following data buffer.\r
	537	//\r
	538	UINT8 DataCount;\r
	539	//\r
5d6507a1	540	// The data buffer address for data read and poll.\r
2cb6eabe	541	//\r
5d6507a1	542	EFI_PHYSICAL_ADDRESS Data;\r
2cb6eabe EL	543	} USB3_DEBUG_PORT_HANDLE;\r
	544	\r
	545	#pragma pack()\r
	546	\r
	547	/**\r
	548	Read XHCI debug register.\r
	549	\r
	550	@param Handle Debug port handle.\r
	551	@param Offset The offset of the debug register.\r
	552	\r
	553	@return The register content read\r
	554	\r
	555	**/\r
	556	UINT32\r
	557	XhcReadDebugReg (\r
	558	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
f0c56276	559	IN UINT32 Offset\r
2cb6eabe EL	560	);\r
	561	\r
	562	/**\r
	563	Set one bit of the debug register while keeping other bits.\r
	564	\r
	565	@param Handle Debug port handle.\r
	566	@param Offset The offset of the debug register.\r
	567	@param Bit The bit mask of the register to set.\r
	568	\r
	569	**/\r
	570	VOID\r
	571	XhcSetDebugRegBit (\r
	572	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
f0c56276 SZ	573	IN UINT32 Offset,\r
f0c56276 SZ	574	IN UINT32 Bit\r
2cb6eabe	575	);\r
77695f4d	576	\r
2cb6eabe EL	577	/**\r
	578	Write the data to the debug register.\r
	579	\r
	580	@param Handle Debug port handle.\r
	581	@param Offset The offset of the debug register.\r
	582	@param Data The data to write.\r
	583	\r
77695f4d	584	**/\r
2cb6eabe EL	585	VOID\r
	586	XhcWriteDebugReg (\r
	587	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
	588	IN UINT32 Offset,\r
	589	IN UINT32 Data\r
	590	);\r
	591	\r
2cb6eabe EL	592	/**\r
	593	Verifies if the bit positions specified by a mask are set in a register.\r
	594	\r
	595	@param[in, out] Register UNITN register\r
	596	@param[in] BitMask 32-bit mask\r
	597	\r
	598	@return BOOLEAN - TRUE if all bits specified by the mask are enabled.\r
77695f4d	599	- FALSE even if one of the bits specified by the mask\r
2cb6eabe EL	600	is not enabled.\r
	601	**/\r
	602	BOOLEAN\r
	603	XhcIsBitSet(\r
77695f4d	604	UINTN Register,\r
2cb6eabe EL	605	UINT32 BitMask\r
	606	);\r
	607	\r
	608	/**\r
	609	Sets bits as per the enabled bit positions in the mask.\r
	610	\r
	611	@param[in, out] Register UINTN register\r
	612	@param[in] BitMask 32-bit mask\r
	613	**/\r
	614	VOID\r
	615	XhcSetR32Bit(\r
77695f4d	616	UINTN Register,\r
2cb6eabe EL	617	UINT32 BitMask\r
	618	);\r
	619	\r
	620	/**\r
	621	Clears bits as per the enabled bit positions in the mask.\r
	622	\r
	623	@param[in, out] Register UINTN register\r
	624	@param[in] BitMask 32-bit mask\r
	625	**/\r
	626	VOID\r
	627	XhcClearR32Bit(\r
77695f4d	628	IN OUT UINTN Register,\r
2cb6eabe EL	629	IN UINT32 BitMask\r
	630	);\r
	631	\r
	632	/**\r
	633	Initialize USB3 debug port.\r
77695f4d	634	\r
2cb6eabe EL	635	This method invokes various internal functions to facilitate\r
	636	detection and initialization of USB3 debug port.\r
	637	\r
	638	@retval RETURN_SUCCESS The serial device was initialized.\r
	639	**/\r
	640	RETURN_STATUS\r
	641	EFIAPI\r
	642	USB3Initialize (\r
	643	VOID\r
	644	);\r
	645	\r
	646	/**\r
	647	Return command register value in XHCI controller.\r
	648	\r
	649	**/\r
	650	UINT16\r
	651	GetXhciPciCommand (\r
	652	VOID\r
	653	);\r
	654	\r
	655	/**\r
	656	Allocate aligned memory for XHC's usage.\r
	657	\r
	658	@param BufferSize The size, in bytes, of the Buffer.\r
77695f4d	659	\r
2cb6eabe EL	660	@return A pointer to the allocated buffer or NULL if allocation fails.\r
	661	\r
	662	**/\r
	663	VOID*\r
	664	AllocateAlignBuffer (\r
	665	IN UINTN BufferSize\r
	666	);\r
	667	\r
	668	/**\r
	669	The real function to initialize USB3 debug port.\r
77695f4d	670	\r
2cb6eabe EL	671	This method invokes various internal functions to facilitate\r
	672	detection and initialization of USB3 debug port.\r
	673	\r
	674	@retval RETURN_SUCCESS The serial device was initialized.\r
	675	**/\r
	676	RETURN_STATUS\r
	677	EFIAPI\r
	678	USB3InitializeReal (\r
	679	VOID\r
	680	);\r
	681	\r
	682	/**\r
	683	Submits bulk transfer to a bulk endpoint of a USB device.\r
	684	\r
	685	@param Handle The instance of debug device.\r
	686	@param Direction The direction of data transfer.\r
	687	@param Data Array of pointers to the buffers of data to transmit\r
	688	from or receive into.\r
	689	@param DataLength The lenght of the data buffer.\r
	690	@param Timeout Indicates the maximum time, in millisecond, which\r
	691	the transfer is allowed to complete.\r
	692	\r
	693	@retval EFI_SUCCESS The transfer was completed successfully.\r
	694	@retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r
	695	@retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
	696	@retval EFI_TIMEOUT The transfer failed due to timeout.\r
	697	@retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r
	698	\r
	699	**/\r
	700	EFI_STATUS\r
	701	EFIAPI\r
	702	XhcDataTransfer (\r
	703	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
	704	IN EFI_USB_DATA_DIRECTION Direction,\r
	705	IN OUT VOID *Data,\r
	706	IN OUT UINTN *DataLength,\r
	707	IN UINTN Timeout\r
	708	);\r
	709	\r
75787f65 SZ	710	/**\r
	711	Initialize usb debug port hardware.\r
	712	\r
	713	@param Handle Debug port handle.\r
	714	\r
	715	@retval TRUE The usb debug port hardware configuration is changed.\r
	716	@retval FALSE The usb debug port hardware configuration is not changed.\r
	717	\r
	718	**/\r
	719	RETURN_STATUS\r
	720	EFIAPI\r
	721	InitializeUsbDebugHardware (\r
	722	IN USB3_DEBUG_PORT_HANDLE *Handle\r
	723	);\r
	724	\r
	725	/**\r
	726	Return USB3 debug instance address pointer.\r
	727	\r
77695f4d	728	**/\r
75787f65 SZ	729	EFI_PHYSICAL_ADDRESS *\r
	730	GetUsb3DebugPortInstanceAddrPtr (\r
	731	VOID\r
	732	);\r
	733	\r
	734	/**\r
	735	Return USB3 debug instance address.\r
	736	\r
77695f4d	737	**/\r
75787f65 SZ	738	USB3_DEBUG_PORT_HANDLE *\r
	739	GetUsb3DebugPortInstance (\r
	740	VOID\r
	741	);\r
	742	\r
	743	#endif //__SERIAL_PORT_LIB_USB__\r