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UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.
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04c980a6
MK		 1/** @file\r
2 Architectural MSR Definitions.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
ba1a2d11 9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
04c980a6
MK		 10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
ba1a2d11
ED		 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
20 May 2018, Volume 4: Model-Specific-Registers (MSR)\r
831d287a 21\r
04c980a6
MK		 22**/\r
23\r
24#ifndef __ARCHITECTURAL_MSR_H__\r
25#define __ARCHITECTURAL_MSR_H__\r
26\r
27/**\r
ba1a2d11 28 See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r
04c980a6
MK		 29\r
30 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r
31 @param EAX Lower 32-bits of MSR value.\r
32 @param EDX Upper 32-bits of MSR value.\r
33\r
34 <b>Example usage</b>\r
35 @code\r
36 UINT64 Msr;\r
37\r
38 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r
39 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r
40 @endcode\r
7de98828 41 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r
04c980a6
MK		 42**/\r
43#define MSR_IA32_P5_MC_ADDR 0x00000000\r
44\r
45\r
46/**\r
ba1a2d11 47 See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
04c980a6
MK		 48\r
49 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r
50 @param EAX Lower 32-bits of MSR value.\r
51 @param EDX Upper 32-bits of MSR value.\r
52\r
53 <b>Example usage</b>\r
54 @code\r
55 UINT64 Msr;\r
56\r
57 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r
58 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r
59 @endcode\r
7de98828 60 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r
04c980a6
MK		 61**/\r
62#define MSR_IA32_P5_MC_TYPE 0x00000001\r
63\r
64\r
65/**\r
66 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r
67 at Display Family / Display Model 0F_03H.\r
68\r
69 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r
70 @param EAX Lower 32-bits of MSR value.\r
71 @param EDX Upper 32-bits of MSR value.\r
72\r
73 <b>Example usage</b>\r
74 @code\r
75 UINT64 Msr;\r
76\r
77 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r
78 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r
79 @endcode\r
7de98828 80 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r
04c980a6
MK		 81**/\r
82#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r
83\r
84\r
85/**\r
ba1a2d11 86 See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /\r
04c980a6
MK		 87 Display Model 05_01H.\r
88\r
89 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r
90 @param EAX Lower 32-bits of MSR value.\r
91 @param EDX Upper 32-bits of MSR value.\r
92\r
93 <b>Example usage</b>\r
94 @code\r
95 UINT64 Msr;\r
96\r
97 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r
98 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r
99 @endcode\r
7de98828 100 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r
04c980a6
MK		 101**/\r
102#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r
103\r
104\r
105/**\r
106 Platform ID (RO) The operating system can use this MSR to determine "slot"\r
107 information for the processor and the proper microcode update to load.\r
108 Introduced at Display Family / Display Model 06_01H.\r
109\r
110 @param ECX MSR_IA32_PLATFORM_ID (0x00000017)\r
111 @param EAX Lower 32-bits of MSR value.\r
112 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r
113 @param EDX Upper 32-bits of MSR value.\r
114 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r
115\r
116 <b>Example usage</b>\r
117 @code\r
118 MSR_IA32_PLATFORM_ID_REGISTER Msr;\r
119\r
120 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
121 @endcode\r
7de98828 122 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
04c980a6
MK		 123**/\r
124#define MSR_IA32_PLATFORM_ID 0x00000017\r
125\r
126/**\r
127 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r
128**/\r
129typedef union {\r
130 ///\r
131 /// Individual bit fields\r
132 ///\r
133 struct {\r
134 UINT32 Reserved1:32;\r
135 UINT32 Reserved2:18;\r
136 ///\r
137 /// [Bits 52:50] Platform Id (RO) Contains information concerning the\r
138 /// intended platform for the processor.\r
139 /// 52 51 50\r
140 /// -- -- --\r
141 /// 0 0 0 Processor Flag 0.\r
142 /// 0 0 1 Processor Flag 1\r
143 /// 0 1 0 Processor Flag 2\r
144 /// 0 1 1 Processor Flag 3\r
145 /// 1 0 0 Processor Flag 4\r
146 /// 1 0 1 Processor Flag 5\r
147 /// 1 1 0 Processor Flag 6\r
148 /// 1 1 1 Processor Flag 7\r
149 ///\r
150 UINT32 PlatformId:3;\r
151 UINT32 Reserved3:11;\r
152 } Bits;\r
153 ///\r
154 /// All bit fields as a 64-bit value\r
155 ///\r
156 UINT64 Uint64;\r
157} MSR_IA32_PLATFORM_ID_REGISTER;\r
158\r
159\r
160/**\r
161 06_01H.\r
162\r
163 @param ECX MSR_IA32_APIC_BASE (0x0000001B)\r
164 @param EAX Lower 32-bits of MSR value.\r
165 Described by the type MSR_IA32_APIC_BASE_REGISTER.\r
166 @param EDX Upper 32-bits of MSR value.\r
167 Described by the type MSR_IA32_APIC_BASE_REGISTER.\r
168\r
169 <b>Example usage</b>\r
170 @code\r
171 MSR_IA32_APIC_BASE_REGISTER Msr;\r
172\r
173 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
174 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r
175 @endcode\r
7de98828 176 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r
04c980a6
MK		 177**/\r
178#define MSR_IA32_APIC_BASE 0x0000001B\r
179\r
180/**\r
181 MSR information returned for MSR index #MSR_IA32_APIC_BASE\r
182**/\r
183typedef union {\r
184 ///\r
185 /// Individual bit fields\r
186 ///\r
187 struct {\r
188 UINT32 Reserved1:8;\r
189 ///\r
190 /// [Bit 8] BSP flag (R/W).\r
191 ///\r
192 UINT32 BSP:1;\r
193 UINT32 Reserved2:1;\r
194 ///\r
195 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r
196 /// Model 06_1AH.\r
197 ///\r
198 UINT32 EXTD:1;\r
199 ///\r
200 /// [Bit 11] APIC Global Enable (R/W).\r
201 ///\r
202 UINT32 EN:1;\r
203 ///\r
204 /// [Bits 31:12] APIC Base (R/W).\r
205 ///\r
206 UINT32 ApicBase:20;\r
207 ///\r
208 /// [Bits 63:32] APIC Base (R/W).\r
209 ///\r
210 UINT32 ApicBaseHi:32;\r
211 } Bits;\r
212 ///\r
213 /// All bit fields as a 64-bit value\r
214 ///\r
215 UINT64 Uint64;\r
216} MSR_IA32_APIC_BASE_REGISTER;\r
217\r
218\r
219/**\r
220 Control Features in Intel 64 Processor (R/W). If any one enumeration\r
221 condition for defined bit field holds.\r
222\r
223 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)\r
224 @param EAX Lower 32-bits of MSR value.\r
225 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r
226 @param EDX Upper 32-bits of MSR value.\r
227 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r
228\r
229 <b>Example usage</b>\r
230 @code\r
231 MSR_IA32_FEATURE_CONTROL_REGISTER Msr;\r
232\r
233 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r
234 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r
235 @endcode\r
7de98828 236 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
04c980a6
MK		 237**/\r
238#define MSR_IA32_FEATURE_CONTROL 0x0000003A\r
239\r
240/**\r
241 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r
242**/\r
243typedef union {\r
244 ///\r
245 /// Individual bit fields\r
246 ///\r
247 struct {\r
248 ///\r
249 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r
250 /// being written, writes to this bit will result in GP(0). Note: Once the\r
251 /// Lock bit is set, the contents of this register cannot be modified.\r
252 /// Therefore the lock bit must be set after configuring support for Intel\r
253 /// Virtualization Technology and prior to transferring control to an\r
254 /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r
255 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r
256 /// is not deasserted. If any one enumeration condition for defined bit\r
257 /// field position greater than bit 0 holds.\r
258 ///\r
259 UINT32 Lock:1;\r
260 ///\r
261 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r
262 /// system executive to use VMX in conjunction with SMX to support\r
263 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r
264 /// when the CPUID function 1 returns VMX feature flag and SMX feature\r
265 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r
266 /// CPUID.01H:ECX[6] = 1.\r
267 ///\r
268 UINT32 EnableVmxInsideSmx:1;\r
269 ///\r
270 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r
271 /// for system executive that do not require SMX. BIOS must set this bit\r
272 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r
273 /// 5). If CPUID.01H:ECX[5] = 1.\r
274 ///\r
275 UINT32 EnableVmxOutsideSmx:1;\r
276 UINT32 Reserved1:5;\r
277 ///\r
278 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r
279 /// in the field represents an enable control for a corresponding SENTER\r
280 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r
281 /// CPUID.01H:ECX[6] = 1.\r
282 ///\r
283 UINT32 SenterLocalFunctionEnables:7;\r
284 ///\r
285 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r
286 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r
287 /// 6] is set. If CPUID.01H:ECX[6] = 1.\r
288 ///\r
289 UINT32 SenterGlobalEnable:1;\r
0f16be6d
HW		 290 UINT32 Reserved2:1;\r
291 ///\r
292 /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
293 /// enable runtime reconfiguration of SGX Launch Control via\r
294 /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
295 ///\r
296 UINT32 SgxLaunchControlEnable:1;\r
04c980a6
MK		 297 ///\r
298 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
0f16be6d 299 /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
04c980a6
MK		 300 ///\r
301 UINT32 SgxEnable:1;\r
302 UINT32 Reserved3:1;\r
303 ///\r
304 /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r
305 /// MSRs associated with LMCE to configure delivery of some machine check\r
306 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r
307 ///\r
308 UINT32 LmceOn:1;\r
309 UINT32 Reserved4:11;\r
310 UINT32 Reserved5:32;\r
311 } Bits;\r
312 ///\r
313 /// All bit fields as a 32-bit value\r
314 ///\r
315 UINT32 Uint32;\r
316 ///\r
317 /// All bit fields as a 64-bit value\r
318 ///\r
319 UINT64 Uint64;\r
320} MSR_IA32_FEATURE_CONTROL_REGISTER;\r
321\r
322\r
323/**\r
324 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r
325 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r
326 a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r
327 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r
328 not affect the internal invariant TSC hardware.\r
329\r
330 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)\r
331 @param EAX Lower 32-bits of MSR value.\r
332 @param EDX Upper 32-bits of MSR value.\r
333\r
334 <b>Example usage</b>\r
335 @code\r
336 UINT64 Msr;\r
337\r
338 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r
339 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r
340 @endcode\r
7de98828 341 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r
04c980a6
MK		 342**/\r
343#define MSR_IA32_TSC_ADJUST 0x0000003B\r
344\r
345\r
346/**\r
347 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r
348 microcode update to be loaded into the processor. See Section 9.11.6,\r
349 "Microcode Update Loader." A processor may prevent writing to this MSR when\r
350 loading guest states on VM entries or saving guest states on VM exits.\r
351 Introduced at Display Family / Display Model 06_01H.\r
352\r
353 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r
354 @param EAX Lower 32-bits of MSR value.\r
355 @param EDX Upper 32-bits of MSR value.\r
356\r
357 <b>Example usage</b>\r
358 @code\r
359 UINT64 Msr;\r
360\r
361 Msr = 0;\r
362 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r
363 @endcode\r
7de98828 364 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r
04c980a6
MK		 365**/\r
366#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r
367\r
368\r
369/**\r
370 BIOS Update Signature (RO) Returns the microcode update signature following\r
371 the execution of CPUID.01H. A processor may prevent writing to this MSR when\r
372 loading guest states on VM entries or saving guest states on VM exits.\r
373 Introduced at Display Family / Display Model 06_01H.\r
374\r
375 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r
376 @param EAX Lower 32-bits of MSR value.\r
377 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r
378 @param EDX Upper 32-bits of MSR value.\r
379 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r
380\r
381 <b>Example usage</b>\r
382 @code\r
383 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;\r
384\r
385 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r
386 @endcode\r
7de98828 387 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r
04c980a6
MK		 388**/\r
389#define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r
390\r
391/**\r
392 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r
393**/\r
394typedef union {\r
395 ///\r
396 /// Individual bit fields\r
397 ///\r
398 struct {\r
399 UINT32 Reserved:32;\r
400 ///\r
401 /// [Bits 63:32] Microcode update signature. This field contains the\r
402 /// signature of the currently loaded microcode update when read following\r
403 /// the execution of the CPUID instruction, function 1. It is required\r
404 /// that this register field be pre-loaded with zero prior to executing\r
405 /// the CPUID, function 1. If the field remains equal to zero, then there\r
406 /// is no microcode update loaded. Another nonzero value will be the\r
407 /// signature.\r
408 ///\r
409 UINT32 MicrocodeUpdateSignature:32;\r
410 } Bits;\r
411 ///\r
412 /// All bit fields as a 64-bit value\r
413 ///\r
414 UINT64 Uint64;\r
415} MSR_IA32_BIOS_SIGN_ID_REGISTER;\r
416\r
417\r
0f16be6d
HW		 418/**\r
419 IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
420 SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
421 default value is the digest of Intel's signing key. Read permitted If\r
422 CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r
423 EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r
424\r
425 @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r
426 @param EAX Lower 32-bits of MSR value.\r
427 @param EDX Upper 32-bits of MSR value.\r
428\r
429 <b>Example usage</b>\r
430 @code\r
431 UINT64 Msr;\r
432\r
433 Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r
434 AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r
435 @endcode\r
436 @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r
437 MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r
438 MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r
439 MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
440 @{\r
441**/\r
442#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
443#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
444#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
445#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
446/// @}\r
447\r
448\r
04c980a6 449/**\r
831d287a 450 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
04c980a6
MK		 451 1.\r
452\r
453 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r
454 @param EAX Lower 32-bits of MSR value.\r
455 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
456 @param EDX Upper 32-bits of MSR value.\r
457 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
458\r
459 <b>Example usage</b>\r
460 @code\r
461 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;\r
462\r
463 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r
464 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r
465 @endcode\r
7de98828 466 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r
04c980a6
MK		 467**/\r
468#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r
469\r
470/**\r
471 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r
472**/\r
473typedef union {\r
474 ///\r
475 /// Individual bit fields\r
476 ///\r
477 struct {\r
478 ///\r
479 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this\r
480 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r
481 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r
482 /// if the bit is 0. This bit is cleared when the logical processor is\r
483 /// reset.\r
484 ///\r
485 UINT32 Valid:1;\r
486 UINT32 Reserved1:1;\r
487 ///\r
ba1a2d11
ED		 488 /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If\r
489 /// IA32_VMX_MISC[28].\r
04c980a6
MK		 490 ///\r
491 UINT32 BlockSmi:1;\r
492 UINT32 Reserved2:9;\r
493 ///\r
494 /// [Bits 31:12] MSEG Base (R/W).\r
495 ///\r
496 UINT32 MsegBase:20;\r
497 UINT32 Reserved3:32;\r
498 } Bits;\r
499 ///\r
500 /// All bit fields as a 32-bit value\r
501 ///\r
502 UINT32 Uint32;\r
503 ///\r
504 /// All bit fields as a 64-bit value\r
505 ///\r
506 UINT64 Uint64;\r
507} MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r
508\r
831d287a
MK		 509/**\r
510 MSEG header that is located at the physical address specified by the MsegBase\r
511 field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r
512**/\r
513typedef struct {\r
a03bb3d2
MK		 514 ///\r
515 /// Different processors may use different MSEG revision identifiers. These\r
516 /// identifiers enable software to avoid using an MSEG header formatted for\r
517 /// one processor on a processor that uses a different format. Software can\r
518 /// discover the MSEG revision identifier that a processor uses by reading\r
519 /// the VMX capability MSR IA32_VMX_MISC.\r
520 //\r
831d287a 521 UINT32 MsegHeaderRevision;\r
a03bb3d2
MK		 522 ///\r
523 /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
524 /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
525 /// processor will be in IA-32e mode after the STM is activated.\r
526 ///\r
831d287a
MK		 527 UINT32 MonitorFeatures;\r
528 UINT32 GdtrLimit;\r
529 UINT32 GdtrBaseOffset;\r
530 UINT32 CsSelector;\r
531 UINT32 EipOffset;\r
532 UINT32 EspOffset;\r
533 UINT32 Cr3Offset;\r
a03bb3d2
MK		 534 ///\r
535 /// Pad header so total size is 2KB\r
536 ///\r
831d287a
MK		 537 UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
538} MSEG_HEADER;\r
539\r
a03bb3d2
MK		 540///\r
541/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
542///\r
543#define STM_FEATURES_IA32E 0x1\r
544///\r
545/// @}\r
546///\r
04c980a6
MK		 547\r
548/**\r
549 Base address of the logical processor's SMRAM image (RO, SMM only). If\r
550 IA32_VMX_MISC[15].\r
551\r
552 @param ECX MSR_IA32_SMBASE (0x0000009E)\r
553 @param EAX Lower 32-bits of MSR value.\r
554 @param EDX Upper 32-bits of MSR value.\r
555\r
556 <b>Example usage</b>\r
557 @code\r
558 UINT64 Msr;\r
559\r
560 Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r
561 @endcode\r
7de98828 562 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r
04c980a6
MK		 563**/\r
564#define MSR_IA32_SMBASE 0x0000009E\r
565\r
566\r
567/**\r
568 General Performance Counters (R/W).\r
569 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r
570\r
571 @param ECX MSR_IA32_PMCn\r
572 @param EAX Lower 32-bits of MSR value.\r
573 @param EDX Upper 32-bits of MSR value.\r
574\r
575 <b>Example usage</b>\r
576 @code\r
577 UINT64 Msr;\r
578\r
579 Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r
580 AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r
581 @endcode\r
7de98828
JF		 582 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r
583 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r
584 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r
585 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r
586 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r
587 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r
588 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r
589 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r
04c980a6
MK		 590 @{\r
591**/\r
592#define MSR_IA32_PMC0 0x000000C1\r
593#define MSR_IA32_PMC1 0x000000C2\r
594#define MSR_IA32_PMC2 0x000000C3\r
595#define MSR_IA32_PMC3 0x000000C4\r
596#define MSR_IA32_PMC4 0x000000C5\r
597#define MSR_IA32_PMC5 0x000000C6\r
598#define MSR_IA32_PMC6 0x000000C7\r
599#define MSR_IA32_PMC7 0x000000C8\r
600/// @}\r
601\r
602\r
603/**\r
604 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r
605 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r
606 to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r
607 wrap-around of IA32_APERF.\r
608\r
609 @param ECX MSR_IA32_MPERF (0x000000E7)\r
610 @param EAX Lower 32-bits of MSR value.\r
611 @param EDX Upper 32-bits of MSR value.\r
612\r
613 <b>Example usage</b>\r
614 @code\r
615 UINT64 Msr;\r
616\r
617 Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r
618 AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r
619 @endcode\r
7de98828 620 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r
04c980a6
MK		 621**/\r
622#define MSR_IA32_MPERF 0x000000E7\r
623\r
624\r
625/**\r
626 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r
627 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r
628 the coordinated clock frequency, when the logical processor is in C0.\r
629 Cleared upon overflow / wrap-around of IA32_MPERF.\r
630\r
631 @param ECX MSR_IA32_APERF (0x000000E8)\r
632 @param EAX Lower 32-bits of MSR value.\r
633 @param EDX Upper 32-bits of MSR value.\r
634\r
635 <b>Example usage</b>\r
636 @code\r
637 UINT64 Msr;\r
638\r
639 Msr = AsmReadMsr64 (MSR_IA32_APERF);\r
640 AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r
641 @endcode\r
7de98828 642 @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r
04c980a6
MK		 643**/\r
644#define MSR_IA32_APERF 0x000000E8\r
645\r
646\r
647/**\r
648 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r
649 Introduced at Display Family / Display Model 06_01H.\r
650\r
651 @param ECX MSR_IA32_MTRRCAP (0x000000FE)\r
652 @param EAX Lower 32-bits of MSR value.\r
653 Described by the type MSR_IA32_MTRRCAP_REGISTER.\r
654 @param EDX Upper 32-bits of MSR value.\r
655 Described by the type MSR_IA32_MTRRCAP_REGISTER.\r
656\r
657 <b>Example usage</b>\r
658 @code\r
659 MSR_IA32_MTRRCAP_REGISTER Msr;\r
660\r
661 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
662 @endcode\r
7de98828 663 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r
04c980a6
MK		 664**/\r
665#define MSR_IA32_MTRRCAP 0x000000FE\r
666\r
667/**\r
668 MSR information returned for MSR index #MSR_IA32_MTRRCAP\r
669**/\r
670typedef union {\r
671 ///\r
672 /// Individual bit fields\r
673 ///\r
674 struct {\r
675 ///\r
676 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r
677 /// processor.\r
678 ///\r
679 UINT32 VCNT:8;\r
680 ///\r
681 /// [Bit 8] Fixed range MTRRs are supported when set.\r
682 ///\r
683 UINT32 FIX:1;\r
684 UINT32 Reserved1:1;\r
685 ///\r
686 /// [Bit 10] WC Supported when set.\r
687 ///\r
688 UINT32 WC:1;\r
689 ///\r
690 /// [Bit 11] SMRR Supported when set.\r
691 ///\r
692 UINT32 SMRR:1;\r
693 UINT32 Reserved2:20;\r
694 UINT32 Reserved3:32;\r
695 } Bits;\r
696 ///\r
697 /// All bit fields as a 32-bit value\r
698 ///\r
699 UINT32 Uint32;\r
700 ///\r
701 /// All bit fields as a 64-bit value\r
702 ///\r
703 UINT64 Uint64;\r
704} MSR_IA32_MTRRCAP_REGISTER;\r
705\r
706\r
707/**\r
708 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
709\r
710 @param ECX MSR_IA32_SYSENTER_CS (0x00000174)\r
711 @param EAX Lower 32-bits of MSR value.\r
712 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r
713 @param EDX Upper 32-bits of MSR value.\r
714 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r
715\r
716 <b>Example usage</b>\r
717 @code\r
718 MSR_IA32_SYSENTER_CS_REGISTER Msr;\r
719\r
720 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r
721 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r
722 @endcode\r
7de98828 723 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r
04c980a6
MK		 724**/\r
725#define MSR_IA32_SYSENTER_CS 0x00000174\r
726\r
727/**\r
728 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r
729**/\r
730typedef union {\r
731 ///\r
732 /// Individual bit fields\r
733 ///\r
734 struct {\r
735 ///\r
736 /// [Bits 15:0] CS Selector.\r
737 ///\r
738 UINT32 CS:16;\r
739 UINT32 Reserved1:16;\r
740 UINT32 Reserved2:32;\r
741 } Bits;\r
742 ///\r
743 /// All bit fields as a 32-bit value\r
744 ///\r
745 UINT32 Uint32;\r
746 ///\r
747 /// All bit fields as a 64-bit value\r
748 ///\r
749 UINT64 Uint64;\r
750} MSR_IA32_SYSENTER_CS_REGISTER;\r
751\r
752\r
753/**\r
754 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
755\r
756 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)\r
757 @param EAX Lower 32-bits of MSR value.\r
758 @param EDX Upper 32-bits of MSR value.\r
759\r
760 <b>Example usage</b>\r
761 @code\r
762 UINT64 Msr;\r
763\r
764 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r
765 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r
766 @endcode\r
7de98828 767 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r
04c980a6
MK		 768**/\r
769#define MSR_IA32_SYSENTER_ESP 0x00000175\r
770\r
771\r
772/**\r
773 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
774\r
775 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)\r
776 @param EAX Lower 32-bits of MSR value.\r
777 @param EDX Upper 32-bits of MSR value.\r
778\r
779 <b>Example usage</b>\r
780 @code\r
781 UINT64 Msr;\r
782\r
783 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r
784 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r
785 @endcode\r
7de98828 786 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r
04c980a6
MK		 787**/\r
788#define MSR_IA32_SYSENTER_EIP 0x00000176\r
789\r
790\r
791/**\r
792 Global Machine Check Capability (RO). Introduced at Display Family / Display\r
793 Model 06_01H.\r
794\r
795 @param ECX MSR_IA32_MCG_CAP (0x00000179)\r
796 @param EAX Lower 32-bits of MSR value.\r
797 Described by the type MSR_IA32_MCG_CAP_REGISTER.\r
798 @param EDX Upper 32-bits of MSR value.\r
799 Described by the type MSR_IA32_MCG_CAP_REGISTER.\r
800\r
801 <b>Example usage</b>\r
802 @code\r
803 MSR_IA32_MCG_CAP_REGISTER Msr;\r
804\r
805 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
806 @endcode\r
7de98828 807 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
04c980a6
MK		 808**/\r
809#define MSR_IA32_MCG_CAP 0x00000179\r
810\r
811/**\r
812 MSR information returned for MSR index #MSR_IA32_MCG_CAP\r
813**/\r
814typedef union {\r
815 ///\r
816 /// Individual bit fields\r
817 ///\r
818 struct {\r
819 ///\r
820 /// [Bits 7:0] Count: Number of reporting banks.\r
821 ///\r
822 UINT32 Count:8;\r
823 ///\r
824 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r
825 ///\r
826 UINT32 MCG_CTL_P:1;\r
827 ///\r
828 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r
829 /// if this bit is set.\r
830 ///\r
831 UINT32 MCG_EXT_P:1;\r
832 ///\r
833 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r
834 /// Introduced at Display Family / Display Model 06_01H.\r
835 ///\r
836 UINT32 MCP_CMCI_P:1;\r
837 ///\r
838 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r
839 /// if this bit is set.\r
840 ///\r
841 UINT32 MCG_TES_P:1;\r
842 UINT32 Reserved1:4;\r
843 ///\r
844 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r
845 /// registers present.\r
846 ///\r
847 UINT32 MCG_EXT_CNT:8;\r
848 ///\r
849 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r
850 /// this bit is set.\r
851 ///\r
852 UINT32 MCG_SER_P:1;\r
853 UINT32 Reserved2:1;\r
854 ///\r
855 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r
856 /// firmware to be invoked when an error is detected so that it may\r
857 /// provide additional platform specific information in an ACPI format\r
858 /// "Generic Error Data Entry" that augments the data included in machine\r
859 /// check bank registers. Introduced at Display Family / Display Model\r
860 /// 06_3EH.\r
861 ///\r
862 UINT32 MCG_ELOG_P:1;\r
863 ///\r
864 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r
865 /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r
866 /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r
867 /// Display Model 06_3EH.\r
868 ///\r
869 UINT32 MCG_LMCE_P:1;\r
870 UINT32 Reserved3:4;\r
871 UINT32 Reserved4:32;\r
872 } Bits;\r
873 ///\r
874 /// All bit fields as a 32-bit value\r
875 ///\r
876 UINT32 Uint32;\r
877 ///\r
878 /// All bit fields as a 64-bit value\r
879 ///\r
880 UINT64 Uint64;\r
881} MSR_IA32_MCG_CAP_REGISTER;\r
882\r
883\r
884/**\r
885 Global Machine Check Status (R/W0). Introduced at Display Family / Display\r
886 Model 06_01H.\r
887\r
888 @param ECX MSR_IA32_MCG_STATUS (0x0000017A)\r
889 @param EAX Lower 32-bits of MSR value.\r
890 Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r
891 @param EDX Upper 32-bits of MSR value.\r
892 Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r
893\r
894 <b>Example usage</b>\r
895 @code\r
896 MSR_IA32_MCG_STATUS_REGISTER Msr;\r
897\r
898 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r
899 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r
900 @endcode\r
7de98828 901 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r
04c980a6
MK		 902**/\r
903#define MSR_IA32_MCG_STATUS 0x0000017A\r
904\r
905/**\r
906 MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r
907**/\r
908typedef union {\r
909 ///\r
910 /// Individual bit fields\r
911 ///\r
912 struct {\r
913 ///\r
914 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r
915 /// Model 06_01H.\r
916 ///\r
917 UINT32 RIPV:1;\r
918 ///\r
919 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r
920 /// Model 06_01H.\r
921 ///\r
922 UINT32 EIPV:1;\r
923 ///\r
924 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r
925 /// / Display Model 06_01H.\r
926 ///\r
927 UINT32 MCIP:1;\r
928 ///\r
929 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r
930 ///\r
931 UINT32 LMCE_S:1;\r
932 UINT32 Reserved1:28;\r
933 UINT32 Reserved2:32;\r
934 } Bits;\r
935 ///\r
936 /// All bit fields as a 32-bit value\r
937 ///\r
938 UINT32 Uint32;\r
939 ///\r
940 /// All bit fields as a 64-bit value\r
941 ///\r
942 UINT64 Uint64;\r
943} MSR_IA32_MCG_STATUS_REGISTER;\r
944\r
945\r
946/**\r
947 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r
948\r
949 @param ECX MSR_IA32_MCG_CTL (0x0000017B)\r
950 @param EAX Lower 32-bits of MSR value.\r
951 @param EDX Upper 32-bits of MSR value.\r
952\r
953 <b>Example usage</b>\r
954 @code\r
955 UINT64 Msr;\r
956\r
957 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r
958 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r
959 @endcode\r
7de98828 960 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r
04c980a6
MK		 961**/\r
962#define MSR_IA32_MCG_CTL 0x0000017B\r
963\r
964\r
965/**\r
966 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r
967\r
968 @param ECX MSR_IA32_PERFEVTSELn\r
969 @param EAX Lower 32-bits of MSR value.\r
970 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r
971 @param EDX Upper 32-bits of MSR value.\r
972 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r
973\r
974 <b>Example usage</b>\r
975 @code\r
976 MSR_IA32_PERFEVTSEL_REGISTER Msr;\r
977\r
978 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r
979 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r
980 @endcode\r
7de98828
JF		 981 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r
982 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r
983 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
984 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
04c980a6
MK		 985 @{\r
986**/\r
987#define MSR_IA32_PERFEVTSEL0 0x00000186\r
988#define MSR_IA32_PERFEVTSEL1 0x00000187\r
989#define MSR_IA32_PERFEVTSEL2 0x00000188\r
990#define MSR_IA32_PERFEVTSEL3 0x00000189\r
991/// @}\r
992\r
993/**\r
994 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r
995 #MSR_IA32_PERFEVTSEL3\r
996**/\r
997typedef union {\r
998 ///\r
999 /// Individual bit fields\r
1000 ///\r
1001 struct {\r
1002 ///\r
1003 /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
1004 ///\r
1005 UINT32 EventSelect:8;\r
1006 ///\r
1007 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
1008 /// detect on the selected event logic.\r
1009 ///\r
1010 UINT32 UMASK:8;\r
1011 ///\r
1012 /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
1013 ///\r
1014 UINT32 USR:1;\r
1015 ///\r
1016 /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
1017 ///\r
1018 UINT32 OS:1;\r
1019 ///\r
1020 /// [Bit 18] Edge: Enables edge detection if set.\r
1021 ///\r
1022 UINT32 E:1;\r
1023 ///\r
1024 /// [Bit 19] PC: enables pin control.\r
1025 ///\r
1026 UINT32 PC:1;\r
1027 ///\r
1028 /// [Bit 20] INT: enables interrupt on counter overflow.\r
1029 ///\r
1030 UINT32 INT:1;\r
1031 ///\r
1032 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
1033 /// event conditions occurring across all logical processors sharing a\r
1034 /// processor core. When set to 0, the counter only increments the\r
1035 /// associated event conditions occurring in the logical processor which\r
1036 /// programmed the MSR.\r
1037 ///\r
1038 UINT32 ANY:1;\r
1039 ///\r
1040 /// [Bit 22] EN: enables the corresponding performance counter to commence\r
1041 /// counting when this bit is set.\r
1042 ///\r
1043 UINT32 EN:1;\r
1044 ///\r
1045 /// [Bit 23] INV: invert the CMASK.\r
1046 ///\r
1047 UINT32 INV:1;\r
1048 ///\r
1049 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
1050 /// performance counter increments each cycle if the event count is\r
1051 /// greater than or equal to the CMASK.\r
1052 ///\r
1053 UINT32 CMASK:8;\r
1054 UINT32 Reserved:32;\r
1055 } Bits;\r
1056 ///\r
1057 /// All bit fields as a 32-bit value\r
1058 ///\r
1059 UINT32 Uint32;\r
1060 ///\r
1061 /// All bit fields as a 64-bit value\r
1062 ///\r
1063 UINT64 Uint64;\r
1064} MSR_IA32_PERFEVTSEL_REGISTER;\r
1065\r
1066\r
1067/**\r
1068 Current performance state(P-State) operating point (RO). Introduced at\r
1069 Display Family / Display Model 0F_03H.\r
1070\r
1071 @param ECX MSR_IA32_PERF_STATUS (0x00000198)\r
1072 @param EAX Lower 32-bits of MSR value.\r
1073 Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r
1074 @param EDX Upper 32-bits of MSR value.\r
1075 Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r
1076\r
1077 <b>Example usage</b>\r
1078 @code\r
1079 MSR_IA32_PERF_STATUS_REGISTER Msr;\r
1080\r
1081 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r
1082 @endcode\r
7de98828 1083 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r
04c980a6
MK		 1084**/\r
1085#define MSR_IA32_PERF_STATUS 0x00000198\r
1086\r
1087/**\r
1088 MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r
1089**/\r
1090typedef union {\r
1091 ///\r
1092 /// Individual bit fields\r
1093 ///\r
1094 struct {\r
1095 ///\r
1096 /// [Bits 15:0] Current performance State Value.\r
1097 ///\r
1098 UINT32 State:16;\r
1099 UINT32 Reserved1:16;\r
1100 UINT32 Reserved2:32;\r
1101 } Bits;\r
1102 ///\r
1103 /// All bit fields as a 32-bit value\r
1104 ///\r
1105 UINT32 Uint32;\r
1106 ///\r
1107 /// All bit fields as a 64-bit value\r
1108 ///\r
1109 UINT64 Uint64;\r
1110} MSR_IA32_PERF_STATUS_REGISTER;\r
1111\r
1112\r
1113/**\r
1114 (R/W). Introduced at Display Family / Display Model 0F_03H.\r
1115\r
1116 @param ECX MSR_IA32_PERF_CTL (0x00000199)\r
1117 @param EAX Lower 32-bits of MSR value.\r
1118 Described by the type MSR_IA32_PERF_CTL_REGISTER.\r
1119 @param EDX Upper 32-bits of MSR value.\r
1120 Described by the type MSR_IA32_PERF_CTL_REGISTER.\r
1121\r
1122 <b>Example usage</b>\r
1123 @code\r
1124 MSR_IA32_PERF_CTL_REGISTER Msr;\r
1125\r
1126 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r
1127 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r
1128 @endcode\r
7de98828 1129 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r
04c980a6
MK		 1130**/\r
1131#define MSR_IA32_PERF_CTL 0x00000199\r
1132\r
1133/**\r
1134 MSR information returned for MSR index #MSR_IA32_PERF_CTL\r
1135**/\r
1136typedef union {\r
1137 ///\r
1138 /// Individual bit fields\r
1139 ///\r
1140 struct {\r
1141 ///\r
1142 /// [Bits 15:0] Target performance State Value.\r
1143 ///\r
1144 UINT32 TargetState:16;\r
1145 UINT32 Reserved1:16;\r
1146 ///\r
1147 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r
1148 /// (Mobile only).\r
1149 ///\r
1150 UINT32 IDA:1;\r
1151 UINT32 Reserved2:31;\r
1152 } Bits;\r
1153 ///\r
1154 /// All bit fields as a 64-bit value\r
1155 ///\r
1156 UINT64 Uint64;\r
1157} MSR_IA32_PERF_CTL_REGISTER;\r
1158\r
1159\r
1160/**\r
1161 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
0f16be6d 1162 Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1163\r
1164 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r
1165 @param EAX Lower 32-bits of MSR value.\r
1166 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r
1167 @param EDX Upper 32-bits of MSR value.\r
1168 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r
1169\r
1170 <b>Example usage</b>\r
1171 @code\r
1172 MSR_IA32_CLOCK_MODULATION_REGISTER Msr;\r
1173\r
1174 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r
1175 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r
1176 @endcode\r
7de98828 1177 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
04c980a6
MK		 1178**/\r
1179#define MSR_IA32_CLOCK_MODULATION 0x0000019A\r
1180\r
1181/**\r
1182 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r
1183**/\r
1184typedef union {\r
1185 ///\r
1186 /// Individual bit fields\r
1187 ///\r
1188 struct {\r
1189 ///\r
1190 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r
1191 /// CPUID.06H:EAX[5] = 1.\r
1192 ///\r
1193 UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r
1194 ///\r
1195 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
0f16be6d 1196 /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1197 ///\r
1198 UINT32 OnDemandClockModulationDutyCycle:3;\r
1199 ///\r
1200 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
0f16be6d 1201 /// If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1202 ///\r
1203 UINT32 OnDemandClockModulationEnable:1;\r
1204 UINT32 Reserved1:27;\r
1205 UINT32 Reserved2:32;\r
1206 } Bits;\r
1207 ///\r
1208 /// All bit fields as a 32-bit value\r
1209 ///\r
1210 UINT32 Uint32;\r
1211 ///\r
1212 /// All bit fields as a 64-bit value\r
1213 ///\r
1214 UINT64 Uint64;\r
1215} MSR_IA32_CLOCK_MODULATION_REGISTER;\r
1216\r
1217\r
1218/**\r
1219 Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
1220 interrupt on temperature transitions detected with the processor's thermal\r
1221 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r
0f16be6d 1222 If CPUID.01H:EDX[22] = 1\r
04c980a6
MK		 1223\r
1224 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r
1225 @param EAX Lower 32-bits of MSR value.\r
1226 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r
1227 @param EDX Upper 32-bits of MSR value.\r
1228 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r
1229\r
1230 <b>Example usage</b>\r
1231 @code\r
1232 MSR_IA32_THERM_INTERRUPT_REGISTER Msr;\r
1233\r
1234 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r
1235 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r
1236 @endcode\r
7de98828 1237 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r
04c980a6
MK		 1238**/\r
1239#define MSR_IA32_THERM_INTERRUPT 0x0000019B\r
1240\r
1241/**\r
1242 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r
1243**/\r
1244typedef union {\r
1245 ///\r
1246 /// Individual bit fields\r
1247 ///\r
1248 struct {\r
1249 ///\r
0f16be6d 1250 /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1251 ///\r
1252 UINT32 HighTempEnable:1;\r
1253 ///\r
0f16be6d 1254 /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1255 ///\r
1256 UINT32 LowTempEnable:1;\r
1257 ///\r
0f16be6d 1258 /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1259 ///\r
1260 UINT32 PROCHOT_Enable:1;\r
1261 ///\r
0f16be6d 1262 /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1263 ///\r
1264 UINT32 FORCEPR_Enable:1;\r
1265 ///\r
1266 /// [Bit 4] Critical Temperature Interrupt Enable.\r
0f16be6d 1267 /// If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1268 ///\r
1269 UINT32 CriticalTempEnable:1;\r
1270 UINT32 Reserved1:3;\r
1271 ///\r
0f16be6d 1272 /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1273 ///\r
1274 UINT32 Threshold1:7;\r
1275 ///\r
0f16be6d 1276 /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1277 ///\r
1278 UINT32 Threshold1Enable:1;\r
1279 ///\r
0f16be6d 1280 /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1281 ///\r
1282 UINT32 Threshold2:7;\r
1283 ///\r
0f16be6d 1284 /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1285 ///\r
1286 UINT32 Threshold2Enable:1;\r
1287 ///\r
1288 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r
1289 ///\r
1290 UINT32 PowerLimitNotificationEnable:1;\r
1291 UINT32 Reserved2:7;\r
1292 UINT32 Reserved3:32;\r
1293 } Bits;\r
1294 ///\r
1295 /// All bit fields as a 32-bit value\r
1296 ///\r
1297 UINT32 Uint32;\r
1298 ///\r
1299 /// All bit fields as a 64-bit value\r
1300 ///\r
1301 UINT64 Uint64;\r
1302} MSR_IA32_THERM_INTERRUPT_REGISTER;\r
1303\r
1304\r
1305/**\r
1306 Thermal Status Information (RO) Contains status information about the\r
1307 processor's thermal sensor and automatic thermal monitoring facilities. See\r
0f16be6d 1308 Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1309\r
1310 @param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r
1311 @param EAX Lower 32-bits of MSR value.\r
1312 Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r
1313 @param EDX Upper 32-bits of MSR value.\r
1314 Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r
1315\r
1316 <b>Example usage</b>\r
1317 @code\r
1318 MSR_IA32_THERM_STATUS_REGISTER Msr;\r
1319\r
1320 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r
1321 @endcode\r
7de98828 1322 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r
04c980a6
MK		 1323**/\r
1324#define MSR_IA32_THERM_STATUS 0x0000019C\r
1325\r
1326/**\r
1327 MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r
1328**/\r
1329typedef union {\r
1330 ///\r
1331 /// Individual bit fields\r
1332 ///\r
1333 struct {\r
1334 ///\r
0f16be6d 1335 /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1336 ///\r
1337 UINT32 ThermalStatus:1;\r
1338 ///\r
0f16be6d 1339 /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1340 ///\r
1341 UINT32 ThermalStatusLog:1;\r
1342 ///\r
0f16be6d 1343 /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1344 ///\r
1345 UINT32 PROCHOT_FORCEPR_Event:1;\r
1346 ///\r
0f16be6d 1347 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1348 ///\r
1349 UINT32 PROCHOT_FORCEPR_Log:1;\r
1350 ///\r
0f16be6d 1351 /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1352 ///\r
1353 UINT32 CriticalTempStatus:1;\r
1354 ///\r
1355 /// [Bit 5] Critical Temperature Status log (R/WC0).\r
0f16be6d 1356 /// If CPUID.01H:EDX[22] = 1.\r
04c980a6
MK		 1357 ///\r
1358 UINT32 CriticalTempStatusLog:1;\r
1359 ///\r
1360 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r
1361 ///\r
1362 UINT32 ThermalThreshold1Status:1;\r
1363 ///\r
1364 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
1365 ///\r
1366 UINT32 ThermalThreshold1Log:1;\r
1367 ///\r
1368 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r
1369 ///\r
1370 UINT32 ThermalThreshold2Status:1;\r
1371 ///\r
1372 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
1373 ///\r
1374 UINT32 ThermalThreshold2Log:1;\r
1375 ///\r
1376 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r
1377 ///\r
1378 UINT32 PowerLimitStatus:1;\r
1379 ///\r
1380 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r
1381 ///\r
1382 UINT32 PowerLimitLog:1;\r
1383 ///\r
1384 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
1385 ///\r
1386 UINT32 CurrentLimitStatus:1;\r
1387 ///\r
1388 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
1389 ///\r
1390 UINT32 CurrentLimitLog:1;\r
1391 ///\r
1392 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
1393 ///\r
1394 UINT32 CrossDomainLimitStatus:1;\r
1395 ///\r
1396 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
1397 ///\r
1398 UINT32 CrossDomainLimitLog:1;\r
1399 ///\r
1400 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r
1401 ///\r
1402 UINT32 DigitalReadout:7;\r
1403 UINT32 Reserved1:4;\r
1404 ///\r
1405 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r
1406 /// 1.\r
1407 ///\r
1408 UINT32 ResolutionInDegreesCelsius:4;\r
1409 ///\r
1410 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r
1411 ///\r
1412 UINT32 ReadingValid:1;\r
1413 UINT32 Reserved2:32;\r
1414 } Bits;\r
1415 ///\r
1416 /// All bit fields as a 32-bit value\r
1417 ///\r
1418 UINT32 Uint32;\r
1419 ///\r
1420 /// All bit fields as a 64-bit value\r
1421 ///\r
1422 UINT64 Uint64;\r
1423} MSR_IA32_THERM_STATUS_REGISTER;\r
1424\r
1425\r
1426/**\r
1427 Enable Misc. Processor Features (R/W) Allows a variety of processor\r
1428 functions to be enabled and disabled.\r
1429\r
1430 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)\r
1431 @param EAX Lower 32-bits of MSR value.\r
1432 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r
1433 @param EDX Upper 32-bits of MSR value.\r
1434 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r
1435\r
1436 <b>Example usage</b>\r
1437 @code\r
1438 MSR_IA32_MISC_ENABLE_REGISTER Msr;\r
1439\r
1440 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r
1441 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r
1442 @endcode\r
7de98828 1443 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
04c980a6
MK		 1444**/\r
1445#define MSR_IA32_MISC_ENABLE 0x000001A0\r
1446\r
1447/**\r
1448 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r
1449**/\r
1450typedef union {\r
1451 ///\r
1452 /// Individual bit fields\r
1453 ///\r
1454 struct {\r
1455 ///\r
1456 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r
1457 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r
1458 /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r
1459 ///\r
1460 UINT32 FastStrings:1;\r
1461 UINT32 Reserved1:2;\r
1462 ///\r
1463 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
1464 /// this bit enables the thermal control circuit (TCC) portion of the\r
1465 /// Intel Thermal Monitor feature. This allows the processor to\r
1466 /// automatically reduce power consumption in response to TCC activation.\r
1467 /// 0 = Disabled. Note: In some products clearing this bit might be\r
1468 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r
0f16be6d
HW		 1469 /// thermal throttling will still be activated. The default value of this\r
1470 /// field varies with product. See respective tables where default value is\r
1471 /// listed. Introduced at Display Family / Display Model 0F_0H.\r
04c980a6
MK		 1472 ///\r
1473 UINT32 AutomaticThermalControlCircuit:1;\r
1474 UINT32 Reserved2:3;\r
1475 ///\r
1476 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
1477 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r
1478 /// Display Family / Display Model 0F_0H.\r
1479 ///\r
1480 UINT32 PerformanceMonitoring:1;\r
1481 UINT32 Reserved3:3;\r
1482 ///\r
1483 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r
1484 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r
1485 /// Display Family / Display Model 0F_0H.\r
1486 ///\r
1487 UINT32 BTS:1;\r
1488 ///\r
0f16be6d 1489 /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
04c980a6
MK		 1490 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
1491 /// Family / Display Model 06_0FH.\r
1492 ///\r
1493 UINT32 PEBS:1;\r
1494 UINT32 Reserved4:3;\r
1495 ///\r
1496 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r
1497 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r
1498 /// Technology enabled. If CPUID.01H: ECX[7] =1.\r
1499 ///\r
1500 UINT32 EIST:1;\r
1501 UINT32 Reserved5:1;\r
1502 ///\r
1503 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r
1504 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r
1505 /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r
1506 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r
1507 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r
1508 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r
1509 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r
1510 /// in the default state. Writing this bit when the SSE3 feature flag is\r
1511 /// set to 0 may generate a #GP exception. Introduced at Display Family /\r
1512 /// Display Model 0F_03H.\r
1513 ///\r
1514 UINT32 MONITOR:1;\r
1515 UINT32 Reserved6:3;\r
1516 ///\r
1517 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
0f16be6d 1518 /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
04c980a6 1519 /// question that allows users to specify when the installed OS does not\r
0f16be6d 1520 /// support CPUID functions greater than 2. Before setting this bit, BIOS\r
04c980a6 1521 /// must execute the CPUID.0H and examine the maximum value returned in\r
0f16be6d
HW		 1522 /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r
1523 /// supported. Otherwise, this bit is not supported. Setting this bit when\r
1524 /// the maximum value is not greater than 2 may generate a #GP exception.\r
04c980a6 1525 /// Setting this bit may cause unexpected behavior in software that\r
0f16be6d 1526 /// depends on the availability of CPUID leaves greater than 2. Introduced\r
04c980a6
MK		 1527 /// at Display Family / Display Model 0F_03H.\r
1528 ///\r
1529 UINT32 LimitCpuidMaxval:1;\r
1530 ///\r
1531 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
1532 /// disabled. xTPR messages are optional messages that allow the processor\r
1533 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r
1534 ///\r
1535 UINT32 xTPR_Message_Disable:1;\r
1536 UINT32 Reserved7:8;\r
1537 UINT32 Reserved8:2;\r
1538 ///\r
1539 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r
1540 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r
1541 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r
1542 /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r
1543 /// paging and take advantage of data only pages. BIOS must not alter the\r
1544 /// contents of this bit location, if XD bit is not supported. Writing\r
1545 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r
1546 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r
1547 ///\r
1548 UINT32 XD:1;\r
1549 UINT32 Reserved9:29;\r
1550 } Bits;\r
1551 ///\r
1552 /// All bit fields as a 64-bit value\r
1553 ///\r
1554 UINT64 Uint64;\r
1555} MSR_IA32_MISC_ENABLE_REGISTER;\r
1556\r
1557\r
1558/**\r
1559 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r
1560\r
1561 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
1562 @param EAX Lower 32-bits of MSR value.\r
1563 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r
1564 @param EDX Upper 32-bits of MSR value.\r
1565 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r
1566\r
1567 <b>Example usage</b>\r
1568 @code\r
1569 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;\r
1570\r
1571 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r
1572 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r
1573 @endcode\r
7de98828 1574 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
04c980a6
MK		 1575**/\r
1576#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r
1577\r
1578/**\r
1579 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r
1580**/\r
1581typedef union {\r
1582 ///\r
1583 /// Individual bit fields\r
1584 ///\r
1585 struct {\r
1586 ///\r
1587 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r
1588 /// performance. 15 indicates preference to maximize energy saving.\r
1589 ///\r
1590 UINT32 PowerPolicyPreference:4;\r
1591 UINT32 Reserved1:28;\r
1592 UINT32 Reserved2:32;\r
1593 } Bits;\r
1594 ///\r
1595 /// All bit fields as a 32-bit value\r
1596 ///\r
1597 UINT32 Uint32;\r
1598 ///\r
1599 /// All bit fields as a 64-bit value\r
1600 ///\r
1601 UINT64 Uint64;\r
1602} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r
1603\r
1604\r
1605/**\r
1606 Package Thermal Status Information (RO) Contains status information about\r
1607 the package's thermal sensor. See Section 14.8, "Package Level Thermal\r
1608 Management.". If CPUID.06H: EAX[6] = 1.\r
1609\r
1610 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r
1611 @param EAX Lower 32-bits of MSR value.\r
1612 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r
1613 @param EDX Upper 32-bits of MSR value.\r
1614 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r
1615\r
1616 <b>Example usage</b>\r
1617 @code\r
1618 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;\r
1619\r
1620 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r
1621 @endcode\r
7de98828 1622 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r
04c980a6
MK		 1623**/\r
1624#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r
1625\r
1626/**\r
1627 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r
1628**/\r
1629typedef union {\r
1630 ///\r
1631 /// Individual bit fields\r
1632 ///\r
1633 struct {\r
1634 ///\r
1635 /// [Bit 0] Pkg Thermal Status (RO):.\r
1636 ///\r
1637 UINT32 ThermalStatus:1;\r
1638 ///\r
1639 /// [Bit 1] Pkg Thermal Status Log (R/W):.\r
1640 ///\r
1641 UINT32 ThermalStatusLog:1;\r
1642 ///\r
1643 /// [Bit 2] Pkg PROCHOT # event (RO).\r
1644 ///\r
1645 UINT32 PROCHOT_Event:1;\r
1646 ///\r
1647 /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r
1648 ///\r
1649 UINT32 PROCHOT_Log:1;\r
1650 ///\r
1651 /// [Bit 4] Pkg Critical Temperature Status (RO).\r
1652 ///\r
1653 UINT32 CriticalTempStatus:1;\r
1654 ///\r
1655 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r
1656 ///\r
1657 UINT32 CriticalTempStatusLog:1;\r
1658 ///\r
1659 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r
1660 ///\r
1661 UINT32 ThermalThreshold1Status:1;\r
1662 ///\r
1663 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r
1664 ///\r
1665 UINT32 ThermalThreshold1Log:1;\r
1666 ///\r
1667 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r
1668 ///\r
1669 UINT32 ThermalThreshold2Status:1;\r
1670 ///\r
1671 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r
1672 ///\r
1673 UINT32 ThermalThreshold2Log:1;\r
1674 ///\r
1675 /// [Bit 10] Pkg Power Limitation Status (RO).\r
1676 ///\r
1677 UINT32 PowerLimitStatus:1;\r
1678 ///\r
1679 /// [Bit 11] Pkg Power Limitation log (R/WC0).\r
1680 ///\r
1681 UINT32 PowerLimitLog:1;\r
1682 UINT32 Reserved1:4;\r
1683 ///\r
1684 /// [Bits 22:16] Pkg Digital Readout (RO).\r
1685 ///\r
1686 UINT32 DigitalReadout:7;\r
1687 UINT32 Reserved2:9;\r
1688 UINT32 Reserved3:32;\r
1689 } Bits;\r
1690 ///\r
1691 /// All bit fields as a 32-bit value\r
1692 ///\r
1693 UINT32 Uint32;\r
1694 ///\r
1695 /// All bit fields as a 64-bit value\r
1696 ///\r
1697 UINT64 Uint64;\r
1698} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r
1699\r
1700\r
1701/**\r
1702 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r
1703 an interrupt on temperature transitions detected with the package's thermal\r
1704 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r
1705 EAX[6] = 1.\r
1706\r
1707 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r
1708 @param EAX Lower 32-bits of MSR value.\r
1709 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r
1710 @param EDX Upper 32-bits of MSR value.\r
1711 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r
1712\r
1713 <b>Example usage</b>\r
1714 @code\r
1715 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;\r
1716\r
1717 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r
1718 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r
1719 @endcode\r
7de98828 1720 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r
04c980a6
MK		 1721**/\r
1722#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r
1723\r
1724/**\r
1725 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r
1726**/\r
1727typedef union {\r
1728 ///\r
1729 /// Individual bit fields\r
1730 ///\r
1731 struct {\r
1732 ///\r
1733 /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r
1734 ///\r
1735 UINT32 HighTempEnable:1;\r
1736 ///\r
1737 /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r
1738 ///\r
1739 UINT32 LowTempEnable:1;\r
1740 ///\r
1741 /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r
1742 ///\r
1743 UINT32 PROCHOT_Enable:1;\r
1744 UINT32 Reserved1:1;\r
1745 ///\r
1746 /// [Bit 4] Pkg Overheat Interrupt Enable.\r
1747 ///\r
1748 UINT32 OverheatEnable:1;\r
1749 UINT32 Reserved2:3;\r
1750 ///\r
1751 /// [Bits 14:8] Pkg Threshold #1 Value.\r
1752 ///\r
1753 UINT32 Threshold1:7;\r
1754 ///\r
1755 /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r
1756 ///\r
1757 UINT32 Threshold1Enable:1;\r
1758 ///\r
1759 /// [Bits 22:16] Pkg Threshold #2 Value.\r
1760 ///\r
1761 UINT32 Threshold2:7;\r
1762 ///\r
1763 /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r
1764 ///\r
1765 UINT32 Threshold2Enable:1;\r
1766 ///\r
1767 /// [Bit 24] Pkg Power Limit Notification Enable.\r
1768 ///\r
1769 UINT32 PowerLimitNotificationEnable:1;\r
1770 UINT32 Reserved3:7;\r
1771 UINT32 Reserved4:32;\r
1772 } Bits;\r
1773 ///\r
1774 /// All bit fields as a 32-bit value\r
1775 ///\r
1776 UINT32 Uint32;\r
1777 ///\r
1778 /// All bit fields as a 64-bit value\r
1779 ///\r
1780 UINT64 Uint64;\r
1781} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r
1782\r
1783\r
1784/**\r
1785 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r
1786 Model 06_0EH.\r
1787\r
1788 @param ECX MSR_IA32_DEBUGCTL (0x000001D9)\r
1789 @param EAX Lower 32-bits of MSR value.\r
1790 Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r
1791 @param EDX Upper 32-bits of MSR value.\r
1792 Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r
1793\r
1794 <b>Example usage</b>\r
1795 @code\r
1796 MSR_IA32_DEBUGCTL_REGISTER Msr;\r
1797\r
1798 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r
1799 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r
1800 @endcode\r
7de98828 1801 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r
04c980a6
MK		 1802**/\r
1803#define MSR_IA32_DEBUGCTL 0x000001D9\r
1804\r
1805/**\r
1806 MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r
1807**/\r
1808typedef union {\r
1809 ///\r
1810 /// Individual bit fields\r
1811 ///\r
1812 struct {\r
1813 ///\r
1814 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r
1815 /// running trace of the most recent branches taken by the processor in\r
1816 /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r
1817 ///\r
1818 UINT32 LBR:1;\r
1819 ///\r
1820 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r
1821 /// EFLAGS.TF as single-step on branches instead of single-step on\r
1822 /// instructions. Introduced at Display Family / Display Model 06_01H.\r
1823 ///\r
1824 UINT32 BTF:1;\r
1825 UINT32 Reserved1:4;\r
1826 ///\r
1827 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r
1828 /// sent. Introduced at Display Family / Display Model 06_0EH.\r
1829 ///\r
1830 UINT32 TR:1;\r
1831 ///\r
1832 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r
1833 /// be logged in a BTS buffer. Introduced at Display Family / Display\r
1834 /// Model 06_0EH.\r
1835 ///\r
1836 UINT32 BTS:1;\r
1837 ///\r
1838 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r
1839 /// fashion. When this bit is set, an interrupt is generated by the BTS\r
1840 /// facility when the BTS buffer is full. Introduced at Display Family /\r
1841 /// Display Model 06_0EH.\r
1842 ///\r
1843 UINT32 BTINT:1;\r
1844 ///\r
1845 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r
1846 /// Introduced at Display Family / Display Model 06_0FH.\r
1847 ///\r
1848 UINT32 BTS_OFF_OS:1;\r
1849 ///\r
1850 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r
1851 /// Introduced at Display Family / Display Model 06_0FH.\r
1852 ///\r
1853 UINT32 BTS_OFF_USR:1;\r
1854 ///\r
1855 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r
1856 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
1857 ///\r
1858 UINT32 FREEZE_LBRS_ON_PMI:1;\r
1859 ///\r
1860 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r
1861 /// global counter control MSR are frozen (address 38FH) on a PMI request.\r
1862 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
1863 ///\r
1864 UINT32 FREEZE_PERFMON_ON_PMI:1;\r
1865 ///\r
1866 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r
1867 /// receive and generate PMI on behalf of the uncore. Introduced at\r
1868 /// Display Family / Display Model 06_1AH.\r
1869 ///\r
1870 UINT32 ENABLE_UNCORE_PMI:1;\r
1871 ///\r
1872 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r
1873 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r
1874 ///\r
1875 UINT32 FREEZE_WHILE_SMM:1;\r
1876 ///\r
1877 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r
1878 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r
1879 ///\r
1880 UINT32 RTM_DEBUG:1;\r
1881 UINT32 Reserved2:16;\r
1882 UINT32 Reserved3:32;\r
1883 } Bits;\r
1884 ///\r
1885 /// All bit fields as a 32-bit value\r
1886 ///\r
1887 UINT32 Uint32;\r
1888 ///\r
1889 /// All bit fields as a 64-bit value\r
1890 ///\r
1891 UINT64 Uint64;\r
1892} MSR_IA32_DEBUGCTL_REGISTER;\r
1893\r
1894\r
1895/**\r
1896 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r
1897 If IA32_MTRRCAP.SMRR[11] = 1.\r
1898\r
1899 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r
1900 @param EAX Lower 32-bits of MSR value.\r
1901 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r
1902 @param EDX Upper 32-bits of MSR value.\r
1903 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r
1904\r
1905 <b>Example usage</b>\r
1906 @code\r
1907 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;\r
1908\r
1909 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r
1910 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r
1911 @endcode\r
7de98828 1912 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r
04c980a6
MK		 1913**/\r
1914#define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r
1915\r
1916/**\r
1917 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r
1918**/\r
1919typedef union {\r
1920 ///\r
1921 /// Individual bit fields\r
1922 ///\r
1923 struct {\r
1924 ///\r
1925 /// [Bits 7:0] Type. Specifies memory type of the range.\r
1926 ///\r
1927 UINT32 Type:8;\r
1928 UINT32 Reserved1:4;\r
1929 ///\r
1930 /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
1931 ///\r
1932 UINT32 PhysBase:20;\r
1933 UINT32 Reserved2:32;\r
1934 } Bits;\r
1935 ///\r
1936 /// All bit fields as a 32-bit value\r
1937 ///\r
1938 UINT32 Uint32;\r
1939 ///\r
1940 /// All bit fields as a 64-bit value\r
1941 ///\r
1942 UINT64 Uint64;\r
1943} MSR_IA32_SMRR_PHYSBASE_REGISTER;\r
1944\r
1945\r
1946/**\r
ba1a2d11 1947 SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If\r
04c980a6
MK		 1948 IA32_MTRRCAP[SMRR] = 1.\r
1949\r
1950 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r
1951 @param EAX Lower 32-bits of MSR value.\r
1952 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r
1953 @param EDX Upper 32-bits of MSR value.\r
1954 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r
1955\r
1956 <b>Example usage</b>\r
1957 @code\r
1958 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;\r
1959\r
1960 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r
1961 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r
1962 @endcode\r
7de98828 1963 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r
04c980a6
MK		 1964**/\r
1965#define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r
1966\r
1967/**\r
1968 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r
1969**/\r
1970typedef union {\r
1971 ///\r
1972 /// Individual bit fields\r
1973 ///\r
1974 struct {\r
1975 UINT32 Reserved1:11;\r
1976 ///\r
1977 /// [Bit 11] Valid Enable range mask.\r
1978 ///\r
1979 UINT32 Valid:1;\r
1980 ///\r
1981 /// [Bits 31:12] PhysMask SMRR address range mask.\r
1982 ///\r
1983 UINT32 PhysMask:20;\r
1984 UINT32 Reserved2:32;\r
1985 } Bits;\r
1986 ///\r
1987 /// All bit fields as a 32-bit value\r
1988 ///\r
1989 UINT32 Uint32;\r
1990 ///\r
1991 /// All bit fields as a 64-bit value\r
1992 ///\r
1993 UINT64 Uint64;\r
1994} MSR_IA32_SMRR_PHYSMASK_REGISTER;\r
1995\r
1996\r
1997/**\r
1998 DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r
1999\r
2000 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r
2001 @param EAX Lower 32-bits of MSR value.\r
2002 @param EDX Upper 32-bits of MSR value.\r
2003\r
2004 <b>Example usage</b>\r
2005 @code\r
2006 UINT64 Msr;\r
2007\r
2008 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r
2009 @endcode\r
7de98828 2010 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r
04c980a6
MK		 2011**/\r
2012#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r
2013\r
2014\r
2015/**\r
2016 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r
2017\r
2018 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)\r
2019 @param EAX Lower 32-bits of MSR value.\r
2020 @param EDX Upper 32-bits of MSR value.\r
2021\r
2022 <b>Example usage</b>\r
2023 @code\r
2024 UINT64 Msr;\r
2025\r
2026 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r
2027 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r
2028 @endcode\r
7de98828 2029 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r
04c980a6
MK		 2030**/\r
2031#define MSR_IA32_CPU_DCA_CAP 0x000001F9\r
2032\r
2033\r
2034/**\r
2035 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r
2036\r
2037 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)\r
2038 @param EAX Lower 32-bits of MSR value.\r
2039 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r
2040 @param EDX Upper 32-bits of MSR value.\r
2041 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r
2042\r
2043 <b>Example usage</b>\r
2044 @code\r
2045 MSR_IA32_DCA_0_CAP_REGISTER Msr;\r
2046\r
2047 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r
2048 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r
2049 @endcode\r
7de98828 2050 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r
04c980a6
MK		 2051**/\r
2052#define MSR_IA32_DCA_0_CAP 0x000001FA\r
2053\r
2054/**\r
2055 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r
2056**/\r
2057typedef union {\r
2058 ///\r
2059 /// Individual bit fields\r
2060 ///\r
2061 struct {\r
2062 ///\r
2063 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r
2064 /// defeatures are set.\r
2065 ///\r
2066 UINT32 DCA_ACTIVE:1;\r
2067 ///\r
2068 /// [Bits 2:1] TRANSACTION.\r
2069 ///\r
2070 UINT32 TRANSACTION:2;\r
2071 ///\r
2072 /// [Bits 6:3] DCA_TYPE.\r
2073 ///\r
2074 UINT32 DCA_TYPE:4;\r
2075 ///\r
2076 /// [Bits 10:7] DCA_QUEUE_SIZE.\r
2077 ///\r
2078 UINT32 DCA_QUEUE_SIZE:4;\r
2079 UINT32 Reserved1:2;\r
2080 ///\r
2081 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r
2082 /// side-effect.\r
2083 ///\r
2084 UINT32 DCA_DELAY:4;\r
2085 UINT32 Reserved2:7;\r
2086 ///\r
2087 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r
2088 ///\r
2089 UINT32 SW_BLOCK:1;\r
2090 UINT32 Reserved3:1;\r
2091 ///\r
2092 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r
2093 ///\r
2094 UINT32 HW_BLOCK:1;\r
2095 UINT32 Reserved4:5;\r
2096 UINT32 Reserved5:32;\r
2097 } Bits;\r
2098 ///\r
2099 /// All bit fields as a 32-bit value\r
2100 ///\r
2101 UINT32 Uint32;\r
2102 ///\r
2103 /// All bit fields as a 64-bit value\r
2104 ///\r
2105 UINT64 Uint64;\r
2106} MSR_IA32_DCA_0_CAP_REGISTER;\r
2107\r
2108\r
2109/**\r
2110 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r
2111 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
2112\r
2113 @param ECX MSR_IA32_MTRR_PHYSBASEn\r
2114 @param EAX Lower 32-bits of MSR value.\r
2115 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r
2116 @param EDX Upper 32-bits of MSR value.\r
2117 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r
2118\r
2119 <b>Example usage</b>\r
2120 @code\r
2121 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;\r
2122\r
2123 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r
2124 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r
2125 @endcode\r
7de98828
JF		 2126 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r
2127 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r
2128 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r
2129 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r
2130 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r
2131 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r
2132 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r
2133 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r
2134 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r
2135 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r
04c980a6
MK		 2136 @{\r
2137**/\r
2138#define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r
2139#define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r
2140#define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r
2141#define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r
2142#define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r
2143#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r
2144#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r
2145#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r
2146#define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r
2147#define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r
2148/// @}\r
2149\r
2150/**\r
2151 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r
2152 #MSR_IA32_MTRR_PHYSBASE9\r
2153**/\r
2154typedef union {\r
2155 ///\r
2156 /// Individual bit fields\r
2157 ///\r
2158 struct {\r
2159 ///\r
2160 /// [Bits 7:0] Type. Specifies memory type of the range.\r
2161 ///\r
2162 UINT32 Type:8;\r
2163 UINT32 Reserved1:4;\r
2164 ///\r
2165 /// [Bits 31:12] PhysBase. MTRR physical Base Address.\r
2166 ///\r
2167 UINT32 PhysBase:20;\r
2168 ///\r
2169 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r
2170 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
2171 /// maximum physical address range supported by the processor. It is\r
2172 /// reported by CPUID leaf function 80000008H. If CPUID does not support\r
2173 /// leaf 80000008H, the processor supports 36-bit physical address size,\r
2174 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
2175 ///\r
2176 UINT32 PhysBaseHi:32;\r
2177 } Bits;\r
2178 ///\r
2179 /// All bit fields as a 64-bit value\r
2180 ///\r
2181 UINT64 Uint64;\r
2182} MSR_IA32_MTRR_PHYSBASE_REGISTER;\r
2183\r
2184\r
2185/**\r
2186 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r
2187 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
2188\r
2189 @param ECX MSR_IA32_MTRR_PHYSMASKn\r
2190 @param EAX Lower 32-bits of MSR value.\r
2191 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r
2192 @param EDX Upper 32-bits of MSR value.\r
2193 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r
2194\r
2195 <b>Example usage</b>\r
2196 @code\r
2197 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;\r
2198\r
2199 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r
2200 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r
2201 @endcode\r
7de98828
JF		 2202 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r
2203 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r
2204 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r
2205 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r
2206 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r
2207 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r
2208 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r
2209 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r
2210 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r
2211 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r
04c980a6
MK		 2212 @{\r
2213**/\r
2214#define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r
2215#define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r
2216#define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r
2217#define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r
2218#define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r
2219#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r
2220#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r
2221#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r
2222#define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r
2223#define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r
2224/// @}\r
2225\r
2226/**\r
2227 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r
2228 #MSR_IA32_MTRR_PHYSMASK9\r
2229**/\r
2230typedef union {\r
2231 ///\r
2232 /// Individual bit fields\r
2233 ///\r
2234 struct {\r
2235 UINT32 Reserved1:11;\r
2236 ///\r
2237 /// [Bit 11] Valid Enable range mask.\r
2238 ///\r
490b048b 2239 UINT32 V:1;\r
04c980a6
MK		 2240 ///\r
2241 /// [Bits 31:12] PhysMask. MTRR address range mask.\r
2242 ///\r
2243 UINT32 PhysMask:20;\r
2244 ///\r
2245 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r
2246 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
2247 /// maximum physical address range supported by the processor. It is\r
2248 /// reported by CPUID leaf function 80000008H. If CPUID does not support\r
2249 /// leaf 80000008H, the processor supports 36-bit physical address size,\r
2250 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
2251 ///\r
2252 UINT32 PhysMaskHi:32;\r
2253 } Bits;\r
2254 ///\r
2255 /// All bit fields as a 64-bit value\r
2256 ///\r
2257 UINT64 Uint64;\r
2258} MSR_IA32_MTRR_PHYSMASK_REGISTER;\r
2259\r
2260\r
2261/**\r
2262 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r
2263\r
2264 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r
2265 @param EAX Lower 32-bits of MSR value.\r
2266 @param EDX Upper 32-bits of MSR value.\r
2267\r
2268 <b>Example usage</b>\r
2269 @code\r
2270 UINT64 Msr;\r
2271\r
2272 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r
2273 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r
2274 @endcode\r
7de98828 2275 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r
04c980a6
MK		 2276**/\r
2277#define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r
2278\r
2279\r
2280/**\r
2281 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r
2282\r
2283 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r
2284 @param EAX Lower 32-bits of MSR value.\r
2285 @param EDX Upper 32-bits of MSR value.\r
2286\r
2287 <b>Example usage</b>\r
2288 @code\r
2289 UINT64 Msr;\r
2290\r
2291 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r
2292 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r
2293 @endcode\r
7de98828 2294 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r
04c980a6
MK		 2295**/\r
2296#define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r
2297\r
2298\r
2299/**\r
2300 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r
2301\r
2302 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r
2303 @param EAX Lower 32-bits of MSR value.\r
2304 @param EDX Upper 32-bits of MSR value.\r
2305\r
2306 <b>Example usage</b>\r
2307 @code\r
2308 UINT64 Msr;\r
2309\r
2310 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r
2311 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r
2312 @endcode\r
7de98828 2313 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r
04c980a6
MK		 2314**/\r
2315#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r
2316\r
2317\r
2318/**\r
2319 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r
2320\r
2321 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r
2322 @param EAX Lower 32-bits of MSR value.\r
2323 @param EDX Upper 32-bits of MSR value.\r
2324\r
2325 <b>Example usage</b>\r
2326 @code\r
2327 UINT64 Msr;\r
2328\r
2329 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r
2330 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r
2331 @endcode\r
7de98828 2332 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r
04c980a6
MK		 2333**/\r
2334#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r
2335\r
2336\r
2337/**\r
2338 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r
2339\r
2340 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r
2341 @param EAX Lower 32-bits of MSR value.\r
2342 @param EDX Upper 32-bits of MSR value.\r
2343\r
2344 <b>Example usage</b>\r
2345 @code\r
2346 UINT64 Msr;\r
2347\r
2348 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r
2349 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r
2350 @endcode\r
7de98828 2351 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r
04c980a6
MK		 2352**/\r
2353#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r
2354\r
2355\r
2356/**\r
2357 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r
2358\r
2359 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r
2360 @param EAX Lower 32-bits of MSR value.\r
2361 @param EDX Upper 32-bits of MSR value.\r
2362\r
2363 <b>Example usage</b>\r
2364 @code\r
2365 UINT64 Msr;\r
2366\r
2367 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r
2368 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r
2369 @endcode\r
7de98828 2370 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r
04c980a6
MK		 2371**/\r
2372#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r
2373\r
2374\r
2375/**\r
2376 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r
2377\r
2378 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r
2379 @param EAX Lower 32-bits of MSR value.\r
2380 @param EDX Upper 32-bits of MSR value.\r
2381\r
2382 <b>Example usage</b>\r
2383 @code\r
2384 UINT64 Msr;\r
2385\r
2386 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r
2387 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r
2388 @endcode\r
7de98828 2389 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r
04c980a6
MK		 2390**/\r
2391#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r
2392\r
2393\r
2394/**\r
2395 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r
2396\r
2397 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r
2398 @param EAX Lower 32-bits of MSR value.\r
2399 @param EDX Upper 32-bits of MSR value.\r
2400\r
2401 <b>Example usage</b>\r
2402 @code\r
2403 UINT64 Msr;\r
2404\r
2405 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r
2406 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r
2407 @endcode\r
7de98828 2408 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r
04c980a6
MK		 2409**/\r
2410#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r
2411\r
2412\r
2413/**\r
2414 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r
2415\r
2416 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r
2417 @param EAX Lower 32-bits of MSR value.\r
2418 @param EDX Upper 32-bits of MSR value.\r
2419\r
2420 <b>Example usage</b>\r
2421 @code\r
2422 UINT64 Msr;\r
2423\r
2424 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r
2425 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r
2426 @endcode\r
7de98828 2427 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r
04c980a6
MK		 2428**/\r
2429#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r
2430\r
2431\r
2432/**\r
2433 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r
2434\r
2435 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r
2436 @param EAX Lower 32-bits of MSR value.\r
2437 @param EDX Upper 32-bits of MSR value.\r
2438\r
2439 <b>Example usage</b>\r
2440 @code\r
2441 UINT64 Msr;\r
2442\r
2443 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r
2444 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r
2445 @endcode\r
7de98828 2446 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r
04c980a6
MK		 2447**/\r
2448#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r
2449\r
2450\r
2451/**\r
2452 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r
2453\r
2454 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r
2455 @param EAX Lower 32-bits of MSR value.\r
2456 @param EDX Upper 32-bits of MSR value.\r
2457\r
2458 <b>Example usage</b>\r
2459 @code\r
2460 UINT64 Msr;\r
2461\r
2462 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r
2463 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r
2464 @endcode\r
7de98828 2465 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r
04c980a6
MK		 2466**/\r
2467#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r
2468\r
2469\r
2470/**\r
2471 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r
2472\r
2473 @param ECX MSR_IA32_PAT (0x00000277)\r
2474 @param EAX Lower 32-bits of MSR value.\r
2475 Described by the type MSR_IA32_PAT_REGISTER.\r
2476 @param EDX Upper 32-bits of MSR value.\r
2477 Described by the type MSR_IA32_PAT_REGISTER.\r
2478\r
2479 <b>Example usage</b>\r
2480 @code\r
2481 MSR_IA32_PAT_REGISTER Msr;\r
2482\r
2483 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r
2484 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r
2485 @endcode\r
7de98828 2486 @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r
04c980a6
MK		 2487**/\r
2488#define MSR_IA32_PAT 0x00000277\r
2489\r
2490/**\r
2491 MSR information returned for MSR index #MSR_IA32_PAT\r
2492**/\r
2493typedef union {\r
2494 ///\r
2495 /// Individual bit fields\r
2496 ///\r
2497 struct {\r
2498 ///\r
2499 /// [Bits 2:0] PA0.\r
2500 ///\r
2501 UINT32 PA0:3;\r
2502 UINT32 Reserved1:5;\r
2503 ///\r
2504 /// [Bits 10:8] PA1.\r
2505 ///\r
2506 UINT32 PA1:3;\r
2507 UINT32 Reserved2:5;\r
2508 ///\r
2509 /// [Bits 18:16] PA2.\r
2510 ///\r
2511 UINT32 PA2:3;\r
2512 UINT32 Reserved3:5;\r
2513 ///\r
2514 /// [Bits 26:24] PA3.\r
2515 ///\r
2516 UINT32 PA3:3;\r
2517 UINT32 Reserved4:5;\r
2518 ///\r
2519 /// [Bits 34:32] PA4.\r
2520 ///\r
2521 UINT32 PA4:3;\r
2522 UINT32 Reserved5:5;\r
2523 ///\r
2524 /// [Bits 42:40] PA5.\r
2525 ///\r
2526 UINT32 PA5:3;\r
2527 UINT32 Reserved6:5;\r
2528 ///\r
2529 /// [Bits 50:48] PA6.\r
2530 ///\r
2531 UINT32 PA6:3;\r
2532 UINT32 Reserved7:5;\r
2533 ///\r
2534 /// [Bits 58:56] PA7.\r
2535 ///\r
2536 UINT32 PA7:3;\r
2537 UINT32 Reserved8:5;\r
2538 } Bits;\r
2539 ///\r
2540 /// All bit fields as a 64-bit value\r
2541 ///\r
2542 UINT64 Uint64;\r
2543} MSR_IA32_PAT_REGISTER;\r
2544\r
2545\r
2546/**\r
2547 Provides the programming interface to use corrected MC error signaling\r
2548 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r
2549\r
2550 @param ECX MSR_IA32_MCn_CTL2\r
2551 @param EAX Lower 32-bits of MSR value.\r
2552 Described by the type MSR_IA32_MC_CTL2_REGISTER.\r
2553 @param EDX Upper 32-bits of MSR value.\r
2554 Described by the type MSR_IA32_MC_CTL2_REGISTER.\r
2555\r
2556 <b>Example usage</b>\r
2557 @code\r
2558 MSR_IA32_MC_CTL2_REGISTER Msr;\r
2559\r
2560 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r
2561 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r
2562 @endcode\r
7de98828
JF		 2563 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.\r
2564 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.\r
2565 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.\r
2566 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.\r
2567 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
2568 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.\r
2569 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.\r
2570 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.\r
2571 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.\r
2572 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.\r
2573 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r
2574 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r
2575 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r
2576 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r
2577 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r
2578 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r
2579 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r
2580 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r
2581 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r
2582 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r
2583 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r
2584 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r
2585 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r
2586 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r
2587 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r
2588 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r
2589 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r
2590 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r
2591 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r
2592 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r
2593 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r
2594 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r
04c980a6
MK		 2595 @{\r
2596**/\r
2597#define MSR_IA32_MC0_CTL2 0x00000280\r
2598#define MSR_IA32_MC1_CTL2 0x00000281\r
2599#define MSR_IA32_MC2_CTL2 0x00000282\r
2600#define MSR_IA32_MC3_CTL2 0x00000283\r
2601#define MSR_IA32_MC4_CTL2 0x00000284\r
2602#define MSR_IA32_MC5_CTL2 0x00000285\r
2603#define MSR_IA32_MC6_CTL2 0x00000286\r
2604#define MSR_IA32_MC7_CTL2 0x00000287\r
2605#define MSR_IA32_MC8_CTL2 0x00000288\r
2606#define MSR_IA32_MC9_CTL2 0x00000289\r
2607#define MSR_IA32_MC10_CTL2 0x0000028A\r
2608#define MSR_IA32_MC11_CTL2 0x0000028B\r
2609#define MSR_IA32_MC12_CTL2 0x0000028C\r
2610#define MSR_IA32_MC13_CTL2 0x0000028D\r
2611#define MSR_IA32_MC14_CTL2 0x0000028E\r
2612#define MSR_IA32_MC15_CTL2 0x0000028F\r
2613#define MSR_IA32_MC16_CTL2 0x00000290\r
2614#define MSR_IA32_MC17_CTL2 0x00000291\r
2615#define MSR_IA32_MC18_CTL2 0x00000292\r
2616#define MSR_IA32_MC19_CTL2 0x00000293\r
2617#define MSR_IA32_MC20_CTL2 0x00000294\r
2618#define MSR_IA32_MC21_CTL2 0x00000295\r
2619#define MSR_IA32_MC22_CTL2 0x00000296\r
2620#define MSR_IA32_MC23_CTL2 0x00000297\r
2621#define MSR_IA32_MC24_CTL2 0x00000298\r
2622#define MSR_IA32_MC25_CTL2 0x00000299\r
2623#define MSR_IA32_MC26_CTL2 0x0000029A\r
2624#define MSR_IA32_MC27_CTL2 0x0000029B\r
2625#define MSR_IA32_MC28_CTL2 0x0000029C\r
2626#define MSR_IA32_MC29_CTL2 0x0000029D\r
2627#define MSR_IA32_MC30_CTL2 0x0000029E\r
2628#define MSR_IA32_MC31_CTL2 0x0000029F\r
2629/// @}\r
2630\r
2631/**\r
2632 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r
2633 to #MSR_IA32_MC31_CTL2\r
2634**/\r
2635typedef union {\r
2636 ///\r
2637 /// Individual bit fields\r
2638 ///\r
2639 struct {\r
2640 ///\r
2641 /// [Bits 14:0] Corrected error count threshold.\r
2642 ///\r
2643 UINT32 CorrectedErrorCountThreshold:15;\r
2644 UINT32 Reserved1:15;\r
2645 ///\r
2646 /// [Bit 30] CMCI_EN.\r
2647 ///\r
2648 UINT32 CMCI_EN:1;\r
2649 UINT32 Reserved2:1;\r
2650 UINT32 Reserved3:32;\r
2651 } Bits;\r
2652 ///\r
2653 /// All bit fields as a 32-bit value\r
2654 ///\r
2655 UINT32 Uint32;\r
2656 ///\r
2657 /// All bit fields as a 64-bit value\r
2658 ///\r
2659 UINT64 Uint64;\r
2660} MSR_IA32_MC_CTL2_REGISTER;\r
2661\r
2662\r
2663/**\r
2664 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r
2665\r
2666 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r
2667 @param EAX Lower 32-bits of MSR value.\r
2668 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r
2669 @param EDX Upper 32-bits of MSR value.\r
2670 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r
2671\r
2672 <b>Example usage</b>\r
2673 @code\r
2674 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;\r
2675\r
2676 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
2677 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r
2678 @endcode\r
7de98828 2679 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r
04c980a6
MK		 2680**/\r
2681#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r
2682\r
2683/**\r
2684 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r
2685**/\r
2686typedef union {\r
2687 ///\r
2688 /// Individual bit fields\r
2689 ///\r
2690 struct {\r
2691 ///\r
2692 /// [Bits 2:0] Default Memory Type.\r
2693 ///\r
2694 UINT32 Type:3;\r
2695 UINT32 Reserved1:7;\r
2696 ///\r
2697 /// [Bit 10] Fixed Range MTRR Enable.\r
2698 ///\r
2699 UINT32 FE:1;\r
2700 ///\r
2701 /// [Bit 11] MTRR Enable.\r
2702 ///\r
2703 UINT32 E:1;\r
2704 UINT32 Reserved2:20;\r
2705 UINT32 Reserved3:32;\r
2706 } Bits;\r
2707 ///\r
2708 /// All bit fields as a 32-bit value\r
2709 ///\r
2710 UINT32 Uint32;\r
2711 ///\r
2712 /// All bit fields as a 64-bit value\r
2713 ///\r
2714 UINT64 Uint64;\r
2715} MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r
2716\r
2717\r
2718/**\r
2719 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r
2720 CPUID.0AH: EDX[4:0] > 0.\r
2721\r
2722 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)\r
2723 @param EAX Lower 32-bits of MSR value.\r
2724 @param EDX Upper 32-bits of MSR value.\r
2725\r
2726 <b>Example usage</b>\r
2727 @code\r
2728 UINT64 Msr;\r
2729\r
2730 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r
2731 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r
2732 @endcode\r
7de98828 2733 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r
04c980a6
MK		 2734**/\r
2735#define MSR_IA32_FIXED_CTR0 0x00000309\r
2736\r
2737\r
2738/**\r
0f16be6d
HW		 2739 Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
2740 CPUID.0AH: EDX[4:0] > 1.\r
04c980a6
MK		 2741\r
2742 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r
2743 @param EAX Lower 32-bits of MSR value.\r
2744 @param EDX Upper 32-bits of MSR value.\r
2745\r
2746 <b>Example usage</b>\r
2747 @code\r
2748 UINT64 Msr;\r
2749\r
2750 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r
2751 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r
2752 @endcode\r
7de98828 2753 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r
04c980a6
MK		 2754**/\r
2755#define MSR_IA32_FIXED_CTR1 0x0000030A\r
2756\r
2757\r
2758/**\r
0f16be6d
HW		 2759 Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
2760 CPUID.0AH: EDX[4:0] > 2.\r
04c980a6
MK		 2761\r
2762 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r
2763 @param EAX Lower 32-bits of MSR value.\r
2764 @param EDX Upper 32-bits of MSR value.\r
2765\r
2766 <b>Example usage</b>\r
2767 @code\r
2768 UINT64 Msr;\r
2769\r
2770 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r
2771 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r
2772 @endcode\r
7de98828 2773 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r
04c980a6
MK		 2774**/\r
2775#define MSR_IA32_FIXED_CTR2 0x0000030B\r
2776\r
2777\r
2778/**\r
2779 RO. If CPUID.01H: ECX[15] = 1.\r
2780\r
2781 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)\r
2782 @param EAX Lower 32-bits of MSR value.\r
2783 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r
2784 @param EDX Upper 32-bits of MSR value.\r
2785 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r
2786\r
2787 <b>Example usage</b>\r
2788 @code\r
2789 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;\r
2790\r
2791 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r
2792 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r
2793 @endcode\r
7de98828 2794 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r
04c980a6
MK		 2795**/\r
2796#define MSR_IA32_PERF_CAPABILITIES 0x00000345\r
2797\r
2798/**\r
2799 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r
2800**/\r
2801typedef union {\r
2802 ///\r
2803 /// Individual bit fields\r
2804 ///\r
2805 struct {\r
2806 ///\r
2807 /// [Bits 5:0] LBR format.\r
2808 ///\r
2809 UINT32 LBR_FMT:6;\r
2810 ///\r
2811 /// [Bit 6] PEBS Trap.\r
2812 ///\r
2813 UINT32 PEBS_TRAP:1;\r
2814 ///\r
2815 /// [Bit 7] PEBSSaveArchRegs.\r
2816 ///\r
2817 UINT32 PEBS_ARCH_REG:1;\r
2818 ///\r
2819 /// [Bits 11:8] PEBS Record Format.\r
2820 ///\r
2821 UINT32 PEBS_REC_FMT:4;\r
2822 ///\r
2823 /// [Bit 12] 1: Freeze while SMM is supported.\r
2824 ///\r
2825 UINT32 SMM_FREEZE:1;\r
2826 ///\r
2827 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r
2828 ///\r
2829 UINT32 FW_WRITE:1;\r
2830 UINT32 Reserved1:18;\r
2831 UINT32 Reserved2:32;\r
2832 } Bits;\r
2833 ///\r
2834 /// All bit fields as a 32-bit value\r
2835 ///\r
2836 UINT32 Uint32;\r
2837 ///\r
2838 /// All bit fields as a 64-bit value\r
2839 ///\r
2840 UINT64 Uint64;\r
2841} MSR_IA32_PERF_CAPABILITIES_REGISTER;\r
2842\r
2843\r
2844/**\r
2845 Fixed-Function Performance Counter Control (R/W) Counter increments while\r
2846 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r
2847 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r
2848 > 1.\r
2849\r
2850 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r
2851 @param EAX Lower 32-bits of MSR value.\r
2852 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r
2853 @param EDX Upper 32-bits of MSR value.\r
2854 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r
2855\r
2856 <b>Example usage</b>\r
2857 @code\r
2858 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;\r
2859\r
2860 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r
2861 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r
2862 @endcode\r
7de98828 2863 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r
04c980a6
MK		 2864**/\r
2865#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r
2866\r
2867/**\r
2868 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r
2869**/\r
2870typedef union {\r
2871 ///\r
2872 /// Individual bit fields\r
2873 ///\r
2874 struct {\r
2875 ///\r
2876 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r
2877 ///\r
2878 UINT32 EN0_OS:1;\r
2879 ///\r
2880 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r
2881 ///\r
2882 UINT32 EN0_Usr:1;\r
2883 ///\r
2884 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r
2885 /// event conditions occurring across all logical processors sharing a\r
2886 /// processor core. When set to 0, the counter only increments the\r
2887 /// associated event conditions occurring in the logical processor which\r
2888 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
2889 ///\r
2890 UINT32 AnyThread0:1;\r
2891 ///\r
2892 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r
2893 ///\r
2894 UINT32 EN0_PMI:1;\r
2895 ///\r
2896 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r
2897 ///\r
2898 UINT32 EN1_OS:1;\r
2899 ///\r
2900 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r
2901 ///\r
2902 UINT32 EN1_Usr:1;\r
2903 ///\r
2904 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r
2905 /// event conditions occurring across all logical processors sharing a\r
2906 /// processor core. When set to 0, the counter only increments the\r
2907 /// associated event conditions occurring in the logical processor which\r
2908 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
2909 ///\r
2910 UINT32 AnyThread1:1;\r
2911 ///\r
2912 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r
2913 ///\r
2914 UINT32 EN1_PMI:1;\r
2915 ///\r
2916 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r
2917 ///\r
2918 UINT32 EN2_OS:1;\r
2919 ///\r
2920 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r
2921 ///\r
2922 UINT32 EN2_Usr:1;\r
2923 ///\r
2924 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r
2925 /// event conditions occurring across all logical processors sharing a\r
2926 /// processor core. When set to 0, the counter only increments the\r
2927 /// associated event conditions occurring in the logical processor which\r
2928 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
2929 ///\r
2930 UINT32 AnyThread2:1;\r
2931 ///\r
2932 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r
2933 ///\r
2934 UINT32 EN2_PMI:1;\r
2935 UINT32 Reserved1:20;\r
2936 UINT32 Reserved2:32;\r
2937 } Bits;\r
2938 ///\r
2939 /// All bit fields as a 32-bit value\r
2940 ///\r
2941 UINT32 Uint32;\r
2942 ///\r
2943 /// All bit fields as a 64-bit value\r
2944 ///\r
2945 UINT64 Uint64;\r
2946} MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r
2947\r
2948\r
2949/**\r
2950 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r
2951\r
2952 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
2953 @param EAX Lower 32-bits of MSR value.\r
2954 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
2955 @param EDX Upper 32-bits of MSR value.\r
2956 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
2957\r
2958 <b>Example usage</b>\r
2959 @code\r
2960 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
2961\r
2962 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r
2963 @endcode\r
7de98828 2964 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
04c980a6
MK		 2965**/\r
2966#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
2967\r
2968/**\r
2969 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r
2970**/\r
2971typedef union {\r
2972 ///\r
2973 /// Individual bit fields\r
2974 ///\r
2975 struct {\r
2976 ///\r
2977 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r
2978 /// EAX[15:8] > 0.\r
2979 ///\r
2980 UINT32 Ovf_PMC0:1;\r
2981 ///\r
2982 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r
2983 /// EAX[15:8] > 1.\r
2984 ///\r
2985 UINT32 Ovf_PMC1:1;\r
2986 ///\r
2987 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r
2988 /// EAX[15:8] > 2.\r
2989 ///\r
2990 UINT32 Ovf_PMC2:1;\r
2991 ///\r
2992 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r
2993 /// EAX[15:8] > 3.\r
2994 ///\r
2995 UINT32 Ovf_PMC3:1;\r
2996 UINT32 Reserved1:28;\r
2997 ///\r
2998 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r
2999 /// CPUID.0AH: EAX[7:0] > 1.\r
3000 ///\r
3001 UINT32 Ovf_FixedCtr0:1;\r
3002 ///\r
3003 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r
3004 /// CPUID.0AH: EAX[7:0] > 1.\r
3005 ///\r
3006 UINT32 Ovf_FixedCtr1:1;\r
3007 ///\r
3008 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r
3009 /// CPUID.0AH: EAX[7:0] > 1.\r
3010 ///\r
3011 UINT32 Ovf_FixedCtr2:1;\r
3012 UINT32 Reserved2:20;\r
3013 ///\r
3014 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r
3015 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
3016 /// && IA32_RTIT_CTL.ToPA = 1.\r
3017 ///\r
3018 UINT32 Trace_ToPA_PMI:1;\r
3019 UINT32 Reserved3:2;\r
3020 ///\r
3021 /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r
3022 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r
3023 /// CPUID.0AH: EAX[7:0] > 3.\r
3024 ///\r
3025 UINT32 LBR_Frz:1;\r
3026 ///\r
3027 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r
3028 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r
3029 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r
3030 ///\r
3031 UINT32 CTR_Frz:1;\r
3032 ///\r
3033 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r
3034 /// include contributions from the direct or indirect operation intel SGX\r
3035 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r
3036 ///\r
3037 UINT32 ASCI:1;\r
3038 ///\r
3039 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r
3040 /// EAX[7:0] > 2.\r
3041 ///\r
3042 UINT32 Ovf_Uncore:1;\r
3043 ///\r
3044 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r
3045 /// EAX[7:0] > 0.\r
3046 ///\r
3047 UINT32 OvfBuf:1;\r
3048 ///\r
3049 /// [Bit 63] CondChgd: status bits of this register has changed. If\r
3050 /// CPUID.0AH: EAX[7:0] > 0.\r
3051 ///\r
3052 UINT32 CondChgd:1;\r
3053 } Bits;\r
3054 ///\r
3055 /// All bit fields as a 64-bit value\r
3056 ///\r
3057 UINT64 Uint64;\r
3058} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
3059\r
3060\r
3061/**\r
3062 Global Performance Counter Control (R/W) Counter increments while the result\r
3063 of ANDing respective enable bit in this MSR with the corresponding OS or USR\r
3064 bits in the general-purpose or fixed counter control MSR is true. If\r
3065 CPUID.0AH: EAX[7:0] > 0.\r
3066\r
3067 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r
3068 @param EAX Lower 32-bits of MSR value.\r
3069 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
3070 @param EDX Upper 32-bits of MSR value.\r
3071 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r
3072\r
3073 <b>Example usage</b>\r
3074 @code\r
3075 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r
3076\r
3077 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r
3078 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r
3079 @endcode\r
7de98828 3080 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
04c980a6
MK		 3081**/\r
3082#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
3083\r
3084/**\r
3085 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r
3086**/\r
3087typedef union {\r
3088 ///\r
3089 /// Individual bit fields\r
3090///\r
3091 struct {\r
3092 ///\r
3093 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r
3094 /// Enable bitmask. Only the first n-1 bits are valid.\r
3095 /// Bits n..31 are reserved.\r
3096 ///\r
3097 UINT32 EN_PMCn:32;\r
3098 ///\r
3099 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r
3100 /// Enable bitmask. Only the first n-1 bits are valid.\r
3101 /// Bits 31:n are reserved.\r
3102 ///\r
3103 UINT32 EN_FIXED_CTRn:32;\r
3104 } Bits;\r
3105 ///\r
3106 /// All bit fields as a 64-bit value\r
3107 ///\r
3108 UINT64 Uint64;\r
3109} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
3110\r
3111\r
3112/**\r
3113 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r
3114 0 && CPUID.0AH: EAX[7:0] <= 3.\r
3115\r
3116 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
3117 @param EAX Lower 32-bits of MSR value.\r
3118 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
3119 @param EDX Upper 32-bits of MSR value.\r
3120 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
3121\r
3122 <b>Example usage</b>\r
3123 @code\r
3124 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r
3125\r
3126 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r
3127 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
3128 @endcode\r
7de98828 3129 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
04c980a6
MK		 3130**/\r
3131#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
3132\r
3133/**\r
3134 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r
3135**/\r
3136typedef union {\r
3137 ///\r
3138 /// Individual bit fields\r
3139 ///\r
3140 struct {\r
3141 ///\r
3142 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r
3143 /// Clear bitmask. Only the first n-1 bits are valid.\r
3144 /// Bits 31:n are reserved.\r
3145 ///\r
3146 UINT32 Ovf_PMCn:32;\r
3147 ///\r
3148 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
3149 /// If CPUID.0AH: EDX[4:0] > n.\r
3150 /// Clear bitmask. Only the first n-1 bits are valid.\r
3151 /// Bits 22:n are reserved.\r
3152 ///\r
3153 UINT32 Ovf_FIXED_CTRn:23;\r
3154 ///\r
3155 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
3156 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r
3157 ///\r
3158 UINT32 Trace_ToPA_PMI:1;\r
3159 UINT32 Reserved2:5;\r
3160 ///\r
3161 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
3162 /// Display Model 06_2EH.\r
3163 ///\r
3164 UINT32 Ovf_Uncore:1;\r
3165 ///\r
3166 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
3167 ///\r
3168 UINT32 OvfBuf:1;\r
3169 ///\r
3170 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
3171 ///\r
3172 UINT32 CondChgd:1;\r
3173 } Bits;\r
3174 ///\r
3175 /// All bit fields as a 64-bit value\r
3176 ///\r
3177 UINT64 Uint64;\r
3178} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
3179\r
3180\r
3181/**\r
3182 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r
3183 EAX[7:0] > 3.\r
3184\r
3185 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
3186 @param EAX Lower 32-bits of MSR value.\r
3187 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
3188 @param EDX Upper 32-bits of MSR value.\r
3189 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
3190\r
3191 <b>Example usage</b>\r
3192 @code\r
3193 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
3194\r
3195 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r
3196 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
3197 @endcode\r
7de98828 3198 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
04c980a6
MK		 3199**/\r
3200#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
3201\r
3202/**\r
3203 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r
3204**/\r
3205typedef union {\r
3206 ///\r
3207 /// Individual bit fields\r
3208 ///\r
3209 struct {\r
3210 ///\r
3211 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r
3212 /// Clear bitmask. Only the first n-1 bits are valid.\r
3213 /// Bits 31:n are reserved.\r
3214 ///\r
3215 UINT32 Ovf_PMCn:32;\r
3216 ///\r
3217 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
3218 /// If CPUID.0AH: EDX[4:0] > n.\r
3219 /// Clear bitmask. Only the first n-1 bits are valid.\r
3220 /// Bits 22:n are reserved.\r
3221 ///\r
3222 UINT32 Ovf_FIXED_CTRn:23;\r
3223 ///\r
3224 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
3225 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r
3226 ///\r
3227 UINT32 Trace_ToPA_PMI:1;\r
3228 UINT32 Reserved2:2;\r
3229 ///\r
3230 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
3231 ///\r
3232 UINT32 LBR_Frz:1;\r
3233 ///\r
3234 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
3235 ///\r
3236 UINT32 CTR_Frz:1;\r
3237 ///\r
3238 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r
3239 ///\r
3240 UINT32 ASCI:1;\r
3241 ///\r
3242 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
3243 /// Display Model 06_2EH.\r
3244 ///\r
3245 UINT32 Ovf_Uncore:1;\r
3246 ///\r
3247 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
3248 ///\r
3249 UINT32 OvfBuf:1;\r
3250 ///\r
3251 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
3252 ///\r
3253 UINT32 CondChgd:1;\r
3254 } Bits;\r
3255 ///\r
3256 /// All bit fields as a 64-bit value\r
3257 ///\r
3258 UINT64 Uint64;\r
3259} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
3260\r
3261\r
3262/**\r
3263 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r
3264 EAX[7:0] > 3.\r
3265\r
3266 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
3267 @param EAX Lower 32-bits of MSR value.\r
3268 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
3269 @param EDX Upper 32-bits of MSR value.\r
3270 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
3271\r
3272 <b>Example usage</b>\r
3273 @code\r
3274 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
3275\r
3276 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r
3277 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
3278 @endcode\r
7de98828 3279 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
04c980a6
MK		 3280**/\r
3281#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
3282\r
3283/**\r
3284 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r
3285**/\r
3286typedef union {\r
3287 ///\r
3288 /// Individual bit fields\r
3289 ///\r
3290 struct {\r
3291 ///\r
3292 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r
3293 /// Set bitmask. Only the first n-1 bits are valid.\r
3294 /// Bits 31:n are reserved.\r
3295 ///\r
3296 UINT32 Ovf_PMCn:32;\r
3297 ///\r
3298 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r
3299 /// If CPUID.0AH: EAX[7:0] > n.\r
3300 /// Set bitmask. Only the first n-1 bits are valid.\r
3301 /// Bits 22:n are reserved.\r
3302 ///\r
3303 UINT32 Ovf_FIXED_CTRn:23;\r
3304 ///\r
3305 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
3306 ///\r
3307 UINT32 Trace_ToPA_PMI:1;\r
3308 UINT32 Reserved2:2;\r
3309 ///\r
3310 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
3311 ///\r
3312 UINT32 LBR_Frz:1;\r
3313 ///\r
3314 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
3315 ///\r
3316 UINT32 CTR_Frz:1;\r
3317 ///\r
3318 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
3319 ///\r
3320 UINT32 ASCI:1;\r
3321 ///\r
3322 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r
3323 ///\r
3324 UINT32 Ovf_Uncore:1;\r
3325 ///\r
3326 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r
3327 ///\r
3328 UINT32 OvfBuf:1;\r
3329 UINT32 Reserved3:1;\r
3330 } Bits;\r
3331 ///\r
3332 /// All bit fields as a 64-bit value\r
3333 ///\r
3334 UINT64 Uint64;\r
3335} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
3336\r
3337\r
3338/**\r
3339 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r
3340 3.\r
3341\r
3342 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r
3343 @param EAX Lower 32-bits of MSR value.\r
3344 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r
3345 @param EDX Upper 32-bits of MSR value.\r
3346 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r
3347\r
3348 <b>Example usage</b>\r
3349 @code\r
3350 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;\r
3351\r
3352 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r
3353 @endcode\r
7de98828 3354 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r
04c980a6
MK		 3355**/\r
3356#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r
3357\r
3358/**\r
3359 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r
3360**/\r
3361typedef union {\r
3362 ///\r
3363 /// Individual bit fields\r
3364 ///\r
3365 struct {\r
3366 ///\r
3367 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.\r
3368 /// Status bitmask. Only the first n-1 bits are valid.\r
3369 /// Bits 31:n are reserved.\r
3370 ///\r
3371 UINT32 IA32_PERFEVTSELn:32;\r
3372 ///\r
3373 /// [Bits 62:32] IA32_FIXED_CTRn in use.\r
3374 /// If CPUID.0AH: EAX[7:0] > n.\r
3375 /// Status bitmask. Only the first n-1 bits are valid.\r
3376 /// Bits 30:n are reserved.\r
3377 ///\r
3378 UINT32 IA32_FIXED_CTRn:31;\r
3379 ///\r
3380 /// [Bit 63] PMI in use.\r
3381 ///\r
3382 UINT32 PMI:1;\r
3383 } Bits;\r
3384 ///\r
3385 /// All bit fields as a 64-bit value\r
3386 ///\r
3387 UINT64 Uint64;\r
3388} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r
3389\r
3390\r
3391/**\r
3392 PEBS Control (R/W).\r
3393\r
3394 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)\r
3395 @param EAX Lower 32-bits of MSR value.\r
3396 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r
3397 @param EDX Upper 32-bits of MSR value.\r
3398 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r
3399\r
3400 <b>Example usage</b>\r
3401 @code\r
3402 MSR_IA32_PEBS_ENABLE_REGISTER Msr;\r
3403\r
3404 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r
3405 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r
3406 @endcode\r
7de98828 3407 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r
04c980a6
MK		 3408**/\r
3409#define MSR_IA32_PEBS_ENABLE 0x000003F1\r
3410\r
3411/**\r
3412 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r
3413**/\r
3414typedef union {\r
3415 ///\r
3416 /// Individual bit fields\r
3417 ///\r
3418 struct {\r
3419 ///\r
3420 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r
3421 /// Display Model 06_0FH.\r
3422 ///\r
3423 UINT32 Enable:1;\r
3424 ///\r
3425 /// [Bits 3:1] Reserved or Model specific.\r
3426 ///\r
3427 UINT32 Reserved1:3;\r
3428 UINT32 Reserved2:28;\r
3429 ///\r
3430 /// [Bits 35:32] Reserved or Model specific.\r
3431 ///\r
3432 UINT32 Reserved3:4;\r
3433 UINT32 Reserved4:28;\r
3434 } Bits;\r
3435 ///\r
3436 /// All bit fields as a 64-bit value\r
3437 ///\r
3438 UINT64 Uint64;\r
3439} MSR_IA32_PEBS_ENABLE_REGISTER;\r
3440\r
3441\r
3442/**\r
3443 MCn_CTL. If IA32_MCG_CAP.CNT > n.\r
3444\r
3445 @param ECX MSR_IA32_MCn_CTL\r
3446 @param EAX Lower 32-bits of MSR value.\r
3447 @param EDX Upper 32-bits of MSR value.\r
3448\r
3449 <b>Example usage</b>\r
3450 @code\r
3451 UINT64 Msr;\r
3452\r
3453 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r
3454 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r
3455 @endcode\r
7de98828
JF		 3456 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.\r
3457 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.\r
3458 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.\r
3459 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.\r
3460 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
3461 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.\r
3462 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.\r
3463 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.\r
3464 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.\r
3465 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.\r
3466 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r
3467 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r
3468 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r
3469 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r
3470 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r
3471 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r
3472 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r
3473 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r
3474 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r
3475 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r
3476 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r
3477 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r
3478 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r
3479 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r
3480 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r
3481 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r
3482 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r
3483 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r
3484 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r
04c980a6
MK		 3485 @{\r
3486**/\r
3487#define MSR_IA32_MC0_CTL 0x00000400\r
3488#define MSR_IA32_MC1_CTL 0x00000404\r
3489#define MSR_IA32_MC2_CTL 0x00000408\r
3490#define MSR_IA32_MC3_CTL 0x0000040C\r
3491#define MSR_IA32_MC4_CTL 0x00000410\r
3492#define MSR_IA32_MC5_CTL 0x00000414\r
3493#define MSR_IA32_MC6_CTL 0x00000418\r
3494#define MSR_IA32_MC7_CTL 0x0000041C\r
3495#define MSR_IA32_MC8_CTL 0x00000420\r
3496#define MSR_IA32_MC9_CTL 0x00000424\r
3497#define MSR_IA32_MC10_CTL 0x00000428\r
3498#define MSR_IA32_MC11_CTL 0x0000042C\r
3499#define MSR_IA32_MC12_CTL 0x00000430\r
3500#define MSR_IA32_MC13_CTL 0x00000434\r
3501#define MSR_IA32_MC14_CTL 0x00000438\r
3502#define MSR_IA32_MC15_CTL 0x0000043C\r
3503#define MSR_IA32_MC16_CTL 0x00000440\r
3504#define MSR_IA32_MC17_CTL 0x00000444\r
3505#define MSR_IA32_MC18_CTL 0x00000448\r
3506#define MSR_IA32_MC19_CTL 0x0000044C\r
3507#define MSR_IA32_MC20_CTL 0x00000450\r
3508#define MSR_IA32_MC21_CTL 0x00000454\r
3509#define MSR_IA32_MC22_CTL 0x00000458\r
3510#define MSR_IA32_MC23_CTL 0x0000045C\r
3511#define MSR_IA32_MC24_CTL 0x00000460\r
3512#define MSR_IA32_MC25_CTL 0x00000464\r
3513#define MSR_IA32_MC26_CTL 0x00000468\r
3514#define MSR_IA32_MC27_CTL 0x0000046C\r
3515#define MSR_IA32_MC28_CTL 0x00000470\r
3516/// @}\r
3517\r
3518\r
3519/**\r
3520 MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r
3521\r
3522 @param ECX MSR_IA32_MCn_STATUS\r
3523 @param EAX Lower 32-bits of MSR value.\r
3524 @param EDX Upper 32-bits of MSR value.\r
3525\r
3526 <b>Example usage</b>\r
3527 @code\r
3528 UINT64 Msr;\r
3529\r
3530 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r
3531 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r
3532 @endcode\r
7de98828
JF		 3533 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.\r
3534 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.\r
3535 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.\r
3536 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.\r
3537 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.\r
3538 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.\r
3539 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.\r
3540 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.\r
3541 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.\r
3542 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.\r
3543 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r
3544 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r
3545 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r
3546 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r
3547 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r
3548 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r
3549 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r
3550 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r
3551 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r
3552 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r
3553 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r
3554 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r
3555 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r
3556 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r
3557 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r
3558 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r
3559 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r
3560 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r
3561 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r
04c980a6
MK		 3562 @{\r
3563**/\r
3564#define MSR_IA32_MC0_STATUS 0x00000401\r
3565#define MSR_IA32_MC1_STATUS 0x00000405\r
3566#define MSR_IA32_MC2_STATUS 0x00000409\r
3567#define MSR_IA32_MC3_STATUS 0x0000040D\r
3568#define MSR_IA32_MC4_STATUS 0x00000411\r
3569#define MSR_IA32_MC5_STATUS 0x00000415\r
3570#define MSR_IA32_MC6_STATUS 0x00000419\r
3571#define MSR_IA32_MC7_STATUS 0x0000041D\r
3572#define MSR_IA32_MC8_STATUS 0x00000421\r
3573#define MSR_IA32_MC9_STATUS 0x00000425\r
3574#define MSR_IA32_MC10_STATUS 0x00000429\r
3575#define MSR_IA32_MC11_STATUS 0x0000042D\r
3576#define MSR_IA32_MC12_STATUS 0x00000431\r
3577#define MSR_IA32_MC13_STATUS 0x00000435\r
3578#define MSR_IA32_MC14_STATUS 0x00000439\r
3579#define MSR_IA32_MC15_STATUS 0x0000043D\r
3580#define MSR_IA32_MC16_STATUS 0x00000441\r
3581#define MSR_IA32_MC17_STATUS 0x00000445\r
3582#define MSR_IA32_MC18_STATUS 0x00000449\r
3583#define MSR_IA32_MC19_STATUS 0x0000044D\r
3584#define MSR_IA32_MC20_STATUS 0x00000451\r
3585#define MSR_IA32_MC21_STATUS 0x00000455\r
3586#define MSR_IA32_MC22_STATUS 0x00000459\r
3587#define MSR_IA32_MC23_STATUS 0x0000045D\r
3588#define MSR_IA32_MC24_STATUS 0x00000461\r
3589#define MSR_IA32_MC25_STATUS 0x00000465\r
3590#define MSR_IA32_MC26_STATUS 0x00000469\r
3591#define MSR_IA32_MC27_STATUS 0x0000046D\r
3592#define MSR_IA32_MC28_STATUS 0x00000471\r
3593/// @}\r
3594\r
3595\r
3596/**\r
3597 MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r
3598\r
3599 @param ECX MSR_IA32_MCn_ADDR\r
3600 @param EAX Lower 32-bits of MSR value.\r
3601 @param EDX Upper 32-bits of MSR value.\r
3602\r
3603 <b>Example usage</b>\r
3604 @code\r
3605 UINT64 Msr;\r
3606\r
3607 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r
3608 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r
3609 @endcode\r
7de98828
JF		 3610 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.\r
3611 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.\r
3612 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.\r
3613 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.\r
3614 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.\r
3615 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.\r
3616 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.\r
3617 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.\r
3618 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.\r
3619 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.\r
3620 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r
3621 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r
3622 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r
3623 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r
3624 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r
3625 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r
3626 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r
3627 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r
3628 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r
3629 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r
3630 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r
3631 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r
3632 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r
3633 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r
3634 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r
3635 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r
3636 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r
3637 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r
3638 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r
04c980a6
MK		 3639 @{\r
3640**/\r
3641#define MSR_IA32_MC0_ADDR 0x00000402\r
3642#define MSR_IA32_MC1_ADDR 0x00000406\r
3643#define MSR_IA32_MC2_ADDR 0x0000040A\r
3644#define MSR_IA32_MC3_ADDR 0x0000040E\r
3645#define MSR_IA32_MC4_ADDR 0x00000412\r
3646#define MSR_IA32_MC5_ADDR 0x00000416\r
3647#define MSR_IA32_MC6_ADDR 0x0000041A\r
3648#define MSR_IA32_MC7_ADDR 0x0000041E\r
3649#define MSR_IA32_MC8_ADDR 0x00000422\r
3650#define MSR_IA32_MC9_ADDR 0x00000426\r
3651#define MSR_IA32_MC10_ADDR 0x0000042A\r
3652#define MSR_IA32_MC11_ADDR 0x0000042E\r
3653#define MSR_IA32_MC12_ADDR 0x00000432\r
3654#define MSR_IA32_MC13_ADDR 0x00000436\r
3655#define MSR_IA32_MC14_ADDR 0x0000043A\r
3656#define MSR_IA32_MC15_ADDR 0x0000043E\r
3657#define MSR_IA32_MC16_ADDR 0x00000442\r
3658#define MSR_IA32_MC17_ADDR 0x00000446\r
3659#define MSR_IA32_MC18_ADDR 0x0000044A\r
3660#define MSR_IA32_MC19_ADDR 0x0000044E\r
3661#define MSR_IA32_MC20_ADDR 0x00000452\r
3662#define MSR_IA32_MC21_ADDR 0x00000456\r
3663#define MSR_IA32_MC22_ADDR 0x0000045A\r
3664#define MSR_IA32_MC23_ADDR 0x0000045E\r
3665#define MSR_IA32_MC24_ADDR 0x00000462\r
3666#define MSR_IA32_MC25_ADDR 0x00000466\r
3667#define MSR_IA32_MC26_ADDR 0x0000046A\r
3668#define MSR_IA32_MC27_ADDR 0x0000046E\r
3669#define MSR_IA32_MC28_ADDR 0x00000472\r
3670/// @}\r
3671\r
3672\r
3673/**\r
3674 MCn_MISC. If IA32_MCG_CAP.CNT > n.\r
3675\r
3676 @param ECX MSR_IA32_MCn_MISC\r
3677 @param EAX Lower 32-bits of MSR value.\r
3678 @param EDX Upper 32-bits of MSR value.\r
3679\r
3680 <b>Example usage</b>\r
3681 @code\r
3682 UINT64 Msr;\r
3683\r
3684 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r
3685 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r
3686 @endcode\r
7de98828
JF		 3687 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.\r
3688 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.\r
3689 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.\r
3690 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.\r
3691 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.\r
3692 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.\r
3693 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
3694 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.\r
3695 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.\r
3696 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.\r
3697 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r
3698 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r
3699 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r
3700 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r
3701 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r
3702 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r
3703 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r
3704 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r
3705 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r
3706 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r
3707 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r
3708 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r
3709 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r
3710 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r
3711 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r
3712 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r
3713 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r
3714 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r
3715 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r
04c980a6
MK		 3716 @{\r
3717**/\r
3718#define MSR_IA32_MC0_MISC 0x00000403\r
3719#define MSR_IA32_MC1_MISC 0x00000407\r
3720#define MSR_IA32_MC2_MISC 0x0000040B\r
3721#define MSR_IA32_MC3_MISC 0x0000040F\r
3722#define MSR_IA32_MC4_MISC 0x00000413\r
3723#define MSR_IA32_MC5_MISC 0x00000417\r
3724#define MSR_IA32_MC6_MISC 0x0000041B\r
3725#define MSR_IA32_MC7_MISC 0x0000041F\r
3726#define MSR_IA32_MC8_MISC 0x00000423\r
3727#define MSR_IA32_MC9_MISC 0x00000427\r
3728#define MSR_IA32_MC10_MISC 0x0000042B\r
3729#define MSR_IA32_MC11_MISC 0x0000042F\r
3730#define MSR_IA32_MC12_MISC 0x00000433\r
3731#define MSR_IA32_MC13_MISC 0x00000437\r
3732#define MSR_IA32_MC14_MISC 0x0000043B\r
3733#define MSR_IA32_MC15_MISC 0x0000043F\r
3734#define MSR_IA32_MC16_MISC 0x00000443\r
3735#define MSR_IA32_MC17_MISC 0x00000447\r
3736#define MSR_IA32_MC18_MISC 0x0000044B\r
3737#define MSR_IA32_MC19_MISC 0x0000044F\r
3738#define MSR_IA32_MC20_MISC 0x00000453\r
3739#define MSR_IA32_MC21_MISC 0x00000457\r
3740#define MSR_IA32_MC22_MISC 0x0000045B\r
3741#define MSR_IA32_MC23_MISC 0x0000045F\r
3742#define MSR_IA32_MC24_MISC 0x00000463\r
3743#define MSR_IA32_MC25_MISC 0x00000467\r
3744#define MSR_IA32_MC26_MISC 0x0000046B\r
3745#define MSR_IA32_MC27_MISC 0x0000046F\r
3746#define MSR_IA32_MC28_MISC 0x00000473\r
3747/// @}\r
3748\r
3749\r
3750/**\r
3751 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r
3752 VMX Information.". If CPUID.01H:ECX.[5] = 1.\r
3753\r
3754 @param ECX MSR_IA32_VMX_BASIC (0x00000480)\r
3755 @param EAX Lower 32-bits of MSR value.\r
3756 @param EDX Upper 32-bits of MSR value.\r
3757\r
3758 <b>Example usage</b>\r
3759 @code\r
831d287a 3760 MSR_IA32_VMX_BASIC_REGISTER Msr;\r
04c980a6 3761\r
831d287a 3762 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r
04c980a6 3763 @endcode\r
7de98828 3764 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r
04c980a6
MK		 3765**/\r
3766#define MSR_IA32_VMX_BASIC 0x00000480\r
3767\r
831d287a
MK		 3768/**\r
3769 MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r
3770**/\r
3771typedef union {\r
3772 ///\r
3773 /// Individual bit fields\r
3774 ///\r
3775 struct {\r
3776 ///\r
3777 /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r
3778 /// that use the same VMCS revision identifier use the same size for VMCS\r
3779 /// regions (see subsequent item on bits 44:32).\r
3780 ///\r
3781 /// @note Earlier versions of this manual specified that the VMCS revision\r
3782 /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r
3783 /// processors produced prior to this change, bit 31 of this MSR was read\r
3784 /// as 0.\r
3785 ///\r
3786 UINT32 VmcsRevisonId:31;\r
3787 UINT32 MustBeZero:1;\r
3788 ///\r
3789 /// [Bit 44:32] Reports the number of bytes that software should allocate\r
3790 /// for the VMXON region and any VMCS region. It is a value greater than\r
3791 /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r
3792 ///\r
3793 UINT32 VmcsSize:13;\r
3794 UINT32 Reserved1:3;\r
3795 ///\r
3796 /// [Bit 48] Indicates the width of the physical addresses that may be used\r
3797 /// for the VMXON region, each VMCS, and data structures referenced by\r
3798 /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r
3799 /// transitions). If the bit is 0, these addresses are limited to the\r
3800 /// processor's physical-address width. If the bit is 1, these addresses\r
3801 /// are limited to 32 bits. This bit is always 0 for processors that\r
3802 /// support Intel 64 architecture.\r
3803 ///\r
3804 /// @note On processors that support Intel 64 architecture, the pointer\r
3805 /// must not set bits beyond the processor's physical address width.\r
3806 ///\r
3807 UINT32 VmcsAddressWidth:1;\r
3808 ///\r
3809 /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r
3810 /// dual-monitor treatment of system-management interrupts and\r
3811 /// system-management mode. See Section 34.15 for details of this treatment.\r
3812 ///\r
3813 UINT32 DualMonitor:1;\r
3814 ///\r
3815 /// [Bit 53:50] report the memory type that should be used for the VMCS,\r
3816 /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r
3817 /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r
3818 /// header. If software needs to access these data structures (e.g., to\r
3819 /// modify the contents of the MSR bitmaps), it can configure the paging\r
3820 /// structures to map them into the linear-address space. If it does so,\r
3821 /// it should establish mappings that use the memory type reported bits\r
3822 /// 53:50 in this MSR.\r
3823 ///\r
3824 /// As of this writing, all processors that support VMX operation indicate\r
3825 /// the write-back type.\r
3826 ///\r
3827 /// If software needs to access these data structures (e.g., to modify\r
3828 /// the contents of the MSR bitmaps), it can configure the paging\r
3829 /// structures to map them into the linear-address space. If it does so,\r
3830 /// it should establish mappings that use the memory type reported in this\r
3831 /// MSR.\r
3832 ///\r
3833 /// @note Alternatively, software may map any of these regions or\r
3834 /// structures with the UC memory type. (This may be necessary for the MSEG\r
3835 /// header.) Doing so is discouraged unless necessary as it will cause the\r
3836 /// performance of software accesses to those structures to suffer.\r
3837 ///\r
3838 ///\r
3839 UINT32 MemoryType:4;\r
3840 ///\r
0f16be6d
HW		 3841 /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
3842 /// the VM-exit instruction-information field on VM exitsdue to execution\r
3843 /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
3844 /// is done only if this bit is read as 1.\r
831d287a
MK		 3845 ///\r
3846 UINT32 InsOutsReporting:1;\r
3847 ///\r
3848 /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r
3849 /// be cleared to 0. See Appendix A.2 for details. It also reports support\r
3850 /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r
3851 /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r
3852 /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r
3853 /// Appendix A.4, and Appendix A.5 for details.\r
3854 ///\r
3855 UINT32 VmxControls:1;\r
3856 UINT32 Reserved2:8;\r
3857 } Bits;\r
3858 ///\r
3859 /// All bit fields as a 64-bit value\r
3860 ///\r
3861 UINT64 Uint64;\r
3862} MSR_IA32_VMX_BASIC_REGISTER;\r
3863\r
3864///\r
3865/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r
3866///\r
3867#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r
3868#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r
3869///\r
3870/// @}\r
3871///\r
3872\r
04c980a6
MK		 3873\r
3874/**\r
3875 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r
3876 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r
3877\r
3878 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r
3879 @param EAX Lower 32-bits of MSR value.\r
3880 @param EDX Upper 32-bits of MSR value.\r
3881\r
3882 <b>Example usage</b>\r
3883 @code\r
3884 UINT64 Msr;\r
3885\r
3886 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r
3887 @endcode\r
7de98828 3888 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r
04c980a6
MK		 3889**/\r
3890#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r
3891\r
3892\r
3893/**\r
3894 Capability Reporting Register of Primary Processor-based VM-execution\r
3895 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r
3896 Controls.". If CPUID.01H:ECX.[5] = 1.\r
3897\r
3898 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r
3899 @param EAX Lower 32-bits of MSR value.\r
3900 @param EDX Upper 32-bits of MSR value.\r
3901\r
3902 <b>Example usage</b>\r
3903 @code\r
3904 UINT64 Msr;\r
3905\r
3906 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r
3907 @endcode\r
7de98828 3908 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r
04c980a6
MK		 3909**/\r
3910#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r
3911\r
3912\r
3913/**\r
3914 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r
3915 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r
3916\r
3917 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r
3918 @param EAX Lower 32-bits of MSR value.\r
3919 @param EDX Upper 32-bits of MSR value.\r
3920\r
3921 <b>Example usage</b>\r
3922 @code\r
3923 UINT64 Msr;\r
3924\r
3925 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r
3926 @endcode\r
7de98828 3927 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r
04c980a6
MK		 3928**/\r
3929#define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r
3930\r
3931\r
3932/**\r
3933 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r
3934 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r
3935\r
3936 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r
3937 @param EAX Lower 32-bits of MSR value.\r
3938 @param EDX Upper 32-bits of MSR value.\r
3939\r
3940 <b>Example usage</b>\r
3941 @code\r
3942 UINT64 Msr;\r
3943\r
3944 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r
3945 @endcode\r
7de98828 3946 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r
04c980a6
MK		 3947**/\r
3948#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r
3949\r
3950\r
3951/**\r
3952 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r
3953 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r
3954\r
3955 @param ECX MSR_IA32_VMX_MISC (0x00000485)\r
3956 @param EAX Lower 32-bits of MSR value.\r
3957 @param EDX Upper 32-bits of MSR value.\r
3958\r
3959 <b>Example usage</b>\r
3960 @code\r
831d287a 3961 IA32_VMX_MISC_REGISTER Msr;\r
04c980a6 3962\r
831d287a 3963 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
04c980a6 3964 @endcode\r
7de98828 3965 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r
04c980a6
MK		 3966**/\r
3967#define MSR_IA32_VMX_MISC 0x00000485\r
3968\r
831d287a
MK		 3969/**\r
3970 MSR information returned for MSR index #IA32_VMX_MISC\r
3971**/\r
3972typedef union {\r
3973 ///\r
3974 /// Individual bit fields\r
3975 ///\r
3976 struct {\r
3977 ///\r
3978 /// [Bits 4:0] Reports a value X that specifies the relationship between the\r
3979 /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r
3980 /// Specifically, the VMX-preemption timer (if it is active) counts down by\r
3981 /// 1 every time bit X in the TSC changes due to a TSC increment.\r
3982 ///\r
3983 UINT32 VmxTimerRatio:5;\r
3984 ///\r
3985 /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r
3986 /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r
3987 /// details. This bit is read as 1 on any logical processor that supports\r
3988 /// the 1-setting of the "unrestricted guest" VM-execution control.\r
3989 ///\r
3990 UINT32 VmExitEferLma:1;\r
3991 ///\r
3992 /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r
3993 ///\r
3994 UINT32 HltActivityStateSupported:1;\r
3995 ///\r
3996 /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r
3997 ///\r
3998 UINT32 ShutdownActivityStateSupported:1;\r
3999 ///\r
4000 /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
4001 ///\r
4002 UINT32 WaitForSipiActivityStateSupported:1;\r
0f16be6d
HW		 4003 UINT32 Reserved1:5;\r
4004 ///\r
4005 /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
4006 /// in VMX operation. If the processor supports Intel PT but does not allow\r
4007 /// it to be used in VMX operation, execution of VMXON clears\r
3b4640ee 4008 /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);\r
0f16be6d
HW		 4009 /// any attempt to set that bit while in VMX operation (including VMX root\r
4010 /// operation) using the WRMSR instruction causes a general-protection\r
4011 /// exception.\r
4012 ///\r
4013 UINT32 ProcessorTraceSupported:1;\r
831d287a
MK		 4014 ///\r
4015 /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
4016 /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
0f16be6d 4017 /// See Section 34.15.6.3.\r
831d287a
MK		 4018 ///\r
4019 UINT32 SmBaseMsrSupported:1;\r
4020 ///\r
4021 /// [Bits 24:16] Indicate the number of CR3-target values supported by the\r
4022 /// processor. This number is a value between 0 and 256, inclusive (bit 24\r
4023 /// is set if and only if bits 23:16 are clear).\r
4024 ///\r
4025 UINT32 NumberOfCr3TargetValues:9;\r
4026 ///\r
4027 /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r
4028 /// number of MSRs that should appear in the VM-exit MSR-store list, the\r
4029 /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if\r
4030 /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the\r
4031 /// recommended maximum number of MSRs to be included in each list. If the\r
4032 /// limit is exceeded, undefined processor behavior may result (including a\r
4033 /// machine check during the VMX transition).\r
4034 ///\r
4035 UINT32 MsrStoreListMaximum:3;\r
4036 ///\r
4037 /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r
4038 /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r
4039 /// (see Section 34.14.4).\r
4040 ///\r
4041 UINT32 BlockSmiSupported:1;\r
4042 ///\r
4043 /// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r
4044 /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r
4045 /// information fields.\r
4046 ///\r
4047 UINT32 VmWriteSupported:1;\r
0f16be6d
HW		 4048 ///\r
4049 /// [Bit 30] If read as 1, VM entry allows injection of a software\r
4050 /// interrupt, software exception, or privileged software exception with an\r
4051 /// instruction length of 0.\r
4052 ///\r
4053 UINT32 VmInjectSupported:1;\r
4054 UINT32 Reserved2:1;\r
831d287a
MK		 4055 ///\r
4056 /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
4057 /// processor.\r
4058 ///\r
4059 UINT32 MsegRevisionIdentifier:32;\r
4060 } Bits;\r
4061 ///\r
4062 /// All bit fields as a 64-bit value\r
4063 ///\r
4064 UINT64 Uint64;\r
4065} IA32_VMX_MISC_REGISTER;\r
4066\r
04c980a6
MK		 4067\r
4068/**\r
4069 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r
4070 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
4071\r
4072 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)\r
4073 @param EAX Lower 32-bits of MSR value.\r
4074 @param EDX Upper 32-bits of MSR value.\r
4075\r
4076 <b>Example usage</b>\r
4077 @code\r
4078 UINT64 Msr;\r
4079\r
4080 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);\r
4081 @endcode\r
7de98828 4082 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r
04c980a6
MK		 4083**/\r
4084#define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r
4085\r
4086\r
4087/**\r
4088 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r
4089 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
4090\r
4091 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)\r
4092 @param EAX Lower 32-bits of MSR value.\r
4093 @param EDX Upper 32-bits of MSR value.\r
4094\r
4095 <b>Example usage</b>\r
4096 @code\r
4097 UINT64 Msr;\r
4098\r
4099 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);\r
4100 @endcode\r
7de98828 4101 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r
04c980a6
MK		 4102**/\r
4103#define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r
4104\r
4105\r
4106/**\r
4107 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r
4108 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r
4109\r
4110 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)\r
4111 @param EAX Lower 32-bits of MSR value.\r
4112 @param EDX Upper 32-bits of MSR value.\r
4113\r
4114 <b>Example usage</b>\r
4115 @code\r
4116 UINT64 Msr;\r
4117\r
4118 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);\r
4119 @endcode\r
7de98828 4120 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r
04c980a6
MK		 4121**/\r
4122#define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r
4123\r
4124\r
4125/**\r
4126 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r
4127 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.\r
4128\r
4129 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)\r
4130 @param EAX Lower 32-bits of MSR value.\r
4131 @param EDX Upper 32-bits of MSR value.\r
4132\r
4133 <b>Example usage</b>\r
4134 @code\r
4135 UINT64 Msr;\r
4136\r
4137 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);\r
4138 @endcode\r
7de98828 4139 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r
04c980a6
MK		 4140**/\r
4141#define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r
4142\r
4143\r
4144/**\r
4145 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r
4146 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.\r
4147\r
4148 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)\r
4149 @param EAX Lower 32-bits of MSR value.\r
4150 @param EDX Upper 32-bits of MSR value.\r
4151\r
4152 <b>Example usage</b>\r
4153 @code\r
4154 UINT64 Msr;\r
4155\r
4156 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);\r
4157 @endcode\r
7de98828 4158 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r
04c980a6
MK		 4159**/\r
4160#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r
4161\r
4162\r
4163/**\r
4164 Capability Reporting Register of Secondary Processor-based VM-execution\r
4165 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution\r
4166 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).\r
4167\r
4168 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)\r
4169 @param EAX Lower 32-bits of MSR value.\r
4170 @param EDX Upper 32-bits of MSR value.\r
4171\r
4172 <b>Example usage</b>\r
4173 @code\r
4174 UINT64 Msr;\r
4175\r
4176 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);\r
4177 @endcode\r
7de98828 4178 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r
04c980a6
MK		 4179**/\r
4180#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r
4181\r
4182\r
4183/**\r
4184 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,\r
4185 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C\r
4186 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).\r
4187\r
4188 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)\r
4189 @param EAX Lower 32-bits of MSR value.\r
4190 @param EDX Upper 32-bits of MSR value.\r
4191\r
4192 <b>Example usage</b>\r
4193 @code\r
4194 UINT64 Msr;\r
4195\r
4196 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);\r
4197 @endcode\r
7de98828 4198 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r
04c980a6
MK		 4199**/\r
4200#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r
4201\r
4202\r
4203/**\r
4204 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r
4205 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (\r
4206 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
4207\r
4208 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)\r
4209 @param EAX Lower 32-bits of MSR value.\r
4210 @param EDX Upper 32-bits of MSR value.\r
4211\r
4212 <b>Example usage</b>\r
4213 @code\r
4214 UINT64 Msr;\r
4215\r
4216 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);\r
4217 @endcode\r
7de98828 4218 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r
04c980a6
MK		 4219**/\r
4220#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r
4221\r
4222\r
4223/**\r
4224 Capability Reporting Register of Primary Processor-based VM-execution Flex\r
4225 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r
4226 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
4227\r
4228 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)\r
4229 @param EAX Lower 32-bits of MSR value.\r
4230 @param EDX Upper 32-bits of MSR value.\r
4231\r
4232 <b>Example usage</b>\r
4233 @code\r
4234 UINT64 Msr;\r
4235\r
4236 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);\r
4237 @endcode\r
7de98828 4238 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r
04c980a6
MK		 4239**/\r
4240#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r
4241\r
4242\r
4243/**\r
4244 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix\r
4245 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
4246\r
4247 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)\r
4248 @param EAX Lower 32-bits of MSR value.\r
4249 @param EDX Upper 32-bits of MSR value.\r
4250\r
4251 <b>Example usage</b>\r
4252 @code\r
4253 UINT64 Msr;\r
4254\r
4255 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);\r
4256 @endcode\r
7de98828 4257 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r
04c980a6
MK		 4258**/\r
4259#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r
4260\r
4261\r
4262/**\r
4263 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r
4264 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
4265\r
4266 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)\r
4267 @param EAX Lower 32-bits of MSR value.\r
4268 @param EDX Upper 32-bits of MSR value.\r
4269\r
4270 <b>Example usage</b>\r
4271 @code\r
4272 UINT64 Msr;\r
4273\r
4274 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);\r
4275 @endcode\r
7de98828 4276 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r
04c980a6
MK		 4277**/\r
4278#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r
4279\r
4280\r
4281/**\r
4282 Capability Reporting Register of VMfunction Controls (R/O). If(\r
4283 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).\r
4284\r
4285 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)\r
4286 @param EAX Lower 32-bits of MSR value.\r
4287 @param EDX Upper 32-bits of MSR value.\r
4288\r
4289 <b>Example usage</b>\r
4290 @code\r
4291 UINT64 Msr;\r
4292\r
4293 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);\r
4294 @endcode\r
7de98828 4295 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r
04c980a6
MK		 4296**/\r
4297#define MSR_IA32_VMX_VMFUNC 0x00000491\r
4298\r
4299\r
4300/**\r
4301 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r
4302 IA32_PERF_CAPABILITIES[ 13] = 1.\r
4303\r
4304 @param ECX MSR_IA32_A_PMCn\r
4305 @param EAX Lower 32-bits of MSR value.\r
4306 @param EDX Upper 32-bits of MSR value.\r
4307\r
4308 <b>Example usage</b>\r
4309 @code\r
4310 UINT64 Msr;\r
4311\r
4312 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);\r
4313 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);\r
4314 @endcode\r
7de98828
JF		 4315 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.\r
4316 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.\r
4317 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.\r
4318 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.\r
4319 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.\r
4320 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.\r
4321 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.\r
4322 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r
04c980a6
MK		 4323 @{\r
4324**/\r
4325#define MSR_IA32_A_PMC0 0x000004C1\r
4326#define MSR_IA32_A_PMC1 0x000004C2\r
4327#define MSR_IA32_A_PMC2 0x000004C3\r
4328#define MSR_IA32_A_PMC3 0x000004C4\r
4329#define MSR_IA32_A_PMC4 0x000004C5\r
4330#define MSR_IA32_A_PMC5 0x000004C6\r
4331#define MSR_IA32_A_PMC6 0x000004C7\r
4332#define MSR_IA32_A_PMC7 0x000004C8\r
4333/// @}\r
4334\r
4335\r
4336/**\r
4337 (R/W). If IA32_MCG_CAP.LMCE_P =1.\r
4338\r
4339 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)\r
4340 @param EAX Lower 32-bits of MSR value.\r
4341 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r
4342 @param EDX Upper 32-bits of MSR value.\r
4343 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.\r
4344\r
4345 <b>Example usage</b>\r
4346 @code\r
4347 MSR_IA32_MCG_EXT_CTL_REGISTER Msr;\r
4348\r
4349 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r
4350 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);\r
4351 @endcode\r
7de98828 4352 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r
04c980a6
MK		 4353**/\r
4354#define MSR_IA32_MCG_EXT_CTL 0x000004D0\r
4355\r
4356/**\r
4357 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r
4358**/\r
4359typedef union {\r
4360 ///\r
4361 /// Individual bit fields\r
4362 ///\r
4363 struct {\r
4364 ///\r
4365 /// [Bit 0] LMCE_EN.\r
4366 ///\r
4367 UINT32 LMCE_EN:1;\r
4368 UINT32 Reserved1:31;\r
4369 UINT32 Reserved2:32;\r
4370 } Bits;\r
4371 ///\r
4372 /// All bit fields as a 32-bit value\r
4373 ///\r
4374 UINT32 Uint32;\r
4375 ///\r
4376 /// All bit fields as a 64-bit value\r
4377 ///\r
4378 UINT64 Uint64;\r
4379} MSR_IA32_MCG_EXT_CTL_REGISTER;\r
4380\r
4381\r
4382/**\r
4383 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r
4384 ECX=0H): EBX[2] = 1.\r
4385\r
4386 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)\r
4387 @param EAX Lower 32-bits of MSR value.\r
4388 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r
4389 @param EDX Upper 32-bits of MSR value.\r
4390 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.\r
4391\r
4392 <b>Example usage</b>\r
4393 @code\r
4394 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;\r
4395\r
4396 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);\r
4397 @endcode\r
7de98828 4398 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r
04c980a6
MK		 4399**/\r
4400#define MSR_IA32_SGX_SVN_STATUS 0x00000500\r
4401\r
4402/**\r
4403 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r
4404**/\r
4405typedef union {\r
4406 ///\r
4407 /// Individual bit fields\r
4408 ///\r
4409 struct {\r
4410 ///\r
ba1a2d11 4411 /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated\r
04c980a6
MK		 4412 /// Code Modules (ACMs)".\r
4413 ///\r
4414 UINT32 Lock:1;\r
4415 UINT32 Reserved1:15;\r
4416 ///\r
ba1a2d11 4417 /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with\r
04c980a6
MK		 4418 /// Authenticated Code Modules (ACMs)".\r
4419 ///\r
4420 UINT32 SGX_SVN_SINIT:8;\r
4421 UINT32 Reserved2:8;\r
4422 UINT32 Reserved3:32;\r
4423 } Bits;\r
4424 ///\r
4425 /// All bit fields as a 32-bit value\r
4426 ///\r
4427 UINT32 Uint32;\r
4428 ///\r
4429 /// All bit fields as a 64-bit value\r
4430 ///\r
4431 UINT64 Uint64;\r
4432} MSR_IA32_SGX_SVN_STATUS_REGISTER;\r
4433\r
4434\r
4435/**\r
4436 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
4437 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r
4438 ) ).\r
4439\r
4440 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)\r
4441 @param EAX Lower 32-bits of MSR value.\r
4442 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r
4443 @param EDX Upper 32-bits of MSR value.\r
4444 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.\r
4445\r
4446 <b>Example usage</b>\r
4447 @code\r
4448 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;\r
4449\r
4450 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r
4451 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);\r
4452 @endcode\r
7de98828 4453 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r
04c980a6
MK		 4454**/\r
4455#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r
4456\r
4457/**\r
4458 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r
4459**/\r
4460typedef union {\r
4461 ///\r
4462 /// Individual bit fields\r
4463 ///\r
4464 struct {\r
4465 UINT32 Reserved:7;\r
4466 ///\r
4467 /// [Bits 31:7] Base physical address.\r
4468 ///\r
4469 UINT32 Base:25;\r
4470 ///\r
4471 /// [Bits 63:32] Base physical address.\r
4472 ///\r
4473 UINT32 BaseHi:32;\r
4474 } Bits;\r
4475 ///\r
4476 /// All bit fields as a 64-bit value\r
4477 ///\r
4478 UINT64 Uint64;\r
4479} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r
4480\r
4481\r
4482/**\r
4483 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r
4484 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r
4485 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).\r
4486\r
4487 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)\r
4488 @param EAX Lower 32-bits of MSR value.\r
4489 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r
4490 @param EDX Upper 32-bits of MSR value.\r
4491 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.\r
4492\r
4493 <b>Example usage</b>\r
4494 @code\r
4495 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;\r
4496\r
4497 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r
4498 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);\r
4499 @endcode\r
7de98828 4500 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r
04c980a6
MK		 4501**/\r
4502#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r
4503\r
4504/**\r
4505 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r
4506**/\r
4507typedef union {\r
4508 ///\r
4509 /// Individual bit fields\r
4510 ///\r
4511 struct {\r
4512 UINT32 Reserved:7;\r
4513 ///\r
4514 /// [Bits 31:7] MaskOrTableOffset.\r
4515 ///\r
4516 UINT32 MaskOrTableOffset:25;\r
4517 ///\r
4518 /// [Bits 63:32] Output Offset.\r
4519 ///\r
4520 UINT32 OutputOffset:32;\r
4521 } Bits;\r
4522 ///\r
4523 /// All bit fields as a 64-bit value\r
4524 ///\r
4525 UINT64 Uint64;\r
4526} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r
4527\r
a2e24a2a
ED		 4528/**\r
4529 Format of ToPA table entries.\r
4530**/\r
4531typedef union {\r
4532 ///\r
4533 /// Individual bit fields\r
4534 ///\r
4535 struct {\r
4536 ///\r
4537 /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
4538 ///\r
4539 UINT32 END:1;\r
4540 UINT32 Reserved1:1;\r
4541 ///\r
4542 /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
4543 ///\r
4544 UINT32 INT:1;\r
4545 UINT32 Reserved2:1;\r
4546 ///\r
4547 /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
4548 ///\r
4549 UINT32 STOP:1;\r
4550 UINT32 Reserved3:1;\r
4551 ///\r
4552 /// [Bit 6:9] Indicates the size of the associated output region. See Section\r
4553 /// 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
4554 ///\r
4555 UINT32 Size:4;\r
4556 UINT32 Reserved4:2;\r
4557 ///\r
4558 /// [Bit 12:31] Output Region Base Physical Address low part.\r
4559 /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.\r
4560 /// ATTENTION: The size of the address field is determined by the processor's\r
4561 /// physical-address width (MAXPHYADDR) in bits, as reported in\r
4562 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
4563 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
4564 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
4565 ///\r
4566 UINT32 Base:20;\r
4567 ///\r
4568 /// [Bit 32:63] Output Region Base Physical Address high part.\r
4569 /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.\r
4570 /// ATTENTION: The size of the address field is determined by the processor's\r
4571 /// physical-address width (MAXPHYADDR) in bits, as reported in\r
4572 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.\r
4573 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
4574 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
4575 ///\r
4576 UINT32 BaseHi:32;\r
4577 } Bits;\r
4578 ///\r
4579 /// All bit fields as a 64-bit value\r
4580 ///\r
4581 UINT64 Uint64;\r
4582} RTIT_TOPA_TABLE_ENTRY;\r
4583\r
4584///\r
4585/// The size of the associated output region usd by Topa.\r
4586///\r
4587typedef enum {\r
4588 RtitTopaMemorySize4K = 0,\r
4589 RtitTopaMemorySize8K,\r
4590 RtitTopaMemorySize16K,\r
4591 RtitTopaMemorySize32K,\r
4592 RtitTopaMemorySize64K,\r
4593 RtitTopaMemorySize128K,\r
4594 RtitTopaMemorySize256K,\r
4595 RtitTopaMemorySize512K,\r
4596 RtitTopaMemorySize1M,\r
4597 RtitTopaMemorySize2M,\r
4598 RtitTopaMemorySize4M,\r
4599 RtitTopaMemorySize8M,\r
4600 RtitTopaMemorySize16M,\r
4601 RtitTopaMemorySize32M,\r
4602 RtitTopaMemorySize64M,\r
4603 RtitTopaMemorySize128M\r
4604} RTIT_TOPA_MEMORY_SIZE;\r
04c980a6
MK		 4605\r
4606/**\r
4607 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
4608\r
4609 @param ECX MSR_IA32_RTIT_CTL (0x00000570)\r
4610 @param EAX Lower 32-bits of MSR value.\r
4611 Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r
4612 @param EDX Upper 32-bits of MSR value.\r
4613 Described by the type MSR_IA32_RTIT_CTL_REGISTER.\r
4614\r
4615 <b>Example usage</b>\r
4616 @code\r
4617 MSR_IA32_RTIT_CTL_REGISTER Msr;\r
4618\r
4619 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
4620 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);\r
4621 @endcode\r
7de98828 4622 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
04c980a6
MK		 4623**/\r
4624#define MSR_IA32_RTIT_CTL 0x00000570\r
4625\r
4626/**\r
4627 MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
4628**/\r
4629typedef union {\r
4630 ///\r
4631 /// Individual bit fields\r
4632 ///\r
4633 struct {\r
4634 ///\r
4635 /// [Bit 0] TraceEn.\r
4636 ///\r
4637 UINT32 TraceEn:1;\r
4638 ///\r
4639 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
4640 ///\r
4641 UINT32 CYCEn:1;\r
4642 ///\r
4643 /// [Bit 2] OS.\r
4644 ///\r
4645 UINT32 OS:1;\r
4646 ///\r
4647 /// [Bit 3] User.\r
4648 ///\r
4649 UINT32 User:1;\r
4382394a
ED		 4650 ///\r
4651 /// [Bit 4] PwrEvtEn.\r
4652 ///\r
4653 UINT32 PwrEvtEn:1;\r
4654 ///\r
4655 /// [Bit 5] FUPonPTW.\r
4656 ///\r
4657 UINT32 FUPonPTW:1;\r
04c980a6
MK		 4658 ///\r
4659 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r
4660 ///\r
4661 UINT32 FabricEn:1;\r
4662 ///\r
4663 /// [Bit 7] CR3 filter.\r
4664 ///\r
4665 UINT32 CR3:1;\r
4666 ///\r
4667 /// [Bit 8] ToPA.\r
4668 ///\r
4669 UINT32 ToPA:1;\r
4670 ///\r
4671 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
4672 ///\r
4673 UINT32 MTCEn:1;\r
4674 ///\r
4675 /// [Bit 10] TSCEn.\r
4676 ///\r
4677 UINT32 TSCEn:1;\r
4678 ///\r
4679 /// [Bit 11] DisRETC.\r
4680 ///\r
4681 UINT32 DisRETC:1;\r
4382394a
ED		 4682 ///\r
4683 /// [Bit 12] PTWEn.\r
4684 ///\r
4685 UINT32 PTWEn:1;\r
04c980a6
MK		 4686 ///\r
4687 /// [Bit 13] BranchEn.\r
4688 ///\r
4689 UINT32 BranchEn:1;\r
4690 ///\r
4691 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
4692 ///\r
4693 UINT32 MTCFreq:4;\r
4694 UINT32 Reserved3:1;\r
4695 ///\r
4696 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
4697 ///\r
4698 UINT32 CYCThresh:4;\r
4699 UINT32 Reserved4:1;\r
4700 ///\r
4701 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
4702 ///\r
4703 UINT32 PSBFreq:4;\r
4704 UINT32 Reserved5:4;\r
4705 ///\r
4706 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r
4707 ///\r
4708 UINT32 ADDR0_CFG:4;\r
4709 ///\r
4710 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r
4711 ///\r
4712 UINT32 ADDR1_CFG:4;\r
4713 ///\r
4714 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r
4715 ///\r
4716 UINT32 ADDR2_CFG:4;\r
4717 ///\r
4718 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r
4719 ///\r
4720 UINT32 ADDR3_CFG:4;\r
4721 UINT32 Reserved6:16;\r
4722 } Bits;\r
4723 ///\r
4724 /// All bit fields as a 64-bit value\r
4725 ///\r
4726 UINT64 Uint64;\r
4727} MSR_IA32_RTIT_CTL_REGISTER;\r
4728\r
4729\r
4730/**\r
4731 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
4732\r
4733 @param ECX MSR_IA32_RTIT_STATUS (0x00000571)\r
4734 @param EAX Lower 32-bits of MSR value.\r
4735 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r
4736 @param EDX Upper 32-bits of MSR value.\r
4737 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.\r
4738\r
4739 <b>Example usage</b>\r
4740 @code\r
4741 MSR_IA32_RTIT_STATUS_REGISTER Msr;\r
4742\r
4743 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);\r
4744 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);\r
4745 @endcode\r
7de98828 4746 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r
04c980a6
MK		 4747**/\r
4748#define MSR_IA32_RTIT_STATUS 0x00000571\r
4749\r
4750/**\r
4751 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r
4752**/\r
4753typedef union {\r
4754 ///\r
4755 /// Individual bit fields\r
4756 ///\r
4757 struct {\r
4758 ///\r
4759 /// [Bit 0] FilterEn, (writes ignored).\r
4760 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r
4761 ///\r
4762 UINT32 FilterEn:1;\r
4763 ///\r
4764 /// [Bit 1] ContexEn, (writes ignored).\r
4765 ///\r
4766 UINT32 ContexEn:1;\r
4767 ///\r
4768 /// [Bit 2] TriggerEn, (writes ignored).\r
4769 ///\r
4770 UINT32 TriggerEn:1;\r
4771 UINT32 Reserved1:1;\r
4772 ///\r
4773 /// [Bit 4] Error.\r
4774 ///\r
4775 UINT32 Error:1;\r
4776 ///\r
4777 /// [Bit 5] Stopped.\r
4778 ///\r
4779 UINT32 Stopped:1;\r
4780 UINT32 Reserved2:26;\r
4781 ///\r
4782 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r
4783 ///\r
4784 UINT32 PacketByteCnt:17;\r
4785 UINT32 Reserved3:15;\r
4786 } Bits;\r
4787 ///\r
4788 /// All bit fields as a 64-bit value\r
4789 ///\r
4790 UINT64 Uint64;\r
4791} MSR_IA32_RTIT_STATUS_REGISTER;\r
4792\r
4793\r
4794/**\r
4795 Trace Filter CR3 Match Register (R/W).\r
4796 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
4797\r
4798 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)\r
4799 @param EAX Lower 32-bits of MSR value.\r
4800 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r
4801 @param EDX Upper 32-bits of MSR value.\r
4802 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.\r
4803\r
4804 <b>Example usage</b>\r
4805 @code\r
4806 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;\r
4807\r
4808 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);\r
4809 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);\r
4810 @endcode\r
7de98828 4811 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r
04c980a6
MK		 4812**/\r
4813#define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r
4814\r
4815/**\r
4816 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r
4817**/\r
4818typedef union {\r
4819 ///\r
4820 /// Individual bit fields\r
4821 ///\r
4822 struct {\r
4823 UINT32 Reserved:5;\r
4824 ///\r
4825 /// [Bits 31:5] CR3[63:5] value to match.\r
4826 ///\r
4827 UINT32 Cr3:27;\r
4828 ///\r
4829 /// [Bits 63:32] CR3[63:5] value to match.\r
4830 ///\r
4831 UINT32 Cr3Hi:32;\r
4832 } Bits;\r
4833 ///\r
4834 /// All bit fields as a 64-bit value\r
4835 ///\r
4836 UINT64 Uint64;\r
4837} MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r
4838\r
4839\r
4840/**\r
4841 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
4842\r
4843 @param ECX MSR_IA32_RTIT_ADDRn_A\r
4844 @param EAX Lower 32-bits of MSR value.\r
4845 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
4846 @param EDX Upper 32-bits of MSR value.\r
4847 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
4848\r
4849 <b>Example usage</b>\r
4850 @code\r
4851 MSR_IA32_RTIT_ADDR_REGISTER Msr;\r
4852\r
4853 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);\r
4854 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);\r
4855 @endcode\r
7de98828
JF		 4856 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.\r
4857 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.\r
4858 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.\r
4859 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r
04c980a6
MK		 4860 @{\r
4861**/\r
4862#define MSR_IA32_RTIT_ADDR0_A 0x00000580\r
4863#define MSR_IA32_RTIT_ADDR1_A 0x00000582\r
4864#define MSR_IA32_RTIT_ADDR2_A 0x00000584\r
4865#define MSR_IA32_RTIT_ADDR3_A 0x00000586\r
4866/// @}\r
4867\r
4868\r
4869/**\r
4870 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
4871\r
4872 @param ECX MSR_IA32_RTIT_ADDRn_B\r
4873 @param EAX Lower 32-bits of MSR value.\r
4874 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
4875 @param EDX Upper 32-bits of MSR value.\r
4876 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.\r
4877\r
4878 <b>Example usage</b>\r
4879 @code\r
4880 MSR_IA32_RTIT_ADDR_REGISTER Msr;\r
4881\r
4882 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);\r
4883 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);\r
4884 @endcode\r
7de98828
JF		 4885 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.\r
4886 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.\r
4887 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.\r
4888 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r
04c980a6
MK		 4889 @{\r
4890**/\r
4891#define MSR_IA32_RTIT_ADDR0_B 0x00000581\r
4892#define MSR_IA32_RTIT_ADDR1_B 0x00000583\r
4893#define MSR_IA32_RTIT_ADDR2_B 0x00000585\r
4894#define MSR_IA32_RTIT_ADDR3_B 0x00000587\r
4895/// @}\r
4896\r
4897\r
4898/**\r
4899 MSR information returned for MSR indexes\r
4900 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r
4901 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B\r
4902**/\r
4903typedef union {\r
4904 ///\r
4905 /// Individual bit fields\r
4906 ///\r
4907 struct {\r
4908 ///\r
4909 /// [Bits 31:0] Virtual Address.\r
4910 ///\r
4911 UINT32 VirtualAddress:32;\r
4912 ///\r
4913 /// [Bits 47:32] Virtual Address.\r
4914 ///\r
4915 UINT32 VirtualAddressHi:16;\r
4916 ///\r
4917 /// [Bits 63:48] SignExt_VA.\r
4918 ///\r
4919 UINT32 SignExt_VA:16;\r
4920 } Bits;\r
4921 ///\r
4922 /// All bit fields as a 64-bit value\r
4923 ///\r
4924 UINT64 Uint64;\r
4925} MSR_IA32_RTIT_ADDR_REGISTER;\r
4926\r
4927\r
4928/**\r
ba1a2d11 4929 DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
04c980a6 4930 buffer management area, which is used to manage the BTS and PEBS buffers.\r
ba1a2d11
ED		 4931 See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(\r
4932 CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS\r
4933 buffer management area, if IA-32e mode is active.\r
04c980a6
MK		 4934\r
4935 @param ECX MSR_IA32_DS_AREA (0x00000600)\r
4936 @param EAX Lower 32-bits of MSR value.\r
4937 Described by the type MSR_IA32_DS_AREA_REGISTER.\r
4938 @param EDX Upper 32-bits of MSR value.\r
4939 Described by the type MSR_IA32_DS_AREA_REGISTER.\r
4940\r
4941 <b>Example usage</b>\r
4942 @code\r
4943 UINT64 Msr;\r
4944\r
4945 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);\r
4946 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);\r
4947 @endcode\r
7de98828 4948 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r
04c980a6
MK		 4949**/\r
4950#define MSR_IA32_DS_AREA 0x00000600\r
4951\r
4952\r
4953/**\r
4954 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r
4955 1.\r
4956\r
4957 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)\r
4958 @param EAX Lower 32-bits of MSR value.\r
4959 @param EDX Upper 32-bits of MSR value.\r
4960\r
4961 <b>Example usage</b>\r
4962 @code\r
4963 UINT64 Msr;\r
4964\r
4965 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);\r
4966 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);\r
4967 @endcode\r
7de98828 4968 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r
04c980a6
MK		 4969**/\r
4970#define MSR_IA32_TSC_DEADLINE 0x000006E0\r
4971\r
4972\r
4973/**\r
4974 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r
4975\r
4976 @param ECX MSR_IA32_PM_ENABLE (0x00000770)\r
4977 @param EAX Lower 32-bits of MSR value.\r
4978 Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r
4979 @param EDX Upper 32-bits of MSR value.\r
4980 Described by the type MSR_IA32_PM_ENABLE_REGISTER.\r
4981\r
4982 <b>Example usage</b>\r
4983 @code\r
4984 MSR_IA32_PM_ENABLE_REGISTER Msr;\r
4985\r
4986 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);\r
4987 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);\r
4988 @endcode\r
7de98828 4989 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r
04c980a6
MK		 4990**/\r
4991#define MSR_IA32_PM_ENABLE 0x00000770\r
4992\r
4993/**\r
4994 MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r
4995**/\r
4996typedef union {\r
4997 ///\r
4998 /// Individual bit fields\r
4999 ///\r
5000 struct {\r
5001 ///\r
5002 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r
5003 /// CPUID.06H:EAX.[7] = 1.\r
5004 ///\r
5005 UINT32 HWP_ENABLE:1;\r
5006 UINT32 Reserved1:31;\r
5007 UINT32 Reserved2:32;\r
5008 } Bits;\r
5009 ///\r
5010 /// All bit fields as a 32-bit value\r
5011 ///\r
5012 UINT32 Uint32;\r
5013 ///\r
5014 /// All bit fields as a 64-bit value\r
5015 ///\r
5016 UINT64 Uint64;\r
5017} MSR_IA32_PM_ENABLE_REGISTER;\r
5018\r
5019\r
5020/**\r
5021 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r
5022\r
5023 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)\r
5024 @param EAX Lower 32-bits of MSR value.\r
5025 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r
5026 @param EDX Upper 32-bits of MSR value.\r
5027 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.\r
5028\r
5029 <b>Example usage</b>\r
5030 @code\r
5031 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;\r
5032\r
5033 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);\r
5034 @endcode\r
7de98828 5035 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r
04c980a6
MK		 5036**/\r
5037#define MSR_IA32_HWP_CAPABILITIES 0x00000771\r
5038\r
5039/**\r
5040 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r
5041**/\r
5042typedef union {\r
5043 ///\r
5044 /// Individual bit fields\r
5045 ///\r
5046 struct {\r
5047 ///\r
5048 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r
5049 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
5050 ///\r
5051 UINT32 Highest_Performance:8;\r
5052 ///\r
5053 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r
5054 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
5055 ///\r
5056 UINT32 Guaranteed_Performance:8;\r
5057 ///\r
5058 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r
5059 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
5060 ///\r
5061 UINT32 Most_Efficient_Performance:8;\r
5062 ///\r
5063 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r
5064 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
5065 ///\r
5066 UINT32 Lowest_Performance:8;\r
5067 UINT32 Reserved:32;\r
5068 } Bits;\r
5069 ///\r
5070 /// All bit fields as a 32-bit value\r
5071 ///\r
5072 UINT32 Uint32;\r
5073 ///\r
5074 /// All bit fields as a 64-bit value\r
5075 ///\r
5076 UINT64 Uint64;\r
5077} MSR_IA32_HWP_CAPABILITIES_REGISTER;\r
5078\r
5079\r
5080/**\r
5081 Power Management Control Hints for All Logical Processors in a Package\r
5082 (R/W). If CPUID.06H:EAX.[11] = 1.\r
5083\r
5084 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)\r
5085 @param EAX Lower 32-bits of MSR value.\r
5086 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r
5087 @param EDX Upper 32-bits of MSR value.\r
5088 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.\r
5089\r
5090 <b>Example usage</b>\r
5091 @code\r
5092 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;\r
5093\r
5094 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);\r
5095 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);\r
5096 @endcode\r
7de98828 5097 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r
04c980a6
MK		 5098**/\r
5099#define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r
5100\r
5101/**\r
5102 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r
5103**/\r
5104typedef union {\r
5105 ///\r
5106 /// Individual bit fields\r
5107 ///\r
5108 struct {\r
5109 ///\r
5110 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
5111 /// CPUID.06H:EAX.[11] = 1.\r
5112 ///\r
5113 UINT32 Minimum_Performance:8;\r
5114 ///\r
5115 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
5116 /// CPUID.06H:EAX.[11] = 1.\r
5117 ///\r
5118 UINT32 Maximum_Performance:8;\r
5119 ///\r
5120 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
5121 /// If CPUID.06H:EAX.[11] = 1.\r
5122 ///\r
5123 UINT32 Desired_Performance:8;\r
5124 ///\r
5125 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
5126 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r
5127 ///\r
5128 UINT32 Energy_Performance_Preference:8;\r
5129 ///\r
5130 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
5131 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r
5132 ///\r
5133 UINT32 Activity_Window:10;\r
5134 UINT32 Reserved:22;\r
5135 } Bits;\r
5136 ///\r
5137 /// All bit fields as a 64-bit value\r
5138 ///\r
5139 UINT64 Uint64;\r
5140} MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r
5141\r
5142\r
5143/**\r
5144 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r
5145\r
5146 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)\r
5147 @param EAX Lower 32-bits of MSR value.\r
5148 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r
5149 @param EDX Upper 32-bits of MSR value.\r
5150 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.\r
5151\r
5152 <b>Example usage</b>\r
5153 @code\r
5154 MSR_IA32_HWP_INTERRUPT_REGISTER Msr;\r
5155\r
5156 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);\r
5157 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);\r
5158 @endcode\r
7de98828 5159 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r
04c980a6
MK		 5160**/\r
5161#define MSR_IA32_HWP_INTERRUPT 0x00000773\r
5162\r
5163/**\r
5164 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r
5165**/\r
5166typedef union {\r
5167 ///\r
5168 /// Individual bit fields\r
5169 ///\r
5170 struct {\r
5171 ///\r
5172 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r
5173 /// Notifications". If CPUID.06H:EAX.[8] = 1.\r
5174 ///\r
5175 UINT32 EN_Guaranteed_Performance_Change:1;\r
5176 ///\r
5177 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r
5178 /// If CPUID.06H:EAX.[8] = 1.\r
5179 ///\r
5180 UINT32 EN_Excursion_Minimum:1;\r
5181 UINT32 Reserved1:30;\r
5182 UINT32 Reserved2:32;\r
5183 } Bits;\r
5184 ///\r
5185 /// All bit fields as a 32-bit value\r
5186 ///\r
5187 UINT32 Uint32;\r
5188 ///\r
5189 /// All bit fields as a 64-bit value\r
5190 ///\r
5191 UINT64 Uint64;\r
5192} MSR_IA32_HWP_INTERRUPT_REGISTER;\r
5193\r
5194\r
5195/**\r
5196 Power Management Control Hints to a Logical Processor (R/W). If\r
5197 CPUID.06H:EAX.[7] = 1.\r
5198\r
5199 @param ECX MSR_IA32_HWP_REQUEST (0x00000774)\r
5200 @param EAX Lower 32-bits of MSR value.\r
5201 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r
5202 @param EDX Upper 32-bits of MSR value.\r
5203 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.\r
5204\r
5205 <b>Example usage</b>\r
5206 @code\r
5207 MSR_IA32_HWP_REQUEST_REGISTER Msr;\r
5208\r
5209 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);\r
5210 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);\r
5211 @endcode\r
7de98828 5212 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r
04c980a6
MK		 5213**/\r
5214#define MSR_IA32_HWP_REQUEST 0x00000774\r
5215\r
5216/**\r
5217 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r
5218**/\r
5219typedef union {\r
5220 ///\r
5221 /// Individual bit fields\r
5222 ///\r
5223 struct {\r
5224 ///\r
5225 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
5226 /// CPUID.06H:EAX.[7] = 1.\r
5227 ///\r
5228 UINT32 Minimum_Performance:8;\r
5229 ///\r
5230 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
5231 /// CPUID.06H:EAX.[7] = 1.\r
5232 ///\r
5233 UINT32 Maximum_Performance:8;\r
5234 ///\r
5235 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
5236 /// If CPUID.06H:EAX.[7] = 1.\r
5237 ///\r
5238 UINT32 Desired_Performance:8;\r
5239 ///\r
5240 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
5241 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r
5242 ///\r
5243 UINT32 Energy_Performance_Preference:8;\r
5244 ///\r
5245 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
5246 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r
5247 ///\r
5248 UINT32 Activity_Window:10;\r
5249 ///\r
5250 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r
5251 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r
5252 ///\r
5253 UINT32 Package_Control:1;\r
5254 UINT32 Reserved:21;\r
5255 } Bits;\r
5256 ///\r
5257 /// All bit fields as a 64-bit value\r
5258 ///\r
5259 UINT64 Uint64;\r
5260} MSR_IA32_HWP_REQUEST_REGISTER;\r
5261\r
5262\r
5263/**\r
5264 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If\r
5265 CPUID.06H:EAX.[7] = 1.\r
5266\r
5267 @param ECX MSR_IA32_HWP_STATUS (0x00000777)\r
5268 @param EAX Lower 32-bits of MSR value.\r
5269 Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r
5270 @param EDX Upper 32-bits of MSR value.\r
5271 Described by the type MSR_IA32_HWP_STATUS_REGISTER.\r
5272\r
5273 <b>Example usage</b>\r
5274 @code\r
5275 MSR_IA32_HWP_STATUS_REGISTER Msr;\r
5276\r
5277 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);\r
5278 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);\r
5279 @endcode\r
7de98828 5280 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r
04c980a6
MK		 5281**/\r
5282#define MSR_IA32_HWP_STATUS 0x00000777\r
5283\r
5284/**\r
5285 MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r
5286**/\r
5287typedef union {\r
5288 ///\r
5289 /// Individual bit fields\r
5290 ///\r
5291 struct {\r
5292 ///\r
5293 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r
5294 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r
5295 ///\r
5296 UINT32 Guaranteed_Performance_Change:1;\r
5297 UINT32 Reserved1:1;\r
5298 ///\r
5299 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r
5300 /// Feedback". If CPUID.06H:EAX.[7] = 1.\r
5301 ///\r
5302 UINT32 Excursion_To_Minimum:1;\r
5303 UINT32 Reserved2:29;\r
5304 UINT32 Reserved3:32;\r
5305 } Bits;\r
5306 ///\r
5307 /// All bit fields as a 32-bit value\r
5308 ///\r
5309 UINT32 Uint32;\r
5310 ///\r
5311 /// All bit fields as a 64-bit value\r
5312 ///\r
5313 UINT64 Uint64;\r
5314} MSR_IA32_HWP_STATUS_REGISTER;\r
5315\r
5316\r
5317/**\r
5318 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r
5319 && IA32_APIC_BASE.[10] = 1.\r
5320\r
5321 @param ECX MSR_IA32_X2APIC_APICID (0x00000802)\r
5322 @param EAX Lower 32-bits of MSR value.\r
5323 @param EDX Upper 32-bits of MSR value.\r
5324\r
5325 <b>Example usage</b>\r
5326 @code\r
5327 UINT64 Msr;\r
5328\r
5329 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);\r
5330 @endcode\r
7de98828 5331 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r
04c980a6
MK		 5332**/\r
5333#define MSR_IA32_X2APIC_APICID 0x00000802\r
5334\r
5335\r
5336/**\r
5337 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
5338 IA32_APIC_BASE.[10] = 1.\r
5339\r
5340 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)\r
5341 @param EAX Lower 32-bits of MSR value.\r
5342 @param EDX Upper 32-bits of MSR value.\r
5343\r
5344 <b>Example usage</b>\r
5345 @code\r
5346 UINT64 Msr;\r
5347\r
5348 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);\r
5349 @endcode\r
7de98828 5350 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r
04c980a6
MK		 5351**/\r
5352#define MSR_IA32_X2APIC_VERSION 0x00000803\r
5353\r
5354\r
5355/**\r
5356 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5357 IA32_APIC_BASE.[10] = 1.\r
5358\r
5359 @param ECX MSR_IA32_X2APIC_TPR (0x00000808)\r
5360 @param EAX Lower 32-bits of MSR value.\r
5361 @param EDX Upper 32-bits of MSR value.\r
5362\r
5363 <b>Example usage</b>\r
5364 @code\r
5365 UINT64 Msr;\r
5366\r
5367 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);\r
5368 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);\r
5369 @endcode\r
7de98828 5370 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r
04c980a6
MK		 5371**/\r
5372#define MSR_IA32_X2APIC_TPR 0x00000808\r
5373\r
5374\r
5375/**\r
5376 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
5377 IA32_APIC_BASE.[10] = 1.\r
5378\r
5379 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)\r
5380 @param EAX Lower 32-bits of MSR value.\r
5381 @param EDX Upper 32-bits of MSR value.\r
5382\r
5383 <b>Example usage</b>\r
5384 @code\r
5385 UINT64 Msr;\r
5386\r
5387 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);\r
5388 @endcode\r
7de98828 5389 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r
04c980a6
MK		 5390**/\r
5391#define MSR_IA32_X2APIC_PPR 0x0000080A\r
5392\r
5393\r
5394/**\r
5395 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r
5396 = 1.\r
5397\r
5398 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)\r
5399 @param EAX Lower 32-bits of MSR value.\r
5400 @param EDX Upper 32-bits of MSR value.\r
5401\r
5402 <b>Example usage</b>\r
5403 @code\r
5404 UINT64 Msr;\r
5405\r
5406 Msr = 0;\r
5407 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);\r
5408 @endcode\r
7de98828 5409 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r
04c980a6
MK		 5410**/\r
5411#define MSR_IA32_X2APIC_EOI 0x0000080B\r
5412\r
5413\r
5414/**\r
5415 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
5416 IA32_APIC_BASE.[10] = 1.\r
5417\r
5418 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)\r
5419 @param EAX Lower 32-bits of MSR value.\r
5420 @param EDX Upper 32-bits of MSR value.\r
5421\r
5422 <b>Example usage</b>\r
5423 @code\r
5424 UINT64 Msr;\r
5425\r
5426 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);\r
5427 @endcode\r
7de98828 5428 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r
04c980a6
MK		 5429**/\r
5430#define MSR_IA32_X2APIC_LDR 0x0000080D\r
5431\r
5432\r
5433/**\r
5434 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r
5435 && IA32_APIC_BASE.[10] = 1.\r
5436\r
5437 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)\r
5438 @param EAX Lower 32-bits of MSR value.\r
5439 @param EDX Upper 32-bits of MSR value.\r
5440\r
5441 <b>Example usage</b>\r
5442 @code\r
5443 UINT64 Msr;\r
5444\r
5445 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);\r
5446 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);\r
5447 @endcode\r
7de98828 5448 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r
04c980a6
MK		 5449**/\r
5450#define MSR_IA32_X2APIC_SIVR 0x0000080F\r
5451\r
5452\r
5453/**\r
5454 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r
5455 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
5456\r
5457 @param ECX MSR_IA32_X2APIC_ISRn\r
5458 @param EAX Lower 32-bits of MSR value.\r
5459 @param EDX Upper 32-bits of MSR value.\r
5460\r
5461 <b>Example usage</b>\r
5462 @code\r
5463 UINT64 Msr;\r
5464\r
5465 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);\r
5466 @endcode\r
7de98828
JF		 5467 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.\r
5468 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.\r
5469 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.\r
5470 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.\r
5471 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.\r
5472 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.\r
5473 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.\r
5474 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r
04c980a6
MK		 5475 @{\r
5476**/\r
5477#define MSR_IA32_X2APIC_ISR0 0x00000810\r
5478#define MSR_IA32_X2APIC_ISR1 0x00000811\r
5479#define MSR_IA32_X2APIC_ISR2 0x00000812\r
5480#define MSR_IA32_X2APIC_ISR3 0x00000813\r
5481#define MSR_IA32_X2APIC_ISR4 0x00000814\r
5482#define MSR_IA32_X2APIC_ISR5 0x00000815\r
5483#define MSR_IA32_X2APIC_ISR6 0x00000816\r
5484#define MSR_IA32_X2APIC_ISR7 0x00000817\r
5485/// @}\r
5486\r
5487\r
5488/**\r
5489 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r
5490 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
5491\r
5492 @param ECX MSR_IA32_X2APIC_TMRn\r
5493 @param EAX Lower 32-bits of MSR value.\r
5494 @param EDX Upper 32-bits of MSR value.\r
5495\r
5496 <b>Example usage</b>\r
5497 @code\r
5498 UINT64 Msr;\r
5499\r
5500 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);\r
5501 @endcode\r
7de98828
JF		 5502 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.\r
5503 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.\r
5504 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.\r
5505 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.\r
5506 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.\r
5507 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.\r
5508 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.\r
5509 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r
04c980a6
MK		 5510 @{\r
5511**/\r
5512#define MSR_IA32_X2APIC_TMR0 0x00000818\r
5513#define MSR_IA32_X2APIC_TMR1 0x00000819\r
5514#define MSR_IA32_X2APIC_TMR2 0x0000081A\r
5515#define MSR_IA32_X2APIC_TMR3 0x0000081B\r
5516#define MSR_IA32_X2APIC_TMR4 0x0000081C\r
5517#define MSR_IA32_X2APIC_TMR5 0x0000081D\r
5518#define MSR_IA32_X2APIC_TMR6 0x0000081E\r
5519#define MSR_IA32_X2APIC_TMR7 0x0000081F\r
5520/// @}\r
5521\r
5522\r
5523/**\r
5524 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r
5525 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
5526\r
5527 @param ECX MSR_IA32_X2APIC_IRRn\r
5528 @param EAX Lower 32-bits of MSR value.\r
5529 @param EDX Upper 32-bits of MSR value.\r
5530\r
5531 <b>Example usage</b>\r
5532 @code\r
5533 UINT64 Msr;\r
5534\r
5535 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);\r
5536 @endcode\r
7de98828
JF		 5537 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.\r
5538 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.\r
5539 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.\r
5540 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.\r
5541 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.\r
5542 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.\r
5543 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.\r
5544 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r
04c980a6
MK		 5545 @{\r
5546**/\r
5547#define MSR_IA32_X2APIC_IRR0 0x00000820\r
5548#define MSR_IA32_X2APIC_IRR1 0x00000821\r
5549#define MSR_IA32_X2APIC_IRR2 0x00000822\r
5550#define MSR_IA32_X2APIC_IRR3 0x00000823\r
5551#define MSR_IA32_X2APIC_IRR4 0x00000824\r
5552#define MSR_IA32_X2APIC_IRR5 0x00000825\r
5553#define MSR_IA32_X2APIC_IRR6 0x00000826\r
5554#define MSR_IA32_X2APIC_IRR7 0x00000827\r
5555/// @}\r
5556\r
5557\r
5558/**\r
5559 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5560 IA32_APIC_BASE.[10] = 1.\r
5561\r
5562 @param ECX MSR_IA32_X2APIC_ESR (0x00000828)\r
5563 @param EAX Lower 32-bits of MSR value.\r
5564 @param EDX Upper 32-bits of MSR value.\r
5565\r
5566 <b>Example usage</b>\r
5567 @code\r
5568 UINT64 Msr;\r
5569\r
5570 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);\r
5571 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);\r
5572 @endcode\r
7de98828 5573 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r
04c980a6
MK		 5574**/\r
5575#define MSR_IA32_X2APIC_ESR 0x00000828\r
5576\r
5577\r
5578/**\r
5579 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r
5580 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
5581\r
5582 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)\r
5583 @param EAX Lower 32-bits of MSR value.\r
5584 @param EDX Upper 32-bits of MSR value.\r
5585\r
5586 <b>Example usage</b>\r
5587 @code\r
5588 UINT64 Msr;\r
5589\r
5590 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);\r
5591 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);\r
5592 @endcode\r
7de98828 5593 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r
04c980a6
MK		 5594**/\r
5595#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r
5596\r
5597\r
5598/**\r
5599 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5600 IA32_APIC_BASE.[10] = 1.\r
5601\r
5602 @param ECX MSR_IA32_X2APIC_ICR (0x00000830)\r
5603 @param EAX Lower 32-bits of MSR value.\r
5604 @param EDX Upper 32-bits of MSR value.\r
5605\r
5606 <b>Example usage</b>\r
5607 @code\r
5608 UINT64 Msr;\r
5609\r
5610 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);\r
5611 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);\r
5612 @endcode\r
7de98828 5613 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r
04c980a6
MK		 5614**/\r
5615#define MSR_IA32_X2APIC_ICR 0x00000830\r
5616\r
5617\r
5618/**\r
5619 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5620 IA32_APIC_BASE.[10] = 1.\r
5621\r
5622 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)\r
5623 @param EAX Lower 32-bits of MSR value.\r
5624 @param EDX Upper 32-bits of MSR value.\r
5625\r
5626 <b>Example usage</b>\r
5627 @code\r
5628 UINT64 Msr;\r
5629\r
5630 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);\r
5631 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);\r
5632 @endcode\r
7de98828 5633 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r
04c980a6
MK		 5634**/\r
5635#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r
5636\r
5637\r
5638/**\r
5639 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r
5640 1 && IA32_APIC_BASE.[10] = 1.\r
5641\r
5642 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)\r
5643 @param EAX Lower 32-bits of MSR value.\r
5644 @param EDX Upper 32-bits of MSR value.\r
5645\r
5646 <b>Example usage</b>\r
5647 @code\r
5648 UINT64 Msr;\r
5649\r
5650 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);\r
5651 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);\r
5652 @endcode\r
7de98828 5653 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r
04c980a6
MK		 5654**/\r
5655#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r
5656\r
5657\r
5658/**\r
5659 x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r
5660 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
5661\r
5662 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)\r
5663 @param EAX Lower 32-bits of MSR value.\r
5664 @param EDX Upper 32-bits of MSR value.\r
5665\r
5666 <b>Example usage</b>\r
5667 @code\r
5668 UINT64 Msr;\r
5669\r
5670 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);\r
5671 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);\r
5672 @endcode\r
7de98828 5673 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r
04c980a6
MK		 5674**/\r
5675#define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r
5676\r
5677\r
5678/**\r
5679 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5680 IA32_APIC_BASE.[10] = 1.\r
5681\r
5682 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)\r
5683 @param EAX Lower 32-bits of MSR value.\r
5684 @param EDX Upper 32-bits of MSR value.\r
5685\r
5686 <b>Example usage</b>\r
5687 @code\r
5688 UINT64 Msr;\r
5689\r
5690 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);\r
5691 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);\r
5692 @endcode\r
7de98828 5693 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r
04c980a6
MK		 5694**/\r
5695#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r
5696\r
5697\r
5698/**\r
5699 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5700 IA32_APIC_BASE.[10] = 1.\r
5701\r
5702 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)\r
5703 @param EAX Lower 32-bits of MSR value.\r
5704 @param EDX Upper 32-bits of MSR value.\r
5705\r
5706 <b>Example usage</b>\r
5707 @code\r
5708 UINT64 Msr;\r
5709\r
5710 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);\r
5711 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);\r
5712 @endcode\r
7de98828 5713 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r
04c980a6
MK		 5714**/\r
5715#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r
5716\r
5717\r
5718/**\r
5719 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5720 IA32_APIC_BASE.[10] = 1.\r
5721\r
5722 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)\r
5723 @param EAX Lower 32-bits of MSR value.\r
5724 @param EDX Upper 32-bits of MSR value.\r
5725\r
5726 <b>Example usage</b>\r
5727 @code\r
5728 UINT64 Msr;\r
5729\r
5730 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);\r
5731 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);\r
5732 @endcode\r
7de98828 5733 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r
04c980a6
MK		 5734**/\r
5735#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r
5736\r
5737\r
5738/**\r
5739 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5740 IA32_APIC_BASE.[10] = 1.\r
5741\r
5742 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)\r
5743 @param EAX Lower 32-bits of MSR value.\r
5744 @param EDX Upper 32-bits of MSR value.\r
5745\r
5746 <b>Example usage</b>\r
5747 @code\r
5748 UINT64 Msr;\r
5749\r
5750 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);\r
5751 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);\r
5752 @endcode\r
7de98828 5753 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r
04c980a6
MK		 5754**/\r
5755#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r
5756\r
5757\r
5758/**\r
5759 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
5760 IA32_APIC_BASE.[10] = 1.\r
5761\r
5762 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)\r
5763 @param EAX Lower 32-bits of MSR value.\r
5764 @param EDX Upper 32-bits of MSR value.\r
5765\r
5766 <b>Example usage</b>\r
5767 @code\r
5768 UINT64 Msr;\r
5769\r
5770 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);\r
5771 @endcode\r
7de98828 5772 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r
04c980a6
MK		 5773**/\r
5774#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r
5775\r
5776\r
5777/**\r
5778 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
5779 IA32_APIC_BASE.[10] = 1.\r
5780\r
5781 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)\r
5782 @param EAX Lower 32-bits of MSR value.\r
5783 @param EDX Upper 32-bits of MSR value.\r
5784\r
5785 <b>Example usage</b>\r
5786 @code\r
5787 UINT64 Msr;\r
5788\r
5789 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);\r
5790 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);\r
5791 @endcode\r
7de98828 5792 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r
04c980a6
MK		 5793**/\r
5794#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r
5795\r
5796\r
5797/**\r
5798 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r
5799 IA32_APIC_BASE.[10] = 1.\r
5800\r
5801 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)\r
5802 @param EAX Lower 32-bits of MSR value.\r
5803 @param EDX Upper 32-bits of MSR value.\r
5804\r
5805 <b>Example usage</b>\r
5806 @code\r
5807 UINT64 Msr;\r
5808\r
5809 Msr = 0;\r
5810 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);\r
5811 @endcode\r
7de98828 5812 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r
04c980a6
MK		 5813**/\r
5814#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r
5815\r
5816\r
5817/**\r
5818 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r
5819\r
5820 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)\r
5821 @param EAX Lower 32-bits of MSR value.\r
5822 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r
5823 @param EDX Upper 32-bits of MSR value.\r
5824 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.\r
5825\r
5826 <b>Example usage</b>\r
5827 @code\r
5828 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;\r
5829\r
5830 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);\r
5831 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);\r
5832 @endcode\r
7de98828 5833 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r
04c980a6
MK		 5834**/\r
5835#define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r
5836\r
5837/**\r
5838 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r
5839**/\r
5840typedef union {\r
5841 ///\r
5842 /// Individual bit fields\r
5843 ///\r
5844 struct {\r
5845 ///\r
5846 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r
5847 /// Default is 0. If CPUID.01H:ECX.[11] = 1.\r
5848 ///\r
5849 UINT32 Enable:1;\r
5850 UINT32 Reserved1:29;\r
5851 ///\r
5852 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r
5853 /// lock bit is set automatically on the first SMI assertion even if not\r
5854 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
5855 ///\r
5856 UINT32 Lock:1;\r
5857 ///\r
5858 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r
5859 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
5860 ///\r
5861 UINT32 DebugOccurred:1;\r
5862 UINT32 Reserved2:32;\r
5863 } Bits;\r
5864 ///\r
5865 /// All bit fields as a 32-bit value\r
5866 ///\r
5867 UINT32 Uint32;\r
5868 ///\r
5869 /// All bit fields as a 64-bit value\r
5870 ///\r
5871 UINT64 Uint64;\r
5872} MSR_IA32_DEBUG_INTERFACE_REGISTER;\r
5873\r
5874\r
5875/**\r
5876 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r
5877\r
5878 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)\r
5879 @param EAX Lower 32-bits of MSR value.\r
5880 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r
5881 @param EDX Upper 32-bits of MSR value.\r
5882 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.\r
5883\r
5884 <b>Example usage</b>\r
5885 @code\r
5886 MSR_IA32_L3_QOS_CFG_REGISTER Msr;\r
5887\r
5888 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);\r
5889 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);\r
5890 @endcode\r
7de98828 5891 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
04c980a6
MK		 5892**/\r
5893#define MSR_IA32_L3_QOS_CFG 0x00000C81\r
5894\r
5895/**\r
5896 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r
5897**/\r
5898typedef union {\r
5899 ///\r
5900 /// Individual bit fields\r
5901 ///\r
5902 struct {\r
5903 ///\r
5904 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r
5905 /// in Code and Data Prioritization (CDP) mode.\r
5906 ///\r
5907 UINT32 Enable:1;\r
5908 UINT32 Reserved1:31;\r
5909 UINT32 Reserved2:32;\r
5910 } Bits;\r
5911 ///\r
5912 /// All bit fields as a 32-bit value\r
5913 ///\r
5914 UINT32 Uint32;\r
5915 ///\r
5916 /// All bit fields as a 64-bit value\r
5917 ///\r
5918 UINT64 Uint64;\r
5919} MSR_IA32_L3_QOS_CFG_REGISTER;\r
5920\r
d05b288a
ED		 5921/**\r
5922 L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).\r
5923\r
5924 @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)\r
5925 @param EAX Lower 32-bits of MSR value.\r
5926 Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
5927 @param EDX Upper 32-bits of MSR value.\r
5928 Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.\r
5929\r
5930 <b>Example usage</b>\r
5931 @code\r
5932 MSR_IA32_L2_QOS_CFG_REGISTER Msr;\r
5933\r
5934 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);\r
5935 AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);\r
5936 @endcode\r
5937 @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.\r
5938**/\r
5939#define MSR_IA32_L2_QOS_CFG 0x00000C82\r
5940\r
5941/**\r
5942 MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG\r
5943**/\r
5944typedef union {\r
5945 ///\r
5946 /// Individual bit fields\r
5947 ///\r
5948 struct {\r
5949 ///\r
5950 /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate\r
5951 /// in Code and Data Prioritization (CDP) mode.\r
5952 ///\r
5953 UINT32 Enable:1;\r
5954 UINT32 Reserved1:31;\r
5955 UINT32 Reserved2:32;\r
5956 } Bits;\r
5957 ///\r
5958 /// All bit fields as a 32-bit value\r
5959 ///\r
5960 UINT32 Uint32;\r
5961 ///\r
5962 /// All bit fields as a 64-bit value\r
5963 ///\r
5964 UINT64 Uint64;\r
5965} MSR_IA32_L2_QOS_CFG_REGISTER;\r
04c980a6
MK		 5966\r
5967/**\r
5968 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]\r
5969 = 1 ).\r
5970\r
5971 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)\r
5972 @param EAX Lower 32-bits of MSR value.\r
5973 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r
5974 @param EDX Upper 32-bits of MSR value.\r
5975 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.\r
5976\r
5977 <b>Example usage</b>\r
5978 @code\r
5979 MSR_IA32_QM_EVTSEL_REGISTER Msr;\r
5980\r
5981 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);\r
5982 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);\r
5983 @endcode\r
7de98828 5984 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
04c980a6
MK		 5985**/\r
5986#define MSR_IA32_QM_EVTSEL 0x00000C8D\r
5987\r
5988/**\r
5989 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r
5990**/\r
5991typedef union {\r
5992 ///\r
5993 /// Individual bit fields\r
5994 ///\r
5995 struct {\r
5996 ///\r
5997 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r
5998 /// IA32_QM_CTR.\r
5999 ///\r
6000 UINT32 EventID:8;\r
6001 UINT32 Reserved:24;\r
6002 ///\r
6003 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r
6004 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r
6005 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
6006 ///\r
6007 UINT32 ResourceMonitoringID:32;\r
6008 } Bits;\r
6009 ///\r
6010 /// All bit fields as a 64-bit value\r
6011 ///\r
6012 UINT64 Uint64;\r
6013} MSR_IA32_QM_EVTSEL_REGISTER;\r
6014\r
6015\r
6016/**\r
6017 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r
6018 ).\r
6019\r
6020 @param ECX MSR_IA32_QM_CTR (0x00000C8E)\r
6021 @param EAX Lower 32-bits of MSR value.\r
6022 Described by the type MSR_IA32_QM_CTR_REGISTER.\r
6023 @param EDX Upper 32-bits of MSR value.\r
6024 Described by the type MSR_IA32_QM_CTR_REGISTER.\r
6025\r
6026 <b>Example usage</b>\r
6027 @code\r
6028 MSR_IA32_QM_CTR_REGISTER Msr;\r
6029\r
6030 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);\r
6031 @endcode\r
7de98828 6032 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r
04c980a6
MK		 6033**/\r
6034#define MSR_IA32_QM_CTR 0x00000C8E\r
6035\r
6036/**\r
6037 MSR information returned for MSR index #MSR_IA32_QM_CTR\r
6038**/\r
6039typedef union {\r
6040 ///\r
6041 /// Individual bit fields\r
6042 ///\r
6043 struct {\r
6044 ///\r
6045 /// [Bits 31:0] Resource Monitored Data.\r
6046 ///\r
6047 UINT32 ResourceMonitoredData:32;\r
6048 ///\r
6049 /// [Bits 61:32] Resource Monitored Data.\r
6050 ///\r
6051 UINT32 ResourceMonitoredDataHi:30;\r
6052 ///\r
6053 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r
6054 /// available or not monitored for this resource or RMID.\r
6055 ///\r
6056 UINT32 Unavailable:1;\r
6057 ///\r
6058 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r
6059 /// written to IA32_PQR_QM_EVTSEL.\r
6060 ///\r
6061 UINT32 Error:1;\r
6062 } Bits;\r
6063 ///\r
6064 /// All bit fields as a 64-bit value\r
6065 ///\r
6066 UINT64 Uint64;\r
6067} MSR_IA32_QM_CTR_REGISTER;\r
6068\r
6069\r
6070/**\r
0f16be6d
HW		 6071 Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
6072 =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
04c980a6
MK		 6073\r
6074 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)\r
6075 @param EAX Lower 32-bits of MSR value.\r
6076 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r
6077 @param EDX Upper 32-bits of MSR value.\r
6078 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.\r
6079\r
6080 <b>Example usage</b>\r
6081 @code\r
6082 MSR_IA32_PQR_ASSOC_REGISTER Msr;\r
6083\r
6084 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);\r
6085 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);\r
6086 @endcode\r
7de98828 6087 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
04c980a6
MK		 6088**/\r
6089#define MSR_IA32_PQR_ASSOC 0x00000C8F\r
6090\r
6091/**\r
6092 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r
6093**/\r
6094typedef union {\r
6095 ///\r
6096 /// Individual bit fields\r
6097 ///\r
6098 struct {\r
6099 ///\r
6100 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware\r
6101 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r
6102 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
6103 ///\r
6104 UINT32 ResourceMonitoringID:32;\r
6105 ///\r
6106 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r
6107 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r
6108 /// ECX=0):EBX.[15] = 1 ).\r
6109 ///\r
6110 UINT32 COS:32;\r
6111 } Bits;\r
6112 ///\r
6113 /// All bit fields as a 64-bit value\r
6114 ///\r
6115 UINT64 Uint64;\r
6116} MSR_IA32_PQR_ASSOC_REGISTER;\r
6117\r
6118\r
6119/**\r
6120 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r
6121 ECX=0H):EBX[14] = 1).\r
6122\r
6123 @param ECX MSR_IA32_BNDCFGS (0x00000D90)\r
6124 @param EAX Lower 32-bits of MSR value.\r
6125 Described by the type MSR_IA32_BNDCFGS_REGISTER.\r
6126 @param EDX Upper 32-bits of MSR value.\r
6127 Described by the type MSR_IA32_BNDCFGS_REGISTER.\r
6128\r
6129 <b>Example usage</b>\r
6130 @code\r
6131 MSR_IA32_BNDCFGS_REGISTER Msr;\r
6132\r
6133 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);\r
6134 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);\r
6135 @endcode\r
7de98828 6136 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r
04c980a6
MK		 6137**/\r
6138#define MSR_IA32_BNDCFGS 0x00000D90\r
6139\r
6140/**\r
6141 MSR information returned for MSR index #MSR_IA32_BNDCFGS\r
6142**/\r
6143typedef union {\r
6144 ///\r
6145 /// Individual bit fields\r
6146 ///\r
6147 struct {\r
6148 ///\r
6149 /// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r
6150 ///\r
6151 UINT32 EN:1;\r
6152 ///\r
6153 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r
6154 /// instructions in the absence of the BND prefix.\r
6155 ///\r
6156 UINT32 BNDPRESERVE:1;\r
6157 UINT32 Reserved:10;\r
6158 ///\r
6159 /// [Bits 31:12] Base Address of Bound Directory.\r
6160 ///\r
6161 UINT32 Base:20;\r
6162 ///\r
6163 /// [Bits 63:32] Base Address of Bound Directory.\r
6164 ///\r
6165 UINT32 BaseHi:32;\r
6166 } Bits;\r
6167 ///\r
6168 /// All bit fields as a 64-bit value\r
6169 ///\r
6170 UINT64 Uint64;\r
6171} MSR_IA32_BNDCFGS_REGISTER;\r
6172\r
6173\r
6174/**\r
6175 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r
6176\r
6177 @param ECX MSR_IA32_XSS (0x00000DA0)\r
6178 @param EAX Lower 32-bits of MSR value.\r
6179 Described by the type MSR_IA32_XSS_REGISTER.\r
6180 @param EDX Upper 32-bits of MSR value.\r
6181 Described by the type MSR_IA32_XSS_REGISTER.\r
6182\r
6183 <b>Example usage</b>\r
6184 @code\r
6185 MSR_IA32_XSS_REGISTER Msr;\r
6186\r
6187 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);\r
6188 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);\r
6189 @endcode\r
7de98828 6190 @note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r
04c980a6
MK		 6191**/\r
6192#define MSR_IA32_XSS 0x00000DA0\r
6193\r
6194/**\r
6195 MSR information returned for MSR index #MSR_IA32_XSS\r
6196**/\r
6197typedef union {\r
6198 ///\r
6199 /// Individual bit fields\r
6200 ///\r
6201 struct {\r
6202 UINT32 Reserved1:8;\r
6203 ///\r
6204 /// [Bit 8] Trace Packet Configuration State (R/W).\r
6205 ///\r
6206 UINT32 TracePacketConfigurationState:1;\r
6207 UINT32 Reserved2:23;\r
6208 UINT32 Reserved3:32;\r
6209 } Bits;\r
6210 ///\r
6211 /// All bit fields as a 32-bit value\r
6212 ///\r
6213 UINT32 Uint32;\r
6214 ///\r
6215 /// All bit fields as a 64-bit value\r
6216 ///\r
6217 UINT64 Uint64;\r
6218} MSR_IA32_XSS_REGISTER;\r
6219\r
6220\r
6221/**\r
6222 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r
6223\r
6224 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)\r
6225 @param EAX Lower 32-bits of MSR value.\r
6226 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r
6227 @param EDX Upper 32-bits of MSR value.\r
6228 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.\r
6229\r
6230 <b>Example usage</b>\r
6231 @code\r
6232 MSR_IA32_PKG_HDC_CTL_REGISTER Msr;\r
6233\r
6234 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);\r
6235 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);\r
6236 @endcode\r
7de98828 6237 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r
04c980a6
MK		 6238**/\r
6239#define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r
6240\r
6241/**\r
6242 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r
6243**/\r
6244typedef union {\r
6245 ///\r
6246 /// Individual bit fields\r
6247 ///\r
6248 struct {\r
6249 ///\r
6250 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled\r
6251 /// logical processors in the package. See Section 14.5.2, "Package level\r
6252 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r
6253 ///\r
6254 UINT32 HDC_Pkg_Enable:1;\r
6255 UINT32 Reserved1:31;\r
6256 UINT32 Reserved2:32;\r
6257 } Bits;\r
6258 ///\r
6259 /// All bit fields as a 32-bit value\r
6260 ///\r
6261 UINT32 Uint32;\r
6262 ///\r
6263 /// All bit fields as a 64-bit value\r
6264 ///\r
6265 UINT64 Uint64;\r
6266} MSR_IA32_PKG_HDC_CTL_REGISTER;\r
6267\r
6268\r
6269/**\r
6270 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r
6271\r
6272 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)\r
6273 @param EAX Lower 32-bits of MSR value.\r
6274 Described by the type MSR_IA32_PM_CTL1_REGISTER.\r
6275 @param EDX Upper 32-bits of MSR value.\r
6276 Described by the type MSR_IA32_PM_CTL1_REGISTER.\r
6277\r
6278 <b>Example usage</b>\r
6279 @code\r
6280 MSR_IA32_PM_CTL1_REGISTER Msr;\r
6281\r
6282 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);\r
6283 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);\r
6284 @endcode\r
7de98828 6285 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r
04c980a6
MK		 6286**/\r
6287#define MSR_IA32_PM_CTL1 0x00000DB1\r
6288\r
6289/**\r
6290 MSR information returned for MSR index #MSR_IA32_PM_CTL1\r
6291**/\r
6292typedef union {\r
6293 ///\r
6294 /// Individual bit fields\r
6295 ///\r
6296 struct {\r
6297 ///\r
6298 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for\r
6299 /// package level HDC control. See Section 14.5.3.\r
6300 /// If CPUID.06H:EAX.[13] = 1.\r
6301 ///\r
6302 UINT32 HDC_Allow_Block:1;\r
6303 UINT32 Reserved1:31;\r
6304 UINT32 Reserved2:32;\r
6305 } Bits;\r
6306 ///\r
6307 /// All bit fields as a 32-bit value\r
6308 ///\r
6309 UINT32 Uint32;\r
6310 ///\r
6311 /// All bit fields as a 64-bit value\r
6312 ///\r
6313 UINT64 Uint64;\r
6314} MSR_IA32_PM_CTL1_REGISTER;\r
6315\r
6316\r
6317/**\r
6318 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r
6319 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r
6320 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.\r
6321\r
6322 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)\r
6323 @param EAX Lower 32-bits of MSR value.\r
6324 @param EDX Upper 32-bits of MSR value.\r
6325\r
6326 <b>Example usage</b>\r
6327 @code\r
6328 UINT64 Msr;\r
6329\r
6330 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);\r
6331 @endcode\r
7de98828 6332 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r
04c980a6
MK		 6333**/\r
6334#define MSR_IA32_THREAD_STALL 0x00000DB2\r
6335\r
6336\r
6337/**\r
6338 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r
6339 CPUID.80000001H:EDX.[2 9]).\r
6340\r
6341 @param ECX MSR_IA32_EFER (0xC0000080)\r
6342 @param EAX Lower 32-bits of MSR value.\r
6343 Described by the type MSR_IA32_EFER_REGISTER.\r
6344 @param EDX Upper 32-bits of MSR value.\r
6345 Described by the type MSR_IA32_EFER_REGISTER.\r
6346\r
6347 <b>Example usage</b>\r
6348 @code\r
6349 MSR_IA32_EFER_REGISTER Msr;\r
6350\r
6351 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
6352 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);\r
6353 @endcode\r
7de98828 6354 @note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r
04c980a6
MK		 6355**/\r
6356#define MSR_IA32_EFER 0xC0000080\r
6357\r
6358/**\r
6359 MSR information returned for MSR index #MSR_IA32_EFER\r
6360**/\r
6361typedef union {\r
6362 ///\r
6363 /// Individual bit fields\r
6364 ///\r
6365 struct {\r
6366 ///\r
6367 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r
6368 /// instructions in 64-bit mode.\r
6369 ///\r
6370 UINT32 SCE:1;\r
6371 UINT32 Reserved1:7;\r
6372 ///\r
6373 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r
6374 /// operation.\r
6375 ///\r
6376 UINT32 LME:1;\r
6377 UINT32 Reserved2:1;\r
6378 ///\r
6379 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r
6380 /// is active when set.\r
6381 ///\r
6382 UINT32 LMA:1;\r
6383 ///\r
6384 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r
6385 ///\r
6386 UINT32 NXE:1;\r
6387 UINT32 Reserved3:20;\r
6388 UINT32 Reserved4:32;\r
6389 } Bits;\r
6390 ///\r
6391 /// All bit fields as a 32-bit value\r
6392 ///\r
6393 UINT32 Uint32;\r
6394 ///\r
6395 /// All bit fields as a 64-bit value\r
6396 ///\r
6397 UINT64 Uint64;\r
6398} MSR_IA32_EFER_REGISTER;\r
6399\r
6400\r
6401/**\r
6402 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
6403\r
6404 @param ECX MSR_IA32_STAR (0xC0000081)\r
6405 @param EAX Lower 32-bits of MSR value.\r
6406 @param EDX Upper 32-bits of MSR value.\r
6407\r
6408 <b>Example usage</b>\r
6409 @code\r
6410 UINT64 Msr;\r
6411\r
6412 Msr = AsmReadMsr64 (MSR_IA32_STAR);\r
6413 AsmWriteMsr64 (MSR_IA32_STAR, Msr);\r
6414 @endcode\r
7de98828 6415 @note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r
04c980a6
MK		 6416**/\r
6417#define MSR_IA32_STAR 0xC0000081\r
6418\r
6419\r
6420/**\r
6421 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
6422\r
6423 @param ECX MSR_IA32_LSTAR (0xC0000082)\r
6424 @param EAX Lower 32-bits of MSR value.\r
6425 @param EDX Upper 32-bits of MSR value.\r
6426\r
6427 <b>Example usage</b>\r
6428 @code\r
6429 UINT64 Msr;\r
6430\r
6431 Msr = AsmReadMsr64 (MSR_IA32_LSTAR);\r
6432 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);\r
6433 @endcode\r
7de98828 6434 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r
04c980a6
MK		 6435**/\r
6436#define MSR_IA32_LSTAR 0xC0000082\r
6437\r
d05b288a
ED		 6438/**\r
6439 IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL\r
6440 instruction is not recognized in compatibility mode. If\r
6441 CPUID.80000001:EDX.[29] = 1.\r
6442\r
6443 @param ECX MSR_IA32_CSTAR (0xC0000083)\r
6444 @param EAX Lower 32-bits of MSR value.\r
6445 @param EDX Upper 32-bits of MSR value.\r
6446\r
6447 <b>Example usage</b>\r
6448 @code\r
6449 UINT64 Msr;\r
6450\r
6451 Msr = AsmReadMsr64 (MSR_IA32_CSTAR);\r
6452 AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);\r
6453 @endcode\r
6454 @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.\r
6455**/\r
6456#define MSR_IA32_CSTAR 0xC0000083\r
04c980a6
MK		 6457\r
6458/**\r
6459 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r
6460\r
6461 @param ECX MSR_IA32_FMASK (0xC0000084)\r
6462 @param EAX Lower 32-bits of MSR value.\r
6463 @param EDX Upper 32-bits of MSR value.\r
6464\r
6465 <b>Example usage</b>\r
6466 @code\r
6467 UINT64 Msr;\r
6468\r
6469 Msr = AsmReadMsr64 (MSR_IA32_FMASK);\r
6470 AsmWriteMsr64 (MSR_IA32_FMASK, Msr);\r
6471 @endcode\r
7de98828 6472 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r
04c980a6
MK		 6473**/\r
6474#define MSR_IA32_FMASK 0xC0000084\r
6475\r
6476\r
6477/**\r
6478 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
6479\r
6480 @param ECX MSR_IA32_FS_BASE (0xC0000100)\r
6481 @param EAX Lower 32-bits of MSR value.\r
6482 @param EDX Upper 32-bits of MSR value.\r
6483\r
6484 <b>Example usage</b>\r
6485 @code\r
6486 UINT64 Msr;\r
6487\r
6488 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);\r
6489 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);\r
6490 @endcode\r
7de98828 6491 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r
04c980a6
MK		 6492**/\r
6493#define MSR_IA32_FS_BASE 0xC0000100\r
6494\r
6495\r
6496/**\r
6497 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
6498\r
6499 @param ECX MSR_IA32_GS_BASE (0xC0000101)\r
6500 @param EAX Lower 32-bits of MSR value.\r
6501 @param EDX Upper 32-bits of MSR value.\r
6502\r
6503 <b>Example usage</b>\r
6504 @code\r
6505 UINT64 Msr;\r
6506\r
6507 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);\r
6508 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);\r
6509 @endcode\r
7de98828 6510 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r
04c980a6
MK		 6511**/\r
6512#define MSR_IA32_GS_BASE 0xC0000101\r
6513\r
6514\r
6515/**\r
6516 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
6517\r
6518 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)\r
6519 @param EAX Lower 32-bits of MSR value.\r
6520 @param EDX Upper 32-bits of MSR value.\r
6521\r
6522 <b>Example usage</b>\r
6523 @code\r
6524 UINT64 Msr;\r
6525\r
6526 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);\r
6527 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);\r
6528 @endcode\r
7de98828 6529 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r
04c980a6
MK		 6530**/\r
6531#define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r
6532\r
6533\r
6534/**\r
6535 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r
6536\r
6537 @param ECX MSR_IA32_TSC_AUX (0xC0000103)\r
6538 @param EAX Lower 32-bits of MSR value.\r
6539 Described by the type MSR_IA32_TSC_AUX_REGISTER.\r
6540 @param EDX Upper 32-bits of MSR value.\r
6541 Described by the type MSR_IA32_TSC_AUX_REGISTER.\r
6542\r
6543 <b>Example usage</b>\r
6544 @code\r
6545 MSR_IA32_TSC_AUX_REGISTER Msr;\r
6546\r
6547 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);\r
6548 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);\r
6549 @endcode\r
7de98828 6550 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r
04c980a6
MK		 6551**/\r
6552#define MSR_IA32_TSC_AUX 0xC0000103\r
6553\r
6554/**\r
6555 MSR information returned for MSR index #MSR_IA32_TSC_AUX\r
6556**/\r
6557typedef union {\r
6558 ///\r
6559 /// Individual bit fields\r
6560 ///\r
6561 struct {\r
6562 ///\r
6563 /// [Bits 31:0] AUX: Auxiliary signature of TSC.\r
6564 ///\r
6565 UINT32 AUX:32;\r
6566 UINT32 Reserved:32;\r
6567 } Bits;\r
6568 ///\r
6569 /// All bit fields as a 32-bit value\r
6570 ///\r
6571 UINT32 Uint32;\r
6572 ///\r
6573 /// All bit fields as a 64-bit value\r
6574 ///\r
6575 UINT64 Uint64;\r
6576} MSR_IA32_TSC_AUX_REGISTER;\r
6577\r
6578#endif\r
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