projects / mirror_edk2.git / blame
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| 04c980a6 MK |
1 | /** @file\r |
| 2 | Architectural MSR Definitions.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| 9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 10 | This program and the accompanying materials\r | |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| 19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 0f16be6d | 20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.\r |
| 04c980a6 | 21 | \r |
| 831d287a MK |
22 | @par Specification Reference:\r |
| 23 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 0f16be6d | 24 | September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.\r |
| 831d287a MK |
25 | \r |
| 26 | @par Specification Reference:\r | |
| 27 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 0f16be6d | 28 | September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.\r |
| 831d287a | 29 | \r |
| 04c980a6 MK |
30 | **/\r |
| 31 | \r | |
| 32 | #ifndef __ARCHITECTURAL_MSR_H__\r | |
| 33 | #define __ARCHITECTURAL_MSR_H__\r | |
| 34 | \r | |
| 35 | /**\r | |
| 0f16be6d | 36 | See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).\r |
| 04c980a6 MK |
37 | \r |
| 38 | @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)\r | |
| 39 | @param EAX Lower 32-bits of MSR value.\r | |
| 40 | @param EDX Upper 32-bits of MSR value.\r | |
| 41 | \r | |
| 42 | <b>Example usage</b>\r | |
| 43 | @code\r | |
| 44 | UINT64 Msr;\r | |
| 45 | \r | |
| 46 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);\r | |
| 47 | AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);\r | |
| 48 | @endcode\r | |
| 7de98828 | 49 | @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r |
| 04c980a6 MK |
50 | **/\r |
| 51 | #define MSR_IA32_P5_MC_ADDR 0x00000000\r | |
| 52 | \r | |
| 53 | \r | |
| 54 | /**\r | |
| 0f16be6d | 55 | See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r |
| 04c980a6 MK |
56 | \r |
| 57 | @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)\r | |
| 58 | @param EAX Lower 32-bits of MSR value.\r | |
| 59 | @param EDX Upper 32-bits of MSR value.\r | |
| 60 | \r | |
| 61 | <b>Example usage</b>\r | |
| 62 | @code\r | |
| 63 | UINT64 Msr;\r | |
| 64 | \r | |
| 65 | Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);\r | |
| 66 | AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);\r | |
| 67 | @endcode\r | |
| 7de98828 | 68 | @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r |
| 04c980a6 MK |
69 | **/\r |
| 70 | #define MSR_IA32_P5_MC_TYPE 0x00000001\r | |
| 71 | \r | |
| 72 | \r | |
| 73 | /**\r | |
| 74 | See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r | |
| 75 | at Display Family / Display Model 0F_03H.\r | |
| 76 | \r | |
| 77 | @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)\r | |
| 78 | @param EAX Lower 32-bits of MSR value.\r | |
| 79 | @param EDX Upper 32-bits of MSR value.\r | |
| 80 | \r | |
| 81 | <b>Example usage</b>\r | |
| 82 | @code\r | |
| 83 | UINT64 Msr;\r | |
| 84 | \r | |
| 85 | Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);\r | |
| 86 | AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);\r | |
| 87 | @endcode\r | |
| 7de98828 | 88 | @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r |
| 04c980a6 MK |
89 | **/\r |
| 90 | #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r | |
| 91 | \r | |
| 92 | \r | |
| 93 | /**\r | |
| 0f16be6d | 94 | See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /\r |
| 04c980a6 MK |
95 | Display Model 05_01H.\r |
| 96 | \r | |
| 97 | @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)\r | |
| 98 | @param EAX Lower 32-bits of MSR value.\r | |
| 99 | @param EDX Upper 32-bits of MSR value.\r | |
| 100 | \r | |
| 101 | <b>Example usage</b>\r | |
| 102 | @code\r | |
| 103 | UINT64 Msr;\r | |
| 104 | \r | |
| 105 | Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);\r | |
| 106 | AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);\r | |
| 107 | @endcode\r | |
| 7de98828 | 108 | @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r |
| 04c980a6 MK |
109 | **/\r |
| 110 | #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r | |
| 111 | \r | |
| 112 | \r | |
| 113 | /**\r | |
| 114 | Platform ID (RO) The operating system can use this MSR to determine "slot"\r | |
| 115 | information for the processor and the proper microcode update to load.\r | |
| 116 | Introduced at Display Family / Display Model 06_01H.\r | |
| 117 | \r | |
| 118 | @param ECX MSR_IA32_PLATFORM_ID (0x00000017)\r | |
| 119 | @param EAX Lower 32-bits of MSR value.\r | |
| 120 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
| 121 | @param EDX Upper 32-bits of MSR value.\r | |
| 122 | Described by the type MSR_IA32_PLATFORM_ID_REGISTER.\r | |
| 123 | \r | |
| 124 | <b>Example usage</b>\r | |
| 125 | @code\r | |
| 126 | MSR_IA32_PLATFORM_ID_REGISTER Msr;\r | |
| 127 | \r | |
| 128 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r | |
| 129 | @endcode\r | |
| 7de98828 | 130 | @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r |
| 04c980a6 MK |
131 | **/\r |
| 132 | #define MSR_IA32_PLATFORM_ID 0x00000017\r | |
| 133 | \r | |
| 134 | /**\r | |
| 135 | MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r | |
| 136 | **/\r | |
| 137 | typedef union {\r | |
| 138 | ///\r | |
| 139 | /// Individual bit fields\r | |
| 140 | ///\r | |
| 141 | struct {\r | |
| 142 | UINT32 Reserved1:32;\r | |
| 143 | UINT32 Reserved2:18;\r | |
| 144 | ///\r | |
| 145 | /// [Bits 52:50] Platform Id (RO) Contains information concerning the\r | |
| 146 | /// intended platform for the processor.\r | |
| 147 | /// 52 51 50\r | |
| 148 | /// -- -- --\r | |
| 149 | /// 0 0 0 Processor Flag 0.\r | |
| 150 | /// 0 0 1 Processor Flag 1\r | |
| 151 | /// 0 1 0 Processor Flag 2\r | |
| 152 | /// 0 1 1 Processor Flag 3\r | |
| 153 | /// 1 0 0 Processor Flag 4\r | |
| 154 | /// 1 0 1 Processor Flag 5\r | |
| 155 | /// 1 1 0 Processor Flag 6\r | |
| 156 | /// 1 1 1 Processor Flag 7\r | |
| 157 | ///\r | |
| 158 | UINT32 PlatformId:3;\r | |
| 159 | UINT32 Reserved3:11;\r | |
| 160 | } Bits;\r | |
| 161 | ///\r | |
| 162 | /// All bit fields as a 64-bit value\r | |
| 163 | ///\r | |
| 164 | UINT64 Uint64;\r | |
| 165 | } MSR_IA32_PLATFORM_ID_REGISTER;\r | |
| 166 | \r | |
| 167 | \r | |
| 168 | /**\r | |
| 169 | 06_01H.\r | |
| 170 | \r | |
| 171 | @param ECX MSR_IA32_APIC_BASE (0x0000001B)\r | |
| 172 | @param EAX Lower 32-bits of MSR value.\r | |
| 173 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
| 174 | @param EDX Upper 32-bits of MSR value.\r | |
| 175 | Described by the type MSR_IA32_APIC_BASE_REGISTER.\r | |
| 176 | \r | |
| 177 | <b>Example usage</b>\r | |
| 178 | @code\r | |
| 179 | MSR_IA32_APIC_BASE_REGISTER Msr;\r | |
| 180 | \r | |
| 181 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r | |
| 182 | AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);\r | |
| 183 | @endcode\r | |
| 7de98828 | 184 | @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r |
| 04c980a6 MK |
185 | **/\r |
| 186 | #define MSR_IA32_APIC_BASE 0x0000001B\r | |
| 187 | \r | |
| 188 | /**\r | |
| 189 | MSR information returned for MSR index #MSR_IA32_APIC_BASE\r | |
| 190 | **/\r | |
| 191 | typedef union {\r | |
| 192 | ///\r | |
| 193 | /// Individual bit fields\r | |
| 194 | ///\r | |
| 195 | struct {\r | |
| 196 | UINT32 Reserved1:8;\r | |
| 197 | ///\r | |
| 198 | /// [Bit 8] BSP flag (R/W).\r | |
| 199 | ///\r | |
| 200 | UINT32 BSP:1;\r | |
| 201 | UINT32 Reserved2:1;\r | |
| 202 | ///\r | |
| 203 | /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r | |
| 204 | /// Model 06_1AH.\r | |
| 205 | ///\r | |
| 206 | UINT32 EXTD:1;\r | |
| 207 | ///\r | |
| 208 | /// [Bit 11] APIC Global Enable (R/W).\r | |
| 209 | ///\r | |
| 210 | UINT32 EN:1;\r | |
| 211 | ///\r | |
| 212 | /// [Bits 31:12] APIC Base (R/W).\r | |
| 213 | ///\r | |
| 214 | UINT32 ApicBase:20;\r | |
| 215 | ///\r | |
| 216 | /// [Bits 63:32] APIC Base (R/W).\r | |
| 217 | ///\r | |
| 218 | UINT32 ApicBaseHi:32;\r | |
| 219 | } Bits;\r | |
| 220 | ///\r | |
| 221 | /// All bit fields as a 64-bit value\r | |
| 222 | ///\r | |
| 223 | UINT64 Uint64;\r | |
| 224 | } MSR_IA32_APIC_BASE_REGISTER;\r | |
| 225 | \r | |
| 226 | \r | |
| 227 | /**\r | |
| 228 | Control Features in Intel 64 Processor (R/W). If any one enumeration\r | |
| 229 | condition for defined bit field holds.\r | |
| 230 | \r | |
| 231 | @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)\r | |
| 232 | @param EAX Lower 32-bits of MSR value.\r | |
| 233 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
| 234 | @param EDX Upper 32-bits of MSR value.\r | |
| 235 | Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.\r | |
| 236 | \r | |
| 237 | <b>Example usage</b>\r | |
| 238 | @code\r | |
| 239 | MSR_IA32_FEATURE_CONTROL_REGISTER Msr;\r | |
| 240 | \r | |
| 241 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);\r | |
| 242 | AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);\r | |
| 243 | @endcode\r | |
| 7de98828 | 244 | @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r |
| 04c980a6 MK |
245 | **/\r |
| 246 | #define MSR_IA32_FEATURE_CONTROL 0x0000003A\r | |
| 247 | \r | |
| 248 | /**\r | |
| 249 | MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r | |
| 250 | **/\r | |
| 251 | typedef union {\r | |
| 252 | ///\r | |
| 253 | /// Individual bit fields\r | |
| 254 | ///\r | |
| 255 | struct {\r | |
| 256 | ///\r | |
| 257 | /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from\r | |
| 258 | /// being written, writes to this bit will result in GP(0). Note: Once the\r | |
| 259 | /// Lock bit is set, the contents of this register cannot be modified.\r | |
| 260 | /// Therefore the lock bit must be set after configuring support for Intel\r | |
| 261 | /// Virtualization Technology and prior to transferring control to an\r | |
| 262 | /// option ROM or the OS. Hence, once the Lock bit is set, the entire\r | |
| 263 | /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD\r | |
| 264 | /// is not deasserted. If any one enumeration condition for defined bit\r | |
| 265 | /// field position greater than bit 0 holds.\r | |
| 266 | ///\r | |
| 267 | UINT32 Lock:1;\r | |
| 268 | ///\r | |
| 269 | /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r | |
| 270 | /// system executive to use VMX in conjunction with SMX to support\r | |
| 271 | /// Intel(R) Trusted Execution Technology. BIOS must set this bit only\r | |
| 272 | /// when the CPUID function 1 returns VMX feature flag and SMX feature\r | |
| 273 | /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r | |
| 274 | /// CPUID.01H:ECX[6] = 1.\r | |
| 275 | ///\r | |
| 276 | UINT32 EnableVmxInsideSmx:1;\r | |
| 277 | ///\r | |
| 278 | /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r | |
| 279 | /// for system executive that do not require SMX. BIOS must set this bit\r | |
| 280 | /// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r | |
| 281 | /// 5). If CPUID.01H:ECX[5] = 1.\r | |
| 282 | ///\r | |
| 283 | UINT32 EnableVmxOutsideSmx:1;\r | |
| 284 | UINT32 Reserved1:5;\r | |
| 285 | ///\r | |
| 286 | /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r | |
| 287 | /// in the field represents an enable control for a corresponding SENTER\r | |
| 288 | /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r | |
| 289 | /// CPUID.01H:ECX[6] = 1.\r | |
| 290 | ///\r | |
| 291 | UINT32 SenterLocalFunctionEnables:7;\r | |
| 292 | ///\r | |
| 293 | /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r | |
| 294 | /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r | |
| 295 | /// 6] is set. If CPUID.01H:ECX[6] = 1.\r | |
| 296 | ///\r | |
| 297 | UINT32 SenterGlobalEnable:1;\r | |
| 0f16be6d HW |
298 | UINT32 Reserved2:1;\r |
| 299 | ///\r | |
| 300 | /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r | |
| 301 | /// enable runtime reconfiguration of SGX Launch Control via\r | |
| 302 | /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r | |
| 303 | ///\r | |
| 304 | UINT32 SgxLaunchControlEnable:1;\r | |
| 04c980a6 MK |
305 | ///\r |
| 306 | /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r | |
| 0f16be6d | 307 | /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r |
| 04c980a6 MK |
308 | ///\r |
| 309 | UINT32 SgxEnable:1;\r | |
| 310 | UINT32 Reserved3:1;\r | |
| 311 | ///\r | |
| 312 | /// [Bit 20] LMCE On (R/WL): When set, system software can program the\r | |
| 313 | /// MSRs associated with LMCE to configure delivery of some machine check\r | |
| 314 | /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r | |
| 315 | ///\r | |
| 316 | UINT32 LmceOn:1;\r | |
| 317 | UINT32 Reserved4:11;\r | |
| 318 | UINT32 Reserved5:32;\r | |
| 319 | } Bits;\r | |
| 320 | ///\r | |
| 321 | /// All bit fields as a 32-bit value\r | |
| 322 | ///\r | |
| 323 | UINT32 Uint32;\r | |
| 324 | ///\r | |
| 325 | /// All bit fields as a 64-bit value\r | |
| 326 | ///\r | |
| 327 | UINT64 Uint64;\r | |
| 328 | } MSR_IA32_FEATURE_CONTROL_REGISTER;\r | |
| 329 | \r | |
| 330 | \r | |
| 331 | /**\r | |
| 332 | Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r | |
| 333 | ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r | |
| 334 | a logical processor. Reset value is Zero. A write to IA32_TSC will modify\r | |
| 335 | the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does\r | |
| 336 | not affect the internal invariant TSC hardware.\r | |
| 337 | \r | |
| 338 | @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)\r | |
| 339 | @param EAX Lower 32-bits of MSR value.\r | |
| 340 | @param EDX Upper 32-bits of MSR value.\r | |
| 341 | \r | |
| 342 | <b>Example usage</b>\r | |
| 343 | @code\r | |
| 344 | UINT64 Msr;\r | |
| 345 | \r | |
| 346 | Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);\r | |
| 347 | AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);\r | |
| 348 | @endcode\r | |
| 7de98828 | 349 | @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r |
| 04c980a6 MK |
350 | **/\r |
| 351 | #define MSR_IA32_TSC_ADJUST 0x0000003B\r | |
| 352 | \r | |
| 353 | \r | |
| 354 | /**\r | |
| 355 | BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r | |
| 356 | microcode update to be loaded into the processor. See Section 9.11.6,\r | |
| 357 | "Microcode Update Loader." A processor may prevent writing to this MSR when\r | |
| 358 | loading guest states on VM entries or saving guest states on VM exits.\r | |
| 359 | Introduced at Display Family / Display Model 06_01H.\r | |
| 360 | \r | |
| 361 | @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)\r | |
| 362 | @param EAX Lower 32-bits of MSR value.\r | |
| 363 | @param EDX Upper 32-bits of MSR value.\r | |
| 364 | \r | |
| 365 | <b>Example usage</b>\r | |
| 366 | @code\r | |
| 367 | UINT64 Msr;\r | |
| 368 | \r | |
| 369 | Msr = 0;\r | |
| 370 | AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);\r | |
| 371 | @endcode\r | |
| 7de98828 | 372 | @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r |
| 04c980a6 MK |
373 | **/\r |
| 374 | #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r | |
| 375 | \r | |
| 376 | \r | |
| 377 | /**\r | |
| 378 | BIOS Update Signature (RO) Returns the microcode update signature following\r | |
| 379 | the execution of CPUID.01H. A processor may prevent writing to this MSR when\r | |
| 380 | loading guest states on VM entries or saving guest states on VM exits.\r | |
| 381 | Introduced at Display Family / Display Model 06_01H.\r | |
| 382 | \r | |
| 383 | @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)\r | |
| 384 | @param EAX Lower 32-bits of MSR value.\r | |
| 385 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
| 386 | @param EDX Upper 32-bits of MSR value.\r | |
| 387 | Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.\r | |
| 388 | \r | |
| 389 | <b>Example usage</b>\r | |
| 390 | @code\r | |
| 391 | MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;\r | |
| 392 | \r | |
| 393 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r | |
| 394 | @endcode\r | |
| 7de98828 | 395 | @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r |
| 04c980a6 MK |
396 | **/\r |
| 397 | #define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r | |
| 398 | \r | |
| 399 | /**\r | |
| 400 | MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r | |
| 401 | **/\r | |
| 402 | typedef union {\r | |
| 403 | ///\r | |
| 404 | /// Individual bit fields\r | |
| 405 | ///\r | |
| 406 | struct {\r | |
| 407 | UINT32 Reserved:32;\r | |
| 408 | ///\r | |
| 409 | /// [Bits 63:32] Microcode update signature. This field contains the\r | |
| 410 | /// signature of the currently loaded microcode update when read following\r | |
| 411 | /// the execution of the CPUID instruction, function 1. It is required\r | |
| 412 | /// that this register field be pre-loaded with zero prior to executing\r | |
| 413 | /// the CPUID, function 1. If the field remains equal to zero, then there\r | |
| 414 | /// is no microcode update loaded. Another nonzero value will be the\r | |
| 415 | /// signature.\r | |
| 416 | ///\r | |
| 417 | UINT32 MicrocodeUpdateSignature:32;\r | |
| 418 | } Bits;\r | |
| 419 | ///\r | |
| 420 | /// All bit fields as a 64-bit value\r | |
| 421 | ///\r | |
| 422 | UINT64 Uint64;\r | |
| 423 | } MSR_IA32_BIOS_SIGN_ID_REGISTER;\r | |
| 424 | \r | |
| 425 | \r | |
| 0f16be6d HW |
426 | /**\r |
| 427 | IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r | |
| 428 | SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r | |
| 429 | default value is the digest of Intel's signing key. Read permitted If\r | |
| 430 | CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):\r | |
| 431 | EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.\r | |
| 432 | \r | |
| 433 | @param ECX MSR_IA32_SGXLEPUBKEYHASHn\r | |
| 434 | @param EAX Lower 32-bits of MSR value.\r | |
| 435 | @param EDX Upper 32-bits of MSR value.\r | |
| 436 | \r | |
| 437 | <b>Example usage</b>\r | |
| 438 | @code\r | |
| 439 | UINT64 Msr;\r | |
| 440 | \r | |
| 441 | Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);\r | |
| 442 | AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);\r | |
| 443 | @endcode\r | |
| 444 | @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.\r | |
| 445 | MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.\r | |
| 446 | MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.\r | |
| 447 | MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r | |
| 448 | @{\r | |
| 449 | **/\r | |
| 450 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r | |
| 451 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r | |
| 452 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r | |
| 453 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r | |
| 454 | /// @}\r | |
| 455 | \r | |
| 456 | \r | |
| 04c980a6 | 457 | /**\r |
| 831d287a | 458 | SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r |
| 04c980a6 MK |
459 | 1.\r |
| 460 | \r | |
| 461 | @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)\r | |
| 462 | @param EAX Lower 32-bits of MSR value.\r | |
| 463 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 464 | @param EDX Upper 32-bits of MSR value.\r | |
| 465 | Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 466 | \r | |
| 467 | <b>Example usage</b>\r | |
| 468 | @code\r | |
| 469 | MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;\r | |
| 470 | \r | |
| 471 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r | |
| 472 | AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);\r | |
| 473 | @endcode\r | |
| 7de98828 | 474 | @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r |
| 04c980a6 MK |
475 | **/\r |
| 476 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r | |
| 477 | \r | |
| 478 | /**\r | |
| 479 | MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r | |
| 480 | **/\r | |
| 481 | typedef union {\r | |
| 482 | ///\r | |
| 483 | /// Individual bit fields\r | |
| 484 | ///\r | |
| 485 | struct {\r | |
| 486 | ///\r | |
| 487 | /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this\r | |
| 488 | /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment\r | |
| 489 | /// (see Section 34.15.6), the dual-monitor treatment cannot be activated\r | |
| 490 | /// if the bit is 0. This bit is cleared when the logical processor is\r | |
| 491 | /// reset.\r | |
| 492 | ///\r | |
| 493 | UINT32 Valid:1;\r | |
| 494 | UINT32 Reserved1:1;\r | |
| 495 | ///\r | |
| 496 | /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the\r | |
| 497 | /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs\r | |
| 498 | /// unless bit 2 is 1 (the value of bit 0 is irrelevant).\r | |
| 499 | ///\r | |
| 500 | UINT32 BlockSmi:1;\r | |
| 501 | UINT32 Reserved2:9;\r | |
| 502 | ///\r | |
| 503 | /// [Bits 31:12] MSEG Base (R/W).\r | |
| 504 | ///\r | |
| 505 | UINT32 MsegBase:20;\r | |
| 506 | UINT32 Reserved3:32;\r | |
| 507 | } Bits;\r | |
| 508 | ///\r | |
| 509 | /// All bit fields as a 32-bit value\r | |
| 510 | ///\r | |
| 511 | UINT32 Uint32;\r | |
| 512 | ///\r | |
| 513 | /// All bit fields as a 64-bit value\r | |
| 514 | ///\r | |
| 515 | UINT64 Uint64;\r | |
| 516 | } MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r | |
| 517 | \r | |
| 831d287a MK |
518 | /**\r |
| 519 | MSEG header that is located at the physical address specified by the MsegBase\r | |
| 520 | field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.\r | |
| 521 | **/\r | |
| 522 | typedef struct {\r | |
| a03bb3d2 MK |
523 | ///\r |
| 524 | /// Different processors may use different MSEG revision identifiers. These\r | |
| 525 | /// identifiers enable software to avoid using an MSEG header formatted for\r | |
| 526 | /// one processor on a processor that uses a different format. Software can\r | |
| 527 | /// discover the MSEG revision identifier that a processor uses by reading\r | |
| 528 | /// the VMX capability MSR IA32_VMX_MISC.\r | |
| 529 | //\r | |
| 831d287a | 530 | UINT32 MsegHeaderRevision;\r |
| a03bb3d2 MK |
531 | ///\r |
| 532 | /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r | |
| 533 | /// is the IA-32e mode SMM feature bit. It indicates whether the logical\r | |
| 534 | /// processor will be in IA-32e mode after the STM is activated.\r | |
| 535 | ///\r | |
| 831d287a MK |
536 | UINT32 MonitorFeatures;\r |
| 537 | UINT32 GdtrLimit;\r | |
| 538 | UINT32 GdtrBaseOffset;\r | |
| 539 | UINT32 CsSelector;\r | |
| 540 | UINT32 EipOffset;\r | |
| 541 | UINT32 EspOffset;\r | |
| 542 | UINT32 Cr3Offset;\r | |
| a03bb3d2 MK |
543 | ///\r |
| 544 | /// Pad header so total size is 2KB\r | |
| 545 | ///\r | |
| 831d287a MK |
546 | UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r |
| 547 | } MSEG_HEADER;\r | |
| 548 | \r | |
| a03bb3d2 MK |
549 | ///\r |
| 550 | /// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r | |
| 551 | ///\r | |
| 552 | #define STM_FEATURES_IA32E 0x1\r | |
| 553 | ///\r | |
| 554 | /// @}\r | |
| 555 | ///\r | |
| 04c980a6 MK |
556 | \r |
| 557 | /**\r | |
| 558 | Base address of the logical processor's SMRAM image (RO, SMM only). If\r | |
| 559 | IA32_VMX_MISC[15].\r | |
| 560 | \r | |
| 561 | @param ECX MSR_IA32_SMBASE (0x0000009E)\r | |
| 562 | @param EAX Lower 32-bits of MSR value.\r | |
| 563 | @param EDX Upper 32-bits of MSR value.\r | |
| 564 | \r | |
| 565 | <b>Example usage</b>\r | |
| 566 | @code\r | |
| 567 | UINT64 Msr;\r | |
| 568 | \r | |
| 569 | Msr = AsmReadMsr64 (MSR_IA32_SMBASE);\r | |
| 570 | @endcode\r | |
| 7de98828 | 571 | @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r |
| 04c980a6 MK |
572 | **/\r |
| 573 | #define MSR_IA32_SMBASE 0x0000009E\r | |
| 574 | \r | |
| 575 | \r | |
| 576 | /**\r | |
| 577 | General Performance Counters (R/W).\r | |
| 578 | MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.\r | |
| 579 | \r | |
| 580 | @param ECX MSR_IA32_PMCn\r | |
| 581 | @param EAX Lower 32-bits of MSR value.\r | |
| 582 | @param EDX Upper 32-bits of MSR value.\r | |
| 583 | \r | |
| 584 | <b>Example usage</b>\r | |
| 585 | @code\r | |
| 586 | UINT64 Msr;\r | |
| 587 | \r | |
| 588 | Msr = AsmReadMsr64 (MSR_IA32_PMC0);\r | |
| 589 | AsmWriteMsr64 (MSR_IA32_PMC0, Msr);\r | |
| 590 | @endcode\r | |
| 7de98828 JF |
591 | @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.\r |
| 592 | MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.\r | |
| 593 | MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.\r | |
| 594 | MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.\r | |
| 595 | MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.\r | |
| 596 | MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.\r | |
| 597 | MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.\r | |
| 598 | MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r | |
| 04c980a6 MK |
599 | @{\r |
| 600 | **/\r | |
| 601 | #define MSR_IA32_PMC0 0x000000C1\r | |
| 602 | #define MSR_IA32_PMC1 0x000000C2\r | |
| 603 | #define MSR_IA32_PMC2 0x000000C3\r | |
| 604 | #define MSR_IA32_PMC3 0x000000C4\r | |
| 605 | #define MSR_IA32_PMC4 0x000000C5\r | |
| 606 | #define MSR_IA32_PMC5 0x000000C6\r | |
| 607 | #define MSR_IA32_PMC6 0x000000C7\r | |
| 608 | #define MSR_IA32_PMC7 0x000000C8\r | |
| 609 | /// @}\r | |
| 610 | \r | |
| 611 | \r | |
| 612 | /**\r | |
| 613 | TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r | |
| 614 | C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r | |
| 615 | to TSC freq.) when the logical processor is in C0. Cleared upon overflow /\r | |
| 616 | wrap-around of IA32_APERF.\r | |
| 617 | \r | |
| 618 | @param ECX MSR_IA32_MPERF (0x000000E7)\r | |
| 619 | @param EAX Lower 32-bits of MSR value.\r | |
| 620 | @param EDX Upper 32-bits of MSR value.\r | |
| 621 | \r | |
| 622 | <b>Example usage</b>\r | |
| 623 | @code\r | |
| 624 | UINT64 Msr;\r | |
| 625 | \r | |
| 626 | Msr = AsmReadMsr64 (MSR_IA32_MPERF);\r | |
| 627 | AsmWriteMsr64 (MSR_IA32_MPERF, Msr);\r | |
| 628 | @endcode\r | |
| 7de98828 | 629 | @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r |
| 04c980a6 MK |
630 | **/\r |
| 631 | #define MSR_IA32_MPERF 0x000000E7\r | |
| 632 | \r | |
| 633 | \r | |
| 634 | /**\r | |
| 635 | Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r | |
| 636 | 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at\r | |
| 637 | the coordinated clock frequency, when the logical processor is in C0.\r | |
| 638 | Cleared upon overflow / wrap-around of IA32_MPERF.\r | |
| 639 | \r | |
| 640 | @param ECX MSR_IA32_APERF (0x000000E8)\r | |
| 641 | @param EAX Lower 32-bits of MSR value.\r | |
| 642 | @param EDX Upper 32-bits of MSR value.\r | |
| 643 | \r | |
| 644 | <b>Example usage</b>\r | |
| 645 | @code\r | |
| 646 | UINT64 Msr;\r | |
| 647 | \r | |
| 648 | Msr = AsmReadMsr64 (MSR_IA32_APERF);\r | |
| 649 | AsmWriteMsr64 (MSR_IA32_APERF, Msr);\r | |
| 650 | @endcode\r | |
| 7de98828 | 651 | @note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r |
| 04c980a6 MK |
652 | **/\r |
| 653 | #define MSR_IA32_APERF 0x000000E8\r | |
| 654 | \r | |
| 655 | \r | |
| 656 | /**\r | |
| 657 | MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r | |
| 658 | Introduced at Display Family / Display Model 06_01H.\r | |
| 659 | \r | |
| 660 | @param ECX MSR_IA32_MTRRCAP (0x000000FE)\r | |
| 661 | @param EAX Lower 32-bits of MSR value.\r | |
| 662 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
| 663 | @param EDX Upper 32-bits of MSR value.\r | |
| 664 | Described by the type MSR_IA32_MTRRCAP_REGISTER.\r | |
| 665 | \r | |
| 666 | <b>Example usage</b>\r | |
| 667 | @code\r | |
| 668 | MSR_IA32_MTRRCAP_REGISTER Msr;\r | |
| 669 | \r | |
| 670 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r | |
| 671 | @endcode\r | |
| 7de98828 | 672 | @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r |
| 04c980a6 MK |
673 | **/\r |
| 674 | #define MSR_IA32_MTRRCAP 0x000000FE\r | |
| 675 | \r | |
| 676 | /**\r | |
| 677 | MSR information returned for MSR index #MSR_IA32_MTRRCAP\r | |
| 678 | **/\r | |
| 679 | typedef union {\r | |
| 680 | ///\r | |
| 681 | /// Individual bit fields\r | |
| 682 | ///\r | |
| 683 | struct {\r | |
| 684 | ///\r | |
| 685 | /// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r | |
| 686 | /// processor.\r | |
| 687 | ///\r | |
| 688 | UINT32 VCNT:8;\r | |
| 689 | ///\r | |
| 690 | /// [Bit 8] Fixed range MTRRs are supported when set.\r | |
| 691 | ///\r | |
| 692 | UINT32 FIX:1;\r | |
| 693 | UINT32 Reserved1:1;\r | |
| 694 | ///\r | |
| 695 | /// [Bit 10] WC Supported when set.\r | |
| 696 | ///\r | |
| 697 | UINT32 WC:1;\r | |
| 698 | ///\r | |
| 699 | /// [Bit 11] SMRR Supported when set.\r | |
| 700 | ///\r | |
| 701 | UINT32 SMRR:1;\r | |
| 702 | UINT32 Reserved2:20;\r | |
| 703 | UINT32 Reserved3:32;\r | |
| 704 | } Bits;\r | |
| 705 | ///\r | |
| 706 | /// All bit fields as a 32-bit value\r | |
| 707 | ///\r | |
| 708 | UINT32 Uint32;\r | |
| 709 | ///\r | |
| 710 | /// All bit fields as a 64-bit value\r | |
| 711 | ///\r | |
| 712 | UINT64 Uint64;\r | |
| 713 | } MSR_IA32_MTRRCAP_REGISTER;\r | |
| 714 | \r | |
| 715 | \r | |
| 716 | /**\r | |
| 717 | SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 718 | \r | |
| 719 | @param ECX MSR_IA32_SYSENTER_CS (0x00000174)\r | |
| 720 | @param EAX Lower 32-bits of MSR value.\r | |
| 721 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
| 722 | @param EDX Upper 32-bits of MSR value.\r | |
| 723 | Described by the type MSR_IA32_SYSENTER_CS_REGISTER.\r | |
| 724 | \r | |
| 725 | <b>Example usage</b>\r | |
| 726 | @code\r | |
| 727 | MSR_IA32_SYSENTER_CS_REGISTER Msr;\r | |
| 728 | \r | |
| 729 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);\r | |
| 730 | AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);\r | |
| 731 | @endcode\r | |
| 7de98828 | 732 | @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r |
| 04c980a6 MK |
733 | **/\r |
| 734 | #define MSR_IA32_SYSENTER_CS 0x00000174\r | |
| 735 | \r | |
| 736 | /**\r | |
| 737 | MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r | |
| 738 | **/\r | |
| 739 | typedef union {\r | |
| 740 | ///\r | |
| 741 | /// Individual bit fields\r | |
| 742 | ///\r | |
| 743 | struct {\r | |
| 744 | ///\r | |
| 745 | /// [Bits 15:0] CS Selector.\r | |
| 746 | ///\r | |
| 747 | UINT32 CS:16;\r | |
| 748 | UINT32 Reserved1:16;\r | |
| 749 | UINT32 Reserved2:32;\r | |
| 750 | } Bits;\r | |
| 751 | ///\r | |
| 752 | /// All bit fields as a 32-bit value\r | |
| 753 | ///\r | |
| 754 | UINT32 Uint32;\r | |
| 755 | ///\r | |
| 756 | /// All bit fields as a 64-bit value\r | |
| 757 | ///\r | |
| 758 | UINT64 Uint64;\r | |
| 759 | } MSR_IA32_SYSENTER_CS_REGISTER;\r | |
| 760 | \r | |
| 761 | \r | |
| 762 | /**\r | |
| 763 | SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 764 | \r | |
| 765 | @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)\r | |
| 766 | @param EAX Lower 32-bits of MSR value.\r | |
| 767 | @param EDX Upper 32-bits of MSR value.\r | |
| 768 | \r | |
| 769 | <b>Example usage</b>\r | |
| 770 | @code\r | |
| 771 | UINT64 Msr;\r | |
| 772 | \r | |
| 773 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);\r | |
| 774 | AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);\r | |
| 775 | @endcode\r | |
| 7de98828 | 776 | @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r |
| 04c980a6 MK |
777 | **/\r |
| 778 | #define MSR_IA32_SYSENTER_ESP 0x00000175\r | |
| 779 | \r | |
| 780 | \r | |
| 781 | /**\r | |
| 782 | SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r | |
| 783 | \r | |
| 784 | @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)\r | |
| 785 | @param EAX Lower 32-bits of MSR value.\r | |
| 786 | @param EDX Upper 32-bits of MSR value.\r | |
| 787 | \r | |
| 788 | <b>Example usage</b>\r | |
| 789 | @code\r | |
| 790 | UINT64 Msr;\r | |
| 791 | \r | |
| 792 | Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);\r | |
| 793 | AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);\r | |
| 794 | @endcode\r | |
| 7de98828 | 795 | @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r |
| 04c980a6 MK |
796 | **/\r |
| 797 | #define MSR_IA32_SYSENTER_EIP 0x00000176\r | |
| 798 | \r | |
| 799 | \r | |
| 800 | /**\r | |
| 801 | Global Machine Check Capability (RO). Introduced at Display Family / Display\r | |
| 802 | Model 06_01H.\r | |
| 803 | \r | |
| 804 | @param ECX MSR_IA32_MCG_CAP (0x00000179)\r | |
| 805 | @param EAX Lower 32-bits of MSR value.\r | |
| 806 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
| 807 | @param EDX Upper 32-bits of MSR value.\r | |
| 808 | Described by the type MSR_IA32_MCG_CAP_REGISTER.\r | |
| 809 | \r | |
| 810 | <b>Example usage</b>\r | |
| 811 | @code\r | |
| 812 | MSR_IA32_MCG_CAP_REGISTER Msr;\r | |
| 813 | \r | |
| 814 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r | |
| 815 | @endcode\r | |
| 7de98828 | 816 | @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r |
| 04c980a6 MK |
817 | **/\r |
| 818 | #define MSR_IA32_MCG_CAP 0x00000179\r | |
| 819 | \r | |
| 820 | /**\r | |
| 821 | MSR information returned for MSR index #MSR_IA32_MCG_CAP\r | |
| 822 | **/\r | |
| 823 | typedef union {\r | |
| 824 | ///\r | |
| 825 | /// Individual bit fields\r | |
| 826 | ///\r | |
| 827 | struct {\r | |
| 828 | ///\r | |
| 829 | /// [Bits 7:0] Count: Number of reporting banks.\r | |
| 830 | ///\r | |
| 831 | UINT32 Count:8;\r | |
| 832 | ///\r | |
| 833 | /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r | |
| 834 | ///\r | |
| 835 | UINT32 MCG_CTL_P:1;\r | |
| 836 | ///\r | |
| 837 | /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r | |
| 838 | /// if this bit is set.\r | |
| 839 | ///\r | |
| 840 | UINT32 MCG_EXT_P:1;\r | |
| 841 | ///\r | |
| 842 | /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r | |
| 843 | /// Introduced at Display Family / Display Model 06_01H.\r | |
| 844 | ///\r | |
| 845 | UINT32 MCP_CMCI_P:1;\r | |
| 846 | ///\r | |
| 847 | /// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r | |
| 848 | /// if this bit is set.\r | |
| 849 | ///\r | |
| 850 | UINT32 MCG_TES_P:1;\r | |
| 851 | UINT32 Reserved1:4;\r | |
| 852 | ///\r | |
| 853 | /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r | |
| 854 | /// registers present.\r | |
| 855 | ///\r | |
| 856 | UINT32 MCG_EXT_CNT:8;\r | |
| 857 | ///\r | |
| 858 | /// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r | |
| 859 | /// this bit is set.\r | |
| 860 | ///\r | |
| 861 | UINT32 MCG_SER_P:1;\r | |
| 862 | UINT32 Reserved2:1;\r | |
| 863 | ///\r | |
| 864 | /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r | |
| 865 | /// firmware to be invoked when an error is detected so that it may\r | |
| 866 | /// provide additional platform specific information in an ACPI format\r | |
| 867 | /// "Generic Error Data Entry" that augments the data included in machine\r | |
| 868 | /// check bank registers. Introduced at Display Family / Display Model\r | |
| 869 | /// 06_3EH.\r | |
| 870 | ///\r | |
| 871 | UINT32 MCG_ELOG_P:1;\r | |
| 872 | ///\r | |
| 873 | /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r | |
| 874 | /// state in IA32_MCG_STATUS and associated MSR necessary to configure\r | |
| 875 | /// Local Machine Check Exception (LMCE). Introduced at Display Family /\r | |
| 876 | /// Display Model 06_3EH.\r | |
| 877 | ///\r | |
| 878 | UINT32 MCG_LMCE_P:1;\r | |
| 879 | UINT32 Reserved3:4;\r | |
| 880 | UINT32 Reserved4:32;\r | |
| 881 | } Bits;\r | |
| 882 | ///\r | |
| 883 | /// All bit fields as a 32-bit value\r | |
| 884 | ///\r | |
| 885 | UINT32 Uint32;\r | |
| 886 | ///\r | |
| 887 | /// All bit fields as a 64-bit value\r | |
| 888 | ///\r | |
| 889 | UINT64 Uint64;\r | |
| 890 | } MSR_IA32_MCG_CAP_REGISTER;\r | |
| 891 | \r | |
| 892 | \r | |
| 893 | /**\r | |
| 894 | Global Machine Check Status (R/W0). Introduced at Display Family / Display\r | |
| 895 | Model 06_01H.\r | |
| 896 | \r | |
| 897 | @param ECX MSR_IA32_MCG_STATUS (0x0000017A)\r | |
| 898 | @param EAX Lower 32-bits of MSR value.\r | |
| 899 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
| 900 | @param EDX Upper 32-bits of MSR value.\r | |
| 901 | Described by the type MSR_IA32_MCG_STATUS_REGISTER.\r | |
| 902 | \r | |
| 903 | <b>Example usage</b>\r | |
| 904 | @code\r | |
| 905 | MSR_IA32_MCG_STATUS_REGISTER Msr;\r | |
| 906 | \r | |
| 907 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r | |
| 908 | AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);\r | |
| 909 | @endcode\r | |
| 7de98828 | 910 | @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r |
| 04c980a6 MK |
911 | **/\r |
| 912 | #define MSR_IA32_MCG_STATUS 0x0000017A\r | |
| 913 | \r | |
| 914 | /**\r | |
| 915 | MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r | |
| 916 | **/\r | |
| 917 | typedef union {\r | |
| 918 | ///\r | |
| 919 | /// Individual bit fields\r | |
| 920 | ///\r | |
| 921 | struct {\r | |
| 922 | ///\r | |
| 923 | /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r | |
| 924 | /// Model 06_01H.\r | |
| 925 | ///\r | |
| 926 | UINT32 RIPV:1;\r | |
| 927 | ///\r | |
| 928 | /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r | |
| 929 | /// Model 06_01H.\r | |
| 930 | ///\r | |
| 931 | UINT32 EIPV:1;\r | |
| 932 | ///\r | |
| 933 | /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r | |
| 934 | /// / Display Model 06_01H.\r | |
| 935 | ///\r | |
| 936 | UINT32 MCIP:1;\r | |
| 937 | ///\r | |
| 938 | /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r | |
| 939 | ///\r | |
| 940 | UINT32 LMCE_S:1;\r | |
| 941 | UINT32 Reserved1:28;\r | |
| 942 | UINT32 Reserved2:32;\r | |
| 943 | } Bits;\r | |
| 944 | ///\r | |
| 945 | /// All bit fields as a 32-bit value\r | |
| 946 | ///\r | |
| 947 | UINT32 Uint32;\r | |
| 948 | ///\r | |
| 949 | /// All bit fields as a 64-bit value\r | |
| 950 | ///\r | |
| 951 | UINT64 Uint64;\r | |
| 952 | } MSR_IA32_MCG_STATUS_REGISTER;\r | |
| 953 | \r | |
| 954 | \r | |
| 955 | /**\r | |
| 956 | Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r | |
| 957 | \r | |
| 958 | @param ECX MSR_IA32_MCG_CTL (0x0000017B)\r | |
| 959 | @param EAX Lower 32-bits of MSR value.\r | |
| 960 | @param EDX Upper 32-bits of MSR value.\r | |
| 961 | \r | |
| 962 | <b>Example usage</b>\r | |
| 963 | @code\r | |
| 964 | UINT64 Msr;\r | |
| 965 | \r | |
| 966 | Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);\r | |
| 967 | AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);\r | |
| 968 | @endcode\r | |
| 7de98828 | 969 | @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r |
| 04c980a6 MK |
970 | **/\r |
| 971 | #define MSR_IA32_MCG_CTL 0x0000017B\r | |
| 972 | \r | |
| 973 | \r | |
| 974 | /**\r | |
| 975 | Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r | |
| 976 | \r | |
| 977 | @param ECX MSR_IA32_PERFEVTSELn\r | |
| 978 | @param EAX Lower 32-bits of MSR value.\r | |
| 979 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
| 980 | @param EDX Upper 32-bits of MSR value.\r | |
| 981 | Described by the type MSR_IA32_PERFEVTSEL_REGISTER.\r | |
| 982 | \r | |
| 983 | <b>Example usage</b>\r | |
| 984 | @code\r | |
| 985 | MSR_IA32_PERFEVTSEL_REGISTER Msr;\r | |
| 986 | \r | |
| 987 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);\r | |
| 988 | AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);\r | |
| 989 | @endcode\r | |
| 7de98828 JF |
990 | @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r |
| 991 | MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r | |
| 992 | MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r | |
| 993 | MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r | |
| 04c980a6 MK |
994 | @{\r |
| 995 | **/\r | |
| 996 | #define MSR_IA32_PERFEVTSEL0 0x00000186\r | |
| 997 | #define MSR_IA32_PERFEVTSEL1 0x00000187\r | |
| 998 | #define MSR_IA32_PERFEVTSEL2 0x00000188\r | |
| 999 | #define MSR_IA32_PERFEVTSEL3 0x00000189\r | |
| 1000 | /// @}\r | |
| 1001 | \r | |
| 1002 | /**\r | |
| 1003 | MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to\r | |
| 1004 | #MSR_IA32_PERFEVTSEL3\r | |
| 1005 | **/\r | |
| 1006 | typedef union {\r | |
| 1007 | ///\r | |
| 1008 | /// Individual bit fields\r | |
| 1009 | ///\r | |
| 1010 | struct {\r | |
| 1011 | ///\r | |
| 1012 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
| 1013 | ///\r | |
| 1014 | UINT32 EventSelect:8;\r | |
| 1015 | ///\r | |
| 1016 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
| 1017 | /// detect on the selected event logic.\r | |
| 1018 | ///\r | |
| 1019 | UINT32 UMASK:8;\r | |
| 1020 | ///\r | |
| 1021 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
| 1022 | ///\r | |
| 1023 | UINT32 USR:1;\r | |
| 1024 | ///\r | |
| 1025 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
| 1026 | ///\r | |
| 1027 | UINT32 OS:1;\r | |
| 1028 | ///\r | |
| 1029 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
| 1030 | ///\r | |
| 1031 | UINT32 E:1;\r | |
| 1032 | ///\r | |
| 1033 | /// [Bit 19] PC: enables pin control.\r | |
| 1034 | ///\r | |
| 1035 | UINT32 PC:1;\r | |
| 1036 | ///\r | |
| 1037 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
| 1038 | ///\r | |
| 1039 | UINT32 INT:1;\r | |
| 1040 | ///\r | |
| 1041 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
| 1042 | /// event conditions occurring across all logical processors sharing a\r | |
| 1043 | /// processor core. When set to 0, the counter only increments the\r | |
| 1044 | /// associated event conditions occurring in the logical processor which\r | |
| 1045 | /// programmed the MSR.\r | |
| 1046 | ///\r | |
| 1047 | UINT32 ANY:1;\r | |
| 1048 | ///\r | |
| 1049 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
| 1050 | /// counting when this bit is set.\r | |
| 1051 | ///\r | |
| 1052 | UINT32 EN:1;\r | |
| 1053 | ///\r | |
| 1054 | /// [Bit 23] INV: invert the CMASK.\r | |
| 1055 | ///\r | |
| 1056 | UINT32 INV:1;\r | |
| 1057 | ///\r | |
| 1058 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
| 1059 | /// performance counter increments each cycle if the event count is\r | |
| 1060 | /// greater than or equal to the CMASK.\r | |
| 1061 | ///\r | |
| 1062 | UINT32 CMASK:8;\r | |
| 1063 | UINT32 Reserved:32;\r | |
| 1064 | } Bits;\r | |
| 1065 | ///\r | |
| 1066 | /// All bit fields as a 32-bit value\r | |
| 1067 | ///\r | |
| 1068 | UINT32 Uint32;\r | |
| 1069 | ///\r | |
| 1070 | /// All bit fields as a 64-bit value\r | |
| 1071 | ///\r | |
| 1072 | UINT64 Uint64;\r | |
| 1073 | } MSR_IA32_PERFEVTSEL_REGISTER;\r | |
| 1074 | \r | |
| 1075 | \r | |
| 1076 | /**\r | |
| 1077 | Current performance state(P-State) operating point (RO). Introduced at\r | |
| 1078 | Display Family / Display Model 0F_03H.\r | |
| 1079 | \r | |
| 1080 | @param ECX MSR_IA32_PERF_STATUS (0x00000198)\r | |
| 1081 | @param EAX Lower 32-bits of MSR value.\r | |
| 1082 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
| 1083 | @param EDX Upper 32-bits of MSR value.\r | |
| 1084 | Described by the type MSR_IA32_PERF_STATUS_REGISTER.\r | |
| 1085 | \r | |
| 1086 | <b>Example usage</b>\r | |
| 1087 | @code\r | |
| 1088 | MSR_IA32_PERF_STATUS_REGISTER Msr;\r | |
| 1089 | \r | |
| 1090 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);\r | |
| 1091 | @endcode\r | |
| 7de98828 | 1092 | @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r |
| 04c980a6 MK |
1093 | **/\r |
| 1094 | #define MSR_IA32_PERF_STATUS 0x00000198\r | |
| 1095 | \r | |
| 1096 | /**\r | |
| 1097 | MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r | |
| 1098 | **/\r | |
| 1099 | typedef union {\r | |
| 1100 | ///\r | |
| 1101 | /// Individual bit fields\r | |
| 1102 | ///\r | |
| 1103 | struct {\r | |
| 1104 | ///\r | |
| 1105 | /// [Bits 15:0] Current performance State Value.\r | |
| 1106 | ///\r | |
| 1107 | UINT32 State:16;\r | |
| 1108 | UINT32 Reserved1:16;\r | |
| 1109 | UINT32 Reserved2:32;\r | |
| 1110 | } Bits;\r | |
| 1111 | ///\r | |
| 1112 | /// All bit fields as a 32-bit value\r | |
| 1113 | ///\r | |
| 1114 | UINT32 Uint32;\r | |
| 1115 | ///\r | |
| 1116 | /// All bit fields as a 64-bit value\r | |
| 1117 | ///\r | |
| 1118 | UINT64 Uint64;\r | |
| 1119 | } MSR_IA32_PERF_STATUS_REGISTER;\r | |
| 1120 | \r | |
| 1121 | \r | |
| 1122 | /**\r | |
| 1123 | (R/W). Introduced at Display Family / Display Model 0F_03H.\r | |
| 1124 | \r | |
| 1125 | @param ECX MSR_IA32_PERF_CTL (0x00000199)\r | |
| 1126 | @param EAX Lower 32-bits of MSR value.\r | |
| 1127 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
| 1128 | @param EDX Upper 32-bits of MSR value.\r | |
| 1129 | Described by the type MSR_IA32_PERF_CTL_REGISTER.\r | |
| 1130 | \r | |
| 1131 | <b>Example usage</b>\r | |
| 1132 | @code\r | |
| 1133 | MSR_IA32_PERF_CTL_REGISTER Msr;\r | |
| 1134 | \r | |
| 1135 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);\r | |
| 1136 | AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);\r | |
| 1137 | @endcode\r | |
| 7de98828 | 1138 | @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r |
| 04c980a6 MK |
1139 | **/\r |
| 1140 | #define MSR_IA32_PERF_CTL 0x00000199\r | |
| 1141 | \r | |
| 1142 | /**\r | |
| 1143 | MSR information returned for MSR index #MSR_IA32_PERF_CTL\r | |
| 1144 | **/\r | |
| 1145 | typedef union {\r | |
| 1146 | ///\r | |
| 1147 | /// Individual bit fields\r | |
| 1148 | ///\r | |
| 1149 | struct {\r | |
| 1150 | ///\r | |
| 1151 | /// [Bits 15:0] Target performance State Value.\r | |
| 1152 | ///\r | |
| 1153 | UINT32 TargetState:16;\r | |
| 1154 | UINT32 Reserved1:16;\r | |
| 1155 | ///\r | |
| 1156 | /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r | |
| 1157 | /// (Mobile only).\r | |
| 1158 | ///\r | |
| 1159 | UINT32 IDA:1;\r | |
| 1160 | UINT32 Reserved2:31;\r | |
| 1161 | } Bits;\r | |
| 1162 | ///\r | |
| 1163 | /// All bit fields as a 64-bit value\r | |
| 1164 | ///\r | |
| 1165 | UINT64 Uint64;\r | |
| 1166 | } MSR_IA32_PERF_CTL_REGISTER;\r | |
| 1167 | \r | |
| 1168 | \r | |
| 1169 | /**\r | |
| 1170 | Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r | |
| 0f16be6d | 1171 | Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1172 | \r |
| 1173 | @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)\r | |
| 1174 | @param EAX Lower 32-bits of MSR value.\r | |
| 1175 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
| 1176 | @param EDX Upper 32-bits of MSR value.\r | |
| 1177 | Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.\r | |
| 1178 | \r | |
| 1179 | <b>Example usage</b>\r | |
| 1180 | @code\r | |
| 1181 | MSR_IA32_CLOCK_MODULATION_REGISTER Msr;\r | |
| 1182 | \r | |
| 1183 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r | |
| 1184 | AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);\r | |
| 1185 | @endcode\r | |
| 7de98828 | 1186 | @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r |
| 04c980a6 MK |
1187 | **/\r |
| 1188 | #define MSR_IA32_CLOCK_MODULATION 0x0000019A\r | |
| 1189 | \r | |
| 1190 | /**\r | |
| 1191 | MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r | |
| 1192 | **/\r | |
| 1193 | typedef union {\r | |
| 1194 | ///\r | |
| 1195 | /// Individual bit fields\r | |
| 1196 | ///\r | |
| 1197 | struct {\r | |
| 1198 | ///\r | |
| 1199 | /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r | |
| 1200 | /// CPUID.06H:EAX[5] = 1.\r | |
| 1201 | ///\r | |
| 1202 | UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r | |
| 1203 | ///\r | |
| 1204 | /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r | |
| 0f16be6d | 1205 | /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1206 | ///\r |
| 1207 | UINT32 OnDemandClockModulationDutyCycle:3;\r | |
| 1208 | ///\r | |
| 1209 | /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r | |
| 0f16be6d | 1210 | /// If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1211 | ///\r |
| 1212 | UINT32 OnDemandClockModulationEnable:1;\r | |
| 1213 | UINT32 Reserved1:27;\r | |
| 1214 | UINT32 Reserved2:32;\r | |
| 1215 | } Bits;\r | |
| 1216 | ///\r | |
| 1217 | /// All bit fields as a 32-bit value\r | |
| 1218 | ///\r | |
| 1219 | UINT32 Uint32;\r | |
| 1220 | ///\r | |
| 1221 | /// All bit fields as a 64-bit value\r | |
| 1222 | ///\r | |
| 1223 | UINT64 Uint64;\r | |
| 1224 | } MSR_IA32_CLOCK_MODULATION_REGISTER;\r | |
| 1225 | \r | |
| 1226 | \r | |
| 1227 | /**\r | |
| 1228 | Thermal Interrupt Control (R/W) Enables and disables the generation of an\r | |
| 1229 | interrupt on temperature transitions detected with the processor's thermal\r | |
| 1230 | sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".\r | |
| 0f16be6d | 1231 | If CPUID.01H:EDX[22] = 1\r |
| 04c980a6 MK |
1232 | \r |
| 1233 | @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)\r | |
| 1234 | @param EAX Lower 32-bits of MSR value.\r | |
| 1235 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
| 1236 | @param EDX Upper 32-bits of MSR value.\r | |
| 1237 | Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.\r | |
| 1238 | \r | |
| 1239 | <b>Example usage</b>\r | |
| 1240 | @code\r | |
| 1241 | MSR_IA32_THERM_INTERRUPT_REGISTER Msr;\r | |
| 1242 | \r | |
| 1243 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);\r | |
| 1244 | AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);\r | |
| 1245 | @endcode\r | |
| 7de98828 | 1246 | @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r |
| 04c980a6 MK |
1247 | **/\r |
| 1248 | #define MSR_IA32_THERM_INTERRUPT 0x0000019B\r | |
| 1249 | \r | |
| 1250 | /**\r | |
| 1251 | MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r | |
| 1252 | **/\r | |
| 1253 | typedef union {\r | |
| 1254 | ///\r | |
| 1255 | /// Individual bit fields\r | |
| 1256 | ///\r | |
| 1257 | struct {\r | |
| 1258 | ///\r | |
| 0f16be6d | 1259 | /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1260 | ///\r |
| 1261 | UINT32 HighTempEnable:1;\r | |
| 1262 | ///\r | |
| 0f16be6d | 1263 | /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1264 | ///\r |
| 1265 | UINT32 LowTempEnable:1;\r | |
| 1266 | ///\r | |
| 0f16be6d | 1267 | /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1268 | ///\r |
| 1269 | UINT32 PROCHOT_Enable:1;\r | |
| 1270 | ///\r | |
| 0f16be6d | 1271 | /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1272 | ///\r |
| 1273 | UINT32 FORCEPR_Enable:1;\r | |
| 1274 | ///\r | |
| 1275 | /// [Bit 4] Critical Temperature Interrupt Enable.\r | |
| 0f16be6d | 1276 | /// If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1277 | ///\r |
| 1278 | UINT32 CriticalTempEnable:1;\r | |
| 1279 | UINT32 Reserved1:3;\r | |
| 1280 | ///\r | |
| 0f16be6d | 1281 | /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1282 | ///\r |
| 1283 | UINT32 Threshold1:7;\r | |
| 1284 | ///\r | |
| 0f16be6d | 1285 | /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1286 | ///\r |
| 1287 | UINT32 Threshold1Enable:1;\r | |
| 1288 | ///\r | |
| 0f16be6d | 1289 | /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1290 | ///\r |
| 1291 | UINT32 Threshold2:7;\r | |
| 1292 | ///\r | |
| 0f16be6d | 1293 | /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1294 | ///\r |
| 1295 | UINT32 Threshold2Enable:1;\r | |
| 1296 | ///\r | |
| 1297 | /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r | |
| 1298 | ///\r | |
| 1299 | UINT32 PowerLimitNotificationEnable:1;\r | |
| 1300 | UINT32 Reserved2:7;\r | |
| 1301 | UINT32 Reserved3:32;\r | |
| 1302 | } Bits;\r | |
| 1303 | ///\r | |
| 1304 | /// All bit fields as a 32-bit value\r | |
| 1305 | ///\r | |
| 1306 | UINT32 Uint32;\r | |
| 1307 | ///\r | |
| 1308 | /// All bit fields as a 64-bit value\r | |
| 1309 | ///\r | |
| 1310 | UINT64 Uint64;\r | |
| 1311 | } MSR_IA32_THERM_INTERRUPT_REGISTER;\r | |
| 1312 | \r | |
| 1313 | \r | |
| 1314 | /**\r | |
| 1315 | Thermal Status Information (RO) Contains status information about the\r | |
| 1316 | processor's thermal sensor and automatic thermal monitoring facilities. See\r | |
| 0f16be6d | 1317 | Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1318 | \r |
| 1319 | @param ECX MSR_IA32_THERM_STATUS (0x0000019C)\r | |
| 1320 | @param EAX Lower 32-bits of MSR value.\r | |
| 1321 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
| 1322 | @param EDX Upper 32-bits of MSR value.\r | |
| 1323 | Described by the type MSR_IA32_THERM_STATUS_REGISTER.\r | |
| 1324 | \r | |
| 1325 | <b>Example usage</b>\r | |
| 1326 | @code\r | |
| 1327 | MSR_IA32_THERM_STATUS_REGISTER Msr;\r | |
| 1328 | \r | |
| 1329 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);\r | |
| 1330 | @endcode\r | |
| 7de98828 | 1331 | @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r |
| 04c980a6 MK |
1332 | **/\r |
| 1333 | #define MSR_IA32_THERM_STATUS 0x0000019C\r | |
| 1334 | \r | |
| 1335 | /**\r | |
| 1336 | MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r | |
| 1337 | **/\r | |
| 1338 | typedef union {\r | |
| 1339 | ///\r | |
| 1340 | /// Individual bit fields\r | |
| 1341 | ///\r | |
| 1342 | struct {\r | |
| 1343 | ///\r | |
| 0f16be6d | 1344 | /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1345 | ///\r |
| 1346 | UINT32 ThermalStatus:1;\r | |
| 1347 | ///\r | |
| 0f16be6d | 1348 | /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1349 | ///\r |
| 1350 | UINT32 ThermalStatusLog:1;\r | |
| 1351 | ///\r | |
| 0f16be6d | 1352 | /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1353 | ///\r |
| 1354 | UINT32 PROCHOT_FORCEPR_Event:1;\r | |
| 1355 | ///\r | |
| 0f16be6d | 1356 | /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1357 | ///\r |
| 1358 | UINT32 PROCHOT_FORCEPR_Log:1;\r | |
| 1359 | ///\r | |
| 0f16be6d | 1360 | /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1361 | ///\r |
| 1362 | UINT32 CriticalTempStatus:1;\r | |
| 1363 | ///\r | |
| 1364 | /// [Bit 5] Critical Temperature Status log (R/WC0).\r | |
| 0f16be6d | 1365 | /// If CPUID.01H:EDX[22] = 1.\r |
| 04c980a6 MK |
1366 | ///\r |
| 1367 | UINT32 CriticalTempStatusLog:1;\r | |
| 1368 | ///\r | |
| 1369 | /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
| 1370 | ///\r | |
| 1371 | UINT32 ThermalThreshold1Status:1;\r | |
| 1372 | ///\r | |
| 1373 | /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
| 1374 | ///\r | |
| 1375 | UINT32 ThermalThreshold1Log:1;\r | |
| 1376 | ///\r | |
| 1377 | /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r | |
| 1378 | ///\r | |
| 1379 | UINT32 ThermalThreshold2Status:1;\r | |
| 1380 | ///\r | |
| 1381 | /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r | |
| 1382 | ///\r | |
| 1383 | UINT32 ThermalThreshold2Log:1;\r | |
| 1384 | ///\r | |
| 1385 | /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r | |
| 1386 | ///\r | |
| 1387 | UINT32 PowerLimitStatus:1;\r | |
| 1388 | ///\r | |
| 1389 | /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r | |
| 1390 | ///\r | |
| 1391 | UINT32 PowerLimitLog:1;\r | |
| 1392 | ///\r | |
| 1393 | /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
| 1394 | ///\r | |
| 1395 | UINT32 CurrentLimitStatus:1;\r | |
| 1396 | ///\r | |
| 1397 | /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
| 1398 | ///\r | |
| 1399 | UINT32 CurrentLimitLog:1;\r | |
| 1400 | ///\r | |
| 1401 | /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r | |
| 1402 | ///\r | |
| 1403 | UINT32 CrossDomainLimitStatus:1;\r | |
| 1404 | ///\r | |
| 1405 | /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r | |
| 1406 | ///\r | |
| 1407 | UINT32 CrossDomainLimitLog:1;\r | |
| 1408 | ///\r | |
| 1409 | /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r | |
| 1410 | ///\r | |
| 1411 | UINT32 DigitalReadout:7;\r | |
| 1412 | UINT32 Reserved1:4;\r | |
| 1413 | ///\r | |
| 1414 | /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r | |
| 1415 | /// 1.\r | |
| 1416 | ///\r | |
| 1417 | UINT32 ResolutionInDegreesCelsius:4;\r | |
| 1418 | ///\r | |
| 1419 | /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r | |
| 1420 | ///\r | |
| 1421 | UINT32 ReadingValid:1;\r | |
| 1422 | UINT32 Reserved2:32;\r | |
| 1423 | } Bits;\r | |
| 1424 | ///\r | |
| 1425 | /// All bit fields as a 32-bit value\r | |
| 1426 | ///\r | |
| 1427 | UINT32 Uint32;\r | |
| 1428 | ///\r | |
| 1429 | /// All bit fields as a 64-bit value\r | |
| 1430 | ///\r | |
| 1431 | UINT64 Uint64;\r | |
| 1432 | } MSR_IA32_THERM_STATUS_REGISTER;\r | |
| 1433 | \r | |
| 1434 | \r | |
| 1435 | /**\r | |
| 1436 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
| 1437 | functions to be enabled and disabled.\r | |
| 1438 | \r | |
| 1439 | @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)\r | |
| 1440 | @param EAX Lower 32-bits of MSR value.\r | |
| 1441 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
| 1442 | @param EDX Upper 32-bits of MSR value.\r | |
| 1443 | Described by the type MSR_IA32_MISC_ENABLE_REGISTER.\r | |
| 1444 | \r | |
| 1445 | <b>Example usage</b>\r | |
| 1446 | @code\r | |
| 1447 | MSR_IA32_MISC_ENABLE_REGISTER Msr;\r | |
| 1448 | \r | |
| 1449 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);\r | |
| 1450 | AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);\r | |
| 1451 | @endcode\r | |
| 7de98828 | 1452 | @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
| 04c980a6 MK |
1453 | **/\r |
| 1454 | #define MSR_IA32_MISC_ENABLE 0x000001A0\r | |
| 1455 | \r | |
| 1456 | /**\r | |
| 1457 | MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r | |
| 1458 | **/\r | |
| 1459 | typedef union {\r | |
| 1460 | ///\r | |
| 1461 | /// Individual bit fields\r | |
| 1462 | ///\r | |
| 1463 | struct {\r | |
| 1464 | ///\r | |
| 1465 | /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for\r | |
| 1466 | /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r | |
| 1467 | /// are disabled. Introduced at Display Family / Display Model 0F_0H.\r | |
| 1468 | ///\r | |
| 1469 | UINT32 FastStrings:1;\r | |
| 1470 | UINT32 Reserved1:2;\r | |
| 1471 | ///\r | |
| 1472 | /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r | |
| 1473 | /// this bit enables the thermal control circuit (TCC) portion of the\r | |
| 1474 | /// Intel Thermal Monitor feature. This allows the processor to\r | |
| 1475 | /// automatically reduce power consumption in response to TCC activation.\r | |
| 1476 | /// 0 = Disabled. Note: In some products clearing this bit might be\r | |
| 1477 | /// ignored in critical thermal conditions, and TM1, TM2 and adaptive\r | |
| 0f16be6d HW |
1478 | /// thermal throttling will still be activated. The default value of this\r |
| 1479 | /// field varies with product. See respective tables where default value is\r | |
| 1480 | /// listed. Introduced at Display Family / Display Model 0F_0H.\r | |
| 04c980a6 MK |
1481 | ///\r |
| 1482 | UINT32 AutomaticThermalControlCircuit:1;\r | |
| 1483 | UINT32 Reserved2:3;\r | |
| 1484 | ///\r | |
| 1485 | /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r | |
| 1486 | /// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r | |
| 1487 | /// Display Family / Display Model 0F_0H.\r | |
| 1488 | ///\r | |
| 1489 | UINT32 PerformanceMonitoring:1;\r | |
| 1490 | UINT32 Reserved3:3;\r | |
| 1491 | ///\r | |
| 1492 | /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r | |
| 1493 | /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r | |
| 1494 | /// Display Family / Display Model 0F_0H.\r | |
| 1495 | ///\r | |
| 1496 | UINT32 BTS:1;\r | |
| 1497 | ///\r | |
| 0f16be6d | 1498 | /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r |
| 04c980a6 MK |
1499 | /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r |
| 1500 | /// Family / Display Model 06_0FH.\r | |
| 1501 | ///\r | |
| 1502 | UINT32 PEBS:1;\r | |
| 1503 | UINT32 Reserved4:3;\r | |
| 1504 | ///\r | |
| 1505 | /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r | |
| 1506 | /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r | |
| 1507 | /// Technology enabled. If CPUID.01H: ECX[7] =1.\r | |
| 1508 | ///\r | |
| 1509 | UINT32 EIST:1;\r | |
| 1510 | UINT32 Reserved5:1;\r | |
| 1511 | ///\r | |
| 1512 | /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r | |
| 1513 | /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r | |
| 1514 | /// indicates that MONITOR/MWAIT are not supported. Software attempts to\r | |
| 1515 | /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit\r | |
| 1516 | /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit\r | |
| 1517 | /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit\r | |
| 1518 | /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it\r | |
| 1519 | /// in the default state. Writing this bit when the SSE3 feature flag is\r | |
| 1520 | /// set to 0 may generate a #GP exception. Introduced at Display Family /\r | |
| 1521 | /// Display Model 0F_03H.\r | |
| 1522 | ///\r | |
| 1523 | UINT32 MONITOR:1;\r | |
| 1524 | UINT32 Reserved6:3;\r | |
| 1525 | ///\r | |
| 1526 | /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r | |
| 0f16be6d | 1527 | /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r |
| 04c980a6 | 1528 | /// question that allows users to specify when the installed OS does not\r |
| 0f16be6d | 1529 | /// support CPUID functions greater than 2. Before setting this bit, BIOS\r |
| 04c980a6 | 1530 | /// must execute the CPUID.0H and examine the maximum value returned in\r |
| 0f16be6d HW |
1531 | /// EAX[7:0]. If the maximum value is greater than 2, this bit is\r |
| 1532 | /// supported. Otherwise, this bit is not supported. Setting this bit when\r | |
| 1533 | /// the maximum value is not greater than 2 may generate a #GP exception.\r | |
| 04c980a6 | 1534 | /// Setting this bit may cause unexpected behavior in software that\r |
| 0f16be6d | 1535 | /// depends on the availability of CPUID leaves greater than 2. Introduced\r |
| 04c980a6 MK |
1536 | /// at Display Family / Display Model 0F_03H.\r |
| 1537 | ///\r | |
| 1538 | UINT32 LimitCpuidMaxval:1;\r | |
| 1539 | ///\r | |
| 1540 | /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r | |
| 1541 | /// disabled. xTPR messages are optional messages that allow the processor\r | |
| 1542 | /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r | |
| 1543 | ///\r | |
| 1544 | UINT32 xTPR_Message_Disable:1;\r | |
| 1545 | UINT32 Reserved7:8;\r | |
| 1546 | UINT32 Reserved8:2;\r | |
| 1547 | ///\r | |
| 1548 | /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r | |
| 1549 | /// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r | |
| 1550 | /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the\r | |
| 1551 | /// Execute Disable Bit feature (if available) allows the OS to enable PAE\r | |
| 1552 | /// paging and take advantage of data only pages. BIOS must not alter the\r | |
| 1553 | /// contents of this bit location, if XD bit is not supported. Writing\r | |
| 1554 | /// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r | |
| 1555 | /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r | |
| 1556 | ///\r | |
| 1557 | UINT32 XD:1;\r | |
| 1558 | UINT32 Reserved9:29;\r | |
| 1559 | } Bits;\r | |
| 1560 | ///\r | |
| 1561 | /// All bit fields as a 64-bit value\r | |
| 1562 | ///\r | |
| 1563 | UINT64 Uint64;\r | |
| 1564 | } MSR_IA32_MISC_ENABLE_REGISTER;\r | |
| 1565 | \r | |
| 1566 | \r | |
| 1567 | /**\r | |
| 1568 | Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r | |
| 1569 | \r | |
| 1570 | @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)\r | |
| 1571 | @param EAX Lower 32-bits of MSR value.\r | |
| 1572 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
| 1573 | @param EDX Upper 32-bits of MSR value.\r | |
| 1574 | Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.\r | |
| 1575 | \r | |
| 1576 | <b>Example usage</b>\r | |
| 1577 | @code\r | |
| 1578 | MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;\r | |
| 1579 | \r | |
| 1580 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);\r | |
| 1581 | AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);\r | |
| 1582 | @endcode\r | |
| 7de98828 | 1583 | @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r |
| 04c980a6 MK |
1584 | **/\r |
| 1585 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r | |
| 1586 | \r | |
| 1587 | /**\r | |
| 1588 | MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r | |
| 1589 | **/\r | |
| 1590 | typedef union {\r | |
| 1591 | ///\r | |
| 1592 | /// Individual bit fields\r | |
| 1593 | ///\r | |
| 1594 | struct {\r | |
| 1595 | ///\r | |
| 1596 | /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r | |
| 1597 | /// performance. 15 indicates preference to maximize energy saving.\r | |
| 1598 | ///\r | |
| 1599 | UINT32 PowerPolicyPreference:4;\r | |
| 1600 | UINT32 Reserved1:28;\r | |
| 1601 | UINT32 Reserved2:32;\r | |
| 1602 | } Bits;\r | |
| 1603 | ///\r | |
| 1604 | /// All bit fields as a 32-bit value\r | |
| 1605 | ///\r | |
| 1606 | UINT32 Uint32;\r | |
| 1607 | ///\r | |
| 1608 | /// All bit fields as a 64-bit value\r | |
| 1609 | ///\r | |
| 1610 | UINT64 Uint64;\r | |
| 1611 | } MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r | |
| 1612 | \r | |
| 1613 | \r | |
| 1614 | /**\r | |
| 1615 | Package Thermal Status Information (RO) Contains status information about\r | |
| 1616 | the package's thermal sensor. See Section 14.8, "Package Level Thermal\r | |
| 1617 | Management.". If CPUID.06H: EAX[6] = 1.\r | |
| 1618 | \r | |
| 1619 | @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)\r | |
| 1620 | @param EAX Lower 32-bits of MSR value.\r | |
| 1621 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
| 1622 | @param EDX Upper 32-bits of MSR value.\r | |
| 1623 | Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.\r | |
| 1624 | \r | |
| 1625 | <b>Example usage</b>\r | |
| 1626 | @code\r | |
| 1627 | MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;\r | |
| 1628 | \r | |
| 1629 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);\r | |
| 1630 | @endcode\r | |
| 7de98828 | 1631 | @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r |
| 04c980a6 MK |
1632 | **/\r |
| 1633 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r | |
| 1634 | \r | |
| 1635 | /**\r | |
| 1636 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r | |
| 1637 | **/\r | |
| 1638 | typedef union {\r | |
| 1639 | ///\r | |
| 1640 | /// Individual bit fields\r | |
| 1641 | ///\r | |
| 1642 | struct {\r | |
| 1643 | ///\r | |
| 1644 | /// [Bit 0] Pkg Thermal Status (RO):.\r | |
| 1645 | ///\r | |
| 1646 | UINT32 ThermalStatus:1;\r | |
| 1647 | ///\r | |
| 1648 | /// [Bit 1] Pkg Thermal Status Log (R/W):.\r | |
| 1649 | ///\r | |
| 1650 | UINT32 ThermalStatusLog:1;\r | |
| 1651 | ///\r | |
| 1652 | /// [Bit 2] Pkg PROCHOT # event (RO).\r | |
| 1653 | ///\r | |
| 1654 | UINT32 PROCHOT_Event:1;\r | |
| 1655 | ///\r | |
| 1656 | /// [Bit 3] Pkg PROCHOT # log (R/WC0).\r | |
| 1657 | ///\r | |
| 1658 | UINT32 PROCHOT_Log:1;\r | |
| 1659 | ///\r | |
| 1660 | /// [Bit 4] Pkg Critical Temperature Status (RO).\r | |
| 1661 | ///\r | |
| 1662 | UINT32 CriticalTempStatus:1;\r | |
| 1663 | ///\r | |
| 1664 | /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r | |
| 1665 | ///\r | |
| 1666 | UINT32 CriticalTempStatusLog:1;\r | |
| 1667 | ///\r | |
| 1668 | /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r | |
| 1669 | ///\r | |
| 1670 | UINT32 ThermalThreshold1Status:1;\r | |
| 1671 | ///\r | |
| 1672 | /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r | |
| 1673 | ///\r | |
| 1674 | UINT32 ThermalThreshold1Log:1;\r | |
| 1675 | ///\r | |
| 1676 | /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r | |
| 1677 | ///\r | |
| 1678 | UINT32 ThermalThreshold2Status:1;\r | |
| 1679 | ///\r | |
| 1680 | /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r | |
| 1681 | ///\r | |
| 1682 | UINT32 ThermalThreshold2Log:1;\r | |
| 1683 | ///\r | |
| 1684 | /// [Bit 10] Pkg Power Limitation Status (RO).\r | |
| 1685 | ///\r | |
| 1686 | UINT32 PowerLimitStatus:1;\r | |
| 1687 | ///\r | |
| 1688 | /// [Bit 11] Pkg Power Limitation log (R/WC0).\r | |
| 1689 | ///\r | |
| 1690 | UINT32 PowerLimitLog:1;\r | |
| 1691 | UINT32 Reserved1:4;\r | |
| 1692 | ///\r | |
| 1693 | /// [Bits 22:16] Pkg Digital Readout (RO).\r | |
| 1694 | ///\r | |
| 1695 | UINT32 DigitalReadout:7;\r | |
| 1696 | UINT32 Reserved2:9;\r | |
| 1697 | UINT32 Reserved3:32;\r | |
| 1698 | } Bits;\r | |
| 1699 | ///\r | |
| 1700 | /// All bit fields as a 32-bit value\r | |
| 1701 | ///\r | |
| 1702 | UINT32 Uint32;\r | |
| 1703 | ///\r | |
| 1704 | /// All bit fields as a 64-bit value\r | |
| 1705 | ///\r | |
| 1706 | UINT64 Uint64;\r | |
| 1707 | } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r | |
| 1708 | \r | |
| 1709 | \r | |
| 1710 | /**\r | |
| 1711 | Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r | |
| 1712 | an interrupt on temperature transitions detected with the package's thermal\r | |
| 1713 | sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:\r | |
| 1714 | EAX[6] = 1.\r | |
| 1715 | \r | |
| 1716 | @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)\r | |
| 1717 | @param EAX Lower 32-bits of MSR value.\r | |
| 1718 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
| 1719 | @param EDX Upper 32-bits of MSR value.\r | |
| 1720 | Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.\r | |
| 1721 | \r | |
| 1722 | <b>Example usage</b>\r | |
| 1723 | @code\r | |
| 1724 | MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;\r | |
| 1725 | \r | |
| 1726 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);\r | |
| 1727 | AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);\r | |
| 1728 | @endcode\r | |
| 7de98828 | 1729 | @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r |
| 04c980a6 MK |
1730 | **/\r |
| 1731 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r | |
| 1732 | \r | |
| 1733 | /**\r | |
| 1734 | MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r | |
| 1735 | **/\r | |
| 1736 | typedef union {\r | |
| 1737 | ///\r | |
| 1738 | /// Individual bit fields\r | |
| 1739 | ///\r | |
| 1740 | struct {\r | |
| 1741 | ///\r | |
| 1742 | /// [Bit 0] Pkg High-Temperature Interrupt Enable.\r | |
| 1743 | ///\r | |
| 1744 | UINT32 HighTempEnable:1;\r | |
| 1745 | ///\r | |
| 1746 | /// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r | |
| 1747 | ///\r | |
| 1748 | UINT32 LowTempEnable:1;\r | |
| 1749 | ///\r | |
| 1750 | /// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r | |
| 1751 | ///\r | |
| 1752 | UINT32 PROCHOT_Enable:1;\r | |
| 1753 | UINT32 Reserved1:1;\r | |
| 1754 | ///\r | |
| 1755 | /// [Bit 4] Pkg Overheat Interrupt Enable.\r | |
| 1756 | ///\r | |
| 1757 | UINT32 OverheatEnable:1;\r | |
| 1758 | UINT32 Reserved2:3;\r | |
| 1759 | ///\r | |
| 1760 | /// [Bits 14:8] Pkg Threshold #1 Value.\r | |
| 1761 | ///\r | |
| 1762 | UINT32 Threshold1:7;\r | |
| 1763 | ///\r | |
| 1764 | /// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r | |
| 1765 | ///\r | |
| 1766 | UINT32 Threshold1Enable:1;\r | |
| 1767 | ///\r | |
| 1768 | /// [Bits 22:16] Pkg Threshold #2 Value.\r | |
| 1769 | ///\r | |
| 1770 | UINT32 Threshold2:7;\r | |
| 1771 | ///\r | |
| 1772 | /// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r | |
| 1773 | ///\r | |
| 1774 | UINT32 Threshold2Enable:1;\r | |
| 1775 | ///\r | |
| 1776 | /// [Bit 24] Pkg Power Limit Notification Enable.\r | |
| 1777 | ///\r | |
| 1778 | UINT32 PowerLimitNotificationEnable:1;\r | |
| 1779 | UINT32 Reserved3:7;\r | |
| 1780 | UINT32 Reserved4:32;\r | |
| 1781 | } Bits;\r | |
| 1782 | ///\r | |
| 1783 | /// All bit fields as a 32-bit value\r | |
| 1784 | ///\r | |
| 1785 | UINT32 Uint32;\r | |
| 1786 | ///\r | |
| 1787 | /// All bit fields as a 64-bit value\r | |
| 1788 | ///\r | |
| 1789 | UINT64 Uint64;\r | |
| 1790 | } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r | |
| 1791 | \r | |
| 1792 | \r | |
| 1793 | /**\r | |
| 1794 | Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r | |
| 1795 | Model 06_0EH.\r | |
| 1796 | \r | |
| 1797 | @param ECX MSR_IA32_DEBUGCTL (0x000001D9)\r | |
| 1798 | @param EAX Lower 32-bits of MSR value.\r | |
| 1799 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
| 1800 | @param EDX Upper 32-bits of MSR value.\r | |
| 1801 | Described by the type MSR_IA32_DEBUGCTL_REGISTER.\r | |
| 1802 | \r | |
| 1803 | <b>Example usage</b>\r | |
| 1804 | @code\r | |
| 1805 | MSR_IA32_DEBUGCTL_REGISTER Msr;\r | |
| 1806 | \r | |
| 1807 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);\r | |
| 1808 | AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);\r | |
| 1809 | @endcode\r | |
| 7de98828 | 1810 | @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r |
| 04c980a6 MK |
1811 | **/\r |
| 1812 | #define MSR_IA32_DEBUGCTL 0x000001D9\r | |
| 1813 | \r | |
| 1814 | /**\r | |
| 1815 | MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r | |
| 1816 | **/\r | |
| 1817 | typedef union {\r | |
| 1818 | ///\r | |
| 1819 | /// Individual bit fields\r | |
| 1820 | ///\r | |
| 1821 | struct {\r | |
| 1822 | ///\r | |
| 1823 | /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a\r | |
| 1824 | /// running trace of the most recent branches taken by the processor in\r | |
| 1825 | /// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r | |
| 1826 | ///\r | |
| 1827 | UINT32 LBR:1;\r | |
| 1828 | ///\r | |
| 1829 | /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r | |
| 1830 | /// EFLAGS.TF as single-step on branches instead of single-step on\r | |
| 1831 | /// instructions. Introduced at Display Family / Display Model 06_01H.\r | |
| 1832 | ///\r | |
| 1833 | UINT32 BTF:1;\r | |
| 1834 | UINT32 Reserved1:4;\r | |
| 1835 | ///\r | |
| 1836 | /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r | |
| 1837 | /// sent. Introduced at Display Family / Display Model 06_0EH.\r | |
| 1838 | ///\r | |
| 1839 | UINT32 TR:1;\r | |
| 1840 | ///\r | |
| 1841 | /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r | |
| 1842 | /// be logged in a BTS buffer. Introduced at Display Family / Display\r | |
| 1843 | /// Model 06_0EH.\r | |
| 1844 | ///\r | |
| 1845 | UINT32 BTS:1;\r | |
| 1846 | ///\r | |
| 1847 | /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r | |
| 1848 | /// fashion. When this bit is set, an interrupt is generated by the BTS\r | |
| 1849 | /// facility when the BTS buffer is full. Introduced at Display Family /\r | |
| 1850 | /// Display Model 06_0EH.\r | |
| 1851 | ///\r | |
| 1852 | UINT32 BTINT:1;\r | |
| 1853 | ///\r | |
| 1854 | /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r | |
| 1855 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
| 1856 | ///\r | |
| 1857 | UINT32 BTS_OFF_OS:1;\r | |
| 1858 | ///\r | |
| 1859 | /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r | |
| 1860 | /// Introduced at Display Family / Display Model 06_0FH.\r | |
| 1861 | ///\r | |
| 1862 | UINT32 BTS_OFF_USR:1;\r | |
| 1863 | ///\r | |
| 1864 | /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r | |
| 1865 | /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
| 1866 | ///\r | |
| 1867 | UINT32 FREEZE_LBRS_ON_PMI:1;\r | |
| 1868 | ///\r | |
| 1869 | /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r | |
| 1870 | /// global counter control MSR are frozen (address 38FH) on a PMI request.\r | |
| 1871 | /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r | |
| 1872 | ///\r | |
| 1873 | UINT32 FREEZE_PERFMON_ON_PMI:1;\r | |
| 1874 | ///\r | |
| 1875 | /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r | |
| 1876 | /// receive and generate PMI on behalf of the uncore. Introduced at\r | |
| 1877 | /// Display Family / Display Model 06_1AH.\r | |
| 1878 | ///\r | |
| 1879 | UINT32 ENABLE_UNCORE_PMI:1;\r | |
| 1880 | ///\r | |
| 1881 | /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r | |
| 1882 | /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r | |
| 1883 | ///\r | |
| 1884 | UINT32 FREEZE_WHILE_SMM:1;\r | |
| 1885 | ///\r | |
| 1886 | /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r | |
| 1887 | /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r | |
| 1888 | ///\r | |
| 1889 | UINT32 RTM_DEBUG:1;\r | |
| 1890 | UINT32 Reserved2:16;\r | |
| 1891 | UINT32 Reserved3:32;\r | |
| 1892 | } Bits;\r | |
| 1893 | ///\r | |
| 1894 | /// All bit fields as a 32-bit value\r | |
| 1895 | ///\r | |
| 1896 | UINT32 Uint32;\r | |
| 1897 | ///\r | |
| 1898 | /// All bit fields as a 64-bit value\r | |
| 1899 | ///\r | |
| 1900 | UINT64 Uint64;\r | |
| 1901 | } MSR_IA32_DEBUGCTL_REGISTER;\r | |
| 1902 | \r | |
| 1903 | \r | |
| 1904 | /**\r | |
| 1905 | SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r | |
| 1906 | If IA32_MTRRCAP.SMRR[11] = 1.\r | |
| 1907 | \r | |
| 1908 | @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)\r | |
| 1909 | @param EAX Lower 32-bits of MSR value.\r | |
| 1910 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
| 1911 | @param EDX Upper 32-bits of MSR value.\r | |
| 1912 | Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.\r | |
| 1913 | \r | |
| 1914 | <b>Example usage</b>\r | |
| 1915 | @code\r | |
| 1916 | MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;\r | |
| 1917 | \r | |
| 1918 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);\r | |
| 1919 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);\r | |
| 1920 | @endcode\r | |
| 7de98828 | 1921 | @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r |
| 04c980a6 MK |
1922 | **/\r |
| 1923 | #define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r | |
| 1924 | \r | |
| 1925 | /**\r | |
| 1926 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r | |
| 1927 | **/\r | |
| 1928 | typedef union {\r | |
| 1929 | ///\r | |
| 1930 | /// Individual bit fields\r | |
| 1931 | ///\r | |
| 1932 | struct {\r | |
| 1933 | ///\r | |
| 1934 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
| 1935 | ///\r | |
| 1936 | UINT32 Type:8;\r | |
| 1937 | UINT32 Reserved1:4;\r | |
| 1938 | ///\r | |
| 1939 | /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r | |
| 1940 | ///\r | |
| 1941 | UINT32 PhysBase:20;\r | |
| 1942 | UINT32 Reserved2:32;\r | |
| 1943 | } Bits;\r | |
| 1944 | ///\r | |
| 1945 | /// All bit fields as a 32-bit value\r | |
| 1946 | ///\r | |
| 1947 | UINT32 Uint32;\r | |
| 1948 | ///\r | |
| 1949 | /// All bit fields as a 64-bit value\r | |
| 1950 | ///\r | |
| 1951 | UINT64 Uint64;\r | |
| 1952 | } MSR_IA32_SMRR_PHYSBASE_REGISTER;\r | |
| 1953 | \r | |
| 1954 | \r | |
| 1955 | /**\r | |
| 1956 | SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If\r | |
| 1957 | IA32_MTRRCAP[SMRR] = 1.\r | |
| 1958 | \r | |
| 1959 | @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)\r | |
| 1960 | @param EAX Lower 32-bits of MSR value.\r | |
| 1961 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
| 1962 | @param EDX Upper 32-bits of MSR value.\r | |
| 1963 | Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.\r | |
| 1964 | \r | |
| 1965 | <b>Example usage</b>\r | |
| 1966 | @code\r | |
| 1967 | MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;\r | |
| 1968 | \r | |
| 1969 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);\r | |
| 1970 | AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);\r | |
| 1971 | @endcode\r | |
| 7de98828 | 1972 | @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r |
| 04c980a6 MK |
1973 | **/\r |
| 1974 | #define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r | |
| 1975 | \r | |
| 1976 | /**\r | |
| 1977 | MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r | |
| 1978 | **/\r | |
| 1979 | typedef union {\r | |
| 1980 | ///\r | |
| 1981 | /// Individual bit fields\r | |
| 1982 | ///\r | |
| 1983 | struct {\r | |
| 1984 | UINT32 Reserved1:11;\r | |
| 1985 | ///\r | |
| 1986 | /// [Bit 11] Valid Enable range mask.\r | |
| 1987 | ///\r | |
| 1988 | UINT32 Valid:1;\r | |
| 1989 | ///\r | |
| 1990 | /// [Bits 31:12] PhysMask SMRR address range mask.\r | |
| 1991 | ///\r | |
| 1992 | UINT32 PhysMask:20;\r | |
| 1993 | UINT32 Reserved2:32;\r | |
| 1994 | } Bits;\r | |
| 1995 | ///\r | |
| 1996 | /// All bit fields as a 32-bit value\r | |
| 1997 | ///\r | |
| 1998 | UINT32 Uint32;\r | |
| 1999 | ///\r | |
| 2000 | /// All bit fields as a 64-bit value\r | |
| 2001 | ///\r | |
| 2002 | UINT64 Uint64;\r | |
| 2003 | } MSR_IA32_SMRR_PHYSMASK_REGISTER;\r | |
| 2004 | \r | |
| 2005 | \r | |
| 2006 | /**\r | |
| 2007 | DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r | |
| 2008 | \r | |
| 2009 | @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)\r | |
| 2010 | @param EAX Lower 32-bits of MSR value.\r | |
| 2011 | @param EDX Upper 32-bits of MSR value.\r | |
| 2012 | \r | |
| 2013 | <b>Example usage</b>\r | |
| 2014 | @code\r | |
| 2015 | UINT64 Msr;\r | |
| 2016 | \r | |
| 2017 | Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);\r | |
| 2018 | @endcode\r | |
| 7de98828 | 2019 | @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r |
| 04c980a6 MK |
2020 | **/\r |
| 2021 | #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r | |
| 2022 | \r | |
| 2023 | \r | |
| 2024 | /**\r | |
| 2025 | If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r | |
| 2026 | \r | |
| 2027 | @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)\r | |
| 2028 | @param EAX Lower 32-bits of MSR value.\r | |
| 2029 | @param EDX Upper 32-bits of MSR value.\r | |
| 2030 | \r | |
| 2031 | <b>Example usage</b>\r | |
| 2032 | @code\r | |
| 2033 | UINT64 Msr;\r | |
| 2034 | \r | |
| 2035 | Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);\r | |
| 2036 | AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);\r | |
| 2037 | @endcode\r | |
| 7de98828 | 2038 | @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r |
| 04c980a6 MK |
2039 | **/\r |
| 2040 | #define MSR_IA32_CPU_DCA_CAP 0x000001F9\r | |
| 2041 | \r | |
| 2042 | \r | |
| 2043 | /**\r | |
| 2044 | DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r | |
| 2045 | \r | |
| 2046 | @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)\r | |
| 2047 | @param EAX Lower 32-bits of MSR value.\r | |
| 2048 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
| 2049 | @param EDX Upper 32-bits of MSR value.\r | |
| 2050 | Described by the type MSR_IA32_DCA_0_CAP_REGISTER.\r | |
| 2051 | \r | |
| 2052 | <b>Example usage</b>\r | |
| 2053 | @code\r | |
| 2054 | MSR_IA32_DCA_0_CAP_REGISTER Msr;\r | |
| 2055 | \r | |
| 2056 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);\r | |
| 2057 | AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);\r | |
| 2058 | @endcode\r | |
| 7de98828 | 2059 | @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r |
| 04c980a6 MK |
2060 | **/\r |
| 2061 | #define MSR_IA32_DCA_0_CAP 0x000001FA\r | |
| 2062 | \r | |
| 2063 | /**\r | |
| 2064 | MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r | |
| 2065 | **/\r | |
| 2066 | typedef union {\r | |
| 2067 | ///\r | |
| 2068 | /// Individual bit fields\r | |
| 2069 | ///\r | |
| 2070 | struct {\r | |
| 2071 | ///\r | |
| 2072 | /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r | |
| 2073 | /// defeatures are set.\r | |
| 2074 | ///\r | |
| 2075 | UINT32 DCA_ACTIVE:1;\r | |
| 2076 | ///\r | |
| 2077 | /// [Bits 2:1] TRANSACTION.\r | |
| 2078 | ///\r | |
| 2079 | UINT32 TRANSACTION:2;\r | |
| 2080 | ///\r | |
| 2081 | /// [Bits 6:3] DCA_TYPE.\r | |
| 2082 | ///\r | |
| 2083 | UINT32 DCA_TYPE:4;\r | |
| 2084 | ///\r | |
| 2085 | /// [Bits 10:7] DCA_QUEUE_SIZE.\r | |
| 2086 | ///\r | |
| 2087 | UINT32 DCA_QUEUE_SIZE:4;\r | |
| 2088 | UINT32 Reserved1:2;\r | |
| 2089 | ///\r | |
| 2090 | /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r | |
| 2091 | /// side-effect.\r | |
| 2092 | ///\r | |
| 2093 | UINT32 DCA_DELAY:4;\r | |
| 2094 | UINT32 Reserved2:7;\r | |
| 2095 | ///\r | |
| 2096 | /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r | |
| 2097 | ///\r | |
| 2098 | UINT32 SW_BLOCK:1;\r | |
| 2099 | UINT32 Reserved3:1;\r | |
| 2100 | ///\r | |
| 2101 | /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r | |
| 2102 | ///\r | |
| 2103 | UINT32 HW_BLOCK:1;\r | |
| 2104 | UINT32 Reserved4:5;\r | |
| 2105 | UINT32 Reserved5:32;\r | |
| 2106 | } Bits;\r | |
| 2107 | ///\r | |
| 2108 | /// All bit fields as a 32-bit value\r | |
| 2109 | ///\r | |
| 2110 | UINT32 Uint32;\r | |
| 2111 | ///\r | |
| 2112 | /// All bit fields as a 64-bit value\r | |
| 2113 | ///\r | |
| 2114 | UINT64 Uint64;\r | |
| 2115 | } MSR_IA32_DCA_0_CAP_REGISTER;\r | |
| 2116 | \r | |
| 2117 | \r | |
| 2118 | /**\r | |
| 2119 | MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
| 2120 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
| 2121 | \r | |
| 2122 | @param ECX MSR_IA32_MTRR_PHYSBASEn\r | |
| 2123 | @param EAX Lower 32-bits of MSR value.\r | |
| 2124 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
| 2125 | @param EDX Upper 32-bits of MSR value.\r | |
| 2126 | Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.\r | |
| 2127 | \r | |
| 2128 | <b>Example usage</b>\r | |
| 2129 | @code\r | |
| 2130 | MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;\r | |
| 2131 | \r | |
| 2132 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);\r | |
| 2133 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);\r | |
| 2134 | @endcode\r | |
| 7de98828 JF |
2135 | @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.\r |
| 2136 | MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.\r | |
| 2137 | MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.\r | |
| 2138 | MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.\r | |
| 2139 | MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.\r | |
| 2140 | MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.\r | |
| 2141 | MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.\r | |
| 2142 | MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.\r | |
| 2143 | MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.\r | |
| 2144 | MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r | |
| 04c980a6 MK |
2145 | @{\r |
| 2146 | **/\r | |
| 2147 | #define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r | |
| 2148 | #define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r | |
| 2149 | #define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r | |
| 2150 | #define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r | |
| 2151 | #define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r | |
| 2152 | #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r | |
| 2153 | #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r | |
| 2154 | #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r | |
| 2155 | #define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r | |
| 2156 | #define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r | |
| 2157 | /// @}\r | |
| 2158 | \r | |
| 2159 | /**\r | |
| 2160 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to\r | |
| 2161 | #MSR_IA32_MTRR_PHYSBASE9\r | |
| 2162 | **/\r | |
| 2163 | typedef union {\r | |
| 2164 | ///\r | |
| 2165 | /// Individual bit fields\r | |
| 2166 | ///\r | |
| 2167 | struct {\r | |
| 2168 | ///\r | |
| 2169 | /// [Bits 7:0] Type. Specifies memory type of the range.\r | |
| 2170 | ///\r | |
| 2171 | UINT32 Type:8;\r | |
| 2172 | UINT32 Reserved1:4;\r | |
| 2173 | ///\r | |
| 2174 | /// [Bits 31:12] PhysBase. MTRR physical Base Address.\r | |
| 2175 | ///\r | |
| 2176 | UINT32 PhysBase:20;\r | |
| 2177 | ///\r | |
| 2178 | /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r | |
| 2179 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
| 2180 | /// maximum physical address range supported by the processor. It is\r | |
| 2181 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
| 2182 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
| 2183 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
| 2184 | ///\r | |
| 2185 | UINT32 PhysBaseHi:32;\r | |
| 2186 | } Bits;\r | |
| 2187 | ///\r | |
| 2188 | /// All bit fields as a 64-bit value\r | |
| 2189 | ///\r | |
| 2190 | UINT64 Uint64;\r | |
| 2191 | } MSR_IA32_MTRR_PHYSBASE_REGISTER;\r | |
| 2192 | \r | |
| 2193 | \r | |
| 2194 | /**\r | |
| 2195 | MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r | |
| 2196 | If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r | |
| 2197 | \r | |
| 2198 | @param ECX MSR_IA32_MTRR_PHYSMASKn\r | |
| 2199 | @param EAX Lower 32-bits of MSR value.\r | |
| 2200 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
| 2201 | @param EDX Upper 32-bits of MSR value.\r | |
| 2202 | Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.\r | |
| 2203 | \r | |
| 2204 | <b>Example usage</b>\r | |
| 2205 | @code\r | |
| 2206 | MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;\r | |
| 2207 | \r | |
| 2208 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);\r | |
| 2209 | AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);\r | |
| 2210 | @endcode\r | |
| 7de98828 JF |
2211 | @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.\r |
| 2212 | MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.\r | |
| 2213 | MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.\r | |
| 2214 | MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.\r | |
| 2215 | MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.\r | |
| 2216 | MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.\r | |
| 2217 | MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.\r | |
| 2218 | MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.\r | |
| 2219 | MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.\r | |
| 2220 | MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r | |
| 04c980a6 MK |
2221 | @{\r |
| 2222 | **/\r | |
| 2223 | #define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r | |
| 2224 | #define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r | |
| 2225 | #define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r | |
| 2226 | #define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r | |
| 2227 | #define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r | |
| 2228 | #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r | |
| 2229 | #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r | |
| 2230 | #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r | |
| 2231 | #define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r | |
| 2232 | #define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r | |
| 2233 | /// @}\r | |
| 2234 | \r | |
| 2235 | /**\r | |
| 2236 | MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to\r | |
| 2237 | #MSR_IA32_MTRR_PHYSMASK9\r | |
| 2238 | **/\r | |
| 2239 | typedef union {\r | |
| 2240 | ///\r | |
| 2241 | /// Individual bit fields\r | |
| 2242 | ///\r | |
| 2243 | struct {\r | |
| 2244 | UINT32 Reserved1:11;\r | |
| 2245 | ///\r | |
| 2246 | /// [Bit 11] Valid Enable range mask.\r | |
| 2247 | ///\r | |
| 490b048b | 2248 | UINT32 V:1;\r |
| 04c980a6 MK |
2249 | ///\r |
| 2250 | /// [Bits 31:12] PhysMask. MTRR address range mask.\r | |
| 2251 | ///\r | |
| 2252 | UINT32 PhysMask:20;\r | |
| 2253 | ///\r | |
| 2254 | /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r | |
| 2255 | /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r | |
| 2256 | /// maximum physical address range supported by the processor. It is\r | |
| 2257 | /// reported by CPUID leaf function 80000008H. If CPUID does not support\r | |
| 2258 | /// leaf 80000008H, the processor supports 36-bit physical address size,\r | |
| 2259 | /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r | |
| 2260 | ///\r | |
| 2261 | UINT32 PhysMaskHi:32;\r | |
| 2262 | } Bits;\r | |
| 2263 | ///\r | |
| 2264 | /// All bit fields as a 64-bit value\r | |
| 2265 | ///\r | |
| 2266 | UINT64 Uint64;\r | |
| 2267 | } MSR_IA32_MTRR_PHYSMASK_REGISTER;\r | |
| 2268 | \r | |
| 2269 | \r | |
| 2270 | /**\r | |
| 2271 | MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2272 | \r | |
| 2273 | @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)\r | |
| 2274 | @param EAX Lower 32-bits of MSR value.\r | |
| 2275 | @param EDX Upper 32-bits of MSR value.\r | |
| 2276 | \r | |
| 2277 | <b>Example usage</b>\r | |
| 2278 | @code\r | |
| 2279 | UINT64 Msr;\r | |
| 2280 | \r | |
| 2281 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);\r | |
| 2282 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);\r | |
| 2283 | @endcode\r | |
| 7de98828 | 2284 | @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r |
| 04c980a6 MK |
2285 | **/\r |
| 2286 | #define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r | |
| 2287 | \r | |
| 2288 | \r | |
| 2289 | /**\r | |
| 2290 | MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2291 | \r | |
| 2292 | @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)\r | |
| 2293 | @param EAX Lower 32-bits of MSR value.\r | |
| 2294 | @param EDX Upper 32-bits of MSR value.\r | |
| 2295 | \r | |
| 2296 | <b>Example usage</b>\r | |
| 2297 | @code\r | |
| 2298 | UINT64 Msr;\r | |
| 2299 | \r | |
| 2300 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);\r | |
| 2301 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);\r | |
| 2302 | @endcode\r | |
| 7de98828 | 2303 | @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r |
| 04c980a6 MK |
2304 | **/\r |
| 2305 | #define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r | |
| 2306 | \r | |
| 2307 | \r | |
| 2308 | /**\r | |
| 2309 | MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2310 | \r | |
| 2311 | @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)\r | |
| 2312 | @param EAX Lower 32-bits of MSR value.\r | |
| 2313 | @param EDX Upper 32-bits of MSR value.\r | |
| 2314 | \r | |
| 2315 | <b>Example usage</b>\r | |
| 2316 | @code\r | |
| 2317 | UINT64 Msr;\r | |
| 2318 | \r | |
| 2319 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);\r | |
| 2320 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);\r | |
| 2321 | @endcode\r | |
| 7de98828 | 2322 | @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r |
| 04c980a6 MK |
2323 | **/\r |
| 2324 | #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r | |
| 2325 | \r | |
| 2326 | \r | |
| 2327 | /**\r | |
| 2328 | See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2329 | \r | |
| 2330 | @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)\r | |
| 2331 | @param EAX Lower 32-bits of MSR value.\r | |
| 2332 | @param EDX Upper 32-bits of MSR value.\r | |
| 2333 | \r | |
| 2334 | <b>Example usage</b>\r | |
| 2335 | @code\r | |
| 2336 | UINT64 Msr;\r | |
| 2337 | \r | |
| 2338 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);\r | |
| 2339 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);\r | |
| 2340 | @endcode\r | |
| 7de98828 | 2341 | @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r |
| 04c980a6 MK |
2342 | **/\r |
| 2343 | #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r | |
| 2344 | \r | |
| 2345 | \r | |
| 2346 | /**\r | |
| 2347 | MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2348 | \r | |
| 2349 | @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)\r | |
| 2350 | @param EAX Lower 32-bits of MSR value.\r | |
| 2351 | @param EDX Upper 32-bits of MSR value.\r | |
| 2352 | \r | |
| 2353 | <b>Example usage</b>\r | |
| 2354 | @code\r | |
| 2355 | UINT64 Msr;\r | |
| 2356 | \r | |
| 2357 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);\r | |
| 2358 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);\r | |
| 2359 | @endcode\r | |
| 7de98828 | 2360 | @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r |
| 04c980a6 MK |
2361 | **/\r |
| 2362 | #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r | |
| 2363 | \r | |
| 2364 | \r | |
| 2365 | /**\r | |
| 2366 | MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2367 | \r | |
| 2368 | @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)\r | |
| 2369 | @param EAX Lower 32-bits of MSR value.\r | |
| 2370 | @param EDX Upper 32-bits of MSR value.\r | |
| 2371 | \r | |
| 2372 | <b>Example usage</b>\r | |
| 2373 | @code\r | |
| 2374 | UINT64 Msr;\r | |
| 2375 | \r | |
| 2376 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);\r | |
| 2377 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);\r | |
| 2378 | @endcode\r | |
| 7de98828 | 2379 | @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r |
| 04c980a6 MK |
2380 | **/\r |
| 2381 | #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r | |
| 2382 | \r | |
| 2383 | \r | |
| 2384 | /**\r | |
| 2385 | MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2386 | \r | |
| 2387 | @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)\r | |
| 2388 | @param EAX Lower 32-bits of MSR value.\r | |
| 2389 | @param EDX Upper 32-bits of MSR value.\r | |
| 2390 | \r | |
| 2391 | <b>Example usage</b>\r | |
| 2392 | @code\r | |
| 2393 | UINT64 Msr;\r | |
| 2394 | \r | |
| 2395 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);\r | |
| 2396 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);\r | |
| 2397 | @endcode\r | |
| 7de98828 | 2398 | @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r |
| 04c980a6 MK |
2399 | **/\r |
| 2400 | #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r | |
| 2401 | \r | |
| 2402 | \r | |
| 2403 | /**\r | |
| 2404 | MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2405 | \r | |
| 2406 | @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)\r | |
| 2407 | @param EAX Lower 32-bits of MSR value.\r | |
| 2408 | @param EDX Upper 32-bits of MSR value.\r | |
| 2409 | \r | |
| 2410 | <b>Example usage</b>\r | |
| 2411 | @code\r | |
| 2412 | UINT64 Msr;\r | |
| 2413 | \r | |
| 2414 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);\r | |
| 2415 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);\r | |
| 2416 | @endcode\r | |
| 7de98828 | 2417 | @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r |
| 04c980a6 MK |
2418 | **/\r |
| 2419 | #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r | |
| 2420 | \r | |
| 2421 | \r | |
| 2422 | /**\r | |
| 2423 | MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2424 | \r | |
| 2425 | @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)\r | |
| 2426 | @param EAX Lower 32-bits of MSR value.\r | |
| 2427 | @param EDX Upper 32-bits of MSR value.\r | |
| 2428 | \r | |
| 2429 | <b>Example usage</b>\r | |
| 2430 | @code\r | |
| 2431 | UINT64 Msr;\r | |
| 2432 | \r | |
| 2433 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);\r | |
| 2434 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);\r | |
| 2435 | @endcode\r | |
| 7de98828 | 2436 | @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r |
| 04c980a6 MK |
2437 | **/\r |
| 2438 | #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r | |
| 2439 | \r | |
| 2440 | \r | |
| 2441 | /**\r | |
| 2442 | MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2443 | \r | |
| 2444 | @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)\r | |
| 2445 | @param EAX Lower 32-bits of MSR value.\r | |
| 2446 | @param EDX Upper 32-bits of MSR value.\r | |
| 2447 | \r | |
| 2448 | <b>Example usage</b>\r | |
| 2449 | @code\r | |
| 2450 | UINT64 Msr;\r | |
| 2451 | \r | |
| 2452 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);\r | |
| 2453 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);\r | |
| 2454 | @endcode\r | |
| 7de98828 | 2455 | @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r |
| 04c980a6 MK |
2456 | **/\r |
| 2457 | #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r | |
| 2458 | \r | |
| 2459 | \r | |
| 2460 | /**\r | |
| 2461 | MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2462 | \r | |
| 2463 | @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)\r | |
| 2464 | @param EAX Lower 32-bits of MSR value.\r | |
| 2465 | @param EDX Upper 32-bits of MSR value.\r | |
| 2466 | \r | |
| 2467 | <b>Example usage</b>\r | |
| 2468 | @code\r | |
| 2469 | UINT64 Msr;\r | |
| 2470 | \r | |
| 2471 | Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);\r | |
| 2472 | AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);\r | |
| 2473 | @endcode\r | |
| 7de98828 | 2474 | @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r |
| 04c980a6 MK |
2475 | **/\r |
| 2476 | #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r | |
| 2477 | \r | |
| 2478 | \r | |
| 2479 | /**\r | |
| 2480 | IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r | |
| 2481 | \r | |
| 2482 | @param ECX MSR_IA32_PAT (0x00000277)\r | |
| 2483 | @param EAX Lower 32-bits of MSR value.\r | |
| 2484 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
| 2485 | @param EDX Upper 32-bits of MSR value.\r | |
| 2486 | Described by the type MSR_IA32_PAT_REGISTER.\r | |
| 2487 | \r | |
| 2488 | <b>Example usage</b>\r | |
| 2489 | @code\r | |
| 2490 | MSR_IA32_PAT_REGISTER Msr;\r | |
| 2491 | \r | |
| 2492 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);\r | |
| 2493 | AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);\r | |
| 2494 | @endcode\r | |
| 7de98828 | 2495 | @note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r |
| 04c980a6 MK |
2496 | **/\r |
| 2497 | #define MSR_IA32_PAT 0x00000277\r | |
| 2498 | \r | |
| 2499 | /**\r | |
| 2500 | MSR information returned for MSR index #MSR_IA32_PAT\r | |
| 2501 | **/\r | |
| 2502 | typedef union {\r | |
| 2503 | ///\r | |
| 2504 | /// Individual bit fields\r | |
| 2505 | ///\r | |
| 2506 | struct {\r | |
| 2507 | ///\r | |
| 2508 | /// [Bits 2:0] PA0.\r | |
| 2509 | ///\r | |
| 2510 | UINT32 PA0:3;\r | |
| 2511 | UINT32 Reserved1:5;\r | |
| 2512 | ///\r | |
| 2513 | /// [Bits 10:8] PA1.\r | |
| 2514 | ///\r | |
| 2515 | UINT32 PA1:3;\r | |
| 2516 | UINT32 Reserved2:5;\r | |
| 2517 | ///\r | |
| 2518 | /// [Bits 18:16] PA2.\r | |
| 2519 | ///\r | |
| 2520 | UINT32 PA2:3;\r | |
| 2521 | UINT32 Reserved3:5;\r | |
| 2522 | ///\r | |
| 2523 | /// [Bits 26:24] PA3.\r | |
| 2524 | ///\r | |
| 2525 | UINT32 PA3:3;\r | |
| 2526 | UINT32 Reserved4:5;\r | |
| 2527 | ///\r | |
| 2528 | /// [Bits 34:32] PA4.\r | |
| 2529 | ///\r | |
| 2530 | UINT32 PA4:3;\r | |
| 2531 | UINT32 Reserved5:5;\r | |
| 2532 | ///\r | |
| 2533 | /// [Bits 42:40] PA5.\r | |
| 2534 | ///\r | |
| 2535 | UINT32 PA5:3;\r | |
| 2536 | UINT32 Reserved6:5;\r | |
| 2537 | ///\r | |
| 2538 | /// [Bits 50:48] PA6.\r | |
| 2539 | ///\r | |
| 2540 | UINT32 PA6:3;\r | |
| 2541 | UINT32 Reserved7:5;\r | |
| 2542 | ///\r | |
| 2543 | /// [Bits 58:56] PA7.\r | |
| 2544 | ///\r | |
| 2545 | UINT32 PA7:3;\r | |
| 2546 | UINT32 Reserved8:5;\r | |
| 2547 | } Bits;\r | |
| 2548 | ///\r | |
| 2549 | /// All bit fields as a 64-bit value\r | |
| 2550 | ///\r | |
| 2551 | UINT64 Uint64;\r | |
| 2552 | } MSR_IA32_PAT_REGISTER;\r | |
| 2553 | \r | |
| 2554 | \r | |
| 2555 | /**\r | |
| 2556 | Provides the programming interface to use corrected MC error signaling\r | |
| 2557 | capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r | |
| 2558 | \r | |
| 2559 | @param ECX MSR_IA32_MCn_CTL2\r | |
| 2560 | @param EAX Lower 32-bits of MSR value.\r | |
| 2561 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
| 2562 | @param EDX Upper 32-bits of MSR value.\r | |
| 2563 | Described by the type MSR_IA32_MC_CTL2_REGISTER.\r | |
| 2564 | \r | |
| 2565 | <b>Example usage</b>\r | |
| 2566 | @code\r | |
| 2567 | MSR_IA32_MC_CTL2_REGISTER Msr;\r | |
| 2568 | \r | |
| 2569 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);\r | |
| 2570 | AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);\r | |
| 2571 | @endcode\r | |
| 7de98828 JF |
2572 | @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.\r |
| 2573 | MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.\r | |
| 2574 | MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.\r | |
| 2575 | MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.\r | |
| 2576 | MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r | |
| 2577 | MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.\r | |
| 2578 | MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.\r | |
| 2579 | MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.\r | |
| 2580 | MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.\r | |
| 2581 | MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.\r | |
| 2582 | MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.\r | |
| 2583 | MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.\r | |
| 2584 | MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.\r | |
| 2585 | MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.\r | |
| 2586 | MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.\r | |
| 2587 | MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.\r | |
| 2588 | MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.\r | |
| 2589 | MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.\r | |
| 2590 | MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.\r | |
| 2591 | MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.\r | |
| 2592 | MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.\r | |
| 2593 | MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.\r | |
| 2594 | MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.\r | |
| 2595 | MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.\r | |
| 2596 | MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.\r | |
| 2597 | MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.\r | |
| 2598 | MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.\r | |
| 2599 | MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.\r | |
| 2600 | MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.\r | |
| 2601 | MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.\r | |
| 2602 | MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.\r | |
| 2603 | MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r | |
| 04c980a6 MK |
2604 | @{\r |
| 2605 | **/\r | |
| 2606 | #define MSR_IA32_MC0_CTL2 0x00000280\r | |
| 2607 | #define MSR_IA32_MC1_CTL2 0x00000281\r | |
| 2608 | #define MSR_IA32_MC2_CTL2 0x00000282\r | |
| 2609 | #define MSR_IA32_MC3_CTL2 0x00000283\r | |
| 2610 | #define MSR_IA32_MC4_CTL2 0x00000284\r | |
| 2611 | #define MSR_IA32_MC5_CTL2 0x00000285\r | |
| 2612 | #define MSR_IA32_MC6_CTL2 0x00000286\r | |
| 2613 | #define MSR_IA32_MC7_CTL2 0x00000287\r | |
| 2614 | #define MSR_IA32_MC8_CTL2 0x00000288\r | |
| 2615 | #define MSR_IA32_MC9_CTL2 0x00000289\r | |
| 2616 | #define MSR_IA32_MC10_CTL2 0x0000028A\r | |
| 2617 | #define MSR_IA32_MC11_CTL2 0x0000028B\r | |
| 2618 | #define MSR_IA32_MC12_CTL2 0x0000028C\r | |
| 2619 | #define MSR_IA32_MC13_CTL2 0x0000028D\r | |
| 2620 | #define MSR_IA32_MC14_CTL2 0x0000028E\r | |
| 2621 | #define MSR_IA32_MC15_CTL2 0x0000028F\r | |
| 2622 | #define MSR_IA32_MC16_CTL2 0x00000290\r | |
| 2623 | #define MSR_IA32_MC17_CTL2 0x00000291\r | |
| 2624 | #define MSR_IA32_MC18_CTL2 0x00000292\r | |
| 2625 | #define MSR_IA32_MC19_CTL2 0x00000293\r | |
| 2626 | #define MSR_IA32_MC20_CTL2 0x00000294\r | |
| 2627 | #define MSR_IA32_MC21_CTL2 0x00000295\r | |
| 2628 | #define MSR_IA32_MC22_CTL2 0x00000296\r | |
| 2629 | #define MSR_IA32_MC23_CTL2 0x00000297\r | |
| 2630 | #define MSR_IA32_MC24_CTL2 0x00000298\r | |
| 2631 | #define MSR_IA32_MC25_CTL2 0x00000299\r | |
| 2632 | #define MSR_IA32_MC26_CTL2 0x0000029A\r | |
| 2633 | #define MSR_IA32_MC27_CTL2 0x0000029B\r | |
| 2634 | #define MSR_IA32_MC28_CTL2 0x0000029C\r | |
| 2635 | #define MSR_IA32_MC29_CTL2 0x0000029D\r | |
| 2636 | #define MSR_IA32_MC30_CTL2 0x0000029E\r | |
| 2637 | #define MSR_IA32_MC31_CTL2 0x0000029F\r | |
| 2638 | /// @}\r | |
| 2639 | \r | |
| 2640 | /**\r | |
| 2641 | MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2\r | |
| 2642 | to #MSR_IA32_MC31_CTL2\r | |
| 2643 | **/\r | |
| 2644 | typedef union {\r | |
| 2645 | ///\r | |
| 2646 | /// Individual bit fields\r | |
| 2647 | ///\r | |
| 2648 | struct {\r | |
| 2649 | ///\r | |
| 2650 | /// [Bits 14:0] Corrected error count threshold.\r | |
| 2651 | ///\r | |
| 2652 | UINT32 CorrectedErrorCountThreshold:15;\r | |
| 2653 | UINT32 Reserved1:15;\r | |
| 2654 | ///\r | |
| 2655 | /// [Bit 30] CMCI_EN.\r | |
| 2656 | ///\r | |
| 2657 | UINT32 CMCI_EN:1;\r | |
| 2658 | UINT32 Reserved2:1;\r | |
| 2659 | UINT32 Reserved3:32;\r | |
| 2660 | } Bits;\r | |
| 2661 | ///\r | |
| 2662 | /// All bit fields as a 32-bit value\r | |
| 2663 | ///\r | |
| 2664 | UINT32 Uint32;\r | |
| 2665 | ///\r | |
| 2666 | /// All bit fields as a 64-bit value\r | |
| 2667 | ///\r | |
| 2668 | UINT64 Uint64;\r | |
| 2669 | } MSR_IA32_MC_CTL2_REGISTER;\r | |
| 2670 | \r | |
| 2671 | \r | |
| 2672 | /**\r | |
| 2673 | MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r | |
| 2674 | \r | |
| 2675 | @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)\r | |
| 2676 | @param EAX Lower 32-bits of MSR value.\r | |
| 2677 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
| 2678 | @param EDX Upper 32-bits of MSR value.\r | |
| 2679 | Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.\r | |
| 2680 | \r | |
| 2681 | <b>Example usage</b>\r | |
| 2682 | @code\r | |
| 2683 | MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;\r | |
| 2684 | \r | |
| 2685 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r | |
| 2686 | AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);\r | |
| 2687 | @endcode\r | |
| 7de98828 | 2688 | @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r |
| 04c980a6 MK |
2689 | **/\r |
| 2690 | #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r | |
| 2691 | \r | |
| 2692 | /**\r | |
| 2693 | MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r | |
| 2694 | **/\r | |
| 2695 | typedef union {\r | |
| 2696 | ///\r | |
| 2697 | /// Individual bit fields\r | |
| 2698 | ///\r | |
| 2699 | struct {\r | |
| 2700 | ///\r | |
| 2701 | /// [Bits 2:0] Default Memory Type.\r | |
| 2702 | ///\r | |
| 2703 | UINT32 Type:3;\r | |
| 2704 | UINT32 Reserved1:7;\r | |
| 2705 | ///\r | |
| 2706 | /// [Bit 10] Fixed Range MTRR Enable.\r | |
| 2707 | ///\r | |
| 2708 | UINT32 FE:1;\r | |
| 2709 | ///\r | |
| 2710 | /// [Bit 11] MTRR Enable.\r | |
| 2711 | ///\r | |
| 2712 | UINT32 E:1;\r | |
| 2713 | UINT32 Reserved2:20;\r | |
| 2714 | UINT32 Reserved3:32;\r | |
| 2715 | } Bits;\r | |
| 2716 | ///\r | |
| 2717 | /// All bit fields as a 32-bit value\r | |
| 2718 | ///\r | |
| 2719 | UINT32 Uint32;\r | |
| 2720 | ///\r | |
| 2721 | /// All bit fields as a 64-bit value\r | |
| 2722 | ///\r | |
| 2723 | UINT64 Uint64;\r | |
| 2724 | } MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r | |
| 2725 | \r | |
| 2726 | \r | |
| 2727 | /**\r | |
| 2728 | Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r | |
| 2729 | CPUID.0AH: EDX[4:0] > 0.\r | |
| 2730 | \r | |
| 2731 | @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)\r | |
| 2732 | @param EAX Lower 32-bits of MSR value.\r | |
| 2733 | @param EDX Upper 32-bits of MSR value.\r | |
| 2734 | \r | |
| 2735 | <b>Example usage</b>\r | |
| 2736 | @code\r | |
| 2737 | UINT64 Msr;\r | |
| 2738 | \r | |
| 2739 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);\r | |
| 2740 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);\r | |
| 2741 | @endcode\r | |
| 7de98828 | 2742 | @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r |
| 04c980a6 MK |
2743 | **/\r |
| 2744 | #define MSR_IA32_FIXED_CTR0 0x00000309\r | |
| 2745 | \r | |
| 2746 | \r | |
| 2747 | /**\r | |
| 0f16be6d HW |
2748 | Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r |
| 2749 | CPUID.0AH: EDX[4:0] > 1.\r | |
| 04c980a6 MK |
2750 | \r |
| 2751 | @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)\r | |
| 2752 | @param EAX Lower 32-bits of MSR value.\r | |
| 2753 | @param EDX Upper 32-bits of MSR value.\r | |
| 2754 | \r | |
| 2755 | <b>Example usage</b>\r | |
| 2756 | @code\r | |
| 2757 | UINT64 Msr;\r | |
| 2758 | \r | |
| 2759 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);\r | |
| 2760 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);\r | |
| 2761 | @endcode\r | |
| 7de98828 | 2762 | @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r |
| 04c980a6 MK |
2763 | **/\r |
| 2764 | #define MSR_IA32_FIXED_CTR1 0x0000030A\r | |
| 2765 | \r | |
| 2766 | \r | |
| 2767 | /**\r | |
| 0f16be6d HW |
2768 | Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r |
| 2769 | CPUID.0AH: EDX[4:0] > 2.\r | |
| 04c980a6 MK |
2770 | \r |
| 2771 | @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)\r | |
| 2772 | @param EAX Lower 32-bits of MSR value.\r | |
| 2773 | @param EDX Upper 32-bits of MSR value.\r | |
| 2774 | \r | |
| 2775 | <b>Example usage</b>\r | |
| 2776 | @code\r | |
| 2777 | UINT64 Msr;\r | |
| 2778 | \r | |
| 2779 | Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);\r | |
| 2780 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);\r | |
| 2781 | @endcode\r | |
| 7de98828 | 2782 | @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r |
| 04c980a6 MK |
2783 | **/\r |
| 2784 | #define MSR_IA32_FIXED_CTR2 0x0000030B\r | |
| 2785 | \r | |
| 2786 | \r | |
| 2787 | /**\r | |
| 2788 | RO. If CPUID.01H: ECX[15] = 1.\r | |
| 2789 | \r | |
| 2790 | @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)\r | |
| 2791 | @param EAX Lower 32-bits of MSR value.\r | |
| 2792 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
| 2793 | @param EDX Upper 32-bits of MSR value.\r | |
| 2794 | Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.\r | |
| 2795 | \r | |
| 2796 | <b>Example usage</b>\r | |
| 2797 | @code\r | |
| 2798 | MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;\r | |
| 2799 | \r | |
| 2800 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);\r | |
| 2801 | AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);\r | |
| 2802 | @endcode\r | |
| 7de98828 | 2803 | @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r |
| 04c980a6 MK |
2804 | **/\r |
| 2805 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345\r | |
| 2806 | \r | |
| 2807 | /**\r | |
| 2808 | MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r | |
| 2809 | **/\r | |
| 2810 | typedef union {\r | |
| 2811 | ///\r | |
| 2812 | /// Individual bit fields\r | |
| 2813 | ///\r | |
| 2814 | struct {\r | |
| 2815 | ///\r | |
| 2816 | /// [Bits 5:0] LBR format.\r | |
| 2817 | ///\r | |
| 2818 | UINT32 LBR_FMT:6;\r | |
| 2819 | ///\r | |
| 2820 | /// [Bit 6] PEBS Trap.\r | |
| 2821 | ///\r | |
| 2822 | UINT32 PEBS_TRAP:1;\r | |
| 2823 | ///\r | |
| 2824 | /// [Bit 7] PEBSSaveArchRegs.\r | |
| 2825 | ///\r | |
| 2826 | UINT32 PEBS_ARCH_REG:1;\r | |
| 2827 | ///\r | |
| 2828 | /// [Bits 11:8] PEBS Record Format.\r | |
| 2829 | ///\r | |
| 2830 | UINT32 PEBS_REC_FMT:4;\r | |
| 2831 | ///\r | |
| 2832 | /// [Bit 12] 1: Freeze while SMM is supported.\r | |
| 2833 | ///\r | |
| 2834 | UINT32 SMM_FREEZE:1;\r | |
| 2835 | ///\r | |
| 2836 | /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r | |
| 2837 | ///\r | |
| 2838 | UINT32 FW_WRITE:1;\r | |
| 2839 | UINT32 Reserved1:18;\r | |
| 2840 | UINT32 Reserved2:32;\r | |
| 2841 | } Bits;\r | |
| 2842 | ///\r | |
| 2843 | /// All bit fields as a 32-bit value\r | |
| 2844 | ///\r | |
| 2845 | UINT32 Uint32;\r | |
| 2846 | ///\r | |
| 2847 | /// All bit fields as a 64-bit value\r | |
| 2848 | ///\r | |
| 2849 | UINT64 Uint64;\r | |
| 2850 | } MSR_IA32_PERF_CAPABILITIES_REGISTER;\r | |
| 2851 | \r | |
| 2852 | \r | |
| 2853 | /**\r | |
| 2854 | Fixed-Function Performance Counter Control (R/W) Counter increments while\r | |
| 2855 | the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r | |
| 2856 | the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]\r | |
| 2857 | > 1.\r | |
| 2858 | \r | |
| 2859 | @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)\r | |
| 2860 | @param EAX Lower 32-bits of MSR value.\r | |
| 2861 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
| 2862 | @param EDX Upper 32-bits of MSR value.\r | |
| 2863 | Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.\r | |
| 2864 | \r | |
| 2865 | <b>Example usage</b>\r | |
| 2866 | @code\r | |
| 2867 | MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;\r | |
| 2868 | \r | |
| 2869 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);\r | |
| 2870 | AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);\r | |
| 2871 | @endcode\r | |
| 7de98828 | 2872 | @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r |
| 04c980a6 MK |
2873 | **/\r |
| 2874 | #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r | |
| 2875 | \r | |
| 2876 | /**\r | |
| 2877 | MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r | |
| 2878 | **/\r | |
| 2879 | typedef union {\r | |
| 2880 | ///\r | |
| 2881 | /// Individual bit fields\r | |
| 2882 | ///\r | |
| 2883 | struct {\r | |
| 2884 | ///\r | |
| 2885 | /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r | |
| 2886 | ///\r | |
| 2887 | UINT32 EN0_OS:1;\r | |
| 2888 | ///\r | |
| 2889 | /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r | |
| 2890 | ///\r | |
| 2891 | UINT32 EN0_Usr:1;\r | |
| 2892 | ///\r | |
| 2893 | /// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r | |
| 2894 | /// event conditions occurring across all logical processors sharing a\r | |
| 2895 | /// processor core. When set to 0, the counter only increments the\r | |
| 2896 | /// associated event conditions occurring in the logical processor which\r | |
| 2897 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2898 | ///\r | |
| 2899 | UINT32 AnyThread0:1;\r | |
| 2900 | ///\r | |
| 2901 | /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r | |
| 2902 | ///\r | |
| 2903 | UINT32 EN0_PMI:1;\r | |
| 2904 | ///\r | |
| 2905 | /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r | |
| 2906 | ///\r | |
| 2907 | UINT32 EN1_OS:1;\r | |
| 2908 | ///\r | |
| 2909 | /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r | |
| 2910 | ///\r | |
| 2911 | UINT32 EN1_Usr:1;\r | |
| 2912 | ///\r | |
| 2913 | /// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r | |
| 2914 | /// event conditions occurring across all logical processors sharing a\r | |
| 2915 | /// processor core. When set to 0, the counter only increments the\r | |
| 2916 | /// associated event conditions occurring in the logical processor which\r | |
| 2917 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2918 | ///\r | |
| 2919 | UINT32 AnyThread1:1;\r | |
| 2920 | ///\r | |
| 2921 | /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r | |
| 2922 | ///\r | |
| 2923 | UINT32 EN1_PMI:1;\r | |
| 2924 | ///\r | |
| 2925 | /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r | |
| 2926 | ///\r | |
| 2927 | UINT32 EN2_OS:1;\r | |
| 2928 | ///\r | |
| 2929 | /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r | |
| 2930 | ///\r | |
| 2931 | UINT32 EN2_Usr:1;\r | |
| 2932 | ///\r | |
| 2933 | /// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r | |
| 2934 | /// event conditions occurring across all logical processors sharing a\r | |
| 2935 | /// processor core. When set to 0, the counter only increments the\r | |
| 2936 | /// associated event conditions occurring in the logical processor which\r | |
| 2937 | /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r | |
| 2938 | ///\r | |
| 2939 | UINT32 AnyThread2:1;\r | |
| 2940 | ///\r | |
| 2941 | /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r | |
| 2942 | ///\r | |
| 2943 | UINT32 EN2_PMI:1;\r | |
| 2944 | UINT32 Reserved1:20;\r | |
| 2945 | UINT32 Reserved2:32;\r | |
| 2946 | } Bits;\r | |
| 2947 | ///\r | |
| 2948 | /// All bit fields as a 32-bit value\r | |
| 2949 | ///\r | |
| 2950 | UINT32 Uint32;\r | |
| 2951 | ///\r | |
| 2952 | /// All bit fields as a 64-bit value\r | |
| 2953 | ///\r | |
| 2954 | UINT64 Uint64;\r | |
| 2955 | } MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r | |
| 2956 | \r | |
| 2957 | \r | |
| 2958 | /**\r | |
| 2959 | Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r | |
| 2960 | \r | |
| 2961 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r | |
| 2962 | @param EAX Lower 32-bits of MSR value.\r | |
| 2963 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2964 | @param EDX Upper 32-bits of MSR value.\r | |
| 2965 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 2966 | \r | |
| 2967 | <b>Example usage</b>\r | |
| 2968 | @code\r | |
| 2969 | MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
| 2970 | \r | |
| 2971 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);\r | |
| 2972 | @endcode\r | |
| 7de98828 | 2973 | @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r |
| 04c980a6 MK |
2974 | **/\r |
| 2975 | #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r | |
| 2976 | \r | |
| 2977 | /**\r | |
| 2978 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r | |
| 2979 | **/\r | |
| 2980 | typedef union {\r | |
| 2981 | ///\r | |
| 2982 | /// Individual bit fields\r | |
| 2983 | ///\r | |
| 2984 | struct {\r | |
| 2985 | ///\r | |
| 2986 | /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r | |
| 2987 | /// EAX[15:8] > 0.\r | |
| 2988 | ///\r | |
| 2989 | UINT32 Ovf_PMC0:1;\r | |
| 2990 | ///\r | |
| 2991 | /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r | |
| 2992 | /// EAX[15:8] > 1.\r | |
| 2993 | ///\r | |
| 2994 | UINT32 Ovf_PMC1:1;\r | |
| 2995 | ///\r | |
| 2996 | /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r | |
| 2997 | /// EAX[15:8] > 2.\r | |
| 2998 | ///\r | |
| 2999 | UINT32 Ovf_PMC2:1;\r | |
| 3000 | ///\r | |
| 3001 | /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r | |
| 3002 | /// EAX[15:8] > 3.\r | |
| 3003 | ///\r | |
| 3004 | UINT32 Ovf_PMC3:1;\r | |
| 3005 | UINT32 Reserved1:28;\r | |
| 3006 | ///\r | |
| 3007 | /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r | |
| 3008 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 3009 | ///\r | |
| 3010 | UINT32 Ovf_FixedCtr0:1;\r | |
| 3011 | ///\r | |
| 3012 | /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r | |
| 3013 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 3014 | ///\r | |
| 3015 | UINT32 Ovf_FixedCtr1:1;\r | |
| 3016 | ///\r | |
| 3017 | /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r | |
| 3018 | /// CPUID.0AH: EAX[7:0] > 1.\r | |
| 3019 | ///\r | |
| 3020 | UINT32 Ovf_FixedCtr2:1;\r | |
| 3021 | UINT32 Reserved2:20;\r | |
| 3022 | ///\r | |
| 3023 | /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r | |
| 3024 | /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r | |
| 3025 | /// && IA32_RTIT_CTL.ToPA = 1.\r | |
| 3026 | ///\r | |
| 3027 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3028 | UINT32 Reserved3:2;\r | |
| 3029 | ///\r | |
| 3030 | /// [Bit 58] LBR_Frz: LBRs are frozen due to -\r | |
| 3031 | /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r | |
| 3032 | /// CPUID.0AH: EAX[7:0] > 3.\r | |
| 3033 | ///\r | |
| 3034 | UINT32 LBR_Frz:1;\r | |
| 3035 | ///\r | |
| 3036 | /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r | |
| 3037 | /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r | |
| 3038 | /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3039 | ///\r | |
| 3040 | UINT32 CTR_Frz:1;\r | |
| 3041 | ///\r | |
| 3042 | /// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r | |
| 3043 | /// include contributions from the direct or indirect operation intel SGX\r | |
| 3044 | /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r | |
| 3045 | ///\r | |
| 3046 | UINT32 ASCI:1;\r | |
| 3047 | ///\r | |
| 3048 | /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r | |
| 3049 | /// EAX[7:0] > 2.\r | |
| 3050 | ///\r | |
| 3051 | UINT32 Ovf_Uncore:1;\r | |
| 3052 | ///\r | |
| 3053 | /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r | |
| 3054 | /// EAX[7:0] > 0.\r | |
| 3055 | ///\r | |
| 3056 | UINT32 OvfBuf:1;\r | |
| 3057 | ///\r | |
| 3058 | /// [Bit 63] CondChgd: status bits of this register has changed. If\r | |
| 3059 | /// CPUID.0AH: EAX[7:0] > 0.\r | |
| 3060 | ///\r | |
| 3061 | UINT32 CondChgd:1;\r | |
| 3062 | } Bits;\r | |
| 3063 | ///\r | |
| 3064 | /// All bit fields as a 64-bit value\r | |
| 3065 | ///\r | |
| 3066 | UINT64 Uint64;\r | |
| 3067 | } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r | |
| 3068 | \r | |
| 3069 | \r | |
| 3070 | /**\r | |
| 3071 | Global Performance Counter Control (R/W) Counter increments while the result\r | |
| 3072 | of ANDing respective enable bit in this MSR with the corresponding OS or USR\r | |
| 3073 | bits in the general-purpose or fixed counter control MSR is true. If\r | |
| 3074 | CPUID.0AH: EAX[7:0] > 0.\r | |
| 3075 | \r | |
| 3076 | @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r | |
| 3077 | @param EAX Lower 32-bits of MSR value.\r | |
| 3078 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 3079 | @param EDX Upper 32-bits of MSR value.\r | |
| 3080 | Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 3081 | \r | |
| 3082 | <b>Example usage</b>\r | |
| 3083 | @code\r | |
| 3084 | MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
| 3085 | \r | |
| 3086 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);\r | |
| 3087 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
| 3088 | @endcode\r | |
| 7de98828 | 3089 | @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r |
| 04c980a6 MK |
3090 | **/\r |
| 3091 | #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r | |
| 3092 | \r | |
| 3093 | /**\r | |
| 3094 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r | |
| 3095 | **/\r | |
| 3096 | typedef union {\r | |
| 3097 | ///\r | |
| 3098 | /// Individual bit fields\r | |
| 3099 | ///\r | |
| 3100 | struct {\r | |
| 3101 | ///\r | |
| 3102 | /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3103 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
| 3104 | /// Bits n..31 are reserved.\r | |
| 3105 | ///\r | |
| 3106 | UINT32 EN_PMCn:32;\r | |
| 3107 | ///\r | |
| 3108 | /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r | |
| 3109 | /// Enable bitmask. Only the first n-1 bits are valid.\r | |
| 3110 | /// Bits 31:n are reserved.\r | |
| 3111 | ///\r | |
| 3112 | UINT32 EN_FIXED_CTRn:32;\r | |
| 3113 | } Bits;\r | |
| 3114 | ///\r | |
| 3115 | /// All bit fields as a 64-bit value\r | |
| 3116 | ///\r | |
| 3117 | UINT64 Uint64;\r | |
| 3118 | } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r | |
| 3119 | \r | |
| 3120 | \r | |
| 3121 | /**\r | |
| 3122 | Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r | |
| 3123 | 0 && CPUID.0AH: EAX[7:0] <= 3.\r | |
| 3124 | \r | |
| 3125 | @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r | |
| 3126 | @param EAX Lower 32-bits of MSR value.\r | |
| 3127 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 3128 | @param EDX Upper 32-bits of MSR value.\r | |
| 3129 | Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
| 3130 | \r | |
| 3131 | <b>Example usage</b>\r | |
| 3132 | @code\r | |
| 3133 | MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r | |
| 3134 | \r | |
| 3135 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);\r | |
| 3136 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r | |
| 3137 | @endcode\r | |
| 7de98828 | 3138 | @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r |
| 04c980a6 MK |
3139 | **/\r |
| 3140 | #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r | |
| 3141 | \r | |
| 3142 | /**\r | |
| 3143 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r | |
| 3144 | **/\r | |
| 3145 | typedef union {\r | |
| 3146 | ///\r | |
| 3147 | /// Individual bit fields\r | |
| 3148 | ///\r | |
| 3149 | struct {\r | |
| 3150 | ///\r | |
| 3151 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3152 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3153 | /// Bits 31:n are reserved.\r | |
| 3154 | ///\r | |
| 3155 | UINT32 Ovf_PMCn:32;\r | |
| 3156 | ///\r | |
| 3157 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
| 3158 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
| 3159 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3160 | /// Bits 22:n are reserved.\r | |
| 3161 | ///\r | |
| 3162 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3163 | ///\r | |
| 3164 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
| 3165 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r | |
| 3166 | ///\r | |
| 3167 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3168 | UINT32 Reserved2:5;\r | |
| 3169 | ///\r | |
| 3170 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
| 3171 | /// Display Model 06_2EH.\r | |
| 3172 | ///\r | |
| 3173 | UINT32 Ovf_Uncore:1;\r | |
| 3174 | ///\r | |
| 3175 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3176 | ///\r | |
| 3177 | UINT32 OvfBuf:1;\r | |
| 3178 | ///\r | |
| 3179 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3180 | ///\r | |
| 3181 | UINT32 CondChgd:1;\r | |
| 3182 | } Bits;\r | |
| 3183 | ///\r | |
| 3184 | /// All bit fields as a 64-bit value\r | |
| 3185 | ///\r | |
| 3186 | UINT64 Uint64;\r | |
| 3187 | } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r | |
| 3188 | \r | |
| 3189 | \r | |
| 3190 | /**\r | |
| 3191 | Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r | |
| 3192 | EAX[7:0] > 3.\r | |
| 3193 | \r | |
| 3194 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r | |
| 3195 | @param EAX Lower 32-bits of MSR value.\r | |
| 3196 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 3197 | @param EDX Upper 32-bits of MSR value.\r | |
| 3198 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
| 3199 | \r | |
| 3200 | <b>Example usage</b>\r | |
| 3201 | @code\r | |
| 3202 | MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r | |
| 3203 | \r | |
| 3204 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);\r | |
| 3205 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r | |
| 3206 | @endcode\r | |
| 7de98828 | 3207 | @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r |
| 04c980a6 MK |
3208 | **/\r |
| 3209 | #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r | |
| 3210 | \r | |
| 3211 | /**\r | |
| 3212 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r | |
| 3213 | **/\r | |
| 3214 | typedef union {\r | |
| 3215 | ///\r | |
| 3216 | /// Individual bit fields\r | |
| 3217 | ///\r | |
| 3218 | struct {\r | |
| 3219 | ///\r | |
| 3220 | /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.\r | |
| 3221 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3222 | /// Bits 31:n are reserved.\r | |
| 3223 | ///\r | |
| 3224 | UINT32 Ovf_PMCn:32;\r | |
| 3225 | ///\r | |
| 3226 | /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r | |
| 3227 | /// If CPUID.0AH: EDX[4:0] > n.\r | |
| 3228 | /// Clear bitmask. Only the first n-1 bits are valid.\r | |
| 3229 | /// Bits 22:n are reserved.\r | |
| 3230 | ///\r | |
| 3231 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3232 | ///\r | |
| 3233 | /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r | |
| 3234 | /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r | |
| 3235 | ///\r | |
| 3236 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3237 | UINT32 Reserved2:2;\r | |
| 3238 | ///\r | |
| 3239 | /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3240 | ///\r | |
| 3241 | UINT32 LBR_Frz:1;\r | |
| 3242 | ///\r | |
| 3243 | /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3244 | ///\r | |
| 3245 | UINT32 CTR_Frz:1;\r | |
| 3246 | ///\r | |
| 3247 | /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3248 | ///\r | |
| 3249 | UINT32 ASCI:1;\r | |
| 3250 | ///\r | |
| 3251 | /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r | |
| 3252 | /// Display Model 06_2EH.\r | |
| 3253 | ///\r | |
| 3254 | UINT32 Ovf_Uncore:1;\r | |
| 3255 | ///\r | |
| 3256 | /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3257 | ///\r | |
| 3258 | UINT32 OvfBuf:1;\r | |
| 3259 | ///\r | |
| 3260 | /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r | |
| 3261 | ///\r | |
| 3262 | UINT32 CondChgd:1;\r | |
| 3263 | } Bits;\r | |
| 3264 | ///\r | |
| 3265 | /// All bit fields as a 64-bit value\r | |
| 3266 | ///\r | |
| 3267 | UINT64 Uint64;\r | |
| 3268 | } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r | |
| 3269 | \r | |
| 3270 | \r | |
| 3271 | /**\r | |
| 3272 | Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r | |
| 3273 | EAX[7:0] > 3.\r | |
| 3274 | \r | |
| 3275 | @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r | |
| 3276 | @param EAX Lower 32-bits of MSR value.\r | |
| 3277 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 3278 | @param EDX Upper 32-bits of MSR value.\r | |
| 3279 | Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
| 3280 | \r | |
| 3281 | <b>Example usage</b>\r | |
| 3282 | @code\r | |
| 3283 | MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r | |
| 3284 | \r | |
| 3285 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);\r | |
| 3286 | AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r | |
| 3287 | @endcode\r | |
| 7de98828 | 3288 | @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r |
| 04c980a6 MK |
3289 | **/\r |
| 3290 | #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r | |
| 3291 | \r | |
| 3292 | /**\r | |
| 3293 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r | |
| 3294 | **/\r | |
| 3295 | typedef union {\r | |
| 3296 | ///\r | |
| 3297 | /// Individual bit fields\r | |
| 3298 | ///\r | |
| 3299 | struct {\r | |
| 3300 | ///\r | |
| 3301 | /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.\r | |
| 3302 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
| 3303 | /// Bits 31:n are reserved.\r | |
| 3304 | ///\r | |
| 3305 | UINT32 Ovf_PMCn:32;\r | |
| 3306 | ///\r | |
| 3307 | /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r | |
| 3308 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
| 3309 | /// Set bitmask. Only the first n-1 bits are valid.\r | |
| 3310 | /// Bits 22:n are reserved.\r | |
| 3311 | ///\r | |
| 3312 | UINT32 Ovf_FIXED_CTRn:23;\r | |
| 3313 | ///\r | |
| 3314 | /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3315 | ///\r | |
| 3316 | UINT32 Trace_ToPA_PMI:1;\r | |
| 3317 | UINT32 Reserved2:2;\r | |
| 3318 | ///\r | |
| 3319 | /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3320 | ///\r | |
| 3321 | UINT32 LBR_Frz:1;\r | |
| 3322 | ///\r | |
| 3323 | /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3324 | ///\r | |
| 3325 | UINT32 CTR_Frz:1;\r | |
| 3326 | ///\r | |
| 3327 | /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3328 | ///\r | |
| 3329 | UINT32 ASCI:1;\r | |
| 3330 | ///\r | |
| 3331 | /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3332 | ///\r | |
| 3333 | UINT32 Ovf_Uncore:1;\r | |
| 3334 | ///\r | |
| 3335 | /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r | |
| 3336 | ///\r | |
| 3337 | UINT32 OvfBuf:1;\r | |
| 3338 | UINT32 Reserved3:1;\r | |
| 3339 | } Bits;\r | |
| 3340 | ///\r | |
| 3341 | /// All bit fields as a 64-bit value\r | |
| 3342 | ///\r | |
| 3343 | UINT64 Uint64;\r | |
| 3344 | } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r | |
| 3345 | \r | |
| 3346 | \r | |
| 3347 | /**\r | |
| 3348 | Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r | |
| 3349 | 3.\r | |
| 3350 | \r | |
| 3351 | @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)\r | |
| 3352 | @param EAX Lower 32-bits of MSR value.\r | |
| 3353 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
| 3354 | @param EDX Upper 32-bits of MSR value.\r | |
| 3355 | Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.\r | |
| 3356 | \r | |
| 3357 | <b>Example usage</b>\r | |
| 3358 | @code\r | |
| 3359 | MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;\r | |
| 3360 | \r | |
| 3361 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);\r | |
| 3362 | @endcode\r | |
| 7de98828 | 3363 | @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r |
| 04c980a6 MK |
3364 | **/\r |
| 3365 | #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r | |
| 3366 | \r | |
| 3367 | /**\r | |
| 3368 | MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r | |
| 3369 | **/\r | |
| 3370 | typedef union {\r | |
| 3371 | ///\r | |
| 3372 | /// Individual bit fields\r | |
| 3373 | ///\r | |
| 3374 | struct {\r | |
| 3375 | ///\r | |
| 3376 | /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.\r | |
| 3377 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
| 3378 | /// Bits 31:n are reserved.\r | |
| 3379 | ///\r | |
| 3380 | UINT32 IA32_PERFEVTSELn:32;\r | |
| 3381 | ///\r | |
| 3382 | /// [Bits 62:32] IA32_FIXED_CTRn in use.\r | |
| 3383 | /// If CPUID.0AH: EAX[7:0] > n.\r | |
| 3384 | /// Status bitmask. Only the first n-1 bits are valid.\r | |
| 3385 | /// Bits 30:n are reserved.\r | |
| 3386 | ///\r | |
| 3387 | UINT32 IA32_FIXED_CTRn:31;\r | |
| 3388 | ///\r | |
| 3389 | /// [Bit 63] PMI in use.\r | |
| 3390 | ///\r | |
| 3391 | UINT32 PMI:1;\r | |
| 3392 | } Bits;\r | |
| 3393 | ///\r | |
| 3394 | /// All bit fields as a 64-bit value\r | |
| 3395 | ///\r | |
| 3396 | UINT64 Uint64;\r | |
| 3397 | } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r | |
| 3398 | \r | |
| 3399 | \r | |
| 3400 | /**\r | |
| 3401 | PEBS Control (R/W).\r | |
| 3402 | \r | |
| 3403 | @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)\r | |
| 3404 | @param EAX Lower 32-bits of MSR value.\r | |
| 3405 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
| 3406 | @param EDX Upper 32-bits of MSR value.\r | |
| 3407 | Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.\r | |
| 3408 | \r | |
| 3409 | <b>Example usage</b>\r | |
| 3410 | @code\r | |
| 3411 | MSR_IA32_PEBS_ENABLE_REGISTER Msr;\r | |
| 3412 | \r | |
| 3413 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);\r | |
| 3414 | AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);\r | |
| 3415 | @endcode\r | |
| 7de98828 | 3416 | @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r |
| 04c980a6 MK |
3417 | **/\r |
| 3418 | #define MSR_IA32_PEBS_ENABLE 0x000003F1\r | |
| 3419 | \r | |
| 3420 | /**\r | |
| 3421 | MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r | |
| 3422 | **/\r | |
| 3423 | typedef union {\r | |
| 3424 | ///\r | |
| 3425 | /// Individual bit fields\r | |
| 3426 | ///\r | |
| 3427 | struct {\r | |
| 3428 | ///\r | |
| 3429 | /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r | |
| 3430 | /// Display Model 06_0FH.\r | |
| 3431 | ///\r | |
| 3432 | UINT32 Enable:1;\r | |
| 3433 | ///\r | |
| 3434 | /// [Bits 3:1] Reserved or Model specific.\r | |
| 3435 | ///\r | |
| 3436 | UINT32 Reserved1:3;\r | |
| 3437 | UINT32 Reserved2:28;\r | |
| 3438 | ///\r | |
| 3439 | /// [Bits 35:32] Reserved or Model specific.\r | |
| 3440 | ///\r | |
| 3441 | UINT32 Reserved3:4;\r | |
| 3442 | UINT32 Reserved4:28;\r | |
| 3443 | } Bits;\r | |
| 3444 | ///\r | |
| 3445 | /// All bit fields as a 64-bit value\r | |
| 3446 | ///\r | |
| 3447 | UINT64 Uint64;\r | |
| 3448 | } MSR_IA32_PEBS_ENABLE_REGISTER;\r | |
| 3449 | \r | |
| 3450 | \r | |
| 3451 | /**\r | |
| 3452 | MCn_CTL. If IA32_MCG_CAP.CNT > n.\r | |
| 3453 | \r | |
| 3454 | @param ECX MSR_IA32_MCn_CTL\r | |
| 3455 | @param EAX Lower 32-bits of MSR value.\r | |
| 3456 | @param EDX Upper 32-bits of MSR value.\r | |
| 3457 | \r | |
| 3458 | <b>Example usage</b>\r | |
| 3459 | @code\r | |
| 3460 | UINT64 Msr;\r | |
| 3461 | \r | |
| 3462 | Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);\r | |
| 3463 | AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);\r | |
| 3464 | @endcode\r | |
| 7de98828 JF |
3465 | @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.\r |
| 3466 | MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.\r | |
| 3467 | MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.\r | |
| 3468 | MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.\r | |
| 3469 | MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r | |
| 3470 | MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.\r | |
| 3471 | MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.\r | |
| 3472 | MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.\r | |
| 3473 | MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.\r | |
| 3474 | MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.\r | |
| 3475 | MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.\r | |
| 3476 | MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.\r | |
| 3477 | MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.\r | |
| 3478 | MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.\r | |
| 3479 | MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.\r | |
| 3480 | MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.\r | |
| 3481 | MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.\r | |
| 3482 | MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.\r | |
| 3483 | MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.\r | |
| 3484 | MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.\r | |
| 3485 | MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.\r | |
| 3486 | MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.\r | |
| 3487 | MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.\r | |
| 3488 | MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.\r | |
| 3489 | MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.\r | |
| 3490 | MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.\r | |
| 3491 | MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.\r | |
| 3492 | MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.\r | |
| 3493 | MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r | |
| 04c980a6 MK |
3494 | @{\r |
| 3495 | **/\r | |
| 3496 | #define MSR_IA32_MC0_CTL 0x00000400\r | |
| 3497 | #define MSR_IA32_MC1_CTL 0x00000404\r | |
| 3498 | #define MSR_IA32_MC2_CTL 0x00000408\r | |
| 3499 | #define MSR_IA32_MC3_CTL 0x0000040C\r | |
| 3500 | #define MSR_IA32_MC4_CTL 0x00000410\r | |
| 3501 | #define MSR_IA32_MC5_CTL 0x00000414\r | |
| 3502 | #define MSR_IA32_MC6_CTL 0x00000418\r | |
| 3503 | #define MSR_IA32_MC7_CTL 0x0000041C\r | |
| 3504 | #define MSR_IA32_MC8_CTL 0x00000420\r | |
| 3505 | #define MSR_IA32_MC9_CTL 0x00000424\r | |
| 3506 | #define MSR_IA32_MC10_CTL 0x00000428\r | |
| 3507 | #define MSR_IA32_MC11_CTL 0x0000042C\r | |
| 3508 | #define MSR_IA32_MC12_CTL 0x00000430\r | |
| 3509 | #define MSR_IA32_MC13_CTL 0x00000434\r | |
| 3510 | #define MSR_IA32_MC14_CTL 0x00000438\r | |
| 3511 | #define MSR_IA32_MC15_CTL 0x0000043C\r | |
| 3512 | #define MSR_IA32_MC16_CTL 0x00000440\r | |
| 3513 | #define MSR_IA32_MC17_CTL 0x00000444\r | |
| 3514 | #define MSR_IA32_MC18_CTL 0x00000448\r | |
| 3515 | #define MSR_IA32_MC19_CTL 0x0000044C\r | |
| 3516 | #define MSR_IA32_MC20_CTL 0x00000450\r | |
| 3517 | #define MSR_IA32_MC21_CTL 0x00000454\r | |
| 3518 | #define MSR_IA32_MC22_CTL 0x00000458\r | |
| 3519 | #define MSR_IA32_MC23_CTL 0x0000045C\r | |
| 3520 | #define MSR_IA32_MC24_CTL 0x00000460\r | |
| 3521 | #define MSR_IA32_MC25_CTL 0x00000464\r | |
| 3522 | #define MSR_IA32_MC26_CTL 0x00000468\r | |
| 3523 | #define MSR_IA32_MC27_CTL 0x0000046C\r | |
| 3524 | #define MSR_IA32_MC28_CTL 0x00000470\r | |
| 3525 | /// @}\r | |
| 3526 | \r | |
| 3527 | \r | |
| 3528 | /**\r | |
| 3529 | MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r | |
| 3530 | \r | |
| 3531 | @param ECX MSR_IA32_MCn_STATUS\r | |
| 3532 | @param EAX Lower 32-bits of MSR value.\r | |
| 3533 | @param EDX Upper 32-bits of MSR value.\r | |
| 3534 | \r | |
| 3535 | <b>Example usage</b>\r | |
| 3536 | @code\r | |
| 3537 | UINT64 Msr;\r | |
| 3538 | \r | |
| 3539 | Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);\r | |
| 3540 | AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);\r | |
| 3541 | @endcode\r | |
| 7de98828 JF |
3542 | @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.\r |
| 3543 | MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.\r | |
| 3544 | MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.\r | |
| 3545 | MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.\r | |
| 3546 | MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.\r | |
| 3547 | MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.\r | |
| 3548 | MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.\r | |
| 3549 | MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.\r | |
| 3550 | MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.\r | |
| 3551 | MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.\r | |
| 3552 | MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.\r | |
| 3553 | MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.\r | |
| 3554 | MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.\r | |
| 3555 | MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.\r | |
| 3556 | MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.\r | |
| 3557 | MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.\r | |
| 3558 | MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.\r | |
| 3559 | MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.\r | |
| 3560 | MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.\r | |
| 3561 | MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.\r | |
| 3562 | MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.\r | |
| 3563 | MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.\r | |
| 3564 | MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.\r | |
| 3565 | MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.\r | |
| 3566 | MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.\r | |
| 3567 | MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.\r | |
| 3568 | MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.\r | |
| 3569 | MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.\r | |
| 3570 | MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r | |
| 04c980a6 MK |
3571 | @{\r |
| 3572 | **/\r | |
| 3573 | #define MSR_IA32_MC0_STATUS 0x00000401\r | |
| 3574 | #define MSR_IA32_MC1_STATUS 0x00000405\r | |
| 3575 | #define MSR_IA32_MC2_STATUS 0x00000409\r | |
| 3576 | #define MSR_IA32_MC3_STATUS 0x0000040D\r | |
| 3577 | #define MSR_IA32_MC4_STATUS 0x00000411\r | |
| 3578 | #define MSR_IA32_MC5_STATUS 0x00000415\r | |
| 3579 | #define MSR_IA32_MC6_STATUS 0x00000419\r | |
| 3580 | #define MSR_IA32_MC7_STATUS 0x0000041D\r | |
| 3581 | #define MSR_IA32_MC8_STATUS 0x00000421\r | |
| 3582 | #define MSR_IA32_MC9_STATUS 0x00000425\r | |
| 3583 | #define MSR_IA32_MC10_STATUS 0x00000429\r | |
| 3584 | #define MSR_IA32_MC11_STATUS 0x0000042D\r | |
| 3585 | #define MSR_IA32_MC12_STATUS 0x00000431\r | |
| 3586 | #define MSR_IA32_MC13_STATUS 0x00000435\r | |
| 3587 | #define MSR_IA32_MC14_STATUS 0x00000439\r | |
| 3588 | #define MSR_IA32_MC15_STATUS 0x0000043D\r | |
| 3589 | #define MSR_IA32_MC16_STATUS 0x00000441\r | |
| 3590 | #define MSR_IA32_MC17_STATUS 0x00000445\r | |
| 3591 | #define MSR_IA32_MC18_STATUS 0x00000449\r | |
| 3592 | #define MSR_IA32_MC19_STATUS 0x0000044D\r | |
| 3593 | #define MSR_IA32_MC20_STATUS 0x00000451\r | |
| 3594 | #define MSR_IA32_MC21_STATUS 0x00000455\r | |
| 3595 | #define MSR_IA32_MC22_STATUS 0x00000459\r | |
| 3596 | #define MSR_IA32_MC23_STATUS 0x0000045D\r | |
| 3597 | #define MSR_IA32_MC24_STATUS 0x00000461\r | |
| 3598 | #define MSR_IA32_MC25_STATUS 0x00000465\r | |
| 3599 | #define MSR_IA32_MC26_STATUS 0x00000469\r | |
| 3600 | #define MSR_IA32_MC27_STATUS 0x0000046D\r | |
| 3601 | #define MSR_IA32_MC28_STATUS 0x00000471\r | |
| 3602 | /// @}\r | |
| 3603 | \r | |
| 3604 | \r | |
| 3605 | /**\r | |
| 3606 | MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r | |
| 3607 | \r | |
| 3608 | @param ECX MSR_IA32_MCn_ADDR\r | |
| 3609 | @param EAX Lower 32-bits of MSR value.\r | |
| 3610 | @param EDX Upper 32-bits of MSR value.\r | |
| 3611 | \r | |
| 3612 | <b>Example usage</b>\r | |
| 3613 | @code\r | |
| 3614 | UINT64 Msr;\r | |
| 3615 | \r | |
| 3616 | Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);\r | |
| 3617 | AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);\r | |
| 3618 | @endcode\r | |
| 7de98828 JF |
3619 | @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.\r |
| 3620 | MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.\r | |
| 3621 | MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.\r | |
| 3622 | MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.\r | |
| 3623 | MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.\r | |
| 3624 | MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.\r | |
| 3625 | MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.\r | |
| 3626 | MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.\r | |
| 3627 | MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.\r | |
| 3628 | MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.\r | |
| 3629 | MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.\r | |
| 3630 | MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.\r | |
| 3631 | MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.\r | |
| 3632 | MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.\r | |
| 3633 | MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.\r | |
| 3634 | MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.\r | |
| 3635 | MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.\r | |
| 3636 | MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.\r | |
| 3637 | MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.\r | |
| 3638 | MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.\r | |
| 3639 | MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.\r | |
| 3640 | MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.\r | |
| 3641 | MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.\r | |
| 3642 | MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.\r | |
| 3643 | MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.\r | |
| 3644 | MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.\r | |
| 3645 | MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.\r | |
| 3646 | MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.\r | |
| 3647 | MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r | |
| 04c980a6 MK |
3648 | @{\r |
| 3649 | **/\r | |
| 3650 | #define MSR_IA32_MC0_ADDR 0x00000402\r | |
| 3651 | #define MSR_IA32_MC1_ADDR 0x00000406\r | |
| 3652 | #define MSR_IA32_MC2_ADDR 0x0000040A\r | |
| 3653 | #define MSR_IA32_MC3_ADDR 0x0000040E\r | |
| 3654 | #define MSR_IA32_MC4_ADDR 0x00000412\r | |
| 3655 | #define MSR_IA32_MC5_ADDR 0x00000416\r | |
| 3656 | #define MSR_IA32_MC6_ADDR 0x0000041A\r | |
| 3657 | #define MSR_IA32_MC7_ADDR 0x0000041E\r | |
| 3658 | #define MSR_IA32_MC8_ADDR 0x00000422\r | |
| 3659 | #define MSR_IA32_MC9_ADDR 0x00000426\r | |
| 3660 | #define MSR_IA32_MC10_ADDR 0x0000042A\r | |
| 3661 | #define MSR_IA32_MC11_ADDR 0x0000042E\r | |
| 3662 | #define MSR_IA32_MC12_ADDR 0x00000432\r | |
| 3663 | #define MSR_IA32_MC13_ADDR 0x00000436\r | |
| 3664 | #define MSR_IA32_MC14_ADDR 0x0000043A\r | |
| 3665 | #define MSR_IA32_MC15_ADDR 0x0000043E\r | |
| 3666 | #define MSR_IA32_MC16_ADDR 0x00000442\r | |
| 3667 | #define MSR_IA32_MC17_ADDR 0x00000446\r | |
| 3668 | #define MSR_IA32_MC18_ADDR 0x0000044A\r | |
| 3669 | #define MSR_IA32_MC19_ADDR 0x0000044E\r | |
| 3670 | #define MSR_IA32_MC20_ADDR 0x00000452\r | |
| 3671 | #define MSR_IA32_MC21_ADDR 0x00000456\r | |
| 3672 | #define MSR_IA32_MC22_ADDR 0x0000045A\r | |
| 3673 | #define MSR_IA32_MC23_ADDR 0x0000045E\r | |
| 3674 | #define MSR_IA32_MC24_ADDR 0x00000462\r | |
| 3675 | #define MSR_IA32_MC25_ADDR 0x00000466\r | |
| 3676 | #define MSR_IA32_MC26_ADDR 0x0000046A\r | |
| 3677 | #define MSR_IA32_MC27_ADDR 0x0000046E\r | |
| 3678 | #define MSR_IA32_MC28_ADDR 0x00000472\r | |
| 3679 | /// @}\r | |
| 3680 | \r | |
| 3681 | \r | |
| 3682 | /**\r | |
| 3683 | MCn_MISC. If IA32_MCG_CAP.CNT > n.\r | |
| 3684 | \r | |
| 3685 | @param ECX MSR_IA32_MCn_MISC\r | |
| 3686 | @param EAX Lower 32-bits of MSR value.\r | |
| 3687 | @param EDX Upper 32-bits of MSR value.\r | |
| 3688 | \r | |
| 3689 | <b>Example usage</b>\r | |
| 3690 | @code\r | |
| 3691 | UINT64 Msr;\r | |
| 3692 | \r | |
| 3693 | Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);\r | |
| 3694 | AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);\r | |
| 3695 | @endcode\r | |
| 7de98828 JF |
3696 | @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.\r |
| 3697 | MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.\r | |
| 3698 | MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.\r | |
| 3699 | MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.\r | |
| 3700 | MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.\r | |
| 3701 | MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.\r | |
| 3702 | MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r | |
| 3703 | MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.\r | |
| 3704 | MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.\r | |
| 3705 | MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.\r | |
| 3706 | MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.\r | |
| 3707 | MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.\r | |
| 3708 | MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.\r | |
| 3709 | MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.\r | |
| 3710 | MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.\r | |
| 3711 | MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.\r | |
| 3712 | MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.\r | |
| 3713 | MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.\r | |
| 3714 | MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.\r | |
| 3715 | MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.\r | |
| 3716 | MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.\r | |
| 3717 | MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.\r | |
| 3718 | MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.\r | |
| 3719 | MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.\r | |
| 3720 | MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.\r | |
| 3721 | MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.\r | |
| 3722 | MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.\r | |
| 3723 | MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.\r | |
| 3724 | MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r | |
| 04c980a6 MK |
3725 | @{\r |
| 3726 | **/\r | |
| 3727 | #define MSR_IA32_MC0_MISC 0x00000403\r | |
| 3728 | #define MSR_IA32_MC1_MISC 0x00000407\r | |
| 3729 | #define MSR_IA32_MC2_MISC 0x0000040B\r | |
| 3730 | #define MSR_IA32_MC3_MISC 0x0000040F\r | |
| 3731 | #define MSR_IA32_MC4_MISC 0x00000413\r | |
| 3732 | #define MSR_IA32_MC5_MISC 0x00000417\r | |
| 3733 | #define MSR_IA32_MC6_MISC 0x0000041B\r | |
| 3734 | #define MSR_IA32_MC7_MISC 0x0000041F\r | |
| 3735 | #define MSR_IA32_MC8_MISC 0x00000423\r | |
| 3736 | #define MSR_IA32_MC9_MISC 0x00000427\r | |
| 3737 | #define MSR_IA32_MC10_MISC 0x0000042B\r | |
| 3738 | #define MSR_IA32_MC11_MISC 0x0000042F\r | |
| 3739 | #define MSR_IA32_MC12_MISC 0x00000433\r | |
| 3740 | #define MSR_IA32_MC13_MISC 0x00000437\r | |
| 3741 | #define MSR_IA32_MC14_MISC 0x0000043B\r | |
| 3742 | #define MSR_IA32_MC15_MISC 0x0000043F\r | |
| 3743 | #define MSR_IA32_MC16_MISC 0x00000443\r | |
| 3744 | #define MSR_IA32_MC17_MISC 0x00000447\r | |
| 3745 | #define MSR_IA32_MC18_MISC 0x0000044B\r | |
| 3746 | #define MSR_IA32_MC19_MISC 0x0000044F\r | |
| 3747 | #define MSR_IA32_MC20_MISC 0x00000453\r | |
| 3748 | #define MSR_IA32_MC21_MISC 0x00000457\r | |
| 3749 | #define MSR_IA32_MC22_MISC 0x0000045B\r | |
| 3750 | #define MSR_IA32_MC23_MISC 0x0000045F\r | |
| 3751 | #define MSR_IA32_MC24_MISC 0x00000463\r | |
| 3752 | #define MSR_IA32_MC25_MISC 0x00000467\r | |
| 3753 | #define MSR_IA32_MC26_MISC 0x0000046B\r | |
| 3754 | #define MSR_IA32_MC27_MISC 0x0000046F\r | |
| 3755 | #define MSR_IA32_MC28_MISC 0x00000473\r | |
| 3756 | /// @}\r | |
| 3757 | \r | |
| 3758 | \r | |
| 3759 | /**\r | |
| 3760 | Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r | |
| 3761 | VMX Information.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3762 | \r | |
| 3763 | @param ECX MSR_IA32_VMX_BASIC (0x00000480)\r | |
| 3764 | @param EAX Lower 32-bits of MSR value.\r | |
| 3765 | @param EDX Upper 32-bits of MSR value.\r | |
| 3766 | \r | |
| 3767 | <b>Example usage</b>\r | |
| 3768 | @code\r | |
| 831d287a | 3769 | MSR_IA32_VMX_BASIC_REGISTER Msr;\r |
| 04c980a6 | 3770 | \r |
| 831d287a | 3771 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);\r |
| 04c980a6 | 3772 | @endcode\r |
| 7de98828 | 3773 | @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r |
| 04c980a6 MK |
3774 | **/\r |
| 3775 | #define MSR_IA32_VMX_BASIC 0x00000480\r | |
| 3776 | \r | |
| 831d287a MK |
3777 | /**\r |
| 3778 | MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r | |
| 3779 | **/\r | |
| 3780 | typedef union {\r | |
| 3781 | ///\r | |
| 3782 | /// Individual bit fields\r | |
| 3783 | ///\r | |
| 3784 | struct {\r | |
| 3785 | ///\r | |
| 3786 | /// [Bits 30:0] VMCS revision identifier used by the processor. Processors\r | |
| 3787 | /// that use the same VMCS revision identifier use the same size for VMCS\r | |
| 3788 | /// regions (see subsequent item on bits 44:32).\r | |
| 3789 | ///\r | |
| 3790 | /// @note Earlier versions of this manual specified that the VMCS revision\r | |
| 3791 | /// identifier was a 32-bit field in bits 31:0 of this MSR. For all\r | |
| 3792 | /// processors produced prior to this change, bit 31 of this MSR was read\r | |
| 3793 | /// as 0.\r | |
| 3794 | ///\r | |
| 3795 | UINT32 VmcsRevisonId:31;\r | |
| 3796 | UINT32 MustBeZero:1;\r | |
| 3797 | ///\r | |
| 3798 | /// [Bit 44:32] Reports the number of bytes that software should allocate\r | |
| 3799 | /// for the VMXON region and any VMCS region. It is a value greater than\r | |
| 3800 | /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r | |
| 3801 | ///\r | |
| 3802 | UINT32 VmcsSize:13;\r | |
| 3803 | UINT32 Reserved1:3;\r | |
| 3804 | ///\r | |
| 3805 | /// [Bit 48] Indicates the width of the physical addresses that may be used\r | |
| 3806 | /// for the VMXON region, each VMCS, and data structures referenced by\r | |
| 3807 | /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX\r | |
| 3808 | /// transitions). If the bit is 0, these addresses are limited to the\r | |
| 3809 | /// processor's physical-address width. If the bit is 1, these addresses\r | |
| 3810 | /// are limited to 32 bits. This bit is always 0 for processors that\r | |
| 3811 | /// support Intel 64 architecture.\r | |
| 3812 | ///\r | |
| 3813 | /// @note On processors that support Intel 64 architecture, the pointer\r | |
| 3814 | /// must not set bits beyond the processor's physical address width.\r | |
| 3815 | ///\r | |
| 3816 | UINT32 VmcsAddressWidth:1;\r | |
| 3817 | ///\r | |
| 3818 | /// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r | |
| 3819 | /// dual-monitor treatment of system-management interrupts and\r | |
| 3820 | /// system-management mode. See Section 34.15 for details of this treatment.\r | |
| 3821 | ///\r | |
| 3822 | UINT32 DualMonitor:1;\r | |
| 3823 | ///\r | |
| 3824 | /// [Bit 53:50] report the memory type that should be used for the VMCS,\r | |
| 3825 | /// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r | |
| 3826 | /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG\r | |
| 3827 | /// header. If software needs to access these data structures (e.g., to\r | |
| 3828 | /// modify the contents of the MSR bitmaps), it can configure the paging\r | |
| 3829 | /// structures to map them into the linear-address space. If it does so,\r | |
| 3830 | /// it should establish mappings that use the memory type reported bits\r | |
| 3831 | /// 53:50 in this MSR.\r | |
| 3832 | ///\r | |
| 3833 | /// As of this writing, all processors that support VMX operation indicate\r | |
| 3834 | /// the write-back type.\r | |
| 3835 | ///\r | |
| 3836 | /// If software needs to access these data structures (e.g., to modify\r | |
| 3837 | /// the contents of the MSR bitmaps), it can configure the paging\r | |
| 3838 | /// structures to map them into the linear-address space. If it does so,\r | |
| 3839 | /// it should establish mappings that use the memory type reported in this\r | |
| 3840 | /// MSR.\r | |
| 3841 | ///\r | |
| 3842 | /// @note Alternatively, software may map any of these regions or\r | |
| 3843 | /// structures with the UC memory type. (This may be necessary for the MSEG\r | |
| 3844 | /// header.) Doing so is discouraged unless necessary as it will cause the\r | |
| 3845 | /// performance of software accesses to those structures to suffer.\r | |
| 3846 | ///\r | |
| 3847 | ///\r | |
| 3848 | UINT32 MemoryType:4;\r | |
| 3849 | ///\r | |
| 0f16be6d HW |
3850 | /// [Bit 54] If bit 54 is read as 1, the processor reports information in\r |
| 3851 | /// the VM-exit instruction-information field on VM exitsdue to execution\r | |
| 3852 | /// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r | |
| 3853 | /// is done only if this bit is read as 1.\r | |
| 831d287a MK |
3854 | ///\r |
| 3855 | UINT32 InsOutsReporting:1;\r | |
| 3856 | ///\r | |
| 3857 | /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r | |
| 3858 | /// be cleared to 0. See Appendix A.2 for details. It also reports support\r | |
| 3859 | /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,\r | |
| 3860 | /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and\r | |
| 3861 | /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r | |
| 3862 | /// Appendix A.4, and Appendix A.5 for details.\r | |
| 3863 | ///\r | |
| 3864 | UINT32 VmxControls:1;\r | |
| 3865 | UINT32 Reserved2:8;\r | |
| 3866 | } Bits;\r | |
| 3867 | ///\r | |
| 3868 | /// All bit fields as a 64-bit value\r | |
| 3869 | ///\r | |
| 3870 | UINT64 Uint64;\r | |
| 3871 | } MSR_IA32_VMX_BASIC_REGISTER;\r | |
| 3872 | \r | |
| 3873 | ///\r | |
| 3874 | /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType\r | |
| 3875 | ///\r | |
| 3876 | #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00\r | |
| 3877 | #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06\r | |
| 3878 | ///\r | |
| 3879 | /// @}\r | |
| 3880 | ///\r | |
| 3881 | \r | |
| 04c980a6 MK |
3882 | \r |
| 3883 | /**\r | |
| 3884 | Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r | |
| 3885 | Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3886 | \r | |
| 3887 | @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)\r | |
| 3888 | @param EAX Lower 32-bits of MSR value.\r | |
| 3889 | @param EDX Upper 32-bits of MSR value.\r | |
| 3890 | \r | |
| 3891 | <b>Example usage</b>\r | |
| 3892 | @code\r | |
| 3893 | UINT64 Msr;\r | |
| 3894 | \r | |
| 3895 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);\r | |
| 3896 | @endcode\r | |
| 7de98828 | 3897 | @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3898 | **/\r |
| 3899 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r | |
| 3900 | \r | |
| 3901 | \r | |
| 3902 | /**\r | |
| 3903 | Capability Reporting Register of Primary Processor-based VM-execution\r | |
| 3904 | Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution\r | |
| 3905 | Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3906 | \r | |
| 3907 | @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)\r | |
| 3908 | @param EAX Lower 32-bits of MSR value.\r | |
| 3909 | @param EDX Upper 32-bits of MSR value.\r | |
| 3910 | \r | |
| 3911 | <b>Example usage</b>\r | |
| 3912 | @code\r | |
| 3913 | UINT64 Msr;\r | |
| 3914 | \r | |
| 3915 | Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);\r | |
| 3916 | @endcode\r | |
| 7de98828 | 3917 | @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r |
| 04c980a6 MK |
3918 | **/\r |
| 3919 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r | |
| 3920 | \r | |
| 3921 | \r | |
| 3922 | /**\r | |
| 3923 | Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r | |
| 3924 | "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3925 | \r | |
| 3926 | @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)\r | |
| 3927 | @param EAX Lower 32-bits of MSR value.\r | |
| 3928 | @param EDX Upper 32-bits of MSR value.\r | |
| 3929 | \r | |
| 3930 | <b>Example usage</b>\r | |
| 3931 | @code\r | |
| 3932 | UINT64 Msr;\r | |
| 3933 | \r | |
| 3934 | Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);\r | |
| 3935 | @endcode\r | |
| 7de98828 | 3936 | @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r |
| 04c980a6 MK |
3937 | **/\r |
| 3938 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r | |
| 3939 | \r | |
| 3940 | \r | |
| 3941 | /**\r | |
| 3942 | Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r | |
| 3943 | "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3944 | \r | |
| 3945 | @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)\r | |
| 3946 | @param EAX Lower 32-bits of MSR value.\r | |
| 3947 | @param EDX Upper 32-bits of MSR value.\r | |
| 3948 | \r | |
| 3949 | <b>Example usage</b>\r | |
| 3950 | @code\r | |
| 3951 | UINT64 Msr;\r | |
| 3952 | \r | |
| 3953 | Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);\r | |
| 3954 | @endcode\r | |
| 7de98828 | 3955 | @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r |
| 04c980a6 MK |
3956 | **/\r |
| 3957 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r | |
| 3958 | \r | |
| 3959 | \r | |
| 3960 | /**\r | |
| 3961 | Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r | |
| 3962 | "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.\r | |
| 3963 | \r | |
| 3964 | @param ECX MSR_IA32_VMX_MISC (0x00000485)\r | |
| 3965 | @param EAX Lower 32-bits of MSR value.\r | |
| 3966 | @param EDX Upper 32-bits of MSR value.\r | |
| 3967 | \r | |
| 3968 | <b>Example usage</b>\r | |
| 3969 | @code\r | |
| 831d287a | 3970 | IA32_VMX_MISC_REGISTER Msr;\r |
| 04c980a6 | 3971 | \r |
| 831d287a | 3972 | Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r |
| 04c980a6 | 3973 | @endcode\r |
| 7de98828 | 3974 | @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r |
| 04c980a6 MK |
3975 | **/\r |
| 3976 | #define MSR_IA32_VMX_MISC 0x00000485\r | |
| 3977 | \r | |
| 831d287a MK |
3978 | /**\r |
| 3979 | MSR information returned for MSR index #IA32_VMX_MISC\r | |
| 3980 | **/\r | |
| 3981 | typedef union {\r | |
| 3982 | ///\r | |
| 3983 | /// Individual bit fields\r | |
| 3984 | ///\r | |
| 3985 | struct {\r | |
| 3986 | ///\r | |
| 3987 | /// [Bits 4:0] Reports a value X that specifies the relationship between the\r | |
| 3988 | /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).\r | |
| 3989 | /// Specifically, the VMX-preemption timer (if it is active) counts down by\r | |
| 3990 | /// 1 every time bit X in the TSC changes due to a TSC increment.\r | |
| 3991 | ///\r | |
| 3992 | UINT32 VmxTimerRatio:5;\r | |
| 3993 | ///\r | |
| 3994 | /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r | |
| 3995 | /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r | |
| 3996 | /// details. This bit is read as 1 on any logical processor that supports\r | |
| 3997 | /// the 1-setting of the "unrestricted guest" VM-execution control.\r | |
| 3998 | ///\r | |
| 3999 | UINT32 VmExitEferLma:1;\r | |
| 4000 | ///\r | |
| 4001 | /// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r | |
| 4002 | ///\r | |
| 4003 | UINT32 HltActivityStateSupported:1;\r | |
| 4004 | ///\r | |
| 4005 | /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r | |
| 4006 | ///\r | |
| 4007 | UINT32 ShutdownActivityStateSupported:1;\r | |
| 4008 | ///\r | |
| 4009 | /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r | |
| 4010 | ///\r | |
| 4011 | UINT32 WaitForSipiActivityStateSupported:1;\r | |
| 0f16be6d HW |
4012 | UINT32 Reserved1:5;\r |
| 4013 | ///\r | |
| 4014 | /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r | |
| 4015 | /// in VMX operation. If the processor supports Intel PT but does not allow\r | |
| 4016 | /// it to be used in VMX operation, execution of VMXON clears\r | |
| 4017 |