projects / mirror_edk2.git / blame
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| c67b579c MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel processors based on the Haswell-E microarchitecture.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| f4c982bf | 9 | Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r |
| c67b579c MK |
10 | This program and the accompanying materials\r |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| 19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 0f16be6d | 20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.12.\r |
| c67b579c MK |
21 | \r |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __HASWELL_E_MSR_H__\r | |
| 25 | #define __HASWELL_E_MSR_H__\r | |
| 26 | \r | |
| 27 | #include <Register/ArchitecturalMsr.h>\r | |
| 28 | \r | |
| f4c982bf JF |
29 | /**\r |
| 30 | Is Intel processors based on the Haswell-E microarchitecture?\r | |
| 31 | \r | |
| 32 | @param DisplayFamily Display Family ID\r | |
| 33 | @param DisplayModel Display Model ID\r | |
| 34 | \r | |
| 35 | @retval TRUE Yes, it is.\r | |
| 36 | @retval FALSE No, it isn't.\r | |
| 37 | **/\r | |
| 38 | #define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 39 | (DisplayFamily == 0x06 && \\r | |
| 40 | ( \\r | |
| 41 | DisplayModel == 0x3F \\r | |
| 42 | ) \\r | |
| 43 | )\r | |
| 44 | \r | |
| 0f16be6d HW |
45 | /**\r |
| 46 | Package. Configured State of Enabled Processor Core Count and Logical\r | |
| 47 | Processor Count (RO) - After a Power-On RESET, enumerates factory\r | |
| 48 | configuration of the number of processor cores and logical processors in the\r | |
| 49 | physical package. - Following the sequence of (i) BIOS modified a\r | |
| 50 | Configuration Mask which selects a subset of processor cores to be active\r | |
| 51 | post RESET and (ii) a RESET event after the modification, enumerates the\r | |
| 52 | current configuration of enabled processor core count and logical processor\r | |
| 53 | count in the physical package.\r | |
| 54 | \r | |
| 55 | @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)\r | |
| 56 | @param EAX Lower 32-bits of MSR value.\r | |
| 57 | Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r | |
| 58 | @param EDX Upper 32-bits of MSR value.\r | |
| 59 | Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.\r | |
| 60 | \r | |
| 61 | <b>Example usage</b>\r | |
| 62 | @code\r | |
| 63 | MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;\r | |
| 64 | \r | |
| 65 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);\r | |
| 66 | @endcode\r | |
| 67 | @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.\r | |
| 68 | **/\r | |
| 69 | #define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035\r | |
| 70 | \r | |
| 71 | /**\r | |
| 72 | MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT\r | |
| 73 | **/\r | |
| 74 | typedef union {\r | |
| 75 | ///\r | |
| 76 | /// Individual bit fields\r | |
| 77 | ///\r | |
| 78 | struct {\r | |
| 79 | ///\r | |
| 80 | /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are\r | |
| 81 | /// currently enabled (by either factory configuration or BIOS\r | |
| 82 | /// configuration) in the physical package.\r | |
| 83 | ///\r | |
| 84 | UINT32 Core_Count:16;\r | |
| 85 | ///\r | |
| 86 | /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that\r | |
| 87 | /// are currently enabled (by either factory configuration or BIOS\r | |
| 88 | /// configuration) in the physical package.\r | |
| 89 | ///\r | |
| 90 | UINT32 Thread_Count:16;\r | |
| 91 | UINT32 Reserved:32;\r | |
| 92 | } Bits;\r | |
| 93 | ///\r | |
| 94 | /// All bit fields as a 32-bit value\r | |
| 95 | ///\r | |
| 96 | UINT32 Uint32;\r | |
| 97 | ///\r | |
| 98 | /// All bit fields as a 64-bit value\r | |
| 99 | ///\r | |
| 100 | UINT64 Uint64;\r | |
| 101 | } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;\r | |
| 102 | \r | |
| 103 | \r | |
| 104 | /**\r | |
| 105 | Thread. A Hardware Assigned ID for the Logical Processor (RO).\r | |
| 106 | \r | |
| 107 | @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)\r | |
| 108 | @param EAX Lower 32-bits of MSR value.\r | |
| 109 | Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r | |
| 110 | @param EDX Upper 32-bits of MSR value.\r | |
| 111 | Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.\r | |
| 112 | \r | |
| 113 | <b>Example usage</b>\r | |
| 114 | @code\r | |
| 115 | MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;\r | |
| 116 | \r | |
| 117 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);\r | |
| 118 | @endcode\r | |
| 119 | @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.\r | |
| 120 | **/\r | |
| 121 | #define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053\r | |
| 122 | \r | |
| 123 | /**\r | |
| 124 | MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO\r | |
| 125 | **/\r | |
| 126 | typedef union {\r | |
| 127 | ///\r | |
| 128 | /// Individual bit fields\r | |
| 129 | ///\r | |
| 130 | struct {\r | |
| 131 | ///\r | |
| 132 | /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific\r | |
| 133 | /// numerical. value physically assigned to each logical processor. This\r | |
| 134 | /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within\r | |
| 135 | /// a physical package.\r | |
| 136 | ///\r | |
| 137 | UINT32 Logical_Processor_ID:8;\r | |
| 138 | UINT32 Reserved1:24;\r | |
| 139 | UINT32 Reserved2:32;\r | |
| 140 | } Bits;\r | |
| 141 | ///\r | |
| 142 | /// All bit fields as a 32-bit value\r | |
| 143 | ///\r | |
| 144 | UINT32 Uint32;\r | |
| 145 | ///\r | |
| 146 | /// All bit fields as a 64-bit value\r | |
| 147 | ///\r | |
| 148 | UINT64 Uint64;\r | |
| 149 | } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;\r | |
| 150 | \r | |
| 151 | \r | |
| c67b579c MK |
152 | /**\r |
| 153 | Core. C-State Configuration Control (R/W) Note: C-state values are processor\r | |
| 154 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
| 155 | or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r | |
| 156 | \r | |
| 157 | @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 158 | @param EAX Lower 32-bits of MSR value.\r | |
| 159 | Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 160 | @param EDX Upper 32-bits of MSR value.\r | |
| 161 | Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 162 | \r | |
| 163 | <b>Example usage</b>\r | |
| 164 | @code\r | |
| 165 | MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 166 | \r | |
| 167 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);\r | |
| 168 | AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 169 | @endcode\r | |
| a73ab083 | 170 | @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
| c67b579c MK |
171 | **/\r |
| 172 | #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
| 173 | \r | |
| 174 | /**\r | |
| 175 | MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL\r | |
| 176 | **/\r | |
| 177 | typedef union {\r | |
| 178 | ///\r | |
| 179 | /// Individual bit fields\r | |
| 180 | ///\r | |
| 181 | struct {\r | |
| 182 | ///\r | |
| 183 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 184 | /// processor-specific C-state code name (consuming the least power) for\r | |
| 185 | /// the package. The default is set as factory-configured package C-state\r | |
| 186 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
| 187 | /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r | |
| 188 | /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r | |
| 189 | /// supported by the processor are available.\r | |
| 190 | ///\r | |
| 191 | UINT32 Limit:3;\r | |
| 192 | UINT32 Reserved1:7;\r | |
| 193 | ///\r | |
| 194 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
| 195 | ///\r | |
| 196 | UINT32 IO_MWAIT:1;\r | |
| 197 | UINT32 Reserved2:4;\r | |
| 198 | ///\r | |
| 199 | /// [Bit 15] CFG Lock (R/WO).\r | |
| 200 | ///\r | |
| 201 | UINT32 CFGLock:1;\r | |
| 202 | UINT32 Reserved3:9;\r | |
| 203 | ///\r | |
| 204 | /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r | |
| 205 | ///\r | |
| 206 | UINT32 C3AutoDemotion:1;\r | |
| 207 | ///\r | |
| 208 | /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r | |
| 209 | ///\r | |
| 210 | UINT32 C1AutoDemotion:1;\r | |
| 211 | ///\r | |
| 212 | /// [Bit 27] Enable C3 Undemotion (R/W).\r | |
| 213 | ///\r | |
| 214 | UINT32 C3Undemotion:1;\r | |
| 215 | ///\r | |
| 216 | /// [Bit 28] Enable C1 Undemotion (R/W).\r | |
| 217 | ///\r | |
| 218 | UINT32 C1Undemotion:1;\r | |
| 219 | ///\r | |
| 220 | /// [Bit 29] Package C State Demotion Enable (R/W).\r | |
| 221 | ///\r | |
| 222 | UINT32 CStateDemotion:1;\r | |
| 223 | ///\r | |
| 224 | /// [Bit 30] Package C State UnDemotion Enable (R/W).\r | |
| 225 | ///\r | |
| 226 | UINT32 CStateUndemotion:1;\r | |
| 227 | UINT32 Reserved4:1;\r | |
| 228 | UINT32 Reserved5:32;\r | |
| 229 | } Bits;\r | |
| 230 | ///\r | |
| 231 | /// All bit fields as a 32-bit value\r | |
| 232 | ///\r | |
| 233 | UINT32 Uint32;\r | |
| 234 | ///\r | |
| 235 | /// All bit fields as a 64-bit value\r | |
| 236 | ///\r | |
| 237 | UINT64 Uint64;\r | |
| 238 | } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
| 239 | \r | |
| 240 | \r | |
| 241 | /**\r | |
| 242 | Thread. Global Machine Check Capability (R/O).\r | |
| 243 | \r | |
| 244 | @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)\r | |
| 245 | @param EAX Lower 32-bits of MSR value.\r | |
| 246 | Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r | |
| 247 | @param EDX Upper 32-bits of MSR value.\r | |
| 248 | Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r | |
| 249 | \r | |
| 250 | <b>Example usage</b>\r | |
| 251 | @code\r | |
| 252 | MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;\r | |
| 253 | \r | |
| 254 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);\r | |
| 255 | @endcode\r | |
| a73ab083 | 256 | @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r |
| c67b579c MK |
257 | **/\r |
| 258 | #define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r | |
| 259 | \r | |
| 260 | /**\r | |
| 261 | MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP\r | |
| 262 | **/\r | |
| 263 | typedef union {\r | |
| 264 | ///\r | |
| 265 | /// Individual bit fields\r | |
| 266 | ///\r | |
| 267 | struct {\r | |
| 268 | ///\r | |
| 269 | /// [Bits 7:0] Count.\r | |
| 270 | ///\r | |
| 271 | UINT32 Count:8;\r | |
| 272 | ///\r | |
| 273 | /// [Bit 8] MCG_CTL_P.\r | |
| 274 | ///\r | |
| 275 | UINT32 MCG_CTL_P:1;\r | |
| 276 | ///\r | |
| 277 | /// [Bit 9] MCG_EXT_P.\r | |
| 278 | ///\r | |
| 279 | UINT32 MCG_EXT_P:1;\r | |
| 280 | ///\r | |
| 281 | /// [Bit 10] MCP_CMCI_P.\r | |
| 282 | ///\r | |
| 283 | UINT32 MCP_CMCI_P:1;\r | |
| 284 | ///\r | |
| 285 | /// [Bit 11] MCG_TES_P.\r | |
| 286 | ///\r | |
| 287 | UINT32 MCG_TES_P:1;\r | |
| 288 | UINT32 Reserved1:4;\r | |
| 289 | ///\r | |
| 290 | /// [Bits 23:16] MCG_EXT_CNT.\r | |
| 291 | ///\r | |
| 292 | UINT32 MCG_EXT_CNT:8;\r | |
| 293 | ///\r | |
| 294 | /// [Bit 24] MCG_SER_P.\r | |
| 295 | ///\r | |
| 296 | UINT32 MCG_SER_P:1;\r | |
| 297 | ///\r | |
| 298 | /// [Bit 25] MCG_EM_P.\r | |
| 299 | ///\r | |
| 300 | UINT32 MCG_EM_P:1;\r | |
| 301 | ///\r | |
| 302 | /// [Bit 26] MCG_ELOG_P.\r | |
| 303 | ///\r | |
| 304 | UINT32 MCG_ELOG_P:1;\r | |
| 305 | UINT32 Reserved2:5;\r | |
| 306 | UINT32 Reserved3:32;\r | |
| 307 | } Bits;\r | |
| 308 | ///\r | |
| 309 | /// All bit fields as a 32-bit value\r | |
| 310 | ///\r | |
| 311 | UINT32 Uint32;\r | |
| 312 | ///\r | |
| 313 | /// All bit fields as a 64-bit value\r | |
| 314 | ///\r | |
| 315 | UINT64 Uint64;\r | |
| 316 | } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;\r | |
| 317 | \r | |
| 318 | \r | |
| 319 | /**\r | |
| 320 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r | |
| 321 | Enhancement. Accessible only while in SMM.\r | |
| 322 | \r | |
| 323 | @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)\r | |
| 324 | @param EAX Lower 32-bits of MSR value.\r | |
| 325 | Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r | |
| 326 | @param EDX Upper 32-bits of MSR value.\r | |
| 327 | Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r | |
| 328 | \r | |
| 329 | <b>Example usage</b>\r | |
| 330 | @code\r | |
| 331 | MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;\r | |
| 332 | \r | |
| 333 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);\r | |
| 334 | AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);\r | |
| 335 | @endcode\r | |
| a73ab083 | 336 | @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r |
| c67b579c MK |
337 | **/\r |
| 338 | #define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r | |
| 339 | \r | |
| 340 | /**\r | |
| 341 | MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP\r | |
| 342 | **/\r | |
| 343 | typedef union {\r | |
| 344 | ///\r | |
| 345 | /// Individual bit fields\r | |
| 346 | ///\r | |
| 347 | struct {\r | |
| 348 | UINT32 Reserved1:32;\r | |
| 349 | UINT32 Reserved2:26;\r | |
| 350 | ///\r | |
| 351 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
| 352 | /// SMM code access restriction is supported and a host-space interface\r | |
| 353 | /// available to SMM handler.\r | |
| 354 | ///\r | |
| 355 | UINT32 SMM_Code_Access_Chk:1;\r | |
| 356 | ///\r | |
| 357 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
| 358 | /// SMM long flow indicator is supported and a host-space interface\r | |
| 359 | /// available to SMM handler.\r | |
| 360 | ///\r | |
| 361 | UINT32 Long_Flow_Indication:1;\r | |
| 362 | UINT32 Reserved3:4;\r | |
| 363 | } Bits;\r | |
| 364 | ///\r | |
| 365 | /// All bit fields as a 64-bit value\r | |
| 366 | ///\r | |
| 367 | UINT64 Uint64;\r | |
| 368 | } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;\r | |
| 369 | \r | |
| 370 | \r | |
| 371 | /**\r | |
| 372 | Package. MC Bank Error Configuration (R/W).\r | |
| 373 | \r | |
| 374 | @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)\r | |
| 375 | @param EAX Lower 32-bits of MSR value.\r | |
| 376 | Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r | |
| 377 | @param EDX Upper 32-bits of MSR value.\r | |
| 378 | Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r | |
| 379 | \r | |
| 380 | <b>Example usage</b>\r | |
| 381 | @code\r | |
| 382 | MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;\r | |
| 383 | \r | |
| 384 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);\r | |
| 385 | AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);\r | |
| 386 | @endcode\r | |
| a73ab083 | 387 | @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r |
| c67b579c MK |
388 | **/\r |
| 389 | #define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r | |
| 390 | \r | |
| 391 | /**\r | |
| 392 | MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL\r | |
| 393 | **/\r | |
| 394 | typedef union {\r | |
| 395 | ///\r | |
| 396 | /// Individual bit fields\r | |
| 397 | ///\r | |
| 398 | struct {\r | |
| 399 | UINT32 Reserved1:1;\r | |
| 400 | ///\r | |
| 401 | /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r | |
| 402 | /// to log additional info in bits 36:32.\r | |
| 403 | ///\r | |
| 404 | UINT32 MemErrorLogEnable:1;\r | |
| 405 | UINT32 Reserved2:30;\r | |
| 406 | UINT32 Reserved3:32;\r | |
| 407 | } Bits;\r | |
| 408 | ///\r | |
| 409 | /// All bit fields as a 32-bit value\r | |
| 410 | ///\r | |
| 411 | UINT32 Uint32;\r | |
| 412 | ///\r | |
| 413 | /// All bit fields as a 64-bit value\r | |
| 414 | ///\r | |
| 415 | UINT64 Uint64;\r | |
| 416 | } MSR_HASWELL_E_ERROR_CONTROL_REGISTER;\r | |
| 417 | \r | |
| 418 | \r | |
| 419 | /**\r | |
| 420 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 421 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 422 | \r | |
| 423 | @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 424 | @param EAX Lower 32-bits of MSR value.\r | |
| 425 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 426 | @param EDX Upper 32-bits of MSR value.\r | |
| 427 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 428 | \r | |
| 429 | <b>Example usage</b>\r | |
| 430 | @code\r | |
| 431 | MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
| 432 | \r | |
| 433 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);\r | |
| 434 | @endcode\r | |
| a73ab083 | 435 | @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
| c67b579c MK |
436 | **/\r |
| 437 | #define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r | |
| 438 | \r | |
| 439 | /**\r | |
| 440 | MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT\r | |
| 441 | **/\r | |
| 442 | typedef union {\r | |
| 443 | ///\r | |
| 444 | /// Individual bit fields\r | |
| 445 | ///\r | |
| 446 | struct {\r | |
| 447 | ///\r | |
| 448 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
| 449 | /// limit of 1 core active.\r | |
| 450 | ///\r | |
| 451 | UINT32 Maximum1C:8;\r | |
| 452 | ///\r | |
| 453 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
| 454 | /// limit of 2 core active.\r | |
| 455 | ///\r | |
| 456 | UINT32 Maximum2C:8;\r | |
| 457 | ///\r | |
| 458 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
| 459 | /// limit of 3 core active.\r | |
| 460 | ///\r | |
| 461 | UINT32 Maximum3C:8;\r | |
| 462 | ///\r | |
| 463 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
| 464 | /// limit of 4 core active.\r | |
| 465 | ///\r | |
| 466 | UINT32 Maximum4C:8;\r | |
| 467 | ///\r | |
| 468 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r | |
| 469 | /// limit of 5 core active.\r | |
| 470 | ///\r | |
| 471 | UINT32 Maximum5C:8;\r | |
| 472 | ///\r | |
| 473 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r | |
| 474 | /// limit of 6 core active.\r | |
| 475 | ///\r | |
| 476 | UINT32 Maximum6C:8;\r | |
| 477 | ///\r | |
| 478 | /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r | |
| 479 | /// limit of 7 core active.\r | |
| 480 | ///\r | |
| 481 | UINT32 Maximum7C:8;\r | |
| 482 | ///\r | |
| 483 | /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r | |
| 484 | /// limit of 8 core active.\r | |
| 485 | ///\r | |
| 486 | UINT32 Maximum8C:8;\r | |
| 487 | } Bits;\r | |
| 488 | ///\r | |
| 489 | /// All bit fields as a 64-bit value\r | |
| 490 | ///\r | |
| 491 | UINT64 Uint64;\r | |
| 492 | } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;\r | |
| 493 | \r | |
| 494 | \r | |
| 495 | /**\r | |
| 496 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 497 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 498 | \r | |
| 499 | @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)\r | |
| 500 | @param EAX Lower 32-bits of MSR value.\r | |
| 501 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r | |
| 502 | @param EDX Upper 32-bits of MSR value.\r | |
| 503 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r | |
| 504 | \r | |
| 505 | <b>Example usage</b>\r | |
| 506 | @code\r | |
| 507 | MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;\r | |
| 508 | \r | |
| 509 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);\r | |
| 510 | @endcode\r | |
| a73ab083 | 511 | @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r |
| c67b579c MK |
512 | **/\r |
| 513 | #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r | |
| 514 | \r | |
| 515 | /**\r | |
| 516 | MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1\r | |
| 517 | **/\r | |
| 518 | typedef union {\r | |
| 519 | ///\r | |
| 520 | /// Individual bit fields\r | |
| 521 | ///\r | |
| 522 | struct {\r | |
| 523 | ///\r | |
| 524 | /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r | |
| 525 | /// limit of 9 core active.\r | |
| 526 | ///\r | |
| 527 | UINT32 Maximum9C:8;\r | |
| 528 | ///\r | |
| 529 | /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r | |
| 530 | /// limit of 10 core active.\r | |
| 531 | ///\r | |
| 532 | UINT32 Maximum10C:8;\r | |
| 533 | ///\r | |
| 534 | /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r | |
| 535 | /// limit of 11 core active.\r | |
| 536 | ///\r | |
| 537 | UINT32 Maximum11C:8;\r | |
| 538 | ///\r | |
| 539 | /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r | |
| 540 | /// limit of 12 core active.\r | |
| 541 | ///\r | |
| 542 | UINT32 Maximum12C:8;\r | |
| 543 | ///\r | |
| 544 | /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r | |
| 545 | /// limit of 13 core active.\r | |
| 546 | ///\r | |
| 547 | UINT32 Maximum13C:8;\r | |
| 548 | ///\r | |
| 549 | /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r | |
| 550 | /// limit of 14 core active.\r | |
| 551 | ///\r | |
| 552 | UINT32 Maximum14C:8;\r | |
| 553 | ///\r | |
| 554 | /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r | |
| 555 | /// limit of 15 core active.\r | |
| 556 | ///\r | |
| 557 | UINT32 Maximum15C:8;\r | |
| 558 | ///\r | |
| 559 | /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio\r | |
| 560 | /// limit of 16 core active.\r | |
| 561 | ///\r | |
| 562 | UINT32 Maximum16C:8;\r | |
| 563 | } Bits;\r | |
| 564 | ///\r | |
| 565 | /// All bit fields as a 64-bit value\r | |
| 566 | ///\r | |
| 567 | UINT64 Uint64;\r | |
| 568 | } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;\r | |
| 569 | \r | |
| 570 | \r | |
| 571 | /**\r | |
| 572 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 573 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 574 | \r | |
| 575 | @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)\r | |
| 576 | @param EAX Lower 32-bits of MSR value.\r | |
| 577 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r | |
| 578 | @param EDX Upper 32-bits of MSR value.\r | |
| 579 | Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r | |
| 580 | \r | |
| 581 | <b>Example usage</b>\r | |
| 582 | @code\r | |
| 583 | MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;\r | |
| 584 | \r | |
| 585 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);\r | |
| 586 | @endcode\r | |
| a73ab083 | 587 | @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.\r |
| c67b579c MK |
588 | **/\r |
| 589 | #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r | |
| 590 | \r | |
| 591 | /**\r | |
| 592 | MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2\r | |
| 593 | **/\r | |
| 594 | typedef union {\r | |
| 595 | ///\r | |
| 596 | /// Individual bit fields\r | |
| 597 | ///\r | |
| 598 | struct {\r | |
| 599 | ///\r | |
| 600 | /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio\r | |
| 601 | /// limit of 17 core active.\r | |
| 602 | ///\r | |
| 603 | UINT32 Maximum17C:8;\r | |
| 604 | ///\r | |
| 605 | /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio\r | |
| 606 | /// limit of 18 core active.\r | |
| 607 | ///\r | |
| 608 | UINT32 Maximum18C:8;\r | |
| 609 | UINT32 Reserved1:16;\r | |
| 610 | UINT32 Reserved2:31;\r | |
| 611 | ///\r | |
| 612 | /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r | |
| 613 | /// the processor uses override configuration specified in\r | |
| 614 | /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and\r | |
| 615 | /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set\r | |
| 616 | /// configuration (Default).\r | |
| 617 | ///\r | |
| 618 | UINT32 TurboRatioLimitConfigurationSemaphore:1;\r | |
| 619 | } Bits;\r | |
| 620 | ///\r | |
| 621 | /// All bit fields as a 64-bit value\r | |
| 622 | ///\r | |
| 623 | UINT64 Uint64;\r | |
| 624 | } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r | |
| 625 | \r | |
| 626 | \r | |
| c67b579c MK |
627 | /**\r |
| 628 | Package. Unit Multipliers used in RAPL Interfaces (R/O).\r | |
| 629 | \r | |
| 630 | @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)\r | |
| 631 | @param EAX Lower 32-bits of MSR value.\r | |
| 632 | Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r | |
| 633 | @param EDX Upper 32-bits of MSR value.\r | |
| 634 | Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r | |
| 635 | \r | |
| 636 | <b>Example usage</b>\r | |
| 637 | @code\r | |
| 638 | MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;\r | |
| 639 | \r | |
| 640 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);\r | |
| 641 | @endcode\r | |
| a73ab083 | 642 | @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
| c67b579c MK |
643 | **/\r |
| 644 | #define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r | |
| 645 | \r | |
| 646 | /**\r | |
| 647 | MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT\r | |
| 648 | **/\r | |
| 649 | typedef union {\r | |
| 650 | ///\r | |
| 651 | /// Individual bit fields\r | |
| 652 | ///\r | |
| 653 | struct {\r | |
| 654 | ///\r | |
| 655 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r | |
| 656 | ///\r | |
| 657 | UINT32 PowerUnits:4;\r | |
| 658 | UINT32 Reserved1:4;\r | |
| 659 | ///\r | |
| 660 | /// [Bits 12:8] Package. Energy Status Units Energy related information\r | |
| 661 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r | |
| 662 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r | |
| 663 | /// micro-joules).\r | |
| 664 | ///\r | |
| 665 | UINT32 EnergyStatusUnits:5;\r | |
| 666 | UINT32 Reserved2:3;\r | |
| 667 | ///\r | |
| 668 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r | |
| 669 | /// Interfaces.".\r | |
| 670 | ///\r | |
| 671 | UINT32 TimeUnits:4;\r | |
| 672 | UINT32 Reserved3:12;\r | |
| 673 | UINT32 Reserved4:32;\r | |
| 674 | } Bits;\r | |
| 675 | ///\r | |
| 676 | /// All bit fields as a 32-bit value\r | |
| 677 | ///\r | |
| 678 | UINT32 Uint32;\r | |
| 679 | ///\r | |
| 680 | /// All bit fields as a 64-bit value\r | |
| 681 | ///\r | |
| 682 | UINT64 Uint64;\r | |
| 683 | } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;\r | |
| 684 | \r | |
| 685 | \r | |
| 686 | /**\r | |
| 687 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
| 688 | Domain.".\r | |
| 689 | \r | |
| 690 | @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)\r | |
| 691 | @param EAX Lower 32-bits of MSR value.\r | |
| 692 | @param EDX Upper 32-bits of MSR value.\r | |
| 693 | \r | |
| 694 | <b>Example usage</b>\r | |
| 695 | @code\r | |
| 696 | UINT64 Msr;\r | |
| 697 | \r | |
| 698 | Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);\r | |
| 699 | AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);\r | |
| 700 | @endcode\r | |
| a73ab083 | 701 | @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r |
| c67b579c MK |
702 | **/\r |
| 703 | #define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r | |
| 704 | \r | |
| 705 | \r | |
| 706 | /**\r | |
| 0f16be6d | 707 | Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.\r |
| c67b579c MK |
708 | \r |
| 709 | @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 710 | @param EAX Lower 32-bits of MSR value.\r | |
| 0f16be6d | 711 | Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r |
| c67b579c | 712 | @param EDX Upper 32-bits of MSR value.\r |
| 0f16be6d | 713 | Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.\r |
| c67b579c MK |
714 | \r |
| 715 | <b>Example usage</b>\r | |
| 716 | @code\r | |
| 0f16be6d | 717 | MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;\r |
| c67b579c | 718 | \r |
| 0f16be6d | 719 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r |
| c67b579c | 720 | @endcode\r |
| a73ab083 | 721 | @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
| c67b579c MK |
722 | **/\r |
| 723 | #define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r | |
| 724 | \r | |
| 0f16be6d HW |
725 | /**\r |
| 726 | MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS\r | |
| 727 | **/\r | |
| 728 | typedef union {\r | |
| 729 | ///\r | |
| 730 | /// Individual bit fields\r | |
| 731 | ///\r | |
| 732 | struct {\r | |
| 733 | ///\r | |
| 734 | /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r | |
| 735 | /// to enable DRAM RAPL mode 0 (Direct VR).\r | |
| 736 | ///\r | |
| 737 | UINT32 Energy:32;\r | |
| 738 | UINT32 Reserved:32;\r | |
| 739 | } Bits;\r | |
| 740 | ///\r | |
| 741 | /// All bit fields as a 32-bit value\r | |
| 742 | ///\r | |
| 743 | UINT32 Uint32;\r | |
| 744 | ///\r | |
| 745 | /// All bit fields as a 64-bit value\r | |
| 746 | ///\r | |
| 747 | UINT64 Uint64;\r | |
| 748 | } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;\r | |
| 749 | \r | |
| c67b579c MK |
750 | \r |
| 751 | /**\r | |
| 752 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 753 | RAPL Domain.".\r | |
| 754 | \r | |
| 755 | @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)\r | |
| 756 | @param EAX Lower 32-bits of MSR value.\r | |
| 757 | @param EDX Upper 32-bits of MSR value.\r | |
| 758 | \r | |
| 759 | <b>Example usage</b>\r | |
| 760 | @code\r | |
| 761 | UINT64 Msr;\r | |
| 762 | \r | |
| 763 | Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);\r | |
| 764 | @endcode\r | |
| a73ab083 | 765 | @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
| c67b579c MK |
766 | **/\r |
| 767 | #define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r | |
| 768 | \r | |
| 769 | \r | |
| 770 | /**\r | |
| 771 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 772 | \r | |
| 773 | @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)\r | |
| 774 | @param EAX Lower 32-bits of MSR value.\r | |
| 775 | @param EDX Upper 32-bits of MSR value.\r | |
| 776 | \r | |
| 777 | <b>Example usage</b>\r | |
| 778 | @code\r | |
| 779 | UINT64 Msr;\r | |
| 780 | \r | |
| 781 | Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);\r | |
| 782 | AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);\r | |
| 783 | @endcode\r | |
| a73ab083 | 784 | @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r |
| c67b579c MK |
785 | **/\r |
| 786 | #define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r | |
| 787 | \r | |
| 788 | \r | |
| 0f16be6d HW |
789 | /**\r |
| 790 | Package. Configuration of PCIE PLL Relative to BCLK(R/W).\r | |
| 791 | \r | |
| 792 | @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)\r | |
| 793 | @param EAX Lower 32-bits of MSR value.\r | |
| 794 | Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r | |
| 795 | @param EDX Upper 32-bits of MSR value.\r | |
| 796 | Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.\r | |
| 797 | \r | |
| 798 | <b>Example usage</b>\r | |
| 799 | @code\r | |
| 800 | MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;\r | |
| 801 | \r | |
| 802 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);\r | |
| 803 | AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);\r | |
| 804 | @endcode\r | |
| 805 | @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.\r | |
| 806 | **/\r | |
| 807 | #define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E\r | |
| 808 | \r | |
| 809 | /**\r | |
| 810 | MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO\r | |
| 811 | **/\r | |
| 812 | typedef union {\r | |
| 813 | ///\r | |
| 814 | /// Individual bit fields\r | |
| 815 | ///\r | |
| 816 | struct {\r | |
| 817 | ///\r | |
| 818 | /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz\r | |
| 819 | /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use\r | |
| 820 | /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz\r | |
| 821 | /// operation.\r | |
| 822 | ///\r | |
| 823 | UINT32 PCIERatio:2;\r | |
| 824 | ///\r | |
| 825 | /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of\r | |
| 826 | /// PCIE Ratio.\r | |
| 827 | ///\r | |
| 828 | UINT32 LPLLSelect:1;\r | |
| 829 | ///\r | |
| 830 | /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out\r | |
| 831 | /// before re-locking Gen2/Gen3 PLLs.\r | |
| 832 | ///\r | |
| 833 | UINT32 LONGRESET:1;\r | |
| 834 | UINT32 Reserved1:28;\r | |
| 835 | UINT32 Reserved2:32;\r | |
| 836 | } Bits;\r | |
| 837 | ///\r | |
| 838 | /// All bit fields as a 32-bit value\r | |
| 839 | ///\r | |
| 840 | UINT32 Uint32;\r | |
| 841 | ///\r | |
| 842 | /// All bit fields as a 64-bit value\r | |
| 843 | ///\r | |
| 844 | UINT64 Uint64;\r | |
| 845 | } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;\r | |
| 846 | \r | |
| 847 | \r | |
| 848 | /**\r | |
| 849 | Package. Reserved (R/O) Reads return 0.\r | |
| 850 | \r | |
| 851 | @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)\r | |
| 852 | @param EAX Lower 32-bits of MSR value.\r | |
| 853 | @param EDX Upper 32-bits of MSR value.\r | |
| 854 | \r | |
| 855 | <b>Example usage</b>\r | |
| 856 | @code\r | |
| 857 | UINT64 Msr;\r | |
| 858 | \r | |
| 859 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);\r | |
| 860 | @endcode\r | |
| 861 | @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
| 862 | **/\r | |
| 863 | #define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639\r | |
| 864 | \r | |
| 865 | \r | |
| c67b579c MK |
866 | /**\r |
| 867 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
| 868 | refers to processor core frequency).\r | |
| 869 | \r | |
| 870 | @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)\r | |
| 871 | @param EAX Lower 32-bits of MSR value.\r | |
| 872 | Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 873 | @param EDX Upper 32-bits of MSR value.\r | |
| 874 | Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 875 | \r | |
| 876 | <b>Example usage</b>\r | |
| 877 | @code\r | |
| 878 | MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 879 | \r | |
| 880 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);\r | |
| 881 | AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 882 | @endcode\r | |
| a73ab083 | 883 | @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r |
| c67b579c MK |
884 | **/\r |
| 885 | #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r | |
| 886 | \r | |
| 887 | /**\r | |
| 888 | MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS\r | |
| 889 | **/\r | |
| 890 | typedef union {\r | |
| 891 | ///\r | |
| 892 | /// Individual bit fields\r | |
| 893 | ///\r | |
| 894 | struct {\r | |
| 895 | ///\r | |
| 896 | /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r | |
| 897 | /// reduced below the operating system request due to assertion of\r | |
| 898 | /// external PROCHOT.\r | |
| 899 | ///\r | |
| 900 | UINT32 PROCHOT_Status:1;\r | |
| 901 | ///\r | |
| 902 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 903 | /// operating system request due to a thermal event.\r | |
| 904 | ///\r | |
| 905 | UINT32 ThermalStatus:1;\r | |
| 906 | ///\r | |
| 907 | /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r | |
| 908 | /// reduced below the operating system request due to PBM limit.\r | |
| 909 | ///\r | |
| 910 | UINT32 PowerBudgetManagementStatus:1;\r | |
| 911 | ///\r | |
| 912 | /// [Bit 3] Platform Configuration Services Status (R0) When set,\r | |
| 913 | /// frequency is reduced below the operating system request due to PCS\r | |
| 914 | /// limit.\r | |
| 915 | ///\r | |
| 916 | UINT32 PlatformConfigurationServicesStatus:1;\r | |
| 917 | UINT32 Reserved1:1;\r | |
| 918 | ///\r | |
| 919 | /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r | |
| 920 | /// When set, frequency is reduced below the operating system request\r | |
| 921 | /// because the processor has detected that utilization is low.\r | |
| 922 | ///\r | |
| 923 | UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r | |
| 924 | ///\r | |
| 925 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 926 | /// below the operating system request due to a thermal alert from the\r | |
| 927 | /// Voltage Regulator.\r | |
| 928 | ///\r | |
| 929 | UINT32 VRThermAlertStatus:1;\r | |
| 930 | UINT32 Reserved2:1;\r | |
| 931 | ///\r | |
| 932 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r | |
| 933 | /// reduced below the operating system request due to electrical design\r | |
| 934 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 935 | ///\r | |
| 936 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 937 | UINT32 Reserved3:1;\r | |
| 938 | ///\r | |
| 939 | /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r | |
| 940 | /// below the operating system request due to Multi-Core Turbo limits.\r | |
| 941 | ///\r | |
| 942 | UINT32 MultiCoreTurboStatus:1;\r | |
| 943 | UINT32 Reserved4:2;\r | |
| 944 | ///\r | |
| 945 | /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r | |
| 946 | /// below max non-turbo P1.\r | |
| 947 | ///\r | |
| 948 | UINT32 FrequencyP1Status:1;\r | |
| 949 | ///\r | |
| 950 | /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r | |
| 951 | /// set, frequency is reduced below max n-core turbo frequency.\r | |
| 952 | ///\r | |
| 953 | UINT32 TurboFrequencyLimitingStatus:1;\r | |
| 954 | ///\r | |
| 955 | /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r | |
| 956 | /// reduced below the operating system request.\r | |
| 957 | ///\r | |
| 958 | UINT32 FrequencyLimitingStatus:1;\r | |
| 959 | ///\r | |
| 960 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 961 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 962 | /// remain set until cleared by software writing 0.\r | |
| 963 | ///\r | |
| 964 | UINT32 PROCHOT_Log:1;\r | |
| 965 | ///\r | |
| 966 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 967 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 968 | /// remain set until cleared by software writing 0.\r | |
| 969 | ///\r | |
| 970 | UINT32 ThermalLog:1;\r | |
| 971 | ///\r | |
| 972 | /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r | |
| 973 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 974 | /// bit will remain set until cleared by software writing 0.\r | |
| 975 | ///\r | |
| 976 | UINT32 PowerBudgetManagementLog:1;\r | |
| 977 | ///\r | |
| 978 | /// [Bit 19] Platform Configuration Services Log When set, indicates that\r | |
| 979 | /// the PCS Status bit has asserted since the log bit was last cleared.\r | |
| 980 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 981 | ///\r | |
| 982 | UINT32 PlatformConfigurationServicesLog:1;\r | |
| 983 | UINT32 Reserved5:1;\r | |
| 984 | ///\r | |
| 985 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r | |
| 986 | /// indicates that the AUBFC Status bit has asserted since the log bit was\r | |
| 987 | /// last cleared. This log bit will remain set until cleared by software\r | |
| 988 | /// writing 0.\r | |
| 989 | ///\r | |
| 990 | UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r | |
| 991 | ///\r | |
| 992 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 993 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 994 | /// log bit will remain set until cleared by software writing 0.\r | |
| 995 | ///\r | |
| 996 | UINT32 VRThermAlertLog:1;\r | |
| 997 | UINT32 Reserved6:1;\r | |
| 998 | ///\r | |
| 999 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r | |
| 1000 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1001 | /// bit will remain set until cleared by software writing 0.\r | |
| 1002 | ///\r | |
| 1003 | UINT32 ElectricalDesignPointLog:1;\r | |
| 1004 | UINT32 Reserved7:1;\r | |
| 1005 | ///\r | |
| 1006 | /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r | |
| 1007 | /// Turbo Status bit has asserted since the log bit was last cleared. This\r | |
| 1008 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1009 | ///\r | |
| 1010 | UINT32 MultiCoreTurboLog:1;\r | |
| 1011 | UINT32 Reserved8:2;\r | |
| 1012 | ///\r | |
| 1013 | /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r | |
| 1014 | /// Frequency P1 Status bit has asserted since the log bit was last\r | |
| 1015 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1016 | /// writing 0.\r | |
| 1017 | ///\r | |
| 1018 | UINT32 CoreFrequencyP1Log:1;\r | |
| 1019 | ///\r | |
| 1020 | /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r | |
| 1021 | /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r | |
| 1022 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1023 | /// remain set until cleared by software writing 0.\r | |
| 1024 | ///\r | |
| 1025 | UINT32 TurboFrequencyLimitingLog:1;\r | |
| 1026 | ///\r | |
| 1027 | /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r | |
| 1028 | /// Frequency Limiting Status bit has asserted since the log bit was last\r | |
| 1029 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1030 | /// writing 0.\r | |
| 1031 | ///\r | |
| 1032 | UINT32 CoreFrequencyLimitingLog:1;\r | |
| 1033 | UINT32 Reserved9:32;\r | |
| 1034 | } Bits;\r | |
| 1035 | ///\r | |
| 1036 | /// All bit fields as a 32-bit value\r | |
| 1037 | ///\r | |
| 1038 | UINT32 Uint32;\r | |
| 1039 | ///\r | |
| 1040 | /// All bit fields as a 64-bit value\r | |
| 1041 | ///\r | |
| 1042 | UINT64 Uint64;\r | |
| 1043 | } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;\r | |
| 1044 | \r | |
| 1045 | \r | |
| 1046 | /**\r | |
| 1047 | THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r | |
| 0f16be6d | 1048 | ECX=0):EBX.RDT-M[bit 12] = 1.\r |
| c67b579c MK |
1049 | \r |
| 1050 | @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)\r | |
| 1051 | @param EAX Lower 32-bits of MSR value.\r | |
| 1052 | Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r | |
| 1053 | @param EDX Upper 32-bits of MSR value.\r | |
| 1054 | Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r | |
| 1055 | \r | |
| 1056 | <b>Example usage</b>\r | |
| 1057 | @code\r | |
| 1058 | MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;\r | |
| 1059 | \r | |
| 1060 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);\r | |
| 1061 | AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);\r | |
| 1062 | @endcode\r | |
| a73ab083 | 1063 | @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r |
| c67b579c MK |
1064 | **/\r |
| 1065 | #define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r | |
| 1066 | \r | |
| 1067 | /**\r | |
| 1068 | MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL\r | |
| 1069 | **/\r | |
| 1070 | typedef union {\r | |
| 1071 | ///\r | |
| 1072 | /// Individual bit fields\r | |
| 1073 | ///\r | |
| 1074 | struct {\r | |
| 1075 | ///\r | |
| 1076 | /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3\r | |
| 1077 | /// occupancy monitoring all other encoding reserved..\r | |
| 1078 | ///\r | |
| 1079 | UINT32 EventID:8;\r | |
| 1080 | UINT32 Reserved1:24;\r | |
| 1081 | ///\r | |
| 1082 | /// [Bits 41:32] RMID (RW).\r | |
| 1083 | ///\r | |
| 1084 | UINT32 RMID:10;\r | |
| 1085 | UINT32 Reserved2:22;\r | |
| 1086 | } Bits;\r | |
| 1087 | ///\r | |
| 1088 | /// All bit fields as a 64-bit value\r | |
| 1089 | ///\r | |
| 1090 | UINT64 Uint64;\r | |
| 1091 | } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;\r | |
| 1092 | \r | |
| 1093 | \r | |
| 1094 | /**\r | |
| 1095 | THREAD. Resource Association Register (R/W)..\r | |
| 1096 | \r | |
| 1097 | @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)\r | |
| 1098 | @param EAX Lower 32-bits of MSR value.\r | |
| 1099 | Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r | |
| 1100 | @param EDX Upper 32-bits of MSR value.\r | |
| 1101 | Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r | |
| 1102 | \r | |
| 1103 | <b>Example usage</b>\r | |
| 1104 | @code\r | |
| 1105 | MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;\r | |
| 1106 | \r | |
| 1107 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);\r | |
| 1108 | AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);\r | |
| 1109 | @endcode\r | |
| a73ab083 | 1110 | @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r |
| c67b579c MK |
1111 | **/\r |
| 1112 | #define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r | |
| 1113 | \r | |
| 1114 | /**\r | |
| 1115 | MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC\r | |
| 1116 | **/\r | |
| 1117 | typedef union {\r | |
| 1118 | ///\r | |
| 1119 | /// Individual bit fields\r | |
| 1120 | ///\r | |
| 1121 | struct {\r | |
| 1122 | ///\r | |
| 1123 | /// [Bits 9:0] RMID.\r | |
| 1124 | ///\r | |
| 1125 | UINT32 RMID:10;\r | |
| 1126 | UINT32 Reserved1:22;\r | |
| 1127 | UINT32 Reserved2:32;\r | |
| 1128 | } Bits;\r | |
| 1129 | ///\r | |
| 1130 | /// All bit fields as a 32-bit value\r | |
| 1131 | ///\r | |
| 1132 | UINT32 Uint32;\r | |
| 1133 | ///\r | |
| 1134 | /// All bit fields as a 64-bit value\r | |
| 1135 | ///\r | |
| 1136 | UINT64 Uint64;\r | |
| 1137 | } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;\r | |
| 1138 | \r | |
| 1139 | \r | |
| 1140 | /**\r | |
| 1141 | Package. Uncore perfmon per-socket global control.\r | |
| 1142 | \r | |
| 1143 | @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)\r | |
| 1144 | @param EAX Lower 32-bits of MSR value.\r | |
| 1145 | @param EDX Upper 32-bits of MSR value.\r | |
| 1146 | \r | |
| 1147 | <b>Example usage</b>\r | |
| 1148 | @code\r | |
| 1149 | UINT64 Msr;\r | |
| 1150 | \r | |
| 1151 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);\r | |
| 1152 | AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);\r | |
| 1153 | @endcode\r | |
| a73ab083 | 1154 | @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r |
| c67b579c MK |
1155 | **/\r |
| 1156 | #define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r | |
| 1157 | \r | |
| 1158 | \r | |
| 1159 | /**\r | |
| 1160 | Package. Uncore perfmon per-socket global status.\r | |
| 1161 | \r | |
| 1162 | @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)\r | |
| 1163 | @param EAX Lower 32-bits of MSR value.\r | |
| 1164 | @param EDX Upper 32-bits of MSR value.\r | |
| 1165 | \r | |
| 1166 | <b>Example usage</b>\r | |
| 1167 | @code\r | |
| 1168 | UINT64 Msr;\r | |
| 1169 | \r | |
| 1170 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);\r | |
| 1171 | AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);\r | |
| 1172 | @endcode\r | |
| a73ab083 | 1173 | @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r |
| c67b579c MK |
1174 | **/\r |
| 1175 | #define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r | |
| 1176 | \r | |
| 1177 | \r | |
| 1178 | /**\r | |
| 1179 | Package. Uncore perfmon per-socket global configuration.\r | |
| 1180 | \r | |
| 1181 | @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)\r | |
| 1182 | @param EAX Lower 32-bits of MSR value.\r | |
| 1183 | @param EDX Upper 32-bits of MSR value.\r | |
| 1184 | \r | |
| 1185 | <b>Example usage</b>\r | |
| 1186 | @code\r | |
| 1187 | UINT64 Msr;\r | |
| 1188 | \r | |
| 1189 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);\r | |
| 1190 | AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);\r | |
| 1191 | @endcode\r | |
| a73ab083 | 1192 | @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r |
| c67b579c MK |
1193 | **/\r |
| 1194 | #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r | |
| 1195 | \r | |
| 1196 | \r | |
| 1197 | /**\r | |
| 1198 | Package. Uncore U-box UCLK fixed counter control.\r | |
| 1199 | \r | |
| 1200 | @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)\r | |
| 1201 | @param EAX Lower 32-bits of MSR value.\r | |
| 1202 | @param EDX Upper 32-bits of MSR value.\r | |
| 1203 | \r | |
| 1204 | <b>Example usage</b>\r | |
| 1205 | @code\r | |
| 1206 | UINT64 Msr;\r | |
| 1207 | \r | |
| 1208 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);\r | |
| 1209 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);\r | |
| 1210 | @endcode\r | |
| a73ab083 | 1211 | @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r |
| c67b579c MK |
1212 | **/\r |
| 1213 | #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r | |
| 1214 | \r | |
| 1215 | \r | |
| 1216 | /**\r | |
| 1217 | Package. Uncore U-box UCLK fixed counter.\r | |
| 1218 | \r | |
| 1219 | @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)\r | |
| 1220 | @param EAX Lower 32-bits of MSR value.\r | |
| 1221 | @param EDX Upper 32-bits of MSR value.\r | |
| 1222 | \r | |
| 1223 | <b>Example usage</b>\r | |
| 1224 | @code\r | |
| 1225 | UINT64 Msr;\r | |
| 1226 | \r | |
| 1227 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);\r | |
| 1228 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);\r | |
| 1229 | @endcode\r | |
| a73ab083 | 1230 | @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r |
| c67b579c MK |
1231 | **/\r |
| 1232 | #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r | |
| 1233 | \r | |
| 1234 | \r | |
| 1235 | /**\r | |
| 1236 | Package. Uncore U-box perfmon event select for U-box counter 0.\r | |
| 1237 | \r | |
| 1238 | @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)\r | |
| 1239 | @param EAX Lower 32-bits of MSR value.\r | |
| 1240 | @param EDX Upper 32-bits of MSR value.\r | |
| 1241 | \r | |
| 1242 | <b>Example usage</b>\r | |
| 1243 | @code\r | |
| 1244 | UINT64 Msr;\r | |
| 1245 | \r | |
| 1246 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);\r | |
| 1247 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);\r | |
| 1248 | @endcode\r | |
| a73ab083 | 1249 | @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
1250 | **/\r |
| 1251 | #define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r | |
| 1252 | \r | |
| 1253 | \r | |
| 1254 | /**\r | |
| 1255 | Package. Uncore U-box perfmon event select for U-box counter 1.\r | |
| 1256 | \r | |
| 1257 | @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)\r | |
| 1258 | @param EAX Lower 32-bits of MSR value.\r | |
| 1259 | @param EDX Upper 32-bits of MSR value.\r | |
| 1260 | \r | |
| 1261 | <b>Example usage</b>\r | |
| 1262 | @code\r | |
| 1263 | UINT64 Msr;\r | |
| 1264 | \r | |
| 1265 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);\r | |
| 1266 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);\r | |
| 1267 | @endcode\r | |
| a73ab083 | 1268 | @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
1269 | **/\r |
| 1270 | #define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r | |
| 1271 | \r | |
| 1272 | \r | |
| 1273 | /**\r | |
| 1274 | Package. Uncore U-box perfmon U-box wide status.\r | |
| 1275 | \r | |
| 1276 | @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)\r | |
| 1277 | @param EAX Lower 32-bits of MSR value.\r | |
| 1278 | @param EDX Upper 32-bits of MSR value.\r | |
| 1279 | \r | |
| 1280 | <b>Example usage</b>\r | |
| 1281 | @code\r | |
| 1282 | UINT64 Msr;\r | |
| 1283 | \r | |
| 1284 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);\r | |
| 1285 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);\r | |
| 1286 | @endcode\r | |
| a73ab083 | 1287 | @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
1288 | **/\r |
| 1289 | #define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r | |
| 1290 | \r | |
| 1291 | \r | |
| 1292 | /**\r | |
| 1293 | Package. Uncore U-box perfmon counter 0.\r | |
| 1294 | \r | |
| 1295 | @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)\r | |
| 1296 | @param EAX Lower 32-bits of MSR value.\r | |
| 1297 | @param EDX Upper 32-bits of MSR value.\r | |
| 1298 | \r | |
| 1299 | <b>Example usage</b>\r | |
| 1300 | @code\r | |
| 1301 | UINT64 Msr;\r | |
| 1302 | \r | |
| 1303 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);\r | |
| 1304 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);\r | |
| 1305 | @endcode\r | |
| a73ab083 | 1306 | @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r |
| c67b579c MK |
1307 | **/\r |
| 1308 | #define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r | |
| 1309 | \r | |
| 1310 | \r | |
| 1311 | /**\r | |
| 1312 | Package. Uncore U-box perfmon counter 1.\r | |
| 1313 | \r | |
| 1314 | @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)\r | |
| 1315 | @param EAX Lower 32-bits of MSR value.\r | |
| 1316 | @param EDX Upper 32-bits of MSR value.\r | |
| 1317 | \r | |
| 1318 | <b>Example usage</b>\r | |
| 1319 | @code\r | |
| 1320 | UINT64 Msr;\r | |
| 1321 | \r | |
| 1322 | Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);\r | |
| 1323 | AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);\r | |
| 1324 | @endcode\r | |
| a73ab083 | 1325 | @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r |
| c67b579c MK |
1326 | **/\r |
| 1327 | #define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r | |
| 1328 | \r | |
| 1329 | \r | |
| 1330 | /**\r | |
| 1331 | Package. Uncore PCU perfmon for PCU-box-wide control.\r | |
| 1332 | \r | |
| 1333 | @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)\r | |
| 1334 | @param EAX Lower 32-bits of MSR value.\r | |
| 1335 | @param EDX Upper 32-bits of MSR value.\r | |
| 1336 | \r | |
| 1337 | <b>Example usage</b>\r | |
| 1338 | @code\r | |
| 1339 | UINT64 Msr;\r | |
| 1340 | \r | |
| 1341 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);\r | |
| 1342 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);\r | |
| 1343 | @endcode\r | |
| a73ab083 | 1344 | @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
1345 | **/\r |
| 1346 | #define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r | |
| 1347 | \r | |
| 1348 | \r | |
| 1349 | /**\r | |
| 1350 | Package. Uncore PCU perfmon event select for PCU counter 0.\r | |
| 1351 | \r | |
| 1352 | @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)\r | |
| 1353 | @param EAX Lower 32-bits of MSR value.\r | |
| 1354 | @param EDX Upper 32-bits of MSR value.\r | |
| 1355 | \r | |
| 1356 | <b>Example usage</b>\r | |
| 1357 | @code\r | |
| 1358 | UINT64 Msr;\r | |
| 1359 | \r | |
| 1360 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);\r | |
| 1361 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);\r | |
| 1362 | @endcode\r | |
| a73ab083 | 1363 | @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
1364 | **/\r |
| 1365 | #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r | |
| 1366 | \r | |
| 1367 | \r | |
| 1368 | /**\r | |
| 1369 | Package. Uncore PCU perfmon event select for PCU counter 1.\r | |
| 1370 | \r | |
| 1371 | @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)\r | |
| 1372 | @param EAX Lower 32-bits of MSR value.\r | |
| 1373 | @param EDX Upper 32-bits of MSR value.\r | |
| 1374 | \r | |
| 1375 | <b>Example usage</b>\r | |
| 1376 | @code\r | |
| 1377 | UINT64 Msr;\r | |
| 1378 | \r | |
| 1379 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);\r | |
| 1380 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);\r | |
| 1381 | @endcode\r | |
| a73ab083 | 1382 | @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
1383 | **/\r |
| 1384 | #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r | |
| 1385 | \r | |
| 1386 | \r | |
| 1387 | /**\r | |
| 1388 | Package. Uncore PCU perfmon event select for PCU counter 2.\r | |
| 1389 | \r | |
| 1390 | @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)\r | |
| 1391 | @param EAX Lower 32-bits of MSR value.\r | |
| 1392 | @param EDX Upper 32-bits of MSR value.\r | |
| 1393 | \r | |
| 1394 | <b>Example usage</b>\r | |
| 1395 | @code\r | |
| 1396 | UINT64 Msr;\r | |
| 1397 | \r | |
| 1398 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);\r | |
| 1399 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);\r | |
| 1400 | @endcode\r | |
| a73ab083 | 1401 | @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
1402 | **/\r |
| 1403 | #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r | |
| 1404 | \r | |
| 1405 | \r | |
| 1406 | /**\r | |
| 1407 | Package. Uncore PCU perfmon event select for PCU counter 3.\r | |
| 1408 | \r | |
| 1409 | @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)\r | |
| 1410 | @param EAX Lower 32-bits of MSR value.\r | |
| 1411 | @param EDX Upper 32-bits of MSR value.\r | |
| 1412 | \r | |
| 1413 | <b>Example usage</b>\r | |
| 1414 | @code\r | |
| 1415 | UINT64 Msr;\r | |
| 1416 | \r | |
| 1417 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);\r | |
| 1418 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);\r | |
| 1419 | @endcode\r | |
| a73ab083 | 1420 | @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
1421 | **/\r |
| 1422 | #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r | |
| 1423 | \r | |
| 1424 | \r | |
| 1425 | /**\r | |
| 1426 | Package. Uncore PCU perfmon box-wide filter.\r | |
| 1427 | \r | |
| 1428 | @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)\r | |
| 1429 | @param EAX Lower 32-bits of MSR value.\r | |
| 1430 | @param EDX Upper 32-bits of MSR value.\r | |
| 1431 | \r | |
| 1432 | <b>Example usage</b>\r | |
| 1433 | @code\r | |
| 1434 | UINT64 Msr;\r | |
| 1435 | \r | |
| 1436 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);\r | |
| 1437 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);\r | |
| 1438 | @endcode\r | |
| a73ab083 | 1439 | @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r |
| c67b579c MK |
1440 | **/\r |
| 1441 | #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r | |
| 1442 | \r | |
| 1443 | \r | |
| 1444 | /**\r | |
| 1445 | Package. Uncore PCU perfmon box wide status.\r | |
| 1446 | \r | |
| 1447 | @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)\r | |
| 1448 | @param EAX Lower 32-bits of MSR value.\r | |
| 1449 | @param EDX Upper 32-bits of MSR value.\r | |
| 1450 | \r | |
| 1451 | <b>Example usage</b>\r | |
| 1452 | @code\r | |
| 1453 | UINT64 Msr;\r | |
| 1454 | \r | |
| 1455 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);\r | |
| 1456 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);\r | |
| 1457 | @endcode\r | |
| a73ab083 | 1458 | @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
1459 | **/\r |
| 1460 | #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r | |
| 1461 | \r | |
| 1462 | \r | |
| 1463 | /**\r | |
| 1464 | Package. Uncore PCU perfmon counter 0.\r | |
| 1465 | \r | |
| 1466 | @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)\r | |
| 1467 | @param EAX Lower 32-bits of MSR value.\r | |
| 1468 | @param EDX Upper 32-bits of MSR value.\r | |
| 1469 | \r | |
| 1470 | <b>Example usage</b>\r | |
| 1471 | @code\r | |
| 1472 | UINT64 Msr;\r | |
| 1473 | \r | |
| 1474 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);\r | |
| 1475 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);\r | |
| 1476 | @endcode\r | |
| a73ab083 | 1477 | @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r |
| c67b579c MK |
1478 | **/\r |
| 1479 | #define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r | |
| 1480 | \r | |
| 1481 | \r | |
| 1482 | /**\r | |
| 1483 | Package. Uncore PCU perfmon counter 1.\r | |
| 1484 | \r | |
| 1485 | @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)\r | |
| 1486 | @param EAX Lower 32-bits of MSR value.\r | |
| 1487 | @param EDX Upper 32-bits of MSR value.\r | |
| 1488 | \r | |
| 1489 | <b>Example usage</b>\r | |
| 1490 | @code\r | |
| 1491 | UINT64 Msr;\r | |
| 1492 | \r | |
| 1493 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);\r | |
| 1494 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);\r | |
| 1495 | @endcode\r | |
| a73ab083 | 1496 | @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r |
| c67b579c MK |
1497 | **/\r |
| 1498 | #define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r | |
| 1499 | \r | |
| 1500 | \r | |
| 1501 | /**\r | |
| 1502 | Package. Uncore PCU perfmon counter 2.\r | |
| 1503 | \r | |
| 1504 | @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)\r | |
| 1505 | @param EAX Lower 32-bits of MSR value.\r | |
| 1506 | @param EDX Upper 32-bits of MSR value.\r | |
| 1507 | \r | |
| 1508 | <b>Example usage</b>\r | |
| 1509 | @code\r | |
| 1510 | UINT64 Msr;\r | |
| 1511 | \r | |
| 1512 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);\r | |
| 1513 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);\r | |
| 1514 | @endcode\r | |
| a73ab083 | 1515 | @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r |
| c67b579c MK |
1516 | **/\r |
| 1517 | #define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r | |
| 1518 | \r | |
| 1519 | \r | |
| 1520 | /**\r | |
| 1521 | Package. Uncore PCU perfmon counter 3.\r | |
| 1522 | \r | |
| 1523 | @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)\r | |
| 1524 | @param EAX Lower 32-bits of MSR value.\r | |
| 1525 | @param EDX Upper 32-bits of MSR value.\r | |
| 1526 | \r | |
| 1527 | <b>Example usage</b>\r | |
| 1528 | @code\r | |
| 1529 | UINT64 Msr;\r | |
| 1530 | \r | |
| 1531 | Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);\r | |
| 1532 | AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);\r | |
| 1533 | @endcode\r | |
| a73ab083 | 1534 | @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r |
| c67b579c MK |
1535 | **/\r |
| 1536 | #define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r | |
| 1537 | \r | |
| 1538 | \r | |
| 1539 | /**\r | |
| 1540 | Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.\r | |
| 1541 | \r | |
| 1542 | @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)\r | |
| 1543 | @param EAX Lower 32-bits of MSR value.\r | |
| 1544 | @param EDX Upper 32-bits of MSR value.\r | |
| 1545 | \r | |
| 1546 | <b>Example usage</b>\r | |
| 1547 | @code\r | |
| 1548 | UINT64 Msr;\r | |
| 1549 | \r | |
| 1550 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);\r | |
| 1551 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);\r | |
| 1552 | @endcode\r | |
| a73ab083 | 1553 | @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
1554 | **/\r |
| 1555 | #define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r | |
| 1556 | \r | |
| 1557 | \r | |
| 1558 | /**\r | |
| 1559 | Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.\r | |
| 1560 | \r | |
| 1561 | @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)\r | |
| 1562 | @param EAX Lower 32-bits of MSR value.\r | |
| 1563 | @param EDX Upper 32-bits of MSR value.\r | |
| 1564 | \r | |
| 1565 | <b>Example usage</b>\r | |
| 1566 | @code\r | |
| 1567 | UINT64 Msr;\r | |
| 1568 | \r | |
| 1569 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);\r | |
| 1570 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);\r | |
| 1571 | @endcode\r | |
| a73ab083 | 1572 | @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
1573 | **/\r |
| 1574 | #define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r | |
| 1575 | \r | |
| 1576 | \r | |
| 1577 | /**\r | |
| 1578 | Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.\r | |
| 1579 | \r | |
| 1580 | @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)\r | |
| 1581 | @param EAX Lower 32-bits of MSR value.\r | |
| 1582 | @param EDX Upper 32-bits of MSR value.\r | |
| 1583 | \r | |
| 1584 | <b>Example usage</b>\r | |
| 1585 | @code\r | |
| 1586 | UINT64 Msr;\r | |
| 1587 | \r | |
| 1588 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);\r | |
| 1589 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);\r | |
| 1590 | @endcode\r | |
| a73ab083 | 1591 | @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
1592 | **/\r |
| 1593 | #define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r | |
| 1594 | \r | |
| 1595 | \r | |
| 1596 | /**\r | |
| 1597 | Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.\r | |
| 1598 | \r | |
| 1599 | @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)\r | |
| 1600 | @param EAX Lower 32-bits of MSR value.\r | |
| 1601 | @param EDX Upper 32-bits of MSR value.\r | |
| 1602 | \r | |
| 1603 | <b>Example usage</b>\r | |
| 1604 | @code\r | |
| 1605 | UINT64 Msr;\r | |
| 1606 | \r | |
| 1607 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);\r | |
| 1608 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);\r | |
| 1609 | @endcode\r | |
| a73ab083 | 1610 | @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
1611 | **/\r |
| 1612 | #define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r | |
| 1613 | \r | |
| 1614 | \r | |
| 1615 | /**\r | |
| 1616 | Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.\r | |
| 1617 | \r | |
| 1618 | @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)\r | |
| 1619 | @param EAX Lower 32-bits of MSR value.\r | |
| 1620 | @param EDX Upper 32-bits of MSR value.\r | |
| 1621 | \r | |
| 1622 | <b>Example usage</b>\r | |
| 1623 | @code\r | |
| 1624 | UINT64 Msr;\r | |
| 1625 | \r | |
| 1626 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);\r | |
| 1627 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);\r | |
| 1628 | @endcode\r | |
| a73ab083 | 1629 | @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
1630 | **/\r |
| 1631 | #define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r | |
| 1632 | \r | |
| 1633 | \r | |
| 1634 | /**\r | |
| 1635 | Package. Uncore SBo 0 perfmon box-wide filter.\r | |
| 1636 | \r | |
| 1637 | @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)\r | |
| 1638 | @param EAX Lower 32-bits of MSR value.\r | |
| 1639 | @param EDX Upper 32-bits of MSR value.\r | |
| 1640 | \r | |
| 1641 | <b>Example usage</b>\r | |
| 1642 | @code\r | |
| 1643 | UINT64 Msr;\r | |
| 1644 | \r | |
| 1645 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);\r | |
| 1646 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);\r | |
| 1647 | @endcode\r | |
| a73ab083 | 1648 | @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.\r |
| c67b579c MK |
1649 | **/\r |
| 1650 | #define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r | |
| 1651 | \r | |
| 1652 | \r | |
| 1653 | /**\r | |
| 1654 | Package. Uncore SBo 0 perfmon counter 0.\r | |
| 1655 | \r | |
| 1656 | @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)\r | |
| 1657 | @param EAX Lower 32-bits of MSR value.\r | |
| 1658 | @param EDX Upper 32-bits of MSR value.\r | |
| 1659 | \r | |
| 1660 | <b>Example usage</b>\r | |
| 1661 | @code\r | |
| 1662 | UINT64 Msr;\r | |
| 1663 | \r | |
| 1664 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);\r | |
| 1665 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);\r | |
| 1666 | @endcode\r | |
| a73ab083 | 1667 | @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r |
| c67b579c MK |
1668 | **/\r |
| 1669 | #define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r | |
| 1670 | \r | |
| 1671 | \r | |
| 1672 | /**\r | |
| 1673 | Package. Uncore SBo 0 perfmon counter 1.\r | |
| 1674 | \r | |
| 1675 | @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)\r | |
| 1676 | @param EAX Lower 32-bits of MSR value.\r | |
| 1677 | @param EDX Upper 32-bits of MSR value.\r | |
| 1678 | \r | |
| 1679 | <b>Example usage</b>\r | |
| 1680 | @code\r | |
| 1681 | UINT64 Msr;\r | |
| 1682 | \r | |
| 1683 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);\r | |
| 1684 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);\r | |
| 1685 | @endcode\r | |
| a73ab083 | 1686 | @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r |
| c67b579c MK |
1687 | **/\r |
| 1688 | #define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r | |
| 1689 | \r | |
| 1690 | \r | |
| 1691 | /**\r | |
| 1692 | Package. Uncore SBo 0 perfmon counter 2.\r | |
| 1693 | \r | |
| 1694 | @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)\r | |
| 1695 | @param EAX Lower 32-bits of MSR value.\r | |
| 1696 | @param EDX Upper 32-bits of MSR value.\r | |
| 1697 | \r | |
| 1698 | <b>Example usage</b>\r | |
| 1699 | @code\r | |
| 1700 | UINT64 Msr;\r | |
| 1701 | \r | |
| 1702 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);\r | |
| 1703 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);\r | |
| 1704 | @endcode\r | |
| a73ab083 | 1705 | @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r |
| c67b579c MK |
1706 | **/\r |
| 1707 | #define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r | |
| 1708 | \r | |
| 1709 | \r | |
| 1710 | /**\r | |
| 1711 | Package. Uncore SBo 0 perfmon counter 3.\r | |
| 1712 | \r | |
| 1713 | @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)\r | |
| 1714 | @param EAX Lower 32-bits of MSR value.\r | |
| 1715 | @param EDX Upper 32-bits of MSR value.\r | |
| 1716 | \r | |
| 1717 | <b>Example usage</b>\r | |
| 1718 | @code\r | |
| 1719 | UINT64 Msr;\r | |
| 1720 | \r | |
| 1721 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);\r | |
| 1722 | AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);\r | |
| 1723 | @endcode\r | |
| a73ab083 | 1724 | @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r |
| c67b579c MK |
1725 | **/\r |
| 1726 | #define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r | |
| 1727 | \r | |
| 1728 | \r | |
| 1729 | /**\r | |
| 1730 | Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.\r | |
| 1731 | \r | |
| 1732 | @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)\r | |
| 1733 | @param EAX Lower 32-bits of MSR value.\r | |
| 1734 | @param EDX Upper 32-bits of MSR value.\r | |
| 1735 | \r | |
| 1736 | <b>Example usage</b>\r | |
| 1737 | @code\r | |
| 1738 | UINT64 Msr;\r | |
| 1739 | \r | |
| 1740 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);\r | |
| 1741 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);\r | |
| 1742 | @endcode\r | |
| a73ab083 | 1743 | @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
1744 | **/\r |
| 1745 | #define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r | |
| 1746 | \r | |
| 1747 | \r | |
| 1748 | /**\r | |
| 1749 | Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.\r | |
| 1750 | \r | |
| 1751 | @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)\r | |
| 1752 | @param EAX Lower 32-bits of MSR value.\r | |
| 1753 | @param EDX Upper 32-bits of MSR value.\r | |
| 1754 | \r | |
| 1755 | <b>Example usage</b>\r | |
| 1756 | @code\r | |
| 1757 | UINT64 Msr;\r | |
| 1758 | \r | |
| 1759 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);\r | |
| 1760 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);\r | |
| 1761 | @endcode\r | |
| a73ab083 | 1762 | @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
1763 | **/\r |
| 1764 | #define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r | |
| 1765 | \r | |
| 1766 | \r | |
| 1767 | /**\r | |
| 1768 | Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.\r | |
| 1769 | \r | |
| 1770 | @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)\r | |
| 1771 | @param EAX Lower 32-bits of MSR value.\r | |
| 1772 | @param EDX Upper 32-bits of MSR value.\r | |
| 1773 | \r | |
| 1774 | <b>Example usage</b>\r | |
| 1775 | @code\r | |
| 1776 | UINT64 Msr;\r | |
| 1777 | \r | |
| 1778 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);\r | |
| 1779 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);\r | |
| 1780 | @endcode\r | |
| a73ab083 | 1781 | @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
1782 | **/\r |
| 1783 | #define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r | |
| 1784 | \r | |
| 1785 | \r | |
| 1786 | /**\r | |
| 1787 | Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.\r | |
| 1788 | \r | |
| 1789 | @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)\r | |
| 1790 | @param EAX Lower 32-bits of MSR value.\r | |
| 1791 | @param EDX Upper 32-bits of MSR value.\r | |
| 1792 | \r | |
| 1793 | <b>Example usage</b>\r | |
| 1794 | @code\r | |
| 1795 | UINT64 Msr;\r | |
| 1796 | \r | |
| 1797 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);\r | |
| 1798 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);\r | |
| 1799 | @endcode\r | |
| a73ab083 | 1800 | @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
1801 | **/\r |
| 1802 | #define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r | |
| 1803 | \r | |
| 1804 | \r | |
| 1805 | /**\r | |
| 1806 | Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.\r | |
| 1807 | \r | |
| 1808 | @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)\r | |
| 1809 | @param EAX Lower 32-bits of MSR value.\r | |
| 1810 | @param EDX Upper 32-bits of MSR value.\r | |
| 1811 | \r | |
| 1812 | <b>Example usage</b>\r | |
| 1813 | @code\r | |
| 1814 | UINT64 Msr;\r | |
| 1815 | \r | |
| 1816 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);\r | |
| 1817 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);\r | |
| 1818 | @endcode\r | |
| a73ab083 | 1819 | @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
1820 | **/\r |
| 1821 | #define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r | |
| 1822 | \r | |
| 1823 | \r | |
| 1824 | /**\r | |
| 1825 | Package. Uncore SBo 1 perfmon box-wide filter.\r | |
| 1826 | \r | |
| 1827 | @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)\r | |
| 1828 | @param EAX Lower 32-bits of MSR value.\r | |
| 1829 | @param EDX Upper 32-bits of MSR value.\r | |
| 1830 | \r | |
| 1831 | <b>Example usage</b>\r | |
| 1832 | @code\r | |
| 1833 | UINT64 Msr;\r | |
| 1834 | \r | |
| 1835 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);\r | |
| 1836 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);\r | |
| 1837 | @endcode\r | |
| a73ab083 | 1838 | @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.\r |
| c67b579c MK |
1839 | **/\r |
| 1840 | #define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r | |
| 1841 | \r | |
| 1842 | \r | |
| 1843 | /**\r | |
| 1844 | Package. Uncore SBo 1 perfmon counter 0.\r | |
| 1845 | \r | |
| 1846 | @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)\r | |
| 1847 | @param EAX Lower 32-bits of MSR value.\r | |
| 1848 | @param EDX Upper 32-bits of MSR value.\r | |
| 1849 | \r | |
| 1850 | <b>Example usage</b>\r | |
| 1851 | @code\r | |
| 1852 | UINT64 Msr;\r | |
| 1853 | \r | |
| 1854 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);\r | |
| 1855 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);\r | |
| 1856 | @endcode\r | |
| a73ab083 | 1857 | @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r |
| c67b579c MK |
1858 | **/\r |
| 1859 | #define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r | |
| 1860 | \r | |
| 1861 | \r | |
| 1862 | /**\r | |
| 1863 | Package. Uncore SBo 1 perfmon counter 1.\r | |
| 1864 | \r | |
| 1865 | @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)\r | |
| 1866 | @param EAX Lower 32-bits of MSR value.\r | |
| 1867 | @param EDX Upper 32-bits of MSR value.\r | |
| 1868 | \r | |
| 1869 | <b>Example usage</b>\r | |
| 1870 | @code\r | |
| 1871 | UINT64 Msr;\r | |
| 1872 | \r | |
| 1873 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);\r | |
| 1874 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);\r | |
| 1875 | @endcode\r | |
| a73ab083 | 1876 | @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r |
| c67b579c MK |
1877 | **/\r |
| 1878 | #define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r | |
| 1879 | \r | |
| 1880 | \r | |
| 1881 | /**\r | |
| 1882 | Package. Uncore SBo 1 perfmon counter 2.\r | |
| 1883 | \r | |
| 1884 | @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)\r | |
| 1885 | @param EAX Lower 32-bits of MSR value.\r | |
| 1886 | @param EDX Upper 32-bits of MSR value.\r | |
| 1887 | \r | |
| 1888 | <b>Example usage</b>\r | |
| 1889 | @code\r | |
| 1890 | UINT64 Msr;\r | |
| 1891 | \r | |
| 1892 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);\r | |
| 1893 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);\r | |
| 1894 | @endcode\r | |
| a73ab083 | 1895 | @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r |
| c67b579c MK |
1896 | **/\r |
| 1897 | #define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r | |
| 1898 | \r | |
| 1899 | \r | |
| 1900 | /**\r | |
| 1901 | Package. Uncore SBo 1 perfmon counter 3.\r | |
| 1902 | \r | |
| 1903 | @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)\r | |
| 1904 | @param EAX Lower 32-bits of MSR value.\r | |
| 1905 | @param EDX Upper 32-bits of MSR value.\r | |
| 1906 | \r | |
| 1907 | <b>Example usage</b>\r | |
| 1908 | @code\r | |
| 1909 | UINT64 Msr;\r | |
| 1910 | \r | |
| 1911 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);\r | |
| 1912 | AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);\r | |
| 1913 | @endcode\r | |
| a73ab083 | 1914 | @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r |
| c67b579c MK |
1915 | **/\r |
| 1916 | #define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r | |
| 1917 | \r | |
| 1918 | \r | |
| 1919 | /**\r | |
| 1920 | Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.\r | |
| 1921 | \r | |
| 1922 | @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)\r | |
| 1923 | @param EAX Lower 32-bits of MSR value.\r | |
| 1924 | @param EDX Upper 32-bits of MSR value.\r | |
| 1925 | \r | |
| 1926 | <b>Example usage</b>\r | |
| 1927 | @code\r | |
| 1928 | UINT64 Msr;\r | |
| 1929 | \r | |
| 1930 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);\r | |
| 1931 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);\r | |
| 1932 | @endcode\r | |
| a73ab083 | 1933 | @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
1934 | **/\r |
| 1935 | #define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r | |
| 1936 | \r | |
| 1937 | \r | |
| 1938 | /**\r | |
| 1939 | Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.\r | |
| 1940 | \r | |
| 1941 | @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)\r | |
| 1942 | @param EAX Lower 32-bits of MSR value.\r | |
| 1943 | @param EDX Upper 32-bits of MSR value.\r | |
| 1944 | \r | |
| 1945 | <b>Example usage</b>\r | |
| 1946 | @code\r | |
| 1947 | UINT64 Msr;\r | |
| 1948 | \r | |
| 1949 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);\r | |
| 1950 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);\r | |
| 1951 | @endcode\r | |
| a73ab083 | 1952 | @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
1953 | **/\r |
| 1954 | #define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r | |
| 1955 | \r | |
| 1956 | \r | |
| 1957 | /**\r | |
| 1958 | Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.\r | |
| 1959 | \r | |
| 1960 | @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)\r | |
| 1961 | @param EAX Lower 32-bits of MSR value.\r | |
| 1962 | @param EDX Upper 32-bits of MSR value.\r | |
| 1963 | \r | |
| 1964 | <b>Example usage</b>\r | |
| 1965 | @code\r | |
| 1966 | UINT64 Msr;\r | |
| 1967 | \r | |
| 1968 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);\r | |
| 1969 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);\r | |
| 1970 | @endcode\r | |
| a73ab083 | 1971 | @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
1972 | **/\r |
| 1973 | #define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r | |
| 1974 | \r | |
| 1975 | \r | |
| 1976 | /**\r | |
| 1977 | Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.\r | |
| 1978 | \r | |
| 1979 | @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)\r | |
| 1980 | @param EAX Lower 32-bits of MSR value.\r | |
| 1981 | @param EDX Upper 32-bits of MSR value.\r | |
| 1982 | \r | |
| 1983 | <b>Example usage</b>\r | |
| 1984 | @code\r | |
| 1985 | UINT64 Msr;\r | |
| 1986 | \r | |
| 1987 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);\r | |
| 1988 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);\r | |
| 1989 | @endcode\r | |
| a73ab083 | 1990 | @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
1991 | **/\r |
| 1992 | #define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r | |
| 1993 | \r | |
| 1994 | \r | |
| 1995 | /**\r | |
| 1996 | Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.\r | |
| 1997 | \r | |
| 1998 | @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)\r | |
| 1999 | @param EAX Lower 32-bits of MSR value.\r | |
| 2000 | @param EDX Upper 32-bits of MSR value.\r | |
| 2001 | \r | |
| 2002 | <b>Example usage</b>\r | |
| 2003 | @code\r | |
| 2004 | UINT64 Msr;\r | |
| 2005 | \r | |
| 2006 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);\r | |
| 2007 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);\r | |
| 2008 | @endcode\r | |
| a73ab083 | 2009 | @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
2010 | **/\r |
| 2011 | #define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r | |
| 2012 | \r | |
| 2013 | \r | |
| 2014 | /**\r | |
| 2015 | Package. Uncore SBo 2 perfmon box-wide filter.\r | |
| 2016 | \r | |
| 2017 | @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)\r | |
| 2018 | @param EAX Lower 32-bits of MSR value.\r | |
| 2019 | @param EDX Upper 32-bits of MSR value.\r | |
| 2020 | \r | |
| 2021 | <b>Example usage</b>\r | |
| 2022 | @code\r | |
| 2023 | UINT64 Msr;\r | |
| 2024 | \r | |
| 2025 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);\r | |
| 2026 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);\r | |
| 2027 | @endcode\r | |
| a73ab083 | 2028 | @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.\r |
| c67b579c MK |
2029 | **/\r |
| 2030 | #define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r | |
| 2031 | \r | |
| 2032 | \r | |
| 2033 | /**\r | |
| 2034 | Package. Uncore SBo 2 perfmon counter 0.\r | |
| 2035 | \r | |
| 2036 | @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)\r | |
| 2037 | @param EAX Lower 32-bits of MSR value.\r | |
| 2038 | @param EDX Upper 32-bits of MSR value.\r | |
| 2039 | \r | |
| 2040 | <b>Example usage</b>\r | |
| 2041 | @code\r | |
| 2042 | UINT64 Msr;\r | |
| 2043 | \r | |
| 2044 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);\r | |
| 2045 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);\r | |
| 2046 | @endcode\r | |
| a73ab083 | 2047 | @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.\r |
| c67b579c MK |
2048 | **/\r |
| 2049 | #define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r | |
| 2050 | \r | |
| 2051 | \r | |
| 2052 | /**\r | |
| 2053 | Package. Uncore SBo 2 perfmon counter 1.\r | |
| 2054 | \r | |
| 2055 | @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)\r | |
| 2056 | @param EAX Lower 32-bits of MSR value.\r | |
| 2057 | @param EDX Upper 32-bits of MSR value.\r | |
| 2058 | \r | |
| 2059 | <b>Example usage</b>\r | |
| 2060 | @code\r | |
| 2061 | UINT64 Msr;\r | |
| 2062 | \r | |
| 2063 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);\r | |
| 2064 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);\r | |
| 2065 | @endcode\r | |
| a73ab083 | 2066 | @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.\r |
| c67b579c MK |
2067 | **/\r |
| 2068 | #define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r | |
| 2069 | \r | |
| 2070 | \r | |
| 2071 | /**\r | |
| 2072 | Package. Uncore SBo 2 perfmon counter 2.\r | |
| 2073 | \r | |
| 2074 | @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)\r | |
| 2075 | @param EAX Lower 32-bits of MSR value.\r | |
| 2076 | @param EDX Upper 32-bits of MSR value.\r | |
| 2077 | \r | |
| 2078 | <b>Example usage</b>\r | |
| 2079 | @code\r | |
| 2080 | UINT64 Msr;\r | |
| 2081 | \r | |
| 2082 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);\r | |
| 2083 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);\r | |
| 2084 | @endcode\r | |
| a73ab083 | 2085 | @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.\r |
| c67b579c MK |
2086 | **/\r |
| 2087 | #define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r | |
| 2088 | \r | |
| 2089 | \r | |
| 2090 | /**\r | |
| 2091 | Package. Uncore SBo 2 perfmon counter 3.\r | |
| 2092 | \r | |
| 2093 | @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)\r | |
| 2094 | @param EAX Lower 32-bits of MSR value.\r | |
| 2095 | @param EDX Upper 32-bits of MSR value.\r | |
| 2096 | \r | |
| 2097 | <b>Example usage</b>\r | |
| 2098 | @code\r | |
| 2099 | UINT64 Msr;\r | |
| 2100 | \r | |
| 2101 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);\r | |
| 2102 | AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);\r | |
| 2103 | @endcode\r | |
| a73ab083 | 2104 | @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.\r |
| c67b579c MK |
2105 | **/\r |
| 2106 | #define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r | |
| 2107 | \r | |
| 2108 | \r | |
| 2109 | /**\r | |
| 2110 | Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.\r | |
| 2111 | \r | |
| 2112 | @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)\r | |
| 2113 | @param EAX Lower 32-bits of MSR value.\r | |
| 2114 | @param EDX Upper 32-bits of MSR value.\r | |
| 2115 | \r | |
| 2116 | <b>Example usage</b>\r | |
| 2117 | @code\r | |
| 2118 | UINT64 Msr;\r | |
| 2119 | \r | |
| 2120 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);\r | |
| 2121 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);\r | |
| 2122 | @endcode\r | |
| a73ab083 | 2123 | @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
2124 | **/\r |
| 2125 | #define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r | |
| 2126 | \r | |
| 2127 | \r | |
| 2128 | /**\r | |
| 2129 | Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.\r | |
| 2130 | \r | |
| 2131 | @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)\r | |
| 2132 | @param EAX Lower 32-bits of MSR value.\r | |
| 2133 | @param EDX Upper 32-bits of MSR value.\r | |
| 2134 | \r | |
| 2135 | <b>Example usage</b>\r | |
| 2136 | @code\r | |
| 2137 | UINT64 Msr;\r | |
| 2138 | \r | |
| 2139 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);\r | |
| 2140 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);\r | |
| 2141 | @endcode\r | |
| a73ab083 | 2142 | @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
2143 | **/\r |
| 2144 | #define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r | |
| 2145 | \r | |
| 2146 | \r | |
| 2147 | /**\r | |
| 2148 | Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.\r | |
| 2149 | \r | |
| 2150 | @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)\r | |
| 2151 | @param EAX Lower 32-bits of MSR value.\r | |
| 2152 | @param EDX Upper 32-bits of MSR value.\r | |
| 2153 | \r | |
| 2154 | <b>Example usage</b>\r | |
| 2155 | @code\r | |
| 2156 | UINT64 Msr;\r | |
| 2157 | \r | |
| 2158 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);\r | |
| 2159 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);\r | |
| 2160 | @endcode\r | |
| a73ab083 | 2161 | @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
2162 | **/\r |
| 2163 | #define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r | |
| 2164 | \r | |
| 2165 | \r | |
| 2166 | /**\r | |
| 2167 | Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.\r | |
| 2168 | \r | |
| 2169 | @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)\r | |
| 2170 | @param EAX Lower 32-bits of MSR value.\r | |
| 2171 | @param EDX Upper 32-bits of MSR value.\r | |
| 2172 | \r | |
| 2173 | <b>Example usage</b>\r | |
| 2174 | @code\r | |
| 2175 | UINT64 Msr;\r | |
| 2176 | \r | |
| 2177 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);\r | |
| 2178 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);\r | |
| 2179 | @endcode\r | |
| a73ab083 | 2180 | @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
2181 | **/\r |
| 2182 | #define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r | |
| 2183 | \r | |
| 2184 | \r | |
| 2185 | /**\r | |
| 2186 | Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.\r | |
| 2187 | \r | |
| 2188 | @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)\r | |
| 2189 | @param EAX Lower 32-bits of MSR value.\r | |
| 2190 | @param EDX Upper 32-bits of MSR value.\r | |
| 2191 | \r | |
| 2192 | <b>Example usage</b>\r | |
| 2193 | @code\r | |
| 2194 | UINT64 Msr;\r | |
| 2195 | \r | |
| 2196 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);\r | |
| 2197 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);\r | |
| 2198 | @endcode\r | |
| a73ab083 | 2199 | @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
2200 | **/\r |
| 2201 | #define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r | |
| 2202 | \r | |
| 2203 | \r | |
| 2204 | /**\r | |
| 2205 | Package. Uncore SBo 3 perfmon box-wide filter.\r | |
| 2206 | \r | |
| 2207 | @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)\r | |
| 2208 | @param EAX Lower 32-bits of MSR value.\r | |
| 2209 | @param EDX Upper 32-bits of MSR value.\r | |
| 2210 | \r | |
| 2211 | <b>Example usage</b>\r | |
| 2212 | @code\r | |
| 2213 | UINT64 Msr;\r | |
| 2214 | \r | |
| 2215 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);\r | |
| 2216 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);\r | |
| 2217 | @endcode\r | |
| a73ab083 | 2218 | @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.\r |
| c67b579c MK |
2219 | **/\r |
| 2220 | #define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r | |
| 2221 | \r | |
| 2222 | \r | |
| 2223 | /**\r | |
| 2224 | Package. Uncore SBo 3 perfmon counter 0.\r | |
| 2225 | \r | |
| 2226 | @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)\r | |
| 2227 | @param EAX Lower 32-bits of MSR value.\r | |
| 2228 | @param EDX Upper 32-bits of MSR value.\r | |
| 2229 | \r | |
| 2230 | <b>Example usage</b>\r | |
| 2231 | @code\r | |
| 2232 | UINT64 Msr;\r | |
| 2233 | \r | |
| 2234 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);\r | |
| 2235 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);\r | |
| 2236 | @endcode\r | |
| a73ab083 | 2237 | @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.\r |
| c67b579c MK |
2238 | **/\r |
| 2239 | #define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r | |
| 2240 | \r | |
| 2241 | \r | |
| 2242 | /**\r | |
| 2243 | Package. Uncore SBo 3 perfmon counter 1.\r | |
| 2244 | \r | |
| 2245 | @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)\r | |
| 2246 | @param EAX Lower 32-bits of MSR value.\r | |
| 2247 | @param EDX Upper 32-bits of MSR value.\r | |
| 2248 | \r | |
| 2249 | <b>Example usage</b>\r | |
| 2250 | @code\r | |
| 2251 | UINT64 Msr;\r | |
| 2252 | \r | |
| 2253 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);\r | |
| 2254 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);\r | |
| 2255 | @endcode\r | |
| a73ab083 | 2256 | @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.\r |
| c67b579c MK |
2257 | **/\r |
| 2258 | #define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r | |
| 2259 | \r | |
| 2260 | \r | |
| 2261 | /**\r | |
| 2262 | Package. Uncore SBo 3 perfmon counter 2.\r | |
| 2263 | \r | |
| 2264 | @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)\r | |
| 2265 | @param EAX Lower 32-bits of MSR value.\r | |
| 2266 | @param EDX Upper 32-bits of MSR value.\r | |
| 2267 | \r | |
| 2268 | <b>Example usage</b>\r | |
| 2269 | @code\r | |
| 2270 | UINT64 Msr;\r | |
| 2271 | \r | |
| 2272 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);\r | |
| 2273 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);\r | |
| 2274 | @endcode\r | |
| a73ab083 | 2275 | @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.\r |
| c67b579c MK |
2276 | **/\r |
| 2277 | #define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r | |
| 2278 | \r | |
| 2279 | \r | |
| 2280 | /**\r | |
| 2281 | Package. Uncore SBo 3 perfmon counter 3.\r | |
| 2282 | \r | |
| 2283 | @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)\r | |
| 2284 | @param EAX Lower 32-bits of MSR value.\r | |
| 2285 | @param EDX Upper 32-bits of MSR value.\r | |
| 2286 | \r | |
| 2287 | <b>Example usage</b>\r | |
| 2288 | @code\r | |
| 2289 | UINT64 Msr;\r | |
| 2290 | \r | |
| 2291 | Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);\r | |
| 2292 | AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);\r | |
| 2293 | @endcode\r | |
| a73ab083 | 2294 | @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.\r |
| c67b579c MK |
2295 | **/\r |
| 2296 | #define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r | |
| 2297 | \r | |
| 2298 | \r | |
| 2299 | /**\r | |
| 2300 | Package. Uncore C-box 0 perfmon for box-wide control.\r | |
| 2301 | \r | |
| 2302 | @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)\r | |
| 2303 | @param EAX Lower 32-bits of MSR value.\r | |
| 2304 | @param EDX Upper 32-bits of MSR value.\r | |
| 2305 | \r | |
| 2306 | <b>Example usage</b>\r | |
| 2307 | @code\r | |
| 2308 | UINT64 Msr;\r | |
| 2309 | \r | |
| 2310 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);\r | |
| 2311 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);\r | |
| 2312 | @endcode\r | |
| a73ab083 | 2313 | @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
2314 | **/\r |
| 2315 | #define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r | |
| 2316 | \r | |
| 2317 | \r | |
| 2318 | /**\r | |
| 2319 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r | |
| 2320 | \r | |
| 2321 | @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)\r | |
| 2322 | @param EAX Lower 32-bits of MSR value.\r | |
| 2323 | @param EDX Upper 32-bits of MSR value.\r | |
| 2324 | \r | |
| 2325 | <b>Example usage</b>\r | |
| 2326 | @code\r | |
| 2327 | UINT64 Msr;\r | |
| 2328 | \r | |
| 2329 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);\r | |
| 2330 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);\r | |
| 2331 | @endcode\r | |
| a73ab083 | 2332 | @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
2333 | **/\r |
| 2334 | #define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r | |
| 2335 | \r | |
| 2336 | \r | |
| 2337 | /**\r | |
| 2338 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r | |
| 2339 | \r | |
| 2340 | @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)\r | |
| 2341 | @param EAX Lower 32-bits of MSR value.\r | |
| 2342 | @param EDX Upper 32-bits of MSR value.\r | |
| 2343 | \r | |
| 2344 | <b>Example usage</b>\r | |
| 2345 | @code\r | |
| 2346 | UINT64 Msr;\r | |
| 2347 | \r | |
| 2348 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);\r | |
| 2349 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);\r | |
| 2350 | @endcode\r | |
| a73ab083 | 2351 | @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
2352 | **/\r |
| 2353 | #define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r | |
| 2354 | \r | |
| 2355 | \r | |
| 2356 | /**\r | |
| 2357 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r | |
| 2358 | \r | |
| 2359 | @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)\r | |
| 2360 | @param EAX Lower 32-bits of MSR value.\r | |
| 2361 | @param EDX Upper 32-bits of MSR value.\r | |
| 2362 | \r | |
| 2363 | <b>Example usage</b>\r | |
| 2364 | @code\r | |
| 2365 | UINT64 Msr;\r | |
| 2366 | \r | |
| 2367 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);\r | |
| 2368 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);\r | |
| 2369 | @endcode\r | |
| a73ab083 | 2370 | @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
2371 | **/\r |
| 2372 | #define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r | |
| 2373 | \r | |
| 2374 | \r | |
| 2375 | /**\r | |
| 2376 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r | |
| 2377 | \r | |
| 2378 | @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)\r | |
| 2379 | @param EAX Lower 32-bits of MSR value.\r | |
| 2380 | @param EDX Upper 32-bits of MSR value.\r | |
| 2381 | \r | |
| 2382 | <b>Example usage</b>\r | |
| 2383 | @code\r | |
| 2384 | UINT64 Msr;\r | |
| 2385 | \r | |
| 2386 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);\r | |
| 2387 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);\r | |
| 2388 | @endcode\r | |
| a73ab083 | 2389 | @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
2390 | **/\r |
| 2391 | #define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r | |
| 2392 | \r | |
| 2393 | \r | |
| 2394 | /**\r | |
| 2395 | Package. Uncore C-box 0 perfmon box wide filter 0.\r | |
| 2396 | \r | |
| 2397 | @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)\r | |
| 2398 | @param EAX Lower 32-bits of MSR value.\r | |
| 2399 | @param EDX Upper 32-bits of MSR value.\r | |
| 2400 | \r | |
| 2401 | <b>Example usage</b>\r | |
| 2402 | @code\r | |
| 2403 | UINT64 Msr;\r | |
| 2404 | \r | |
| 2405 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);\r | |
| 2406 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);\r | |
| 2407 | @endcode\r | |
| a73ab083 | 2408 | @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
2409 | **/\r |
| 2410 | #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r | |
| 2411 | \r | |
| 2412 | \r | |
| 2413 | /**\r | |
| 2414 | Package. Uncore C-box 0 perfmon box wide filter 1.\r | |
| 2415 | \r | |
| 2416 | @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)\r | |
| 2417 | @param EAX Lower 32-bits of MSR value.\r | |
| 2418 | @param EDX Upper 32-bits of MSR value.\r | |
| 2419 | \r | |
| 2420 | <b>Example usage</b>\r | |
| 2421 | @code\r | |
| 2422 | UINT64 Msr;\r | |
| 2423 | \r | |
| 2424 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);\r | |
| 2425 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);\r | |
| 2426 | @endcode\r | |
| a73ab083 | 2427 | @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
2428 | **/\r |
| 2429 | #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r | |
| 2430 | \r | |
| 2431 | \r | |
| 2432 | /**\r | |
| 2433 | Package. Uncore C-box 0 perfmon box wide status.\r | |
| 2434 | \r | |
| 2435 | @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)\r | |
| 2436 | @param EAX Lower 32-bits of MSR value.\r | |
| 2437 | @param EDX Upper 32-bits of MSR value.\r | |
| 2438 | \r | |
| 2439 | <b>Example usage</b>\r | |
| 2440 | @code\r | |
| 2441 | UINT64 Msr;\r | |
| 2442 | \r | |
| 2443 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);\r | |
| 2444 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);\r | |
| 2445 | @endcode\r | |
| a73ab083 | 2446 | @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
2447 | **/\r |
| 2448 | #define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r | |
| 2449 | \r | |
| 2450 | \r | |
| 2451 | /**\r | |
| 2452 | Package. Uncore C-box 0 perfmon counter 0.\r | |
| 2453 | \r | |
| 2454 | @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)\r | |
| 2455 | @param EAX Lower 32-bits of MSR value.\r | |
| 2456 | @param EDX Upper 32-bits of MSR value.\r | |
| 2457 | \r | |
| 2458 | <b>Example usage</b>\r | |
| 2459 | @code\r | |
| 2460 | UINT64 Msr;\r | |
| 2461 | \r | |
| 2462 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);\r | |
| 2463 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);\r | |
| 2464 | @endcode\r | |
| a73ab083 | 2465 | @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r |
| c67b579c MK |
2466 | **/\r |
| 2467 | #define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r | |
| 2468 | \r | |
| 2469 | \r | |
| 2470 | /**\r | |
| 2471 | Package. Uncore C-box 0 perfmon counter 1.\r | |
| 2472 | \r | |
| 2473 | @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)\r | |
| 2474 | @param EAX Lower 32-bits of MSR value.\r | |
| 2475 | @param EDX Upper 32-bits of MSR value.\r | |
| 2476 | \r | |
| 2477 | <b>Example usage</b>\r | |
| 2478 | @code\r | |
| 2479 | UINT64 Msr;\r | |
| 2480 | \r | |
| 2481 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);\r | |
| 2482 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);\r | |
| 2483 | @endcode\r | |
| a73ab083 | 2484 | @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r |
| c67b579c MK |
2485 | **/\r |
| 2486 | #define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r | |
| 2487 | \r | |
| 2488 | \r | |
| 2489 | /**\r | |
| 2490 | Package. Uncore C-box 0 perfmon counter 2.\r | |
| 2491 | \r | |
| 2492 | @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)\r | |
| 2493 | @param EAX Lower 32-bits of MSR value.\r | |
| 2494 | @param EDX Upper 32-bits of MSR value.\r | |
| 2495 | \r | |
| 2496 | <b>Example usage</b>\r | |
| 2497 | @code\r | |
| 2498 | UINT64 Msr;\r | |
| 2499 | \r | |
| 2500 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);\r | |
| 2501 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);\r | |
| 2502 | @endcode\r | |
| a73ab083 | 2503 | @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r |
| c67b579c MK |
2504 | **/\r |
| 2505 | #define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r | |
| 2506 | \r | |
| 2507 | \r | |
| 2508 | /**\r | |
| 2509 | Package. Uncore C-box 0 perfmon counter 3.\r | |
| 2510 | \r | |
| 2511 | @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)\r | |
| 2512 | @param EAX Lower 32-bits of MSR value.\r | |
| 2513 | @param EDX Upper 32-bits of MSR value.\r | |
| 2514 | \r | |
| 2515 | <b>Example usage</b>\r | |
| 2516 | @code\r | |
| 2517 | UINT64 Msr;\r | |
| 2518 | \r | |
| 2519 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);\r | |
| 2520 | AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);\r | |
| 2521 | @endcode\r | |
| a73ab083 | 2522 | @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r |
| c67b579c MK |
2523 | **/\r |
| 2524 | #define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r | |
| 2525 | \r | |
| 2526 | \r | |
| 2527 | /**\r | |
| 2528 | Package. Uncore C-box 1 perfmon for box-wide control.\r | |
| 2529 | \r | |
| 2530 | @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)\r | |
| 2531 | @param EAX Lower 32-bits of MSR value.\r | |
| 2532 | @param EDX Upper 32-bits of MSR value.\r | |
| 2533 | \r | |
| 2534 | <b>Example usage</b>\r | |
| 2535 | @code\r | |
| 2536 | UINT64 Msr;\r | |
| 2537 | \r | |
| 2538 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);\r | |
| 2539 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);\r | |
| 2540 | @endcode\r | |
| a73ab083 | 2541 | @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
2542 | **/\r |
| 2543 | #define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r | |
| 2544 | \r | |
| 2545 | \r | |
| 2546 | /**\r | |
| 2547 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r | |
| 2548 | \r | |
| 2549 | @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)\r | |
| 2550 | @param EAX Lower 32-bits of MSR value.\r | |
| 2551 | @param EDX Upper 32-bits of MSR value.\r | |
| 2552 | \r | |
| 2553 | <b>Example usage</b>\r | |
| 2554 | @code\r | |
| 2555 | UINT64 Msr;\r | |
| 2556 | \r | |
| 2557 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);\r | |
| 2558 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);\r | |
| 2559 | @endcode\r | |
| a73ab083 | 2560 | @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
2561 | **/\r |
| 2562 | #define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r | |
| 2563 | \r | |
| 2564 | \r | |
| 2565 | /**\r | |
| 2566 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r | |
| 2567 | \r | |
| 2568 | @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)\r | |
| 2569 | @param EAX Lower 32-bits of MSR value.\r | |
| 2570 | @param EDX Upper 32-bits of MSR value.\r | |
| 2571 | \r | |
| 2572 | <b>Example usage</b>\r | |
| 2573 | @code\r | |
| 2574 | UINT64 Msr;\r | |
| 2575 | \r | |
| 2576 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);\r | |
| 2577 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);\r | |
| 2578 | @endcode\r | |
| a73ab083 | 2579 | @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
2580 | **/\r |
| 2581 | #define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r | |
| 2582 | \r | |
| 2583 | \r | |
| 2584 | /**\r | |
| 2585 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r | |
| 2586 | \r | |
| 2587 | @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)\r | |
| 2588 | @param EAX Lower 32-bits of MSR value.\r | |
| 2589 | @param EDX Upper 32-bits of MSR value.\r | |
| 2590 | \r | |
| 2591 | <b>Example usage</b>\r | |
| 2592 | @code\r | |
| 2593 | UINT64 Msr;\r | |
| 2594 | \r | |
| 2595 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);\r | |
| 2596 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);\r | |
| 2597 | @endcode\r | |
| a73ab083 | 2598 | @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
2599 | **/\r |
| 2600 | #define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r | |
| 2601 | \r | |
| 2602 | \r | |
| 2603 | /**\r | |
| 2604 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r | |
| 2605 | \r | |
| 2606 | @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)\r | |
| 2607 | @param EAX Lower 32-bits of MSR value.\r | |
| 2608 | @param EDX Upper 32-bits of MSR value.\r | |
| 2609 | \r | |
| 2610 | <b>Example usage</b>\r | |
| 2611 | @code\r | |
| 2612 | UINT64 Msr;\r | |
| 2613 | \r | |
| 2614 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);\r | |
| 2615 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);\r | |
| 2616 | @endcode\r | |
| a73ab083 | 2617 | @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
2618 | **/\r |
| 2619 | #define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r | |
| 2620 | \r | |
| 2621 | \r | |
| 2622 | /**\r | |
| 2623 | Package. Uncore C-box 1 perfmon box wide filter 0.\r | |
| 2624 | \r | |
| 2625 | @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)\r | |
| 2626 | @param EAX Lower 32-bits of MSR value.\r | |
| 2627 | @param EDX Upper 32-bits of MSR value.\r | |
| 2628 | \r | |
| 2629 | <b>Example usage</b>\r | |
| 2630 | @code\r | |
| 2631 | UINT64 Msr;\r | |
| 2632 | \r | |
| 2633 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);\r | |
| 2634 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);\r | |
| 2635 | @endcode\r | |
| a73ab083 | 2636 | @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
2637 | **/\r |
| 2638 | #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r | |
| 2639 | \r | |
| 2640 | \r | |
| 2641 | /**\r | |
| 2642 | Package. Uncore C-box 1 perfmon box wide filter1.\r | |
| 2643 | \r | |
| 2644 | @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)\r | |
| 2645 | @param EAX Lower 32-bits of MSR value.\r | |
| 2646 | @param EDX Upper 32-bits of MSR value.\r | |
| 2647 | \r | |
| 2648 | <b>Example usage</b>\r | |
| 2649 | @code\r | |
| 2650 | UINT64 Msr;\r | |
| 2651 | \r | |
| 2652 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);\r | |
| 2653 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);\r | |
| 2654 | @endcode\r | |
| a73ab083 | 2655 | @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
2656 | **/\r |
| 2657 | #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r | |
| 2658 | \r | |
| 2659 | \r | |
| 2660 | /**\r | |
| 2661 | Package. Uncore C-box 1 perfmon box wide status.\r | |
| 2662 | \r | |
| 2663 | @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)\r | |
| 2664 | @param EAX Lower 32-bits of MSR value.\r | |
| 2665 | @param EDX Upper 32-bits of MSR value.\r | |
| 2666 | \r | |
| 2667 | <b>Example usage</b>\r | |
| 2668 | @code\r | |
| 2669 | UINT64 Msr;\r | |
| 2670 | \r | |
| 2671 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);\r | |
| 2672 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);\r | |
| 2673 | @endcode\r | |
| a73ab083 | 2674 | @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
2675 | **/\r |
| 2676 | #define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r | |
| 2677 | \r | |
| 2678 | \r | |
| 2679 | /**\r | |
| 2680 | Package. Uncore C-box 1 perfmon counter 0.\r | |
| 2681 | \r | |
| 2682 | @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)\r | |
| 2683 | @param EAX Lower 32-bits of MSR value.\r | |
| 2684 | @param EDX Upper 32-bits of MSR value.\r | |
| 2685 | \r | |
| 2686 | <b>Example usage</b>\r | |
| 2687 | @code\r | |
| 2688 | UINT64 Msr;\r | |
| 2689 | \r | |
| 2690 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);\r | |
| 2691 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);\r | |
| 2692 | @endcode\r | |
| a73ab083 | 2693 | @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r |
| c67b579c MK |
2694 | **/\r |
| 2695 | #define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r | |
| 2696 | \r | |
| 2697 | \r | |
| 2698 | /**\r | |
| 2699 | Package. Uncore C-box 1 perfmon counter 1.\r | |
| 2700 | \r | |
| 2701 | @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)\r | |
| 2702 | @param EAX Lower 32-bits of MSR value.\r | |
| 2703 | @param EDX Upper 32-bits of MSR value.\r | |
| 2704 | \r | |
| 2705 | <b>Example usage</b>\r | |
| 2706 | @code\r | |
| 2707 | UINT64 Msr;\r | |
| 2708 | \r | |
| 2709 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);\r | |
| 2710 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);\r | |
| 2711 | @endcode\r | |
| a73ab083 | 2712 | @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r |
| c67b579c MK |
2713 | **/\r |
| 2714 | #define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r | |
| 2715 | \r | |
| 2716 | \r | |
| 2717 | /**\r | |
| 2718 | Package. Uncore C-box 1 perfmon counter 2.\r | |
| 2719 | \r | |
| 2720 | @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)\r | |
| 2721 | @param EAX Lower 32-bits of MSR value.\r | |
| 2722 | @param EDX Upper 32-bits of MSR value.\r | |
| 2723 | \r | |
| 2724 | <b>Example usage</b>\r | |
| 2725 | @code\r | |
| 2726 | UINT64 Msr;\r | |
| 2727 | \r | |
| 2728 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);\r | |
| 2729 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);\r | |
| 2730 | @endcode\r | |
| a73ab083 | 2731 | @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r |
| c67b579c MK |
2732 | **/\r |
| 2733 | #define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r | |
| 2734 | \r | |
| 2735 | \r | |
| 2736 | /**\r | |
| 2737 | Package. Uncore C-box 1 perfmon counter 3.\r | |
| 2738 | \r | |
| 2739 | @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)\r | |
| 2740 | @param EAX Lower 32-bits of MSR value.\r | |
| 2741 | @param EDX Upper 32-bits of MSR value.\r | |
| 2742 | \r | |
| 2743 | <b>Example usage</b>\r | |
| 2744 | @code\r | |
| 2745 | UINT64 Msr;\r | |
| 2746 | \r | |
| 2747 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);\r | |
| 2748 | AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);\r | |
| 2749 | @endcode\r | |
| a73ab083 | 2750 | @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r |
| c67b579c MK |
2751 | **/\r |
| 2752 | #define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r | |
| 2753 | \r | |
| 2754 | \r | |
| 2755 | /**\r | |
| 2756 | Package. Uncore C-box 2 perfmon for box-wide control.\r | |
| 2757 | \r | |
| 2758 | @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)\r | |
| 2759 | @param EAX Lower 32-bits of MSR value.\r | |
| 2760 | @param EDX Upper 32-bits of MSR value.\r | |
| 2761 | \r | |
| 2762 | <b>Example usage</b>\r | |
| 2763 | @code\r | |
| 2764 | UINT64 Msr;\r | |
| 2765 | \r | |
| 2766 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);\r | |
| 2767 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);\r | |
| 2768 | @endcode\r | |
| a73ab083 | 2769 | @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
2770 | **/\r |
| 2771 | #define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r | |
| 2772 | \r | |
| 2773 | \r | |
| 2774 | /**\r | |
| 2775 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r | |
| 2776 | \r | |
| 2777 | @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)\r | |
| 2778 | @param EAX Lower 32-bits of MSR value.\r | |
| 2779 | @param EDX Upper 32-bits of MSR value.\r | |
| 2780 | \r | |
| 2781 | <b>Example usage</b>\r | |
| 2782 | @code\r | |
| 2783 | UINT64 Msr;\r | |
| 2784 | \r | |
| 2785 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);\r | |
| 2786 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);\r | |
| 2787 | @endcode\r | |
| a73ab083 | 2788 | @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
2789 | **/\r |
| 2790 | #define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r | |
| 2791 | \r | |
| 2792 | \r | |
| 2793 | /**\r | |
| 2794 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r | |
| 2795 | \r | |
| 2796 | @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)\r | |
| 2797 | @param EAX Lower 32-bits of MSR value.\r | |
| 2798 | @param EDX Upper 32-bits of MSR value.\r | |
| 2799 | \r | |
| 2800 | <b>Example usage</b>\r | |
| 2801 | @code\r | |
| 2802 | UINT64 Msr;\r | |
| 2803 | \r | |
| 2804 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);\r | |
| 2805 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);\r | |
| 2806 | @endcode\r | |
| a73ab083 | 2807 | @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
2808 | **/\r |
| 2809 | #define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r | |
| 2810 | \r | |
| 2811 | \r | |
| 2812 | /**\r | |
| 2813 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r | |
| 2814 | \r | |
| 2815 | @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)\r | |
| 2816 | @param EAX Lower 32-bits of MSR value.\r | |
| 2817 | @param EDX Upper 32-bits of MSR value.\r | |
| 2818 | \r | |
| 2819 | <b>Example usage</b>\r | |
| 2820 | @code\r | |
| 2821 | UINT64 Msr;\r | |
| 2822 | \r | |
| 2823 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);\r | |
| 2824 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);\r | |
| 2825 | @endcode\r | |
| a73ab083 | 2826 | @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
2827 | **/\r |
| 2828 | #define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r | |
| 2829 | \r | |
| 2830 | \r | |
| 2831 | /**\r | |
| 2832 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r | |
| 2833 | \r | |
| 2834 | @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)\r | |
| 2835 | @param EAX Lower 32-bits of MSR value.\r | |
| 2836 | @param EDX Upper 32-bits of MSR value.\r | |
| 2837 | \r | |
| 2838 | <b>Example usage</b>\r | |
| 2839 | @code\r | |
| 2840 | UINT64 Msr;\r | |
| 2841 | \r | |
| 2842 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);\r | |
| 2843 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);\r | |
| 2844 | @endcode\r | |
| a73ab083 | 2845 | @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
2846 | **/\r |
| 2847 | #define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r | |
| 2848 | \r | |
| 2849 | \r | |
| 2850 | /**\r | |
| 2851 | Package. Uncore C-box 2 perfmon box wide filter 0.\r | |
| 2852 | \r | |
| 2853 | @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)\r | |
| 2854 | @param EAX Lower 32-bits of MSR value.\r | |
| 2855 | @param EDX Upper 32-bits of MSR value.\r | |
| 2856 | \r | |
| 2857 | <b>Example usage</b>\r | |
| 2858 | @code\r | |
| 2859 | UINT64 Msr;\r | |
| 2860 | \r | |
| 2861 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);\r | |
| 2862 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);\r | |
| 2863 | @endcode\r | |
| a73ab083 | 2864 | @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
2865 | **/\r |
| 2866 | #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r | |
| 2867 | \r | |
| 2868 | \r | |
| 2869 | /**\r | |
| 2870 | Package. Uncore C-box 2 perfmon box wide filter1.\r | |
| 2871 | \r | |
| 2872 | @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)\r | |
| 2873 | @param EAX Lower 32-bits of MSR value.\r | |
| 2874 | @param EDX Upper 32-bits of MSR value.\r | |
| 2875 | \r | |
| 2876 | <b>Example usage</b>\r | |
| 2877 | @code\r | |
| 2878 | UINT64 Msr;\r | |
| 2879 | \r | |
| 2880 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);\r | |
| 2881 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);\r | |
| 2882 | @endcode\r | |
| a73ab083 | 2883 | @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
2884 | **/\r |
| 2885 | #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r | |
| 2886 | \r | |
| 2887 | \r | |
| 2888 | /**\r | |
| 2889 | Package. Uncore C-box 2 perfmon box wide status.\r | |
| 2890 | \r | |
| 2891 | @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)\r | |
| 2892 | @param EAX Lower 32-bits of MSR value.\r | |
| 2893 | @param EDX Upper 32-bits of MSR value.\r | |
| 2894 | \r | |
| 2895 | <b>Example usage</b>\r | |
| 2896 | @code\r | |
| 2897 | UINT64 Msr;\r | |
| 2898 | \r | |
| 2899 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);\r | |
| 2900 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);\r | |
| 2901 | @endcode\r | |
| a73ab083 | 2902 | @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
2903 | **/\r |
| 2904 | #define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r | |
| 2905 | \r | |
| 2906 | \r | |
| 2907 | /**\r | |
| 2908 | Package. Uncore C-box 2 perfmon counter 0.\r | |
| 2909 | \r | |
| 2910 | @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)\r | |
| 2911 | @param EAX Lower 32-bits of MSR value.\r | |
| 2912 | @param EDX Upper 32-bits of MSR value.\r | |
| 2913 | \r | |
| 2914 | <b>Example usage</b>\r | |
| 2915 | @code\r | |
| 2916 | UINT64 Msr;\r | |
| 2917 | \r | |
| 2918 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);\r | |
| 2919 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);\r | |
| 2920 | @endcode\r | |
| a73ab083 | 2921 | @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r |
| c67b579c MK |
2922 | **/\r |
| 2923 | #define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r | |
| 2924 | \r | |
| 2925 | \r | |
| 2926 | /**\r | |
| 2927 | Package. Uncore C-box 2 perfmon counter 1.\r | |
| 2928 | \r | |
| 2929 | @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)\r | |
| 2930 | @param EAX Lower 32-bits of MSR value.\r | |
| 2931 | @param EDX Upper 32-bits of MSR value.\r | |
| 2932 | \r | |
| 2933 | <b>Example usage</b>\r | |
| 2934 | @code\r | |
| 2935 | UINT64 Msr;\r | |
| 2936 | \r | |
| 2937 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);\r | |
| 2938 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);\r | |
| 2939 | @endcode\r | |
| a73ab083 | 2940 | @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r |
| c67b579c MK |
2941 | **/\r |
| 2942 | #define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r | |
| 2943 | \r | |
| 2944 | \r | |
| 2945 | /**\r | |
| 2946 | Package. Uncore C-box 2 perfmon counter 2.\r | |
| 2947 | \r | |
| 2948 | @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)\r | |
| 2949 | @param EAX Lower 32-bits of MSR value.\r | |
| 2950 | @param EDX Upper 32-bits of MSR value.\r | |
| 2951 | \r | |
| 2952 | <b>Example usage</b>\r | |
| 2953 | @code\r | |
| 2954 | UINT64 Msr;\r | |
| 2955 | \r | |
| 2956 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);\r | |
| 2957 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);\r | |
| 2958 | @endcode\r | |
| a73ab083 | 2959 | @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r |
| c67b579c MK |
2960 | **/\r |
| 2961 | #define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r | |
| 2962 | \r | |
| 2963 | \r | |
| 2964 | /**\r | |
| 2965 | Package. Uncore C-box 2 perfmon counter 3.\r | |
| 2966 | \r | |
| 2967 | @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)\r | |
| 2968 | @param EAX Lower 32-bits of MSR value.\r | |
| 2969 | @param EDX Upper 32-bits of MSR value.\r | |
| 2970 | \r | |
| 2971 | <b>Example usage</b>\r | |
| 2972 | @code\r | |
| 2973 | UINT64 Msr;\r | |
| 2974 | \r | |
| 2975 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);\r | |
| 2976 | AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);\r | |
| 2977 | @endcode\r | |
| a73ab083 | 2978 | @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r |
| c67b579c MK |
2979 | **/\r |
| 2980 | #define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r | |
| 2981 | \r | |
| 2982 | \r | |
| 2983 | /**\r | |
| 2984 | Package. Uncore C-box 3 perfmon for box-wide control.\r | |
| 2985 | \r | |
| 2986 | @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)\r | |
| 2987 | @param EAX Lower 32-bits of MSR value.\r | |
| 2988 | @param EDX Upper 32-bits of MSR value.\r | |
| 2989 | \r | |
| 2990 | <b>Example usage</b>\r | |
| 2991 | @code\r | |
| 2992 | UINT64 Msr;\r | |
| 2993 | \r | |
| 2994 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);\r | |
| 2995 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);\r | |
| 2996 | @endcode\r | |
| a73ab083 | 2997 | @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
2998 | **/\r |
| 2999 | #define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r | |
| 3000 | \r | |
| 3001 | \r | |
| 3002 | /**\r | |
| 3003 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r | |
| 3004 | \r | |
| 3005 | @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)\r | |
| 3006 | @param EAX Lower 32-bits of MSR value.\r | |
| 3007 | @param EDX Upper 32-bits of MSR value.\r | |
| 3008 | \r | |
| 3009 | <b>Example usage</b>\r | |
| 3010 | @code\r | |
| 3011 | UINT64 Msr;\r | |
| 3012 | \r | |
| 3013 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);\r | |
| 3014 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);\r | |
| 3015 | @endcode\r | |
| a73ab083 | 3016 | @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
3017 | **/\r |
| 3018 | #define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r | |
| 3019 | \r | |
| 3020 | \r | |
| 3021 | /**\r | |
| 3022 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r | |
| 3023 | \r | |
| 3024 | @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)\r | |
| 3025 | @param EAX Lower 32-bits of MSR value.\r | |
| 3026 | @param EDX Upper 32-bits of MSR value.\r | |
| 3027 | \r | |
| 3028 | <b>Example usage</b>\r | |
| 3029 | @code\r | |
| 3030 | UINT64 Msr;\r | |
| 3031 | \r | |
| 3032 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);\r | |
| 3033 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);\r | |
| 3034 | @endcode\r | |
| a73ab083 | 3035 | @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
3036 | **/\r |
| 3037 | #define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r | |
| 3038 | \r | |
| 3039 | \r | |
| 3040 | /**\r | |
| 3041 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r | |
| 3042 | \r | |
| 3043 | @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)\r | |
| 3044 | @param EAX Lower 32-bits of MSR value.\r | |
| 3045 | @param EDX Upper 32-bits of MSR value.\r | |
| 3046 | \r | |
| 3047 | <b>Example usage</b>\r | |
| 3048 | @code\r | |
| 3049 | UINT64 Msr;\r | |
| 3050 | \r | |
| 3051 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);\r | |
| 3052 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);\r | |
| 3053 | @endcode\r | |
| a73ab083 | 3054 | @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
3055 | **/\r |
| 3056 | #define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r | |
| 3057 | \r | |
| 3058 | \r | |
| 3059 | /**\r | |
| 3060 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r | |
| 3061 | \r | |
| 3062 | @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)\r | |
| 3063 | @param EAX Lower 32-bits of MSR value.\r | |
| 3064 | @param EDX Upper 32-bits of MSR value.\r | |
| 3065 | \r | |
| 3066 | <b>Example usage</b>\r | |
| 3067 | @code\r | |
| 3068 | UINT64 Msr;\r | |
| 3069 | \r | |
| 3070 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);\r | |
| 3071 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);\r | |
| 3072 | @endcode\r | |
| a73ab083 | 3073 | @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
3074 | **/\r |
| 3075 | #define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r | |
| 3076 | \r | |
| 3077 | \r | |
| 3078 | /**\r | |
| 3079 | Package. Uncore C-box 3 perfmon box wide filter 0.\r | |
| 3080 | \r | |
| 3081 | @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)\r | |
| 3082 | @param EAX Lower 32-bits of MSR value.\r | |
| 3083 | @param EDX Upper 32-bits of MSR value.\r | |
| 3084 | \r | |
| 3085 | <b>Example usage</b>\r | |
| 3086 | @code\r | |
| 3087 | UINT64 Msr;\r | |
| 3088 | \r | |
| 3089 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);\r | |
| 3090 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);\r | |
| 3091 | @endcode\r | |
| a73ab083 | 3092 | @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
3093 | **/\r |
| 3094 | #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r | |
| 3095 | \r | |
| 3096 | \r | |
| 3097 | /**\r | |
| 3098 | Package. Uncore C-box 3 perfmon box wide filter1.\r | |
| 3099 | \r | |
| 3100 | @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)\r | |
| 3101 | @param EAX Lower 32-bits of MSR value.\r | |
| 3102 | @param EDX Upper 32-bits of MSR value.\r | |
| 3103 | \r | |
| 3104 | <b>Example usage</b>\r | |
| 3105 | @code\r | |
| 3106 | UINT64 Msr;\r | |
| 3107 | \r | |
| 3108 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);\r | |
| 3109 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);\r | |
| 3110 | @endcode\r | |
| a73ab083 | 3111 | @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
3112 | **/\r |
| 3113 | #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r | |
| 3114 | \r | |
| 3115 | \r | |
| 3116 | /**\r | |
| 3117 | Package. Uncore C-box 3 perfmon box wide status.\r | |
| 3118 | \r | |
| 3119 | @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)\r | |
| 3120 | @param EAX Lower 32-bits of MSR value.\r | |
| 3121 | @param EDX Upper 32-bits of MSR value.\r | |
| 3122 | \r | |
| 3123 | <b>Example usage</b>\r | |
| 3124 | @code\r | |
| 3125 | UINT64 Msr;\r | |
| 3126 | \r | |
| 3127 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);\r | |
| 3128 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);\r | |
| 3129 | @endcode\r | |
| a73ab083 | 3130 | @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
3131 | **/\r |
| 3132 | #define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r | |
| 3133 | \r | |
| 3134 | \r | |
| 3135 | /**\r | |
| 3136 | Package. Uncore C-box 3 perfmon counter 0.\r | |
| 3137 | \r | |
| 3138 | @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)\r | |
| 3139 | @param EAX Lower 32-bits of MSR value.\r | |
| 3140 | @param EDX Upper 32-bits of MSR value.\r | |
| 3141 | \r | |
| 3142 | <b>Example usage</b>\r | |
| 3143 | @code\r | |
| 3144 | UINT64 Msr;\r | |
| 3145 | \r | |
| 3146 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);\r | |
| 3147 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);\r | |
| 3148 | @endcode\r | |
| a73ab083 | 3149 | @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r |
| c67b579c MK |
3150 | **/\r |
| 3151 | #define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r | |
| 3152 | \r | |
| 3153 | \r | |
| 3154 | /**\r | |
| 3155 | Package. Uncore C-box 3 perfmon counter 1.\r | |
| 3156 | \r | |
| 3157 | @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)\r | |
| 3158 | @param EAX Lower 32-bits of MSR value.\r | |
| 3159 | @param EDX Upper 32-bits of MSR value.\r | |
| 3160 | \r | |
| 3161 | <b>Example usage</b>\r | |
| 3162 | @code\r | |
| 3163 | UINT64 Msr;\r | |
| 3164 | \r | |
| 3165 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);\r | |
| 3166 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);\r | |
| 3167 | @endcode\r | |
| a73ab083 | 3168 | @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r |
| c67b579c MK |
3169 | **/\r |
| 3170 | #define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r | |
| 3171 | \r | |
| 3172 | \r | |
| 3173 | /**\r | |
| 3174 | Package. Uncore C-box 3 perfmon counter 2.\r | |
| 3175 | \r | |
| 3176 | @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)\r | |
| 3177 | @param EAX Lower 32-bits of MSR value.\r | |
| 3178 | @param EDX Upper 32-bits of MSR value.\r | |
| 3179 | \r | |
| 3180 | <b>Example usage</b>\r | |
| 3181 | @code\r | |
| 3182 | UINT64 Msr;\r | |
| 3183 | \r | |
| 3184 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);\r | |
| 3185 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);\r | |
| 3186 | @endcode\r | |
| a73ab083 | 3187 | @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r |
| c67b579c MK |
3188 | **/\r |
| 3189 | #define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r | |
| 3190 | \r | |
| 3191 | \r | |
| 3192 | /**\r | |
| 3193 | Package. Uncore C-box 3 perfmon counter 3.\r | |
| 3194 | \r | |
| 3195 | @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)\r | |
| 3196 | @param EAX Lower 32-bits of MSR value.\r | |
| 3197 | @param EDX Upper 32-bits of MSR value.\r | |
| 3198 | \r | |
| 3199 | <b>Example usage</b>\r | |
| 3200 | @code\r | |
| 3201 | UINT64 Msr;\r | |
| 3202 | \r | |
| 3203 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);\r | |
| 3204 | AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);\r | |
| 3205 | @endcode\r | |
| a73ab083 | 3206 | @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r |
| c67b579c MK |
3207 | **/\r |
| 3208 | #define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r | |
| 3209 | \r | |
| 3210 | \r | |
| 3211 | /**\r | |
| 3212 | Package. Uncore C-box 4 perfmon for box-wide control.\r | |
| 3213 | \r | |
| 3214 | @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)\r | |
| 3215 | @param EAX Lower 32-bits of MSR value.\r | |
| 3216 | @param EDX Upper 32-bits of MSR value.\r | |
| 3217 | \r | |
| 3218 | <b>Example usage</b>\r | |
| 3219 | @code\r | |
| 3220 | UINT64 Msr;\r | |
| 3221 | \r | |
| 3222 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);\r | |
| 3223 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);\r | |
| 3224 | @endcode\r | |
| a73ab083 | 3225 | @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
3226 | **/\r |
| 3227 | #define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r | |
| 3228 | \r | |
| 3229 | \r | |
| 3230 | /**\r | |
| 3231 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r | |
| 3232 | \r | |
| 3233 | @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)\r | |
| 3234 | @param EAX Lower 32-bits of MSR value.\r | |
| 3235 | @param EDX Upper 32-bits of MSR value.\r | |
| 3236 | \r | |
| 3237 | <b>Example usage</b>\r | |
| 3238 | @code\r | |
| 3239 | UINT64 Msr;\r | |
| 3240 | \r | |
| 3241 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);\r | |
| 3242 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);\r | |
| 3243 | @endcode\r | |
| a73ab083 | 3244 | @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
3245 | **/\r |
| 3246 | #define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r | |
| 3247 | \r | |
| 3248 | \r | |
| 3249 | /**\r | |
| 3250 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r | |
| 3251 | \r | |
| 3252 | @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)\r | |
| 3253 | @param EAX Lower 32-bits of MSR value.\r | |
| 3254 | @param EDX Upper 32-bits of MSR value.\r | |
| 3255 | \r | |
| 3256 | <b>Example usage</b>\r | |
| 3257 | @code\r | |
| 3258 | UINT64 Msr;\r | |
| 3259 | \r | |
| 3260 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);\r | |
| 3261 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);\r | |
| 3262 | @endcode\r | |
| a73ab083 | 3263 | @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
3264 | **/\r |
| 3265 | #define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r | |
| 3266 | \r | |
| 3267 | \r | |
| 3268 | /**\r | |
| 3269 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r | |
| 3270 | \r | |
| 3271 | @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)\r | |
| 3272 | @param EAX Lower 32-bits of MSR value.\r | |
| 3273 | @param EDX Upper 32-bits of MSR value.\r | |
| 3274 | \r | |
| 3275 | <b>Example usage</b>\r | |
| 3276 | @code\r | |
| 3277 | UINT64 Msr;\r | |
| 3278 | \r | |
| 3279 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);\r | |
| 3280 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);\r | |
| 3281 | @endcode\r | |
| a73ab083 | 3282 | @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
3283 | **/\r |
| 3284 | #define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r | |
| 3285 | \r | |
| 3286 | \r | |
| 3287 | /**\r | |
| 3288 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r | |
| 3289 | \r | |
| 3290 | @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)\r | |
| 3291 | @param EAX Lower 32-bits of MSR value.\r | |
| 3292 | @param EDX Upper 32-bits of MSR value.\r | |
| 3293 | \r | |
| 3294 | <b>Example usage</b>\r | |
| 3295 | @code\r | |
| 3296 | UINT64 Msr;\r | |
| 3297 | \r | |
| 3298 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);\r | |
| 3299 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);\r | |
| 3300 | @endcode\r | |
| a73ab083 | 3301 | @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
3302 | **/\r |
| 3303 | #define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r | |
| 3304 | \r | |
| 3305 | \r | |
| 3306 | /**\r | |
| 3307 | Package. Uncore C-box 4 perfmon box wide filter 0.\r | |
| 3308 | \r | |
| 3309 | @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)\r | |
| 3310 | @param EAX Lower 32-bits of MSR value.\r | |
| 3311 | @param EDX Upper 32-bits of MSR value.\r | |
| 3312 | \r | |
| 3313 | <b>Example usage</b>\r | |
| 3314 | @code\r | |
| 3315 | UINT64 Msr;\r | |
| 3316 | \r | |
| 3317 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);\r | |
| 3318 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);\r | |
| 3319 | @endcode\r | |
| a73ab083 | 3320 | @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
3321 | **/\r |
| 3322 | #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r | |
| 3323 | \r | |
| 3324 | \r | |
| 3325 | /**\r | |
| 3326 | Package. Uncore C-box 4 perfmon box wide filter1.\r | |
| 3327 | \r | |
| 3328 | @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)\r | |
| 3329 | @param EAX Lower 32-bits of MSR value.\r | |
| 3330 | @param EDX Upper 32-bits of MSR value.\r | |
| 3331 | \r | |
| 3332 | <b>Example usage</b>\r | |
| 3333 | @code\r | |
| 3334 | UINT64 Msr;\r | |
| 3335 | \r | |
| 3336 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);\r | |
| 3337 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);\r | |
| 3338 | @endcode\r | |
| a73ab083 | 3339 | @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
3340 | **/\r |
| 3341 | #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r | |
| 3342 | \r | |
| 3343 | \r | |
| 3344 | /**\r | |
| 3345 | Package. Uncore C-box 4 perfmon box wide status.\r | |
| 3346 | \r | |
| 3347 | @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)\r | |
| 3348 | @param EAX Lower 32-bits of MSR value.\r | |
| 3349 | @param EDX Upper 32-bits of MSR value.\r | |
| 3350 | \r | |
| 3351 | <b>Example usage</b>\r | |
| 3352 | @code\r | |
| 3353 | UINT64 Msr;\r | |
| 3354 | \r | |
| 3355 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);\r | |
| 3356 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);\r | |
| 3357 | @endcode\r | |
| a73ab083 | 3358 | @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
3359 | **/\r |
| 3360 | #define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r | |
| 3361 | \r | |
| 3362 | \r | |
| 3363 | /**\r | |
| 3364 | Package. Uncore C-box 4 perfmon counter 0.\r | |
| 3365 | \r | |
| 3366 | @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)\r | |
| 3367 | @param EAX Lower 32-bits of MSR value.\r | |
| 3368 | @param EDX Upper 32-bits of MSR value.\r | |
| 3369 | \r | |
| 3370 | <b>Example usage</b>\r | |
| 3371 | @code\r | |
| 3372 | UINT64 Msr;\r | |
| 3373 | \r | |
| 3374 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);\r | |
| 3375 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);\r | |
| 3376 | @endcode\r | |
| a73ab083 | 3377 | @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r |
| c67b579c MK |
3378 | **/\r |
| 3379 | #define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r | |
| 3380 | \r | |
| 3381 | \r | |
| 3382 | /**\r | |
| 3383 | Package. Uncore C-box 4 perfmon counter 1.\r | |
| 3384 | \r | |
| 3385 | @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)\r | |
| 3386 | @param EAX Lower 32-bits of MSR value.\r | |
| 3387 | @param EDX Upper 32-bits of MSR value.\r | |
| 3388 | \r | |
| 3389 | <b>Example usage</b>\r | |
| 3390 | @code\r | |
| 3391 | UINT64 Msr;\r | |
| 3392 | \r | |
| 3393 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);\r | |
| 3394 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);\r | |
| 3395 | @endcode\r | |
| a73ab083 | 3396 | @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r |
| c67b579c MK |
3397 | **/\r |
| 3398 | #define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r | |
| 3399 | \r | |
| 3400 | \r | |
| 3401 | /**\r | |
| 3402 | Package. Uncore C-box 4 perfmon counter 2.\r | |
| 3403 | \r | |
| 3404 | @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)\r | |
| 3405 | @param EAX Lower 32-bits of MSR value.\r | |
| 3406 | @param EDX Upper 32-bits of MSR value.\r | |
| 3407 | \r | |
| 3408 | <b>Example usage</b>\r | |
| 3409 | @code\r | |
| 3410 | UINT64 Msr;\r | |
| 3411 | \r | |
| 3412 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);\r | |
| 3413 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);\r | |
| 3414 | @endcode\r | |
| a73ab083 | 3415 | @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r |
| c67b579c MK |
3416 | **/\r |
| 3417 | #define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r | |
| 3418 | \r | |
| 3419 | \r | |
| 3420 | /**\r | |
| 3421 | Package. Uncore C-box 4 perfmon counter 3.\r | |
| 3422 | \r | |
| 3423 | @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)\r | |
| 3424 | @param EAX Lower 32-bits of MSR value.\r | |
| 3425 | @param EDX Upper 32-bits of MSR value.\r | |
| 3426 | \r | |
| 3427 | <b>Example usage</b>\r | |
| 3428 | @code\r | |
| 3429 | UINT64 Msr;\r | |
| 3430 | \r | |
| 3431 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);\r | |
| 3432 | AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);\r | |
| 3433 | @endcode\r | |
| a73ab083 | 3434 | @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r |
| c67b579c MK |
3435 | **/\r |
| 3436 | #define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r | |
| 3437 | \r | |
| 3438 | \r | |
| 3439 | /**\r | |
| 3440 | Package. Uncore C-box 5 perfmon for box-wide control.\r | |
| 3441 | \r | |
| 3442 | @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)\r | |
| 3443 | @param EAX Lower 32-bits of MSR value.\r | |
| 3444 | @param EDX Upper 32-bits of MSR value.\r | |
| 3445 | \r | |
| 3446 | <b>Example usage</b>\r | |
| 3447 | @code\r | |
| 3448 | UINT64 Msr;\r | |
| 3449 | \r | |
| 3450 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);\r | |
| 3451 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);\r | |
| 3452 | @endcode\r | |
| a73ab083 | 3453 | @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
3454 | **/\r |
| 3455 | #define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r | |
| 3456 | \r | |
| 3457 | \r | |
| 3458 | /**\r | |
| 3459 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r | |
| 3460 | \r | |
| 3461 | @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)\r | |
| 3462 | @param EAX Lower 32-bits of MSR value.\r | |
| 3463 | @param EDX Upper 32-bits of MSR value.\r | |
| 3464 | \r | |
| 3465 | <b>Example usage</b>\r | |
| 3466 | @code\r | |
| 3467 | UINT64 Msr;\r | |
| 3468 | \r | |
| 3469 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);\r | |
| 3470 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);\r | |
| 3471 | @endcode\r | |
| a73ab083 | 3472 | @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
3473 | **/\r |
| 3474 | #define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r | |
| 3475 | \r | |
| 3476 | \r | |
| 3477 | /**\r | |
| 3478 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r | |
| 3479 | \r | |
| 3480 | @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)\r | |
| 3481 | @param EAX Lower 32-bits of MSR value.\r | |
| 3482 | @param EDX Upper 32-bits of MSR value.\r | |
| 3483 | \r | |
| 3484 | <b>Example usage</b>\r | |
| 3485 | @code\r | |
| 3486 | UINT64 Msr;\r | |
| 3487 | \r | |
| 3488 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);\r | |
| 3489 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);\r | |
| 3490 | @endcode\r | |
| a73ab083 | 3491 | @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
3492 | **/\r |
| 3493 | #define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r | |
| 3494 | \r | |
| 3495 | \r | |
| 3496 | /**\r | |
| 3497 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r | |
| 3498 | \r | |
| 3499 | @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)\r | |
| 3500 | @param EAX Lower 32-bits of MSR value.\r | |
| 3501 | @param EDX Upper 32-bits of MSR value.\r | |
| 3502 | \r | |
| 3503 | <b>Example usage</b>\r | |
| 3504 | @code\r | |
| 3505 | UINT64 Msr;\r | |
| 3506 | \r | |
| 3507 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);\r | |
| 3508 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);\r | |
| 3509 | @endcode\r | |
| a73ab083 | 3510 | @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
3511 | **/\r |
| 3512 | #define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r | |
| 3513 | \r | |
| 3514 | \r | |
| 3515 | /**\r | |
| 3516 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r | |
| 3517 | \r | |
| 3518 | @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)\r | |
| 3519 | @param EAX Lower 32-bits of MSR value.\r | |
| 3520 | @param EDX Upper 32-bits of MSR value.\r | |
| 3521 | \r | |
| 3522 | <b>Example usage</b>\r | |
| 3523 | @code\r | |
| 3524 | UINT64 Msr;\r | |
| 3525 | \r | |
| 3526 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);\r | |
| 3527 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);\r | |
| 3528 | @endcode\r | |
| a73ab083 | 3529 | @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
3530 | **/\r |
| 3531 | #define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r | |
| 3532 | \r | |
| 3533 | \r | |
| 3534 | /**\r | |
| 3535 | Package. Uncore C-box 5 perfmon box wide filter 0.\r | |
| 3536 | \r | |
| 3537 | @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)\r | |
| 3538 | @param EAX Lower 32-bits of MSR value.\r | |
| 3539 | @param EDX Upper 32-bits of MSR value.\r | |
| 3540 | \r | |
| 3541 | <b>Example usage</b>\r | |
| 3542 | @code\r | |
| 3543 | UINT64 Msr;\r | |
| 3544 | \r | |
| 3545 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);\r | |
| 3546 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);\r | |
| 3547 | @endcode\r | |
| a73ab083 | 3548 | @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
3549 | **/\r |
| 3550 | #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r | |
| 3551 | \r | |
| 3552 | \r | |
| 3553 | /**\r | |
| 3554 | Package. Uncore C-box 5 perfmon box wide filter1.\r | |
| 3555 | \r | |
| 3556 | @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)\r | |
| 3557 | @param EAX Lower 32-bits of MSR value.\r | |
| 3558 | @param EDX Upper 32-bits of MSR value.\r | |
| 3559 | \r | |
| 3560 | <b>Example usage</b>\r | |
| 3561 | @code\r | |
| 3562 | UINT64 Msr;\r | |
| 3563 | \r | |
| 3564 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);\r | |
| 3565 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);\r | |
| 3566 | @endcode\r | |
| a73ab083 | 3567 | @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
3568 | **/\r |
| 3569 | #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r | |
| 3570 | \r | |
| 3571 | \r | |
| 3572 | /**\r | |
| 3573 | Package. Uncore C-box 5 perfmon box wide status.\r | |
| 3574 | \r | |
| 3575 | @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)\r | |
| 3576 | @param EAX Lower 32-bits of MSR value.\r | |
| 3577 | @param EDX Upper 32-bits of MSR value.\r | |
| 3578 | \r | |
| 3579 | <b>Example usage</b>\r | |
| 3580 | @code\r | |
| 3581 | UINT64 Msr;\r | |
| 3582 | \r | |
| 3583 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);\r | |
| 3584 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);\r | |
| 3585 | @endcode\r | |
| a73ab083 | 3586 | @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
3587 | **/\r |
| 3588 | #define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r | |
| 3589 | \r | |
| 3590 | \r | |
| 3591 | /**\r | |
| 3592 | Package. Uncore C-box 5 perfmon counter 0.\r | |
| 3593 | \r | |
| 3594 | @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)\r | |
| 3595 | @param EAX Lower 32-bits of MSR value.\r | |
| 3596 | @param EDX Upper 32-bits of MSR value.\r | |
| 3597 | \r | |
| 3598 | <b>Example usage</b>\r | |
| 3599 | @code\r | |
| 3600 | UINT64 Msr;\r | |
| 3601 | \r | |
| 3602 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);\r | |
| 3603 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);\r | |
| 3604 | @endcode\r | |
| a73ab083 | 3605 | @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r |
| c67b579c MK |
3606 | **/\r |
| 3607 | #define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r | |
| 3608 | \r | |
| 3609 | \r | |
| 3610 | /**\r | |
| 3611 | Package. Uncore C-box 5 perfmon counter 1.\r | |
| 3612 | \r | |
| 3613 | @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)\r | |
| 3614 | @param EAX Lower 32-bits of MSR value.\r | |
| 3615 | @param EDX Upper 32-bits of MSR value.\r | |
| 3616 | \r | |
| 3617 | <b>Example usage</b>\r | |
| 3618 | @code\r | |
| 3619 | UINT64 Msr;\r | |
| 3620 | \r | |
| 3621 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);\r | |
| 3622 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);\r | |
| 3623 | @endcode\r | |
| a73ab083 | 3624 | @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r |
| c67b579c MK |
3625 | **/\r |
| 3626 | #define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r | |
| 3627 | \r | |
| 3628 | \r | |
| 3629 | /**\r | |
| 3630 | Package. Uncore C-box 5 perfmon counter 2.\r | |
| 3631 | \r | |
| 3632 | @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)\r | |
| 3633 | @param EAX Lower 32-bits of MSR value.\r | |
| 3634 | @param EDX Upper 32-bits of MSR value.\r | |
| 3635 | \r | |
| 3636 | <b>Example usage</b>\r | |
| 3637 | @code\r | |
| 3638 | UINT64 Msr;\r | |
| 3639 | \r | |
| 3640 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);\r | |
| 3641 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);\r | |
| 3642 | @endcode\r | |
| a73ab083 | 3643 | @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r |
| c67b579c MK |
3644 | **/\r |
| 3645 | #define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r | |
| 3646 | \r | |
| 3647 | \r | |
| 3648 | /**\r | |
| 3649 | Package. Uncore C-box 5 perfmon counter 3.\r | |
| 3650 | \r | |
| 3651 | @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)\r | |
| 3652 | @param EAX Lower 32-bits of MSR value.\r | |
| 3653 | @param EDX Upper 32-bits of MSR value.\r | |
| 3654 | \r | |
| 3655 | <b>Example usage</b>\r | |
| 3656 | @code\r | |
| 3657 | UINT64 Msr;\r | |
| 3658 | \r | |
| 3659 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);\r | |
| 3660 | AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);\r | |
| 3661 | @endcode\r | |
| a73ab083 | 3662 | @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r |
| c67b579c MK |
3663 | **/\r |
| 3664 | #define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r | |
| 3665 | \r | |
| 3666 | \r | |
| 3667 | /**\r | |
| 3668 | Package. Uncore C-box 6 perfmon for box-wide control.\r | |
| 3669 | \r | |
| 3670 | @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)\r | |
| 3671 | @param EAX Lower 32-bits of MSR value.\r | |
| 3672 | @param EDX Upper 32-bits of MSR value.\r | |
| 3673 | \r | |
| 3674 | <b>Example usage</b>\r | |
| 3675 | @code\r | |
| 3676 | UINT64 Msr;\r | |
| 3677 | \r | |
| 3678 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);\r | |
| 3679 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);\r | |
| 3680 | @endcode\r | |
| a73ab083 | 3681 | @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
3682 | **/\r |
| 3683 | #define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r | |
| 3684 | \r | |
| 3685 | \r | |
| 3686 | /**\r | |
| 3687 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r | |
| 3688 | \r | |
| 3689 | @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)\r | |
| 3690 | @param EAX Lower 32-bits of MSR value.\r | |
| 3691 | @param EDX Upper 32-bits of MSR value.\r | |
| 3692 | \r | |
| 3693 | <b>Example usage</b>\r | |
| 3694 | @code\r | |
| 3695 | UINT64 Msr;\r | |
| 3696 | \r | |
| 3697 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);\r | |
| 3698 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);\r | |
| 3699 | @endcode\r | |
| a73ab083 | 3700 | @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
3701 | **/\r |
| 3702 | #define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r | |
| 3703 | \r | |
| 3704 | \r | |
| 3705 | /**\r | |
| 3706 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r | |
| 3707 | \r | |
| 3708 | @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)\r | |
| 3709 | @param EAX Lower 32-bits of MSR value.\r | |
| 3710 | @param EDX Upper 32-bits of MSR value.\r | |
| 3711 | \r | |
| 3712 | <b>Example usage</b>\r | |
| 3713 | @code\r | |
| 3714 | UINT64 Msr;\r | |
| 3715 | \r | |
| 3716 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);\r | |
| 3717 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);\r | |
| 3718 | @endcode\r | |
| a73ab083 | 3719 | @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
3720 | **/\r |
| 3721 | #define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r | |
| 3722 | \r | |
| 3723 | \r | |
| 3724 | /**\r | |
| 3725 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r | |
| 3726 | \r | |
| 3727 | @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)\r | |
| 3728 | @param EAX Lower 32-bits of MSR value.\r | |
| 3729 | @param EDX Upper 32-bits of MSR value.\r | |
| 3730 | \r | |
| 3731 | <b>Example usage</b>\r | |
| 3732 | @code\r | |
| 3733 | UINT64 Msr;\r | |
| 3734 | \r | |
| 3735 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);\r | |
| 3736 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);\r | |
| 3737 | @endcode\r | |
| a73ab083 | 3738 | @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
3739 | **/\r |
| 3740 | #define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r | |
| 3741 | \r | |
| 3742 | \r | |
| 3743 | /**\r | |
| 3744 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r | |
| 3745 | \r | |
| 3746 | @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)\r | |
| 3747 | @param EAX Lower 32-bits of MSR value.\r | |
| 3748 | @param EDX Upper 32-bits of MSR value.\r | |
| 3749 | \r | |
| 3750 | <b>Example usage</b>\r | |
| 3751 | @code\r | |
| 3752 | UINT64 Msr;\r | |
| 3753 | \r | |
| 3754 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);\r | |
| 3755 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);\r | |
| 3756 | @endcode\r | |
| a73ab083 | 3757 | @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
3758 | **/\r |
| 3759 | #define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r | |
| 3760 | \r | |
| 3761 | \r | |
| 3762 | /**\r | |
| 3763 | Package. Uncore C-box 6 perfmon box wide filter 0.\r | |
| 3764 | \r | |
| 3765 | @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)\r | |
| 3766 | @param EAX Lower 32-bits of MSR value.\r | |
| 3767 | @param EDX Upper 32-bits of MSR value.\r | |
| 3768 | \r | |
| 3769 | <b>Example usage</b>\r | |
| 3770 | @code\r | |
| 3771 | UINT64 Msr;\r | |
| 3772 | \r | |
| 3773 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);\r | |
| 3774 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);\r | |
| 3775 | @endcode\r | |
| a73ab083 | 3776 | @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
3777 | **/\r |
| 3778 | #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r | |
| 3779 | \r | |
| 3780 | \r | |
| 3781 | /**\r | |
| 3782 | Package. Uncore C-box 6 perfmon box wide filter1.\r | |
| 3783 | \r | |
| 3784 | @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)\r | |
| 3785 | @param EAX Lower 32-bits of MSR value.\r | |
| 3786 | @param EDX Upper 32-bits of MSR value.\r | |
| 3787 | \r | |
| 3788 | <b>Example usage</b>\r | |
| 3789 | @code\r | |
| 3790 | UINT64 Msr;\r | |
| 3791 | \r | |
| 3792 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);\r | |
| 3793 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);\r | |
| 3794 | @endcode\r | |
| a73ab083 | 3795 | @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
3796 | **/\r |
| 3797 | #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r | |
| 3798 | \r | |
| 3799 | \r | |
| 3800 | /**\r | |
| 3801 | Package. Uncore C-box 6 perfmon box wide status.\r | |
| 3802 | \r | |
| 3803 | @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)\r | |
| 3804 | @param EAX Lower 32-bits of MSR value.\r | |
| 3805 | @param EDX Upper 32-bits of MSR value.\r | |
| 3806 | \r | |
| 3807 | <b>Example usage</b>\r | |
| 3808 | @code\r | |
| 3809 | UINT64 Msr;\r | |
| 3810 | \r | |
| 3811 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);\r | |
| 3812 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);\r | |
| 3813 | @endcode\r | |
| a73ab083 | 3814 | @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
3815 | **/\r |
| 3816 | #define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r | |
| 3817 | \r | |
| 3818 | \r | |
| 3819 | /**\r | |
| 3820 | Package. Uncore C-box 6 perfmon counter 0.\r | |
| 3821 | \r | |
| 3822 | @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)\r | |
| 3823 | @param EAX Lower 32-bits of MSR value.\r | |
| 3824 | @param EDX Upper 32-bits of MSR value.\r | |
| 3825 | \r | |
| 3826 | <b>Example usage</b>\r | |
| 3827 | @code\r | |
| 3828 | UINT64 Msr;\r | |
| 3829 | \r | |
| 3830 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);\r | |
| 3831 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);\r | |
| 3832 | @endcode\r | |
| a73ab083 | 3833 | @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r |
| c67b579c MK |
3834 | **/\r |
| 3835 | #define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r | |
| 3836 | \r | |
| 3837 | \r | |
| 3838 | /**\r | |
| 3839 | Package. Uncore C-box 6 perfmon counter 1.\r | |
| 3840 | \r | |
| 3841 | @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)\r | |
| 3842 | @param EAX Lower 32-bits of MSR value.\r | |
| 3843 | @param EDX Upper 32-bits of MSR value.\r | |
| 3844 | \r | |
| 3845 | <b>Example usage</b>\r | |
| 3846 | @code\r | |
| 3847 | UINT64 Msr;\r | |
| 3848 | \r | |
| 3849 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);\r | |
| 3850 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);\r | |
| 3851 | @endcode\r | |
| a73ab083 | 3852 | @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r |
| c67b579c MK |
3853 | **/\r |
| 3854 | #define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r | |
| 3855 | \r | |
| 3856 | \r | |
| 3857 | /**\r | |
| 3858 | Package. Uncore C-box 6 perfmon counter 2.\r | |
| 3859 | \r | |
| 3860 | @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)\r | |
| 3861 | @param EAX Lower 32-bits of MSR value.\r | |
| 3862 | @param EDX Upper 32-bits of MSR value.\r | |
| 3863 | \r | |
| 3864 | <b>Example usage</b>\r | |
| 3865 | @code\r | |
| 3866 | UINT64 Msr;\r | |
| 3867 | \r | |
| 3868 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);\r | |
| 3869 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);\r | |
| 3870 | @endcode\r | |
| a73ab083 | 3871 | @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r |
| c67b579c MK |
3872 | **/\r |
| 3873 | #define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r | |
| 3874 | \r | |
| 3875 | \r | |
| 3876 | /**\r | |
| 3877 | Package. Uncore C-box 6 perfmon counter 3.\r | |
| 3878 | \r | |
| 3879 | @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)\r | |
| 3880 | @param EAX Lower 32-bits of MSR value.\r | |
| 3881 | @param EDX Upper 32-bits of MSR value.\r | |
| 3882 | \r | |
| 3883 | <b>Example usage</b>\r | |
| 3884 | @code\r | |
| 3885 | UINT64 Msr;\r | |
| 3886 | \r | |
| 3887 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);\r | |
| 3888 | AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);\r | |
| 3889 | @endcode\r | |
| a73ab083 | 3890 | @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r |
| c67b579c MK |
3891 | **/\r |
| 3892 | #define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r | |
| 3893 | \r | |
| 3894 | \r | |
| 3895 | /**\r | |
| 3896 | Package. Uncore C-box 7 perfmon for box-wide control.\r | |
| 3897 | \r | |
| 3898 | @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)\r | |
| 3899 | @param EAX Lower 32-bits of MSR value.\r | |
| 3900 | @param EDX Upper 32-bits of MSR value.\r | |
| 3901 | \r | |
| 3902 | <b>Example usage</b>\r | |
| 3903 | @code\r | |
| 3904 | UINT64 Msr;\r | |
| 3905 | \r | |
| 3906 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);\r | |
| 3907 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);\r | |
| 3908 | @endcode\r | |
| a73ab083 | 3909 | @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
3910 | **/\r |
| 3911 | #define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r | |
| 3912 | \r | |
| 3913 | \r | |
| 3914 | /**\r | |
| 3915 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r | |
| 3916 | \r | |
| 3917 | @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)\r | |
| 3918 | @param EAX Lower 32-bits of MSR value.\r | |
| 3919 | @param EDX Upper 32-bits of MSR value.\r | |
| 3920 | \r | |
| 3921 | <b>Example usage</b>\r | |
| 3922 | @code\r | |
| 3923 | UINT64 Msr;\r | |
| 3924 | \r | |
| 3925 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);\r | |
| 3926 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);\r | |
| 3927 | @endcode\r | |
| a73ab083 | 3928 | @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
3929 | **/\r |
| 3930 | #define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r | |
| 3931 | \r | |
| 3932 | \r | |
| 3933 | /**\r | |
| 3934 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r | |
| 3935 | \r | |
| 3936 | @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)\r | |
| 3937 | @param EAX Lower 32-bits of MSR value.\r | |
| 3938 | @param EDX Upper 32-bits of MSR value.\r | |
| 3939 | \r | |
| 3940 | <b>Example usage</b>\r | |
| 3941 | @code\r | |
| 3942 | UINT64 Msr;\r | |
| 3943 | \r | |
| 3944 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);\r | |
| 3945 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);\r | |
| 3946 | @endcode\r | |
| a73ab083 | 3947 | @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
3948 | **/\r |
| 3949 | #define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r | |
| 3950 | \r | |
| 3951 | \r | |
| 3952 | /**\r | |
| 3953 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r | |
| 3954 | \r | |
| 3955 | @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)\r | |
| 3956 | @param EAX Lower 32-bits of MSR value.\r | |
| 3957 | @param EDX Upper 32-bits of MSR value.\r | |
| 3958 | \r | |
| 3959 | <b>Example usage</b>\r | |
| 3960 | @code\r | |
| 3961 | UINT64 Msr;\r | |
| 3962 | \r | |
| 3963 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);\r | |
| 3964 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);\r | |
| 3965 | @endcode\r | |
| a73ab083 | 3966 | @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
3967 | **/\r |
| 3968 | #define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r | |
| 3969 | \r | |
| 3970 | \r | |
| 3971 | /**\r | |
| 3972 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r | |
| 3973 | \r | |
| 3974 | @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)\r | |
| 3975 | @param EAX Lower 32-bits of MSR value.\r | |
| 3976 | @param EDX Upper 32-bits of MSR value.\r | |
| 3977 | \r | |
| 3978 | <b>Example usage</b>\r | |
| 3979 | @code\r | |
| 3980 | UINT64 Msr;\r | |
| 3981 | \r | |
| 3982 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);\r | |
| 3983 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);\r | |
| 3984 | @endcode\r | |
| a73ab083 | 3985 | @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
3986 | **/\r |
| 3987 | #define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r | |
| 3988 | \r | |
| 3989 | \r | |
| 3990 | /**\r | |
| 3991 | Package. Uncore C-box 7 perfmon box wide filter 0.\r | |
| 3992 | \r | |
| 3993 | @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)\r | |
| 3994 | @param EAX Lower 32-bits of MSR value.\r | |
| 3995 | @param EDX Upper 32-bits of MSR value.\r | |
| 3996 | \r | |
| 3997 | <b>Example usage</b>\r | |
| 3998 | @code\r | |
| 3999 | UINT64 Msr;\r | |
| 4000 | \r | |
| 4001 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);\r | |
| 4002 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);\r | |
| 4003 | @endcode\r | |
| a73ab083 | 4004 | @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
4005 | **/\r |
| 4006 | #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r | |
| 4007 | \r | |
| 4008 | \r | |
| 4009 | /**\r | |
| 4010 | Package. Uncore C-box 7 perfmon box wide filter1.\r | |
| 4011 | \r | |
| 4012 | @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)\r | |
| 4013 | @param EAX Lower 32-bits of MSR value.\r | |
| 4014 | @param EDX Upper 32-bits of MSR value.\r | |
| 4015 | \r | |
| 4016 | <b>Example usage</b>\r | |
| 4017 | @code\r | |
| 4018 | UINT64 Msr;\r | |
| 4019 | \r | |
| 4020 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);\r | |
| 4021 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);\r | |
| 4022 | @endcode\r | |
| a73ab083 | 4023 | @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
4024 | **/\r |
| 4025 | #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r | |
| 4026 | \r | |
| 4027 | \r | |
| 4028 | /**\r | |
| 4029 | Package. Uncore C-box 7 perfmon box wide status.\r | |
| 4030 | \r | |
| 4031 | @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)\r | |
| 4032 | @param EAX Lower 32-bits of MSR value.\r | |
| 4033 | @param EDX Upper 32-bits of MSR value.\r | |
| 4034 | \r | |
| 4035 | <b>Example usage</b>\r | |
| 4036 | @code\r | |
| 4037 | UINT64 Msr;\r | |
| 4038 | \r | |
| 4039 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);\r | |
| 4040 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);\r | |
| 4041 | @endcode\r | |
| a73ab083 | 4042 | @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
4043 | **/\r |
| 4044 | #define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r | |
| 4045 | \r | |
| 4046 | \r | |
| 4047 | /**\r | |
| 4048 | Package. Uncore C-box 7 perfmon counter 0.\r | |
| 4049 | \r | |
| 4050 | @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)\r | |
| 4051 | @param EAX Lower 32-bits of MSR value.\r | |
| 4052 | @param EDX Upper 32-bits of MSR value.\r | |
| 4053 | \r | |
| 4054 | <b>Example usage</b>\r | |
| 4055 | @code\r | |
| 4056 | UINT64 Msr;\r | |
| 4057 | \r | |
| 4058 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);\r | |
| 4059 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);\r | |
| 4060 | @endcode\r | |
| a73ab083 | 4061 | @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r |
| c67b579c MK |
4062 | **/\r |
| 4063 | #define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r | |
| 4064 | \r | |
| 4065 | \r | |
| 4066 | /**\r | |
| 4067 | Package. Uncore C-box 7 perfmon counter 1.\r | |
| 4068 | \r | |
| 4069 | @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)\r | |
| 4070 | @param EAX Lower 32-bits of MSR value.\r | |
| 4071 | @param EDX Upper 32-bits of MSR value.\r | |
| 4072 | \r | |
| 4073 | <b>Example usage</b>\r | |
| 4074 | @code\r | |
| 4075 | UINT64 Msr;\r | |
| 4076 | \r | |
| 4077 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);\r | |
| 4078 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);\r | |
| 4079 | @endcode\r | |
| a73ab083 | 4080 | @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r |
| c67b579c MK |
4081 | **/\r |
| 4082 | #define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r | |
| 4083 | \r | |
| 4084 | \r | |
| 4085 | /**\r | |
| 4086 | Package. Uncore C-box 7 perfmon counter 2.\r | |
| 4087 | \r | |
| 4088 | @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)\r | |
| 4089 | @param EAX Lower 32-bits of MSR value.\r | |
| 4090 | @param EDX Upper 32-bits of MSR value.\r | |
| 4091 | \r | |
| 4092 | <b>Example usage</b>\r | |
| 4093 | @code\r | |
| 4094 | UINT64 Msr;\r | |
| 4095 | \r | |
| 4096 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);\r | |
| 4097 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);\r | |
| 4098 | @endcode\r | |
| a73ab083 | 4099 | @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r |
| c67b579c MK |
4100 | **/\r |
| 4101 | #define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r | |
| 4102 | \r | |
| 4103 | \r | |
| 4104 | /**\r | |
| 4105 | Package. Uncore C-box 7 perfmon counter 3.\r | |
| 4106 | \r | |
| 4107 | @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)\r | |
| 4108 | @param EAX Lower 32-bits of MSR value.\r | |
| 4109 | @param EDX Upper 32-bits of MSR value.\r | |
| 4110 | \r | |
| 4111 | <b>Example usage</b>\r | |
| 4112 | @code\r | |
| 4113 | UINT64 Msr;\r | |
| 4114 | \r | |
| 4115 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);\r | |
| 4116 | AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);\r | |
| 4117 | @endcode\r | |
| a73ab083 | 4118 | @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r |
| c67b579c MK |
4119 | **/\r |
| 4120 | #define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r | |
| 4121 | \r | |
| 4122 | \r | |
| 4123 | /**\r | |
| 4124 | Package. Uncore C-box 8 perfmon local box wide control.\r | |
| 4125 | \r | |
| 4126 | @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)\r | |
| 4127 | @param EAX Lower 32-bits of MSR value.\r | |
| 4128 | @param EDX Upper 32-bits of MSR value.\r | |
| 4129 | \r | |
| 4130 | <b>Example usage</b>\r | |
| 4131 | @code\r | |
| 4132 | UINT64 Msr;\r | |
| 4133 | \r | |
| 4134 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);\r | |
| 4135 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);\r | |
| 4136 | @endcode\r | |
| a73ab083 | 4137 | @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
4138 | **/\r |
| 4139 | #define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r | |
| 4140 | \r | |
| 4141 | \r | |
| 4142 | /**\r | |
| 4143 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r | |
| 4144 | \r | |
| 4145 | @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)\r | |
| 4146 | @param EAX Lower 32-bits of MSR value.\r | |
| 4147 | @param EDX Upper 32-bits of MSR value.\r | |
| 4148 | \r | |
| 4149 | <b>Example usage</b>\r | |
| 4150 | @code\r | |
| 4151 | UINT64 Msr;\r | |
| 4152 | \r | |
| 4153 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);\r | |
| 4154 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);\r | |
| 4155 | @endcode\r | |
| a73ab083 | 4156 | @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
4157 | **/\r |
| 4158 | #define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r | |
| 4159 | \r | |
| 4160 | \r | |
| 4161 | /**\r | |
| 4162 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r | |
| 4163 | \r | |
| 4164 | @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)\r | |
| 4165 | @param EAX Lower 32-bits of MSR value.\r | |
| 4166 | @param EDX Upper 32-bits of MSR value.\r | |
| 4167 | \r | |
| 4168 | <b>Example usage</b>\r | |
| 4169 | @code\r | |
| 4170 | UINT64 Msr;\r | |
| 4171 | \r | |
| 4172 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);\r | |
| 4173 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);\r | |
| 4174 | @endcode\r | |
| a73ab083 | 4175 | @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
4176 | **/\r |
| 4177 | #define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r | |
| 4178 | \r | |
| 4179 | \r | |
| 4180 | /**\r | |
| 4181 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r | |
| 4182 | \r | |
| 4183 | @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)\r | |
| 4184 | @param EAX Lower 32-bits of MSR value.\r | |
| 4185 | @param EDX Upper 32-bits of MSR value.\r | |
| 4186 | \r | |
| 4187 | <b>Example usage</b>\r | |
| 4188 | @code\r | |
| 4189 | UINT64 Msr;\r | |
| 4190 | \r | |
| 4191 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);\r | |
| 4192 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);\r | |
| 4193 | @endcode\r | |
| a73ab083 | 4194 | @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
4195 | **/\r |
| 4196 | #define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r | |
| 4197 | \r | |
| 4198 | \r | |
| 4199 | /**\r | |
| 4200 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r | |
| 4201 | \r | |
| 4202 | @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)\r | |
| 4203 | @param EAX Lower 32-bits of MSR value.\r | |
| 4204 | @param EDX Upper 32-bits of MSR value.\r | |
| 4205 | \r | |
| 4206 | <b>Example usage</b>\r | |
| 4207 | @code\r | |
| 4208 | UINT64 Msr;\r | |
| 4209 | \r | |
| 4210 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);\r | |
| 4211 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);\r | |
| 4212 | @endcode\r | |
| a73ab083 | 4213 | @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
4214 | **/\r |
| 4215 | #define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r | |
| 4216 | \r | |
| 4217 | \r | |
| 4218 | /**\r | |
| 4219 | Package. Uncore C-box 8 perfmon box wide filter0.\r | |
| 4220 | \r | |
| 4221 | @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)\r | |
| 4222 | @param EAX Lower 32-bits of MSR value.\r | |
| 4223 | @param EDX Upper 32-bits of MSR value.\r | |
| 4224 | \r | |
| 4225 | <b>Example usage</b>\r | |
| 4226 | @code\r | |
| 4227 | UINT64 Msr;\r | |
| 4228 | \r | |
| 4229 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);\r | |
| 4230 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);\r | |
| 4231 | @endcode\r | |
| a73ab083 | 4232 | @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
4233 | **/\r |
| 4234 | #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r | |
| 4235 | \r | |
| 4236 | \r | |
| 4237 | /**\r | |
| 4238 | Package. Uncore C-box 8 perfmon box wide filter1.\r | |
| 4239 | \r | |
| 4240 | @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)\r | |
| 4241 | @param EAX Lower 32-bits of MSR value.\r | |
| 4242 | @param EDX Upper 32-bits of MSR value.\r | |
| 4243 | \r | |
| 4244 | <b>Example usage</b>\r | |
| 4245 | @code\r | |
| 4246 | UINT64 Msr;\r | |
| 4247 | \r | |
| 4248 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);\r | |
| 4249 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);\r | |
| 4250 | @endcode\r | |
| a73ab083 | 4251 | @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
4252 | **/\r |
| 4253 | #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r | |
| 4254 | \r | |
| 4255 | \r | |
| 4256 | /**\r | |
| 4257 | Package. Uncore C-box 8 perfmon box wide status.\r | |
| 4258 | \r | |
| 4259 | @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)\r | |
| 4260 | @param EAX Lower 32-bits of MSR value.\r | |
| 4261 | @param EDX Upper 32-bits of MSR value.\r | |
| 4262 | \r | |
| 4263 | <b>Example usage</b>\r | |
| 4264 | @code\r | |
| 4265 | UINT64 Msr;\r | |
| 4266 | \r | |
| 4267 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);\r | |
| 4268 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);\r | |
| 4269 | @endcode\r | |
| a73ab083 | 4270 | @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
4271 | **/\r |
| 4272 | #define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r | |
| 4273 | \r | |
| 4274 | \r | |
| 4275 | /**\r | |
| 4276 | Package. Uncore C-box 8 perfmon counter 0.\r | |
| 4277 | \r | |
| 4278 | @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)\r | |
| 4279 | @param EAX Lower 32-bits of MSR value.\r | |
| 4280 | @param EDX Upper 32-bits of MSR value.\r | |
| 4281 | \r | |
| 4282 | <b>Example usage</b>\r | |
| 4283 | @code\r | |
| 4284 | UINT64 Msr;\r | |
| 4285 | \r | |
| 4286 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);\r | |
| 4287 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);\r | |
| 4288 | @endcode\r | |
| a73ab083 | 4289 | @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r |
| c67b579c MK |
4290 | **/\r |
| 4291 | #define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r | |
| 4292 | \r | |
| 4293 | \r | |
| 4294 | /**\r | |
| 4295 | Package. Uncore C-box 8 perfmon counter 1.\r | |
| 4296 | \r | |
| 4297 | @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)\r | |
| 4298 | @param EAX Lower 32-bits of MSR value.\r | |
| 4299 | @param EDX Upper 32-bits of MSR value.\r | |
| 4300 | \r | |
| 4301 | <b>Example usage</b>\r | |
| 4302 | @code\r | |
| 4303 | UINT64 Msr;\r | |
| 4304 | \r | |
| 4305 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);\r | |
| 4306 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);\r | |
| 4307 | @endcode\r | |
| a73ab083 | 4308 | @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r |
| c67b579c MK |
4309 | **/\r |
| 4310 | #define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r | |
| 4311 | \r | |
| 4312 | \r | |
| 4313 | /**\r | |
| 4314 | Package. Uncore C-box 8 perfmon counter 2.\r | |
| 4315 | \r | |
| 4316 | @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)\r | |
| 4317 | @param EAX Lower 32-bits of MSR value.\r | |
| 4318 | @param EDX Upper 32-bits of MSR value.\r | |
| 4319 | \r | |
| 4320 | <b>Example usage</b>\r | |
| 4321 | @code\r | |
| 4322 | UINT64 Msr;\r | |
| 4323 | \r | |
| 4324 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);\r | |
| 4325 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);\r | |
| 4326 | @endcode\r | |
| a73ab083 | 4327 | @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r |
| c67b579c MK |
4328 | **/\r |
| 4329 | #define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r | |
| 4330 | \r | |
| 4331 | \r | |
| 4332 | /**\r | |
| 4333 | Package. Uncore C-box 8 perfmon counter 3.\r | |
| 4334 | \r | |
| 4335 | @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)\r | |
| 4336 | @param EAX Lower 32-bits of MSR value.\r | |
| 4337 | @param EDX Upper 32-bits of MSR value.\r | |
| 4338 | \r | |
| 4339 | <b>Example usage</b>\r | |
| 4340 | @code\r | |
| 4341 | UINT64 Msr;\r | |
| 4342 | \r | |
| 4343 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);\r | |
| 4344 | AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);\r | |
| 4345 | @endcode\r | |
| a73ab083 | 4346 | @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r |
| c67b579c MK |
4347 | **/\r |
| 4348 | #define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r | |
| 4349 | \r | |
| 4350 | \r | |
| 4351 | /**\r | |
| 4352 | Package. Uncore C-box 9 perfmon local box wide control.\r | |
| 4353 | \r | |
| 4354 | @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)\r | |
| 4355 | @param EAX Lower 32-bits of MSR value.\r | |
| 4356 | @param EDX Upper 32-bits of MSR value.\r | |
| 4357 | \r | |
| 4358 | <b>Example usage</b>\r | |
| 4359 | @code\r | |
| 4360 | UINT64 Msr;\r | |
| 4361 | \r | |
| 4362 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);\r | |
| 4363 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);\r | |
| 4364 | @endcode\r | |
| a73ab083 | 4365 | @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
4366 | **/\r |
| 4367 | #define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r | |
| 4368 | \r | |
| 4369 | \r | |
| 4370 | /**\r | |
| 4371 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r | |
| 4372 | \r | |
| 4373 | @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)\r | |
| 4374 | @param EAX Lower 32-bits of MSR value.\r | |
| 4375 | @param EDX Upper 32-bits of MSR value.\r | |
| 4376 | \r | |
| 4377 | <b>Example usage</b>\r | |
| 4378 | @code\r | |
| 4379 | UINT64 Msr;\r | |
| 4380 | \r | |
| 4381 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);\r | |
| 4382 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);\r | |
| 4383 | @endcode\r | |
| a73ab083 | 4384 | @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
4385 | **/\r |
| 4386 | #define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r | |
| 4387 | \r | |
| 4388 | \r | |
| 4389 | /**\r | |
| 4390 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r | |
| 4391 | \r | |
| 4392 | @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)\r | |
| 4393 | @param EAX Lower 32-bits of MSR value.\r | |
| 4394 | @param EDX Upper 32-bits of MSR value.\r | |
| 4395 | \r | |
| 4396 | <b>Example usage</b>\r | |
| 4397 | @code\r | |
| 4398 | UINT64 Msr;\r | |
| 4399 | \r | |
| 4400 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);\r | |
| 4401 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);\r | |
| 4402 | @endcode\r | |
| a73ab083 | 4403 | @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
4404 | **/\r |
| 4405 | #define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r | |
| 4406 | \r | |
| 4407 | \r | |
| 4408 | /**\r | |
| 4409 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r | |
| 4410 | \r | |
| 4411 | @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)\r | |
| 4412 | @param EAX Lower 32-bits of MSR value.\r | |
| 4413 | @param EDX Upper 32-bits of MSR value.\r | |
| 4414 | \r | |
| 4415 | <b>Example usage</b>\r | |
| 4416 | @code\r | |
| 4417 | UINT64 Msr;\r | |
| 4418 | \r | |
| 4419 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);\r | |
| 4420 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);\r | |
| 4421 | @endcode\r | |
| a73ab083 | 4422 | @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
4423 | **/\r |
| 4424 | #define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r | |
| 4425 | \r | |
| 4426 | \r | |
| 4427 | /**\r | |
| 4428 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r | |
| 4429 | \r | |
| 4430 | @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)\r | |
| 4431 | @param EAX Lower 32-bits of MSR value.\r | |
| 4432 | @param EDX Upper 32-bits of MSR value.\r | |
| 4433 | \r | |
| 4434 | <b>Example usage</b>\r | |
| 4435 | @code\r | |
| 4436 | UINT64 Msr;\r | |
| 4437 | \r | |
| 4438 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);\r | |
| 4439 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);\r | |
| 4440 | @endcode\r | |
| a73ab083 | 4441 | @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
4442 | **/\r |
| 4443 | #define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r | |
| 4444 | \r | |
| 4445 | \r | |
| 4446 | /**\r | |
| 4447 | Package. Uncore C-box 9 perfmon box wide filter0.\r | |
| 4448 | \r | |
| 4449 | @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)\r | |
| 4450 | @param EAX Lower 32-bits of MSR value.\r | |
| 4451 | @param EDX Upper 32-bits of MSR value.\r | |
| 4452 | \r | |
| 4453 | <b>Example usage</b>\r | |
| 4454 | @code\r | |
| 4455 | UINT64 Msr;\r | |
| 4456 | \r | |
| 4457 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);\r | |
| 4458 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);\r | |
| 4459 | @endcode\r | |
| a73ab083 | 4460 | @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
4461 | **/\r |
| 4462 | #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r | |
| 4463 | \r | |
| 4464 | \r | |
| 4465 | /**\r | |
| 4466 | Package. Uncore C-box 9 perfmon box wide filter1.\r | |
| 4467 | \r | |
| 4468 | @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)\r | |
| 4469 | @param EAX Lower 32-bits of MSR value.\r | |
| 4470 | @param EDX Upper 32-bits of MSR value.\r | |
| 4471 | \r | |
| 4472 | <b>Example usage</b>\r | |
| 4473 | @code\r | |
| 4474 | UINT64 Msr;\r | |
| 4475 | \r | |
| 4476 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);\r | |
| 4477 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);\r | |
| 4478 | @endcode\r | |
| a73ab083 | 4479 | @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
4480 | **/\r |
| 4481 | #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r | |
| 4482 | \r | |
| 4483 | \r | |
| 4484 | /**\r | |
| 4485 | Package. Uncore C-box 9 perfmon box wide status.\r | |
| 4486 | \r | |
| 4487 | @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)\r | |
| 4488 | @param EAX Lower 32-bits of MSR value.\r | |
| 4489 | @param EDX Upper 32-bits of MSR value.\r | |
| 4490 | \r | |
| 4491 | <b>Example usage</b>\r | |
| 4492 | @code\r | |
| 4493 | UINT64 Msr;\r | |
| 4494 | \r | |
| 4495 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);\r | |
| 4496 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);\r | |
| 4497 | @endcode\r | |
| a73ab083 | 4498 | @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
4499 | **/\r |
| 4500 | #define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r | |
| 4501 | \r | |
| 4502 | \r | |
| 4503 | /**\r | |
| 4504 | Package. Uncore C-box 9 perfmon counter 0.\r | |
| 4505 | \r | |
| 4506 | @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)\r | |
| 4507 | @param EAX Lower 32-bits of MSR value.\r | |
| 4508 | @param EDX Upper 32-bits of MSR value.\r | |
| 4509 | \r | |
| 4510 | <b>Example usage</b>\r | |
| 4511 | @code\r | |
| 4512 | UINT64 Msr;\r | |
| 4513 | \r | |
| 4514 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);\r | |
| 4515 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);\r | |
| 4516 | @endcode\r | |
| a73ab083 | 4517 | @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r |
| c67b579c MK |
4518 | **/\r |
| 4519 | #define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r | |
| 4520 | \r | |
| 4521 | \r | |
| 4522 | /**\r | |
| 4523 | Package. Uncore C-box 9 perfmon counter 1.\r | |
| 4524 | \r | |
| 4525 | @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)\r | |
| 4526 | @param EAX Lower 32-bits of MSR value.\r | |
| 4527 | @param EDX Upper 32-bits of MSR value.\r | |
| 4528 | \r | |
| 4529 | <b>Example usage</b>\r | |
| 4530 | @code\r | |
| 4531 | UINT64 Msr;\r | |
| 4532 | \r | |
| 4533 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);\r | |
| 4534 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);\r | |
| 4535 | @endcode\r | |
| a73ab083 | 4536 | @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r |
| c67b579c MK |
4537 | **/\r |
| 4538 | #define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r | |
| 4539 | \r | |
| 4540 | \r | |
| 4541 | /**\r | |
| 4542 | Package. Uncore C-box 9 perfmon counter 2.\r | |
| 4543 | \r | |
| 4544 | @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)\r | |
| 4545 | @param EAX Lower 32-bits of MSR value.\r | |
| 4546 | @param EDX Upper 32-bits of MSR value.\r | |
| 4547 | \r | |
| 4548 | <b>Example usage</b>\r | |
| 4549 | @code\r | |
| 4550 | UINT64 Msr;\r | |
| 4551 | \r | |
| 4552 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);\r | |
| 4553 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);\r | |
| 4554 | @endcode\r | |
| a73ab083 | 4555 | @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r |
| c67b579c MK |
4556 | **/\r |
| 4557 | #define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r | |
| 4558 | \r | |
| 4559 | \r | |
| 4560 | /**\r | |
| 4561 | Package. Uncore C-box 9 perfmon counter 3.\r | |
| 4562 | \r | |
| 4563 | @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)\r | |
| 4564 | @param EAX Lower 32-bits of MSR value.\r | |
| 4565 | @param EDX Upper 32-bits of MSR value.\r | |
| 4566 | \r | |
| 4567 | <b>Example usage</b>\r | |
| 4568 | @code\r | |
| 4569 | UINT64 Msr;\r | |
| 4570 | \r | |
| 4571 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);\r | |
| 4572 | AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);\r | |
| 4573 | @endcode\r | |
| a73ab083 | 4574 | @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r |
| c67b579c MK |
4575 | **/\r |
| 4576 | #define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r | |
| 4577 | \r | |
| 4578 | \r | |
| 4579 | /**\r | |
| 4580 | Package. Uncore C-box 10 perfmon local box wide control.\r | |
| 4581 | \r | |
| 4582 | @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)\r | |
| 4583 | @param EAX Lower 32-bits of MSR value.\r | |
| 4584 | @param EDX Upper 32-bits of MSR value.\r | |
| 4585 | \r | |
| 4586 | <b>Example usage</b>\r | |
| 4587 | @code\r | |
| 4588 | UINT64 Msr;\r | |
| 4589 | \r | |
| 4590 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);\r | |
| 4591 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);\r | |
| 4592 | @endcode\r | |
| a73ab083 | 4593 | @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
4594 | **/\r |
| 4595 | #define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r | |
| 4596 | \r | |
| 4597 | \r | |
| 4598 | /**\r | |
| 4599 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r | |
| 4600 | \r | |
| 4601 | @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)\r | |
| 4602 | @param EAX Lower 32-bits of MSR value.\r | |
| 4603 | @param EDX Upper 32-bits of MSR value.\r | |
| 4604 | \r | |
| 4605 | <b>Example usage</b>\r | |
| 4606 | @code\r | |
| 4607 | UINT64 Msr;\r | |
| 4608 | \r | |
| 4609 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);\r | |
| 4610 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);\r | |
| 4611 | @endcode\r | |
| a73ab083 | 4612 | @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
4613 | **/\r |
| 4614 | #define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r | |
| 4615 | \r | |
| 4616 | \r | |
| 4617 | /**\r | |
| 4618 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r | |
| 4619 | \r | |
| 4620 | @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)\r | |
| 4621 | @param EAX Lower 32-bits of MSR value.\r | |
| 4622 | @param EDX Upper 32-bits of MSR value.\r | |
| 4623 | \r | |
| 4624 | <b>Example usage</b>\r | |
| 4625 | @code\r | |
| 4626 | UINT64 Msr;\r | |
| 4627 | \r | |
| 4628 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);\r | |
| 4629 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);\r | |
| 4630 | @endcode\r | |
| a73ab083 | 4631 | @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
4632 | **/\r |
| 4633 | #define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r | |
| 4634 | \r | |
| 4635 | \r | |
| 4636 | /**\r | |
| 4637 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r | |
| 4638 | \r | |
| 4639 | @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)\r | |
| 4640 | @param EAX Lower 32-bits of MSR value.\r | |
| 4641 | @param EDX Upper 32-bits of MSR value.\r | |
| 4642 | \r | |
| 4643 | <b>Example usage</b>\r | |
| 4644 | @code\r | |
| 4645 | UINT64 Msr;\r | |
| 4646 | \r | |
| 4647 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);\r | |
| 4648 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);\r | |
| 4649 | @endcode\r | |
| a73ab083 | 4650 | @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
4651 | **/\r |
| 4652 | #define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r | |
| 4653 | \r | |
| 4654 | \r | |
| 4655 | /**\r | |
| 4656 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r | |
| 4657 | \r | |
| 4658 | @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)\r | |
| 4659 | @param EAX Lower 32-bits of MSR value.\r | |
| 4660 | @param EDX Upper 32-bits of MSR value.\r | |
| 4661 | \r | |
| 4662 | <b>Example usage</b>\r | |
| 4663 | @code\r | |
| 4664 | UINT64 Msr;\r | |
| 4665 | \r | |
| 4666 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);\r | |
| 4667 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);\r | |
| 4668 | @endcode\r | |
| a73ab083 | 4669 | @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
4670 | **/\r |
| 4671 | #define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r | |
| 4672 | \r | |
| 4673 | \r | |
| 4674 | /**\r | |
| 4675 | Package. Uncore C-box 10 perfmon box wide filter0.\r | |
| 4676 | \r | |
| 4677 | @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)\r | |
| 4678 | @param EAX Lower 32-bits of MSR value.\r | |
| 4679 | @param EDX Upper 32-bits of MSR value.\r | |
| 4680 | \r | |
| 4681 | <b>Example usage</b>\r | |
| 4682 | @code\r | |
| 4683 | UINT64 Msr;\r | |
| 4684 | \r | |
| 4685 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);\r | |
| 4686 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);\r | |
| 4687 | @endcode\r | |
| a73ab083 | 4688 | @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
4689 | **/\r |
| 4690 | #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r | |
| 4691 | \r | |
| 4692 | \r | |
| 4693 | /**\r | |
| 4694 | Package. Uncore C-box 10 perfmon box wide filter1.\r | |
| 4695 | \r | |
| 4696 | @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)\r | |
| 4697 | @param EAX Lower 32-bits of MSR value.\r | |
| 4698 | @param EDX Upper 32-bits of MSR value.\r | |
| 4699 | \r | |
| 4700 | <b>Example usage</b>\r | |
| 4701 | @code\r | |
| 4702 | UINT64 Msr;\r | |
| 4703 | \r | |
| 4704 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);\r | |
| 4705 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);\r | |
| 4706 | @endcode\r | |
| a73ab083 | 4707 | @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
4708 | **/\r |
| 4709 | #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r | |
| 4710 | \r | |
| 4711 | \r | |
| 4712 | /**\r | |
| 4713 | Package. Uncore C-box 10 perfmon box wide status.\r | |
| 4714 | \r | |
| 4715 | @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)\r | |
| 4716 | @param EAX Lower 32-bits of MSR value.\r | |
| 4717 | @param EDX Upper 32-bits of MSR value.\r | |
| 4718 | \r | |
| 4719 | <b>Example usage</b>\r | |
| 4720 | @code\r | |
| 4721 | UINT64 Msr;\r | |
| 4722 | \r | |
| 4723 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);\r | |
| 4724 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);\r | |
| 4725 | @endcode\r | |
| a73ab083 | 4726 | @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
4727 | **/\r |
| 4728 | #define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r | |
| 4729 | \r | |
| 4730 | \r | |
| 4731 | /**\r | |
| 4732 | Package. Uncore C-box 10 perfmon counter 0.\r | |
| 4733 | \r | |
| 4734 | @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)\r | |
| 4735 | @param EAX Lower 32-bits of MSR value.\r | |
| 4736 | @param EDX Upper 32-bits of MSR value.\r | |
| 4737 | \r | |
| 4738 | <b>Example usage</b>\r | |
| 4739 | @code\r | |
| 4740 | UINT64 Msr;\r | |
| 4741 | \r | |
| 4742 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);\r | |
| 4743 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);\r | |
| 4744 | @endcode\r | |
| a73ab083 | 4745 | @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r |
| c67b579c MK |
4746 | **/\r |
| 4747 | #define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r | |
| 4748 | \r | |
| 4749 | \r | |
| 4750 | /**\r | |
| 4751 | Package. Uncore C-box 10 perfmon counter 1.\r | |
| 4752 | \r | |
| 4753 | @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)\r | |
| 4754 | @param EAX Lower 32-bits of MSR value.\r | |
| 4755 | @param EDX Upper 32-bits of MSR value.\r | |
| 4756 | \r | |
| 4757 | <b>Example usage</b>\r | |
| 4758 | @code\r | |
| 4759 | UINT64 Msr;\r | |
| 4760 | \r | |
| 4761 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);\r | |
| 4762 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);\r | |
| 4763 | @endcode\r | |
| a73ab083 | 4764 | @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r |
| c67b579c MK |
4765 | **/\r |
| 4766 | #define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r | |
| 4767 | \r | |
| 4768 | \r | |
| 4769 | /**\r | |
| 4770 | Package. Uncore C-box 10 perfmon counter 2.\r | |
| 4771 | \r | |
| 4772 | @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)\r | |
| 4773 | @param EAX Lower 32-bits of MSR value.\r | |
| 4774 | @param EDX Upper 32-bits of MSR value.\r | |
| 4775 | \r | |
| 4776 | <b>Example usage</b>\r | |
| 4777 | @code\r | |
| 4778 | UINT64 Msr;\r | |
| 4779 | \r | |
| 4780 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);\r | |
| 4781 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);\r | |
| 4782 | @endcode\r | |
| a73ab083 | 4783 | @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r |
| c67b579c MK |
4784 | **/\r |
| 4785 | #define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r | |
| 4786 | \r | |
| 4787 | \r | |
| 4788 | /**\r | |
| 4789 | Package. Uncore C-box 10 perfmon counter 3.\r | |
| 4790 | \r | |
| 4791 | @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)\r | |
| 4792 | @param EAX Lower 32-bits of MSR value.\r | |
| 4793 | @param EDX Upper 32-bits of MSR value.\r | |
| 4794 | \r | |
| 4795 | <b>Example usage</b>\r | |
| 4796 | @code\r | |
| 4797 | UINT64 Msr;\r | |
| 4798 | \r | |
| 4799 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);\r | |
| 4800 | AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);\r | |
| 4801 | @endcode\r | |
| a73ab083 | 4802 | @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r |
| c67b579c MK |
4803 | **/\r |
| 4804 | #define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r | |
| 4805 | \r | |
| 4806 | \r | |
| 4807 | /**\r | |
| 4808 | Package. Uncore C-box 11 perfmon local box wide control.\r | |
| 4809 | \r | |
| 4810 | @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)\r | |
| 4811 | @param EAX Lower 32-bits of MSR value.\r | |
| 4812 | @param EDX Upper 32-bits of MSR value.\r | |
| 4813 | \r | |
| 4814 | <b>Example usage</b>\r | |
| 4815 | @code\r | |
| 4816 | UINT64 Msr;\r | |
| 4817 | \r | |
| 4818 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);\r | |
| 4819 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);\r | |
| 4820 | @endcode\r | |
| a73ab083 | 4821 | @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
4822 | **/\r |
| 4823 | #define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r | |
| 4824 | \r | |
| 4825 | \r | |
| 4826 | /**\r | |
| 4827 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r | |
| 4828 | \r | |
| 4829 | @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)\r | |
| 4830 | @param EAX Lower 32-bits of MSR value.\r | |
| 4831 | @param EDX Upper 32-bits of MSR value.\r | |
| 4832 | \r | |
| 4833 | <b>Example usage</b>\r | |
| 4834 | @code\r | |
| 4835 | UINT64 Msr;\r | |
| 4836 | \r | |
| 4837 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);\r | |
| 4838 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);\r | |
| 4839 | @endcode\r | |
| a73ab083 | 4840 | @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
4841 | **/\r |
| 4842 | #define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r | |
| 4843 | \r | |
| 4844 | \r | |
| 4845 | /**\r | |
| 4846 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r | |
| 4847 | \r | |
| 4848 | @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)\r | |
| 4849 | @param EAX Lower 32-bits of MSR value.\r | |
| 4850 | @param EDX Upper 32-bits of MSR value.\r | |
| 4851 | \r | |
| 4852 | <b>Example usage</b>\r | |
| 4853 | @code\r | |
| 4854 | UINT64 Msr;\r | |
| 4855 | \r | |
| 4856 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);\r | |
| 4857 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);\r | |
| 4858 | @endcode\r | |
| a73ab083 | 4859 | @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
4860 | **/\r |
| 4861 | #define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r | |
| 4862 | \r | |
| 4863 | \r | |
| 4864 | /**\r | |
| 4865 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r | |
| 4866 | \r | |
| 4867 | @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)\r | |
| 4868 | @param EAX Lower 32-bits of MSR value.\r | |
| 4869 | @param EDX Upper 32-bits of MSR value.\r | |
| 4870 | \r | |
| 4871 | <b>Example usage</b>\r | |
| 4872 | @code\r | |
| 4873 | UINT64 Msr;\r | |
| 4874 | \r | |
| 4875 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);\r | |
| 4876 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);\r | |
| 4877 | @endcode\r | |
| a73ab083 | 4878 | @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
4879 | **/\r |
| 4880 | #define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r | |
| 4881 | \r | |
| 4882 | \r | |
| 4883 | /**\r | |
| 4884 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r | |
| 4885 | \r | |
| 4886 | @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)\r | |
| 4887 | @param EAX Lower 32-bits of MSR value.\r | |
| 4888 | @param EDX Upper 32-bits of MSR value.\r | |
| 4889 | \r | |
| 4890 | <b>Example usage</b>\r | |
| 4891 | @code\r | |
| 4892 | UINT64 Msr;\r | |
| 4893 | \r | |
| 4894 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);\r | |
| 4895 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);\r | |
| 4896 | @endcode\r | |
| a73ab083 | 4897 | @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
4898 | **/\r |
| 4899 | #define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r | |
| 4900 | \r | |
| 4901 | \r | |
| 4902 | /**\r | |
| 4903 | Package. Uncore C-box 11 perfmon box wide filter0.\r | |
| 4904 | \r | |
| 4905 | @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)\r | |
| 4906 | @param EAX Lower 32-bits of MSR value.\r | |
| 4907 | @param EDX Upper 32-bits of MSR value.\r | |
| 4908 | \r | |
| 4909 | <b>Example usage</b>\r | |
| 4910 | @code\r | |
| 4911 | UINT64 Msr;\r | |
| 4912 | \r | |
| 4913 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);\r | |
| 4914 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);\r | |
| 4915 | @endcode\r | |
| a73ab083 | 4916 | @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
4917 | **/\r |
| 4918 | #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r | |
| 4919 | \r | |
| 4920 | \r | |
| 4921 | /**\r | |
| 4922 | Package. Uncore C-box 11 perfmon box wide filter1.\r | |
| 4923 | \r | |
| 4924 | @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)\r | |
| 4925 | @param EAX Lower 32-bits of MSR value.\r | |
| 4926 | @param EDX Upper 32-bits of MSR value.\r | |
| 4927 | \r | |
| 4928 | <b>Example usage</b>\r | |
| 4929 | @code\r | |
| 4930 | UINT64 Msr;\r | |
| 4931 | \r | |
| 4932 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);\r | |
| 4933 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);\r | |
| 4934 | @endcode\r | |
| a73ab083 | 4935 | @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
4936 | **/\r |
| 4937 | #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r | |
| 4938 | \r | |
| 4939 | \r | |
| 4940 | /**\r | |
| 4941 | Package. Uncore C-box 11 perfmon box wide status.\r | |
| 4942 | \r | |
| 4943 | @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)\r | |
| 4944 | @param EAX Lower 32-bits of MSR value.\r | |
| 4945 | @param EDX Upper 32-bits of MSR value.\r | |
| 4946 | \r | |
| 4947 | <b>Example usage</b>\r | |
| 4948 | @code\r | |
| 4949 | UINT64 Msr;\r | |
| 4950 | \r | |
| 4951 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);\r | |
| 4952 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);\r | |
| 4953 | @endcode\r | |
| a73ab083 | 4954 | @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
4955 | **/\r |
| 4956 | #define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r | |
| 4957 | \r | |
| 4958 | \r | |
| 4959 | /**\r | |
| 4960 | Package. Uncore C-box 11 perfmon counter 0.\r | |
| 4961 | \r | |
| 4962 | @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)\r | |
| 4963 | @param EAX Lower 32-bits of MSR value.\r | |
| 4964 | @param EDX Upper 32-bits of MSR value.\r | |
| 4965 | \r | |
| 4966 | <b>Example usage</b>\r | |
| 4967 | @code\r | |
| 4968 | UINT64 Msr;\r | |
| 4969 | \r | |
| 4970 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);\r | |
| 4971 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);\r | |
| 4972 | @endcode\r | |
| a73ab083 | 4973 | @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r |
| c67b579c MK |
4974 | **/\r |
| 4975 | #define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r | |
| 4976 | \r | |
| 4977 | \r | |
| 4978 | /**\r | |
| 4979 | Package. Uncore C-box 11 perfmon counter 1.\r | |
| 4980 | \r | |
| 4981 | @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)\r | |
| 4982 | @param EAX Lower 32-bits of MSR value.\r | |
| 4983 | @param EDX Upper 32-bits of MSR value.\r | |
| 4984 | \r | |
| 4985 | <b>Example usage</b>\r | |
| 4986 | @code\r | |
| 4987 | UINT64 Msr;\r | |
| 4988 | \r | |
| 4989 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);\r | |
| 4990 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);\r | |
| 4991 | @endcode\r | |
| a73ab083 | 4992 | @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r |
| c67b579c MK |
4993 | **/\r |
| 4994 | #define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r | |
| 4995 | \r | |
| 4996 | \r | |
| 4997 | /**\r | |
| 4998 | Package. Uncore C-box 11 perfmon counter 2.\r | |
| 4999 | \r | |
| 5000 | @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)\r | |
| 5001 | @param EAX Lower 32-bits of MSR value.\r | |
| 5002 | @param EDX Upper 32-bits of MSR value.\r | |
| 5003 | \r | |
| 5004 | <b>Example usage</b>\r | |
| 5005 | @code\r | |
| 5006 | UINT64 Msr;\r | |
| 5007 | \r | |
| 5008 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);\r | |
| 5009 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);\r | |
| 5010 | @endcode\r | |
| a73ab083 | 5011 | @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r |
| c67b579c MK |
5012 | **/\r |
| 5013 | #define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r | |
| 5014 | \r | |
| 5015 | \r | |
| 5016 | /**\r | |
| 5017 | Package. Uncore C-box 11 perfmon counter 3.\r | |
| 5018 | \r | |
| 5019 | @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)\r | |
| 5020 | @param EAX Lower 32-bits of MSR value.\r | |
| 5021 | @param EDX Upper 32-bits of MSR value.\r | |
| 5022 | \r | |
| 5023 | <b>Example usage</b>\r | |
| 5024 | @code\r | |
| 5025 | UINT64 Msr;\r | |
| 5026 | \r | |
| 5027 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);\r | |
| 5028 | AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);\r | |
| 5029 | @endcode\r | |
| a73ab083 | 5030 | @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r |
| c67b579c MK |
5031 | **/\r |
| 5032 | #define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r | |
| 5033 | \r | |
| 5034 | \r | |
| 5035 | /**\r | |
| 5036 | Package. Uncore C-box 12 perfmon local box wide control.\r | |
| 5037 | \r | |
| 5038 | @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)\r | |
| 5039 | @param EAX Lower 32-bits of MSR value.\r | |
| 5040 | @param EDX Upper 32-bits of MSR value.\r | |
| 5041 | \r | |
| 5042 | <b>Example usage</b>\r | |
| 5043 | @code\r | |
| 5044 | UINT64 Msr;\r | |
| 5045 | \r | |
| 5046 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);\r | |
| 5047 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);\r | |
| 5048 | @endcode\r | |
| a73ab083 | 5049 | @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
5050 | **/\r |
| 5051 | #define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r | |
| 5052 | \r | |
| 5053 | \r | |
| 5054 | /**\r | |
| 5055 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r | |
| 5056 | \r | |
| 5057 | @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)\r | |
| 5058 | @param EAX Lower 32-bits of MSR value.\r | |
| 5059 | @param EDX Upper 32-bits of MSR value.\r | |
| 5060 | \r | |
| 5061 | <b>Example usage</b>\r | |
| 5062 | @code\r | |
| 5063 | UINT64 Msr;\r | |
| 5064 | \r | |
| 5065 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);\r | |
| 5066 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);\r | |
| 5067 | @endcode\r | |
| a73ab083 | 5068 | @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
5069 | **/\r |
| 5070 | #define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r | |
| 5071 | \r | |
| 5072 | \r | |
| 5073 | /**\r | |
| 5074 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r | |
| 5075 | \r | |
| 5076 | @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)\r | |
| 5077 | @param EAX Lower 32-bits of MSR value.\r | |
| 5078 | @param EDX Upper 32-bits of MSR value.\r | |
| 5079 | \r | |
| 5080 | <b>Example usage</b>\r | |
| 5081 | @code\r | |
| 5082 | UINT64 Msr;\r | |
| 5083 | \r | |
| 5084 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);\r | |
| 5085 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);\r | |
| 5086 | @endcode\r | |
| a73ab083 | 5087 | @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
5088 | **/\r |
| 5089 | #define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r | |
| 5090 | \r | |
| 5091 | \r | |
| 5092 | /**\r | |
| 5093 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r | |
| 5094 | \r | |
| 5095 | @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)\r | |
| 5096 | @param EAX Lower 32-bits of MSR value.\r | |
| 5097 | @param EDX Upper 32-bits of MSR value.\r | |
| 5098 | \r | |
| 5099 | <b>Example usage</b>\r | |
| 5100 | @code\r | |
| 5101 | UINT64 Msr;\r | |
| 5102 | \r | |
| 5103 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);\r | |
| 5104 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);\r | |
| 5105 | @endcode\r | |
| a73ab083 | 5106 | @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
5107 | **/\r |
| 5108 | #define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r | |
| 5109 | \r | |
| 5110 | \r | |
| 5111 | /**\r | |
| 5112 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r | |
| 5113 | \r | |
| 5114 | @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)\r | |
| 5115 | @param EAX Lower 32-bits of MSR value.\r | |
| 5116 | @param EDX Upper 32-bits of MSR value.\r | |
| 5117 | \r | |
| 5118 | <b>Example usage</b>\r | |
| 5119 | @code\r | |
| 5120 | UINT64 Msr;\r | |
| 5121 | \r | |
| 5122 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);\r | |
| 5123 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);\r | |
| 5124 | @endcode\r | |
| a73ab083 | 5125 | @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
5126 | **/\r |
| 5127 | #define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r | |
| 5128 | \r | |
| 5129 | \r | |
| 5130 | /**\r | |
| 5131 | Package. Uncore C-box 12 perfmon box wide filter0.\r | |
| 5132 | \r | |
| 5133 | @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)\r | |
| 5134 | @param EAX Lower 32-bits of MSR value.\r | |
| 5135 | @param EDX Upper 32-bits of MSR value.\r | |
| 5136 | \r | |
| 5137 | <b>Example usage</b>\r | |
| 5138 | @code\r | |
| 5139 | UINT64 Msr;\r | |
| 5140 | \r | |
| 5141 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);\r | |
| 5142 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);\r | |
| 5143 | @endcode\r | |
| a73ab083 | 5144 | @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
5145 | **/\r |
| 5146 | #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r | |
| 5147 | \r | |
| 5148 | \r | |
| 5149 | /**\r | |
| 5150 | Package. Uncore C-box 12 perfmon box wide filter1.\r | |
| 5151 | \r | |
| 5152 | @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)\r | |
| 5153 | @param EAX Lower 32-bits of MSR value.\r | |
| 5154 | @param EDX Upper 32-bits of MSR value.\r | |
| 5155 | \r | |
| 5156 | <b>Example usage</b>\r | |
| 5157 | @code\r | |
| 5158 | UINT64 Msr;\r | |
| 5159 | \r | |
| 5160 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);\r | |
| 5161 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);\r | |
| 5162 | @endcode\r | |
| a73ab083 | 5163 | @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
5164 | **/\r |
| 5165 | #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r | |
| 5166 | \r | |
| 5167 | \r | |
| 5168 | /**\r | |
| 5169 | Package. Uncore C-box 12 perfmon box wide status.\r | |
| 5170 | \r | |
| 5171 | @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)\r | |
| 5172 | @param EAX Lower 32-bits of MSR value.\r | |
| 5173 | @param EDX Upper 32-bits of MSR value.\r | |
| 5174 | \r | |
| 5175 | <b>Example usage</b>\r | |
| 5176 | @code\r | |
| 5177 | UINT64 Msr;\r | |
| 5178 | \r | |
| 5179 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);\r | |
| 5180 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);\r | |
| 5181 | @endcode\r | |
| a73ab083 | 5182 | @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
5183 | **/\r |
| 5184 | #define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r | |
| 5185 | \r | |
| 5186 | \r | |
| 5187 | /**\r | |
| 5188 | Package. Uncore C-box 12 perfmon counter 0.\r | |
| 5189 | \r | |
| 5190 | @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)\r | |
| 5191 | @param EAX Lower 32-bits of MSR value.\r | |
| 5192 | @param EDX Upper 32-bits of MSR value.\r | |
| 5193 | \r | |
| 5194 | <b>Example usage</b>\r | |
| 5195 | @code\r | |
| 5196 | UINT64 Msr;\r | |
| 5197 | \r | |
| 5198 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);\r | |
| 5199 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);\r | |
| 5200 | @endcode\r | |
| a73ab083 | 5201 | @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r |
| c67b579c MK |
5202 | **/\r |
| 5203 | #define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r | |
| 5204 | \r | |
| 5205 | \r | |
| 5206 | /**\r | |
| 5207 | Package. Uncore C-box 12 perfmon counter 1.\r | |
| 5208 | \r | |
| 5209 | @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)\r | |
| 5210 | @param EAX Lower 32-bits of MSR value.\r | |
| 5211 | @param EDX Upper 32-bits of MSR value.\r | |
| 5212 | \r | |
| 5213 | <b>Example usage</b>\r | |
| 5214 | @code\r | |
| 5215 | UINT64 Msr;\r | |
| 5216 | \r | |
| 5217 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);\r | |
| 5218 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);\r | |
| 5219 | @endcode\r | |
| a73ab083 | 5220 | @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r |
| c67b579c MK |
5221 | **/\r |
| 5222 | #define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r | |
| 5223 | \r | |
| 5224 | \r | |
| 5225 | /**\r | |
| 5226 | Package. Uncore C-box 12 perfmon counter 2.\r | |
| 5227 | \r | |
| 5228 | @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)\r | |
| 5229 | @param EAX Lower 32-bits of MSR value.\r | |
| 5230 | @param EDX Upper 32-bits of MSR value.\r | |
| 5231 | \r | |
| 5232 | <b>Example usage</b>\r | |
| 5233 | @code\r | |
| 5234 | UINT64 Msr;\r | |
| 5235 | \r | |
| 5236 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);\r | |
| 5237 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);\r | |
| 5238 | @endcode\r | |
| a73ab083 | 5239 | @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r |
| c67b579c MK |
5240 | **/\r |
| 5241 | #define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r | |
| 5242 | \r | |
| 5243 | \r | |
| 5244 | /**\r | |
| 5245 | Package. Uncore C-box 12 perfmon counter 3.\r | |
| 5246 | \r | |
| 5247 | @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)\r | |
| 5248 | @param EAX Lower 32-bits of MSR value.\r | |
| 5249 | @param EDX Upper 32-bits of MSR value.\r | |
| 5250 | \r | |
| 5251 | <b>Example usage</b>\r | |
| 5252 | @code\r | |
| 5253 | UINT64 Msr;\r | |
| 5254 | \r | |
| 5255 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);\r | |
| 5256 | AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);\r | |
| 5257 | @endcode\r | |
| a73ab083 | 5258 | @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r |
| c67b579c MK |
5259 | **/\r |
| 5260 | #define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r | |
| 5261 | \r | |
| 5262 | \r | |
| 5263 | /**\r | |
| 5264 | Package. Uncore C-box 13 perfmon local box wide control.\r | |
| 5265 | \r | |
| 5266 | @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)\r | |
| 5267 | @param EAX Lower 32-bits of MSR value.\r | |
| 5268 | @param EDX Upper 32-bits of MSR value.\r | |
| 5269 | \r | |
| 5270 | <b>Example usage</b>\r | |
| 5271 | @code\r | |
| 5272 | UINT64 Msr;\r | |
| 5273 | \r | |
| 5274 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);\r | |
| 5275 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);\r | |
| 5276 | @endcode\r | |
| a73ab083 | 5277 | @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
5278 | **/\r |
| 5279 | #define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r | |
| 5280 | \r | |
| 5281 | \r | |
| 5282 | /**\r | |
| 5283 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r | |
| 5284 | \r | |
| 5285 | @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)\r | |
| 5286 | @param EAX Lower 32-bits of MSR value.\r | |
| 5287 | @param EDX Upper 32-bits of MSR value.\r | |
| 5288 | \r | |
| 5289 | <b>Example usage</b>\r | |
| 5290 | @code\r | |
| 5291 | UINT64 Msr;\r | |
| 5292 | \r | |
| 5293 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);\r | |
| 5294 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);\r | |
| 5295 | @endcode\r | |
| a73ab083 | 5296 | @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
5297 | **/\r |
| 5298 | #define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r | |
| 5299 | \r | |
| 5300 | \r | |
| 5301 | /**\r | |
| 5302 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r | |
| 5303 | \r | |
| 5304 | @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)\r | |
| 5305 | @param EAX Lower 32-bits of MSR value.\r | |
| 5306 | @param EDX Upper 32-bits of MSR value.\r | |
| 5307 | \r | |
| 5308 | <b>Example usage</b>\r | |
| 5309 | @code\r | |
| 5310 | UINT64 Msr;\r | |
| 5311 | \r | |
| 5312 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);\r | |
| 5313 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);\r | |
| 5314 | @endcode\r | |
| a73ab083 | 5315 | @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
5316 | **/\r |
| 5317 | #define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r | |
| 5318 | \r | |
| 5319 | \r | |
| 5320 | /**\r | |
| 5321 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r | |
| 5322 | \r | |
| 5323 | @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)\r | |
| 5324 | @param EAX Lower 32-bits of MSR value.\r | |
| 5325 | @param EDX Upper 32-bits of MSR value.\r | |
| 5326 | \r | |
| 5327 | <b>Example usage</b>\r | |
| 5328 | @code\r | |
| 5329 | UINT64 Msr;\r | |
| 5330 | \r | |
| 5331 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);\r | |
| 5332 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);\r | |
| 5333 | @endcode\r | |
| a73ab083 | 5334 | @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
5335 | **/\r |
| 5336 | #define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r | |
| 5337 | \r | |
| 5338 | \r | |
| 5339 | /**\r | |
| 5340 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r | |
| 5341 | \r | |
| 5342 | @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)\r | |
| 5343 | @param EAX Lower 32-bits of MSR value.\r | |
| 5344 | @param EDX Upper 32-bits of MSR value.\r | |
| 5345 | \r | |
| 5346 | <b>Example usage</b>\r | |
| 5347 | @code\r | |
| 5348 | UINT64 Msr;\r | |
| 5349 | \r | |
| 5350 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);\r | |
| 5351 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);\r | |
| 5352 | @endcode\r | |
| a73ab083 | 5353 | @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
5354 | **/\r |
| 5355 | #define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r | |
| 5356 | \r | |
| 5357 | \r | |
| 5358 | /**\r | |
| 5359 | Package. Uncore C-box 13 perfmon box wide filter0.\r | |
| 5360 | \r | |
| 5361 | @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)\r | |
| 5362 | @param EAX Lower 32-bits of MSR value.\r | |
| 5363 | @param EDX Upper 32-bits of MSR value.\r | |
| 5364 | \r | |
| 5365 | <b>Example usage</b>\r | |
| 5366 | @code\r | |
| 5367 | UINT64 Msr;\r | |
| 5368 | \r | |
| 5369 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);\r | |
| 5370 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);\r | |
| 5371 | @endcode\r | |
| a73ab083 | 5372 | @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
5373 | **/\r |
| 5374 | #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r | |
| 5375 | \r | |
| 5376 | \r | |
| 5377 | /**\r | |
| 5378 | Package. Uncore C-box 13 perfmon box wide filter1.\r | |
| 5379 | \r | |
| 5380 | @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)\r | |
| 5381 | @param EAX Lower 32-bits of MSR value.\r | |
| 5382 | @param EDX Upper 32-bits of MSR value.\r | |
| 5383 | \r | |
| 5384 | <b>Example usage</b>\r | |
| 5385 | @code\r | |
| 5386 | UINT64 Msr;\r | |
| 5387 | \r | |
| 5388 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);\r | |
| 5389 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);\r | |
| 5390 | @endcode\r | |
| a73ab083 | 5391 | @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
5392 | **/\r |
| 5393 | #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r | |
| 5394 | \r | |
| 5395 | \r | |
| 5396 | /**\r | |
| 5397 | Package. Uncore C-box 13 perfmon box wide status.\r | |
| 5398 | \r | |
| 5399 | @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)\r | |
| 5400 | @param EAX Lower 32-bits of MSR value.\r | |
| 5401 | @param EDX Upper 32-bits of MSR value.\r | |
| 5402 | \r | |
| 5403 | <b>Example usage</b>\r | |
| 5404 | @code\r | |
| 5405 | UINT64 Msr;\r | |
| 5406 | \r | |
| 5407 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);\r | |
| 5408 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);\r | |
| 5409 | @endcode\r | |
| a73ab083 | 5410 | @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
5411 | **/\r |
| 5412 | #define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r | |
| 5413 | \r | |
| 5414 | \r | |
| 5415 | /**\r | |
| 5416 | Package. Uncore C-box 13 perfmon counter 0.\r | |
| 5417 | \r | |
| 5418 | @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)\r | |
| 5419 | @param EAX Lower 32-bits of MSR value.\r | |
| 5420 | @param EDX Upper 32-bits of MSR value.\r | |
| 5421 | \r | |
| 5422 | <b>Example usage</b>\r | |
| 5423 | @code\r | |
| 5424 | UINT64 Msr;\r | |
| 5425 | \r | |
| 5426 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);\r | |
| 5427 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);\r | |
| 5428 | @endcode\r | |
| a73ab083 | 5429 | @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r |
| c67b579c MK |
5430 | **/\r |
| 5431 | #define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r | |
| 5432 | \r | |
| 5433 | \r | |
| 5434 | /**\r | |
| 5435 | Package. Uncore C-box 13 perfmon counter 1.\r | |
| 5436 | \r | |
| 5437 | @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)\r | |
| 5438 | @param EAX Lower 32-bits of MSR value.\r | |
| 5439 | @param EDX Upper 32-bits of MSR value.\r | |
| 5440 | \r | |
| 5441 | <b>Example usage</b>\r | |
| 5442 | @code\r | |
| 5443 | UINT64 Msr;\r | |
| 5444 | \r | |
| 5445 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);\r | |
| 5446 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);\r | |
| 5447 | @endcode\r | |
| a73ab083 | 5448 | @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r |
| c67b579c MK |
5449 | **/\r |
| 5450 | #define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r | |
| 5451 | \r | |
| 5452 | \r | |
| 5453 | /**\r | |
| 5454 | Package. Uncore C-box 13 perfmon counter 2.\r | |
| 5455 | \r | |
| 5456 | @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)\r | |
| 5457 | @param EAX Lower 32-bits of MSR value.\r | |
| 5458 | @param EDX Upper 32-bits of MSR value.\r | |
| 5459 | \r | |
| 5460 | <b>Example usage</b>\r | |
| 5461 | @code\r | |
| 5462 | UINT64 Msr;\r | |
| 5463 | \r | |
| 5464 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);\r | |
| 5465 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);\r | |
| 5466 | @endcode\r | |
| a73ab083 | 5467 | @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r |
| c67b579c MK |
5468 | **/\r |
| 5469 | #define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r | |
| 5470 | \r | |
| 5471 | \r | |
| 5472 | /**\r | |
| 5473 | Package. Uncore C-box 13 perfmon counter 3.\r | |
| 5474 | \r | |
| 5475 | @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)\r | |
| 5476 | @param EAX Lower 32-bits of MSR value.\r | |
| 5477 | @param EDX Upper 32-bits of MSR value.\r | |
| 5478 | \r | |
| 5479 | <b>Example usage</b>\r | |
| 5480 | @code\r | |
| 5481 | UINT64 Msr;\r | |
| 5482 | \r | |
| 5483 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);\r | |
| 5484 | AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);\r | |
| 5485 | @endcode\r | |
| a73ab083 | 5486 | @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r |
| c67b579c MK |
5487 | **/\r |
| 5488 | #define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r | |
| 5489 | \r | |
| 5490 | \r | |
| 5491 | /**\r | |
| 5492 | Package. Uncore C-box 14 perfmon local box wide control.\r | |
| 5493 | \r | |
| 5494 | @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)\r | |
| 5495 | @param EAX Lower 32-bits of MSR value.\r | |
| 5496 | @param EDX Upper 32-bits of MSR value.\r | |
| 5497 | \r | |
| 5498 | <b>Example usage</b>\r | |
| 5499 | @code\r | |
| 5500 | UINT64 Msr;\r | |
| 5501 | \r | |
| 5502 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);\r | |
| 5503 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);\r | |
| 5504 | @endcode\r | |
| a73ab083 | 5505 | @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
5506 | **/\r |
| 5507 | #define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r | |
| 5508 | \r | |
| 5509 | \r | |
| 5510 | /**\r | |
| 5511 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r | |
| 5512 | \r | |
| 5513 | @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)\r | |
| 5514 | @param EAX Lower 32-bits of MSR value.\r | |
| 5515 | @param EDX Upper 32-bits of MSR value.\r | |
| 5516 | \r | |
| 5517 | <b>Example usage</b>\r | |
| 5518 | @code\r | |
| 5519 | UINT64 Msr;\r | |
| 5520 | \r | |
| 5521 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);\r | |
| 5522 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);\r | |
| 5523 | @endcode\r | |
| a73ab083 | 5524 | @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
5525 | **/\r |
| 5526 | #define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r | |
| 5527 | \r | |
| 5528 | \r | |
| 5529 | /**\r | |
| 5530 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r | |
| 5531 | \r | |
| 5532 | @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)\r | |
| 5533 | @param EAX Lower 32-bits of MSR value.\r | |
| 5534 | @param EDX Upper 32-bits of MSR value.\r | |
| 5535 | \r | |
| 5536 | <b>Example usage</b>\r | |
| 5537 | @code\r | |
| 5538 | UINT64 Msr;\r | |
| 5539 | \r | |
| 5540 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);\r | |
| 5541 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);\r | |
| 5542 | @endcode\r | |
| a73ab083 | 5543 | @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
5544 | **/\r |
| 5545 | #define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r | |
| 5546 | \r | |
| 5547 | \r | |
| 5548 | /**\r | |
| 5549 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r | |
| 5550 | \r | |
| 5551 | @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)\r | |
| 5552 | @param EAX Lower 32-bits of MSR value.\r | |
| 5553 | @param EDX Upper 32-bits of MSR value.\r | |
| 5554 | \r | |
| 5555 | <b>Example usage</b>\r | |
| 5556 | @code\r | |
| 5557 | UINT64 Msr;\r | |
| 5558 | \r | |
| 5559 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);\r | |
| 5560 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);\r | |
| 5561 | @endcode\r | |
| a73ab083 | 5562 | @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
5563 | **/\r |
| 5564 | #define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r | |
| 5565 | \r | |
| 5566 | \r | |
| 5567 | /**\r | |
| 5568 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r | |
| 5569 | \r | |
| 5570 | @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)\r | |
| 5571 | @param EAX Lower 32-bits of MSR value.\r | |
| 5572 | @param EDX Upper 32-bits of MSR value.\r | |
| 5573 | \r | |
| 5574 | <b>Example usage</b>\r | |
| 5575 | @code\r | |
| 5576 | UINT64 Msr;\r | |
| 5577 | \r | |
| 5578 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);\r | |
| 5579 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);\r | |
| 5580 | @endcode\r | |
| a73ab083 | 5581 | @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
5582 | **/\r |
| 5583 | #define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r | |
| 5584 | \r | |
| 5585 | \r | |
| 5586 | /**\r | |
| 5587 | Package. Uncore C-box 14 perfmon box wide filter0.\r | |
| 5588 | \r | |
| 5589 | @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)\r | |
| 5590 | @param EAX Lower 32-bits of MSR value.\r | |
| 5591 | @param EDX Upper 32-bits of MSR value.\r | |
| 5592 | \r | |
| 5593 | <b>Example usage</b>\r | |
| 5594 | @code\r | |
| 5595 | UINT64 Msr;\r | |
| 5596 | \r | |
| 5597 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);\r | |
| 5598 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);\r | |
| 5599 | @endcode\r | |
| a73ab083 | 5600 | @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r |
| c67b579c MK |
5601 | **/\r |
| 5602 | #define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r | |
| 5603 | \r | |
| 5604 | \r | |
| 5605 | /**\r | |
| 5606 | Package. Uncore C-box 14 perfmon box wide filter1.\r | |
| 5607 | \r | |
| 5608 | @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)\r | |
| 5609 | @param EAX Lower 32-bits of MSR value.\r | |
| 5610 | @param EDX Upper 32-bits of MSR value.\r | |
| 5611 | \r | |
| 5612 | <b>Example usage</b>\r | |
| 5613 | @code\r | |
| 5614 | UINT64 Msr;\r | |
| 5615 | \r | |
| 5616 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);\r | |
| 5617 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);\r | |
| 5618 | @endcode\r | |
| a73ab083 | 5619 | @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
5620 | **/\r |
| 5621 | #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r | |
| 5622 | \r | |
| 5623 | \r | |
| 5624 | /**\r | |
| 5625 | Package. Uncore C-box 14 perfmon box wide status.\r | |
| 5626 | \r | |
| 5627 | @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)\r | |
| 5628 | @param EAX Lower 32-bits of MSR value.\r | |
| 5629 | @param EDX Upper 32-bits of MSR value.\r | |
| 5630 | \r | |
| 5631 | <b>Example usage</b>\r | |
| 5632 | @code\r | |
| 5633 | UINT64 Msr;\r | |
| 5634 | \r | |
| 5635 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);\r | |
| 5636 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);\r | |
| 5637 | @endcode\r | |
| a73ab083 | 5638 | @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
5639 | **/\r |
| 5640 | #define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r | |
| 5641 | \r | |
| 5642 | \r | |
| 5643 | /**\r | |
| 5644 | Package. Uncore C-box 14 perfmon counter 0.\r | |
| 5645 | \r | |
| 5646 | @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)\r | |
| 5647 | @param EAX Lower 32-bits of MSR value.\r | |
| 5648 | @param EDX Upper 32-bits of MSR value.\r | |
| 5649 | \r | |
| 5650 | <b>Example usage</b>\r | |
| 5651 | @code\r | |
| 5652 | UINT64 Msr;\r | |
| 5653 | \r | |
| 5654 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);\r | |
| 5655 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);\r | |
| 5656 | @endcode\r | |
| a73ab083 | 5657 | @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r |
| c67b579c MK |
5658 | **/\r |
| 5659 | #define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r | |
| 5660 | \r | |
| 5661 | \r | |
| 5662 | /**\r | |
| 5663 | Package. Uncore C-box 14 perfmon counter 1.\r | |
| 5664 | \r | |
| 5665 | @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)\r | |
| 5666 | @param EAX Lower 32-bits of MSR value.\r | |
| 5667 | @param EDX Upper 32-bits of MSR value.\r | |
| 5668 | \r | |
| 5669 | <b>Example usage</b>\r | |
| 5670 | @code\r | |
| 5671 | UINT64 Msr;\r | |
| 5672 | \r | |
| 5673 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);\r | |
| 5674 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);\r | |
| 5675 | @endcode\r | |
| a73ab083 | 5676 | @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r |
| c67b579c MK |
5677 | **/\r |
| 5678 | #define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r | |
| 5679 | \r | |
| 5680 | \r | |
| 5681 | /**\r | |
| 5682 | Package. Uncore C-box 14 perfmon counter 2.\r | |
| 5683 | \r | |
| 5684 | @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)\r | |
| 5685 | @param EAX Lower 32-bits of MSR value.\r | |
| 5686 | @param EDX Upper 32-bits of MSR value.\r | |
| 5687 | \r | |
| 5688 | <b>Example usage</b>\r | |
| 5689 | @code\r | |
| 5690 | UINT64 Msr;\r | |
| 5691 | \r | |
| 5692 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);\r | |
| 5693 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);\r | |
| 5694 | @endcode\r | |
| a73ab083 | 5695 | @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r |
| c67b579c MK |
5696 | **/\r |
| 5697 | #define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r | |
| 5698 | \r | |
| 5699 | \r | |
| 5700 | /**\r | |
| 5701 | Package. Uncore C-box 14 perfmon counter 3.\r | |
| 5702 | \r | |
| 5703 | @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)\r | |
| 5704 | @param EAX Lower 32-bits of MSR value.\r | |
| 5705 | @param EDX Upper 32-bits of MSR value.\r | |
| 5706 | \r | |
| 5707 | <b>Example usage</b>\r | |
| 5708 | @code\r | |
| 5709 | UINT64 Msr;\r | |
| 5710 | \r | |
| 5711 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);\r | |
| 5712 | AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);\r | |
| 5713 | @endcode\r | |
| a73ab083 | 5714 | @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r |
| c67b579c MK |
5715 | **/\r |
| 5716 | #define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r | |
| 5717 | \r | |
| 5718 | \r | |
| 5719 | /**\r | |
| 5720 | Package. Uncore C-box 15 perfmon local box wide control.\r | |
| 5721 | \r | |
| 5722 | @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)\r | |
| 5723 | @param EAX Lower 32-bits of MSR value.\r | |
| 5724 | @param EDX Upper 32-bits of MSR value.\r | |
| 5725 | \r | |
| 5726 | <b>Example usage</b>\r | |
| 5727 | @code\r | |
| 5728 | UINT64 Msr;\r | |
| 5729 | \r | |
| 5730 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);\r | |
| 5731 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);\r | |
| 5732 | @endcode\r | |
| a73ab083 | 5733 | @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
5734 | **/\r |
| 5735 | #define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r | |
| 5736 | \r | |
| 5737 | \r | |
| 5738 | /**\r | |
| 5739 | Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.\r | |
| 5740 | \r | |
| 5741 | @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)\r | |
| 5742 | @param EAX Lower 32-bits of MSR value.\r | |
| 5743 | @param EDX Upper 32-bits of MSR value.\r | |
| 5744 | \r | |
| 5745 | <b>Example usage</b>\r | |
| 5746 | @code\r | |
| 5747 | UINT64 Msr;\r | |
| 5748 | \r | |
| 5749 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);\r | |
| 5750 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);\r | |
| 5751 | @endcode\r | |
| a73ab083 | 5752 | @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
5753 | **/\r |
| 5754 | #define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r | |
| 5755 | \r | |
| 5756 | \r | |
| 5757 | /**\r | |
| 5758 | Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.\r | |
| 5759 | \r | |
| 5760 | @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)\r | |
| 5761 | @param EAX Lower 32-bits of MSR value.\r | |
| 5762 | @param EDX Upper 32-bits of MSR value.\r | |
| 5763 | \r | |
| 5764 | <b>Example usage</b>\r | |
| 5765 | @code\r | |
| 5766 | UINT64 Msr;\r | |
| 5767 | \r | |
| 5768 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);\r | |
| 5769 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);\r | |
| 5770 | @endcode\r | |
| a73ab083 | 5771 | @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
5772 | **/\r |
| 5773 | #define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r | |
| 5774 | \r | |
| 5775 | \r | |
| 5776 | /**\r | |
| 5777 | Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.\r | |
| 5778 | \r | |
| 5779 | @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)\r | |
| 5780 | @param EAX Lower 32-bits of MSR value.\r | |
| 5781 | @param EDX Upper 32-bits of MSR value.\r | |
| 5782 | \r | |
| 5783 | <b>Example usage</b>\r | |
| 5784 | @code\r | |
| 5785 | UINT64 Msr;\r | |
| 5786 | \r | |
| 5787 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);\r | |
| 5788 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);\r | |
| 5789 | @endcode\r | |
| a73ab083 | 5790 | @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
5791 | **/\r |
| 5792 | #define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r | |
| 5793 | \r | |
| 5794 | \r | |
| 5795 | /**\r | |
| 5796 | Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.\r | |
| 5797 | \r | |
| 5798 | @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)\r | |
| 5799 | @param EAX Lower 32-bits of MSR value.\r | |
| 5800 | @param EDX Upper 32-bits of MSR value.\r | |
| 5801 | \r | |
| 5802 | <b>Example usage</b>\r | |
| 5803 | @code\r | |
| 5804 | UINT64 Msr;\r | |
| 5805 | \r | |
| 5806 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);\r | |
| 5807 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);\r | |
| 5808 | @endcode\r | |
| a73ab083 | 5809 | @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
5810 | **/\r |
| 5811 | #define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r | |
| 5812 | \r | |
| 5813 | \r | |
| 5814 | /**\r | |
| 5815 | Package. Uncore C-box 15 perfmon box wide filter0.\r | |
| 5816 | \r | |
| 5817 | @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)\r | |
| 5818 | @param EAX Lower 32-bits of MSR value.\r | |
| 5819 | @param EDX Upper 32-bits of MSR value.\r | |
| 5820 | \r | |
| 5821 | <b>Example usage</b>\r | |
| 5822 | @code\r | |
| 5823 | UINT64 Msr;\r | |
| 5824 | \r | |
| 5825 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);\r | |
| 5826 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);\r | |
| 5827 | @endcode\r | |
| a73ab083 | 5828 | @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
5829 | **/\r |
| 5830 | #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r | |
| 5831 | \r | |
| 5832 | \r | |
| 5833 | /**\r | |
| 5834 | Package. Uncore C-box 15 perfmon box wide filter1.\r | |
| 5835 | \r | |
| 5836 | @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)\r | |
| 5837 | @param EAX Lower 32-bits of MSR value.\r | |
| 5838 | @param EDX Upper 32-bits of MSR value.\r | |
| 5839 | \r | |
| 5840 | <b>Example usage</b>\r | |
| 5841 | @code\r | |
| 5842 | UINT64 Msr;\r | |
| 5843 | \r | |
| 5844 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);\r | |
| 5845 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);\r | |
| 5846 | @endcode\r | |
| a73ab083 | 5847 | @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
5848 | **/\r |
| 5849 | #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r | |
| 5850 | \r | |
| 5851 | \r | |
| 5852 | /**\r | |
| 5853 | Package. Uncore C-box 15 perfmon box wide status.\r | |
| 5854 | \r | |
| 5855 | @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)\r | |
| 5856 | @param EAX Lower 32-bits of MSR value.\r | |
| 5857 | @param EDX Upper 32-bits of MSR value.\r | |
| 5858 | \r | |
| 5859 | <b>Example usage</b>\r | |
| 5860 | @code\r | |
| 5861 | UINT64 Msr;\r | |
| 5862 | \r | |
| 5863 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);\r | |
| 5864 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);\r | |
| 5865 | @endcode\r | |
| a73ab083 | 5866 | @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
5867 | **/\r |
| 5868 | #define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r | |
| 5869 | \r | |
| 5870 | \r | |
| 5871 | /**\r | |
| 5872 | Package. Uncore C-box 15 perfmon counter 0.\r | |
| 5873 | \r | |
| 5874 | @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)\r | |
| 5875 | @param EAX Lower 32-bits of MSR value.\r | |
| 5876 | @param EDX Upper 32-bits of MSR value.\r | |
| 5877 | \r | |
| 5878 | <b>Example usage</b>\r | |
| 5879 | @code\r | |
| 5880 | UINT64 Msr;\r | |
| 5881 | \r | |
| 5882 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);\r | |
| 5883 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);\r | |
| 5884 | @endcode\r | |
| a73ab083 | 5885 | @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.\r |
| c67b579c MK |
5886 | **/\r |
| 5887 | #define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r | |
| 5888 | \r | |
| 5889 | \r | |
| 5890 | /**\r | |
| 5891 | Package. Uncore C-box 15 perfmon counter 1.\r | |
| 5892 | \r | |
| 5893 | @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)\r | |
| 5894 | @param EAX Lower 32-bits of MSR value.\r | |
| 5895 | @param EDX Upper 32-bits of MSR value.\r | |
| 5896 | \r | |
| 5897 | <b>Example usage</b>\r | |
| 5898 | @code\r | |
| 5899 | UINT64 Msr;\r | |
| 5900 | \r | |
| 5901 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);\r | |
| 5902 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);\r | |
| 5903 | @endcode\r | |
| a73ab083 | 5904 | @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.\r |
| c67b579c MK |
5905 | **/\r |
| 5906 | #define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r | |
| 5907 | \r | |
| 5908 | \r | |
| 5909 | /**\r | |
| 5910 | Package. Uncore C-box 15 perfmon counter 2.\r | |
| 5911 | \r | |
| 5912 | @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)\r | |
| 5913 | @param EAX Lower 32-bits of MSR value.\r | |
| 5914 | @param EDX Upper 32-bits of MSR value.\r | |
| 5915 | \r | |
| 5916 | <b>Example usage</b>\r | |
| 5917 | @code\r | |
| 5918 | UINT64 Msr;\r | |
| 5919 | \r | |
| 5920 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);\r | |
| 5921 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);\r | |
| 5922 | @endcode\r | |
| a73ab083 | 5923 | @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.\r |
| c67b579c MK |
5924 | **/\r |
| 5925 | #define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r | |
| 5926 | \r | |
| 5927 | \r | |
| 5928 | /**\r | |
| 5929 | Package. Uncore C-box 15 perfmon counter 3.\r | |
| 5930 | \r | |
| 5931 | @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)\r | |
| 5932 | @param EAX Lower 32-bits of MSR value.\r | |
| 5933 | @param EDX Upper 32-bits of MSR value.\r | |
| 5934 | \r | |
| 5935 | <b>Example usage</b>\r | |
| 5936 | @code\r | |
| 5937 | UINT64 Msr;\r | |
| 5938 | \r | |
| 5939 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);\r | |
| 5940 | AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);\r | |
| 5941 | @endcode\r | |
| a73ab083 | 5942 | @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.\r |
| c67b579c MK |
5943 | **/\r |
| 5944 | #define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r | |
| 5945 | \r | |
| 5946 | \r | |
| 5947 | /**\r | |
| 5948 | Package. Uncore C-box 16 perfmon for box-wide control.\r | |
| 5949 | \r | |
| 5950 | @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)\r | |
| 5951 | @param EAX Lower 32-bits of MSR value.\r | |
| 5952 | @param EDX Upper 32-bits of MSR value.\r | |
| 5953 | \r | |
| 5954 | <b>Example usage</b>\r | |
| 5955 | @code\r | |
| 5956 | UINT64 Msr;\r | |
| 5957 | \r | |
| 5958 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);\r | |
| 5959 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);\r | |
| 5960 | @endcode\r | |
| a73ab083 | 5961 | @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
5962 | **/\r |
| 5963 | #define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r | |
| 5964 | \r | |
| 5965 | \r | |
| 5966 | /**\r | |
| 5967 | Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.\r | |
| 5968 | \r | |
| 5969 | @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)\r | |
| 5970 | @param EAX Lower 32-bits of MSR value.\r | |
| 5971 | @param EDX Upper 32-bits of MSR value.\r | |
| 5972 | \r | |
| 5973 | <b>Example usage</b>\r | |
| 5974 | @code\r | |
| 5975 | UINT64 Msr;\r | |
| 5976 | \r | |
| 5977 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);\r | |
| 5978 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);\r | |
| 5979 | @endcode\r | |
| a73ab083 | 5980 | @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
5981 | **/\r |
| 5982 | #define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r | |
| 5983 | \r | |
| 5984 | \r | |
| 5985 | /**\r | |
| 5986 | Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.\r | |
| 5987 | \r | |
| 5988 | @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)\r | |
| 5989 | @param EAX Lower 32-bits of MSR value.\r | |
| 5990 | @param EDX Upper 32-bits of MSR value.\r | |
| 5991 | \r | |
| 5992 | <b>Example usage</b>\r | |
| 5993 | @code\r | |
| 5994 | UINT64 Msr;\r | |
| 5995 | \r | |
| 5996 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);\r | |
| 5997 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);\r | |
| 5998 | @endcode\r | |
| a73ab083 | 5999 | @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
6000 | **/\r |
| 6001 | #define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r | |
| 6002 | \r | |
| 6003 | \r | |
| 6004 | /**\r | |
| 6005 | Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.\r | |
| 6006 | \r | |
| 6007 | @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)\r | |
| 6008 | @param EAX Lower 32-bits of MSR value.\r | |
| 6009 | @param EDX Upper 32-bits of MSR value.\r | |
| 6010 | \r | |
| 6011 | <b>Example usage</b>\r | |
| 6012 | @code\r | |
| 6013 | UINT64 Msr;\r | |
| 6014 | \r | |
| 6015 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);\r | |
| 6016 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);\r | |
| 6017 | @endcode\r | |
| a73ab083 | 6018 | @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
6019 | **/\r |
| 6020 | #define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r | |
| 6021 | \r | |
| 6022 | \r | |
| 6023 | /**\r | |
| 6024 | Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.\r | |
| 6025 | \r | |
| 6026 | @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)\r | |
| 6027 | @param EAX Lower 32-bits of MSR value.\r | |
| 6028 | @param EDX Upper 32-bits of MSR value.\r | |
| 6029 | \r | |
| 6030 | <b>Example usage</b>\r | |
| 6031 | @code\r | |
| 6032 | UINT64 Msr;\r | |
| 6033 | \r | |
| 6034 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);\r | |
| 6035 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);\r | |
| 6036 | @endcode\r | |
| a73ab083 | 6037 | @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
6038 | **/\r |
| 6039 | #define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r | |
| 6040 | \r | |
| 6041 | \r | |
| 6042 | /**\r | |
| 6043 | Package. Uncore C-box 16 perfmon box wide filter 0.\r | |
| 6044 | \r | |
| 6045 | @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)\r | |
| 6046 | @param EAX Lower 32-bits of MSR value.\r | |
| 6047 | @param EDX Upper 32-bits of MSR value.\r | |
| 6048 | \r | |
| 6049 | <b>Example usage</b>\r | |
| 6050 | @code\r | |
| 6051 | UINT64 Msr;\r | |
| 6052 | \r | |
| 6053 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);\r | |
| 6054 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);\r | |
| 6055 | @endcode\r | |
| a73ab083 | 6056 | @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
6057 | **/\r |
| 6058 | #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r | |
| 6059 | \r | |
| 6060 | \r | |
| 6061 | /**\r | |
| 6062 | Package. Uncore C-box 16 perfmon box wide filter 1.\r | |
| 6063 | \r | |
| 6064 | @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)\r | |
| 6065 | @param EAX Lower 32-bits of MSR value.\r | |
| 6066 | @param EDX Upper 32-bits of MSR value.\r | |
| 6067 | \r | |
| 6068 | <b>Example usage</b>\r | |
| 6069 | @code\r | |
| 6070 | UINT64 Msr;\r | |
| 6071 | \r | |
| 6072 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);\r | |
| 6073 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);\r | |
| 6074 | @endcode\r | |
| a73ab083 | 6075 | @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
6076 | **/\r |
| 6077 | #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r | |
| 6078 | \r | |
| 6079 | \r | |
| 6080 | /**\r | |
| 6081 | Package. Uncore C-box 16 perfmon box wide status.\r | |
| 6082 | \r | |
| 6083 | @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)\r | |
| 6084 | @param EAX Lower 32-bits of MSR value.\r | |
| 6085 | @param EDX Upper 32-bits of MSR value.\r | |
| 6086 | \r | |
| 6087 | <b>Example usage</b>\r | |
| 6088 | @code\r | |
| 6089 | UINT64 Msr;\r | |
| 6090 | \r | |
| 6091 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);\r | |
| 6092 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);\r | |
| 6093 | @endcode\r | |
| a73ab083 | 6094 | @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
6095 | **/\r |
| 6096 | #define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r | |
| 6097 | \r | |
| 6098 | \r | |
| 6099 | /**\r | |
| 6100 | Package. Uncore C-box 16 perfmon counter 0.\r | |
| 6101 | \r | |
| 6102 | @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)\r | |
| 6103 | @param EAX Lower 32-bits of MSR value.\r | |
| 6104 | @param EDX Upper 32-bits of MSR value.\r | |
| 6105 | \r | |
| 6106 | <b>Example usage</b>\r | |
| 6107 | @code\r | |
| 6108 | UINT64 Msr;\r | |
| 6109 | \r | |
| 6110 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);\r | |
| 6111 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);\r | |
| 6112 | @endcode\r | |
| a73ab083 | 6113 | @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.\r |
| c67b579c MK |
6114 | **/\r |
| 6115 | #define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r | |
| 6116 | \r | |
| 6117 | \r | |
| 6118 | /**\r | |
| 6119 | Package. Uncore C-box 16 perfmon counter 1.\r | |
| 6120 | \r | |
| 6121 | @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)\r | |
| 6122 | @param EAX Lower 32-bits of MSR value.\r | |
| 6123 | @param EDX Upper 32-bits of MSR value.\r | |
| 6124 | \r | |
| 6125 | <b>Example usage</b>\r | |
| 6126 | @code\r | |
| 6127 | UINT64 Msr;\r | |
| 6128 | \r | |
| 6129 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);\r | |
| 6130 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);\r | |
| 6131 | @endcode\r | |
| a73ab083 | 6132 | @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.\r |
| c67b579c MK |
6133 | **/\r |
| 6134 | #define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r | |
| 6135 | \r | |
| 6136 | \r | |
| 6137 | /**\r | |
| 6138 | Package. Uncore C-box 16 perfmon counter 2.\r | |
| 6139 | \r | |
| 6140 | @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)\r | |
| 6141 | @param EAX Lower 32-bits of MSR value.\r | |
| 6142 | @param EDX Upper 32-bits of MSR value.\r | |
| 6143 | \r | |
| 6144 | <b>Example usage</b>\r | |
| 6145 | @code\r | |
| 6146 | UINT64 Msr;\r | |
| 6147 | \r | |
| 6148 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);\r | |
| 6149 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);\r | |
| 6150 | @endcode\r | |
| a73ab083 | 6151 | @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.\r |
| c67b579c MK |
6152 | **/\r |
| 6153 | #define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r | |
| 6154 | \r | |
| 6155 | \r | |
| 6156 | /**\r | |
| 6157 | Package. Uncore C-box 16 perfmon counter 3.\r | |
| 6158 | \r | |
| 6159 | @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)\r | |
| 6160 | @param EAX Lower 32-bits of MSR value.\r | |
| 6161 | @param EDX Upper 32-bits of MSR value.\r | |
| 6162 | \r | |
| 6163 | <b>Example usage</b>\r | |
| 6164 | @code\r | |
| 6165 | UINT64 Msr;\r | |
| 6166 | \r | |
| 6167 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);\r | |
| 6168 | AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);\r | |
| 6169 | @endcode\r | |
| a73ab083 | 6170 | @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.\r |
| c67b579c MK |
6171 | **/\r |
| 6172 | #define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r | |
| 6173 | \r | |
| 6174 | \r | |
| 6175 | /**\r | |
| 6176 | Package. Uncore C-box 17 perfmon for box-wide control.\r | |
| 6177 | \r | |
| 6178 | @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)\r | |
| 6179 | @param EAX Lower 32-bits of MSR value.\r | |
| 6180 | @param EDX Upper 32-bits of MSR value.\r | |
| 6181 | \r | |
| 6182 | <b>Example usage</b>\r | |
| 6183 | @code\r | |
| 6184 | UINT64 Msr;\r | |
| 6185 | \r | |
| 6186 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);\r | |
| 6187 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);\r | |
| 6188 | @endcode\r | |
| a73ab083 | 6189 | @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.\r |
| c67b579c MK |
6190 | **/\r |
| 6191 | #define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r | |
| 6192 | \r | |
| 6193 | \r | |
| 6194 | /**\r | |
| 6195 | Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.\r | |
| 6196 | \r | |
| 6197 | @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)\r | |
| 6198 | @param EAX Lower 32-bits of MSR value.\r | |
| 6199 | @param EDX Upper 32-bits of MSR value.\r | |
| 6200 | \r | |
| 6201 | <b>Example usage</b>\r | |
| 6202 | @code\r | |
| 6203 | UINT64 Msr;\r | |
| 6204 | \r | |
| 6205 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);\r | |
| 6206 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);\r | |
| 6207 | @endcode\r | |
| a73ab083 | 6208 | @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.\r |
| c67b579c MK |
6209 | **/\r |
| 6210 | #define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r | |
| 6211 | \r | |
| 6212 | \r | |
| 6213 | /**\r | |
| 6214 | Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.\r | |
| 6215 | \r | |
| 6216 | @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)\r | |
| 6217 | @param EAX Lower 32-bits of MSR value.\r | |
| 6218 | @param EDX Upper 32-bits of MSR value.\r | |
| 6219 | \r | |
| 6220 | <b>Example usage</b>\r | |
| 6221 | @code\r | |
| 6222 | UINT64 Msr;\r | |
| 6223 | \r | |
| 6224 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);\r | |
| 6225 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);\r | |
| 6226 | @endcode\r | |
| a73ab083 | 6227 | @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.\r |
| c67b579c MK |
6228 | **/\r |
| 6229 | #define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r | |
| 6230 | \r | |
| 6231 | \r | |
| 6232 | /**\r | |
| 6233 | Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.\r | |
| 6234 | \r | |
| 6235 | @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)\r | |
| 6236 | @param EAX Lower 32-bits of MSR value.\r | |
| 6237 | @param EDX Upper 32-bits of MSR value.\r | |
| 6238 | \r | |
| 6239 | <b>Example usage</b>\r | |
| 6240 | @code\r | |
| 6241 | UINT64 Msr;\r | |
| 6242 | \r | |
| 6243 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);\r | |
| 6244 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);\r | |
| 6245 | @endcode\r | |
| a73ab083 | 6246 | @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.\r |
| c67b579c MK |
6247 | **/\r |
| 6248 | #define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r | |
| 6249 | \r | |
| 6250 | \r | |
| 6251 | /**\r | |
| 6252 | Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.\r | |
| 6253 | \r | |
| 6254 | @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)\r | |
| 6255 | @param EAX Lower 32-bits of MSR value.\r | |
| 6256 | @param EDX Upper 32-bits of MSR value.\r | |
| 6257 | \r | |
| 6258 | <b>Example usage</b>\r | |
| 6259 | @code\r | |
| 6260 | UINT64 Msr;\r | |
| 6261 | \r | |
| 6262 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);\r | |
| 6263 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);\r | |
| 6264 | @endcode\r | |
| a73ab083 | 6265 | @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.\r |
| c67b579c MK |
6266 | **/\r |
| 6267 | #define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r | |
| 6268 | \r | |
| 6269 | \r | |
| 6270 | /**\r | |
| 6271 | Package. Uncore C-box 17 perfmon box wide filter 0.\r | |
| 6272 | \r | |
| 6273 | @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)\r | |
| 6274 | @param EAX Lower 32-bits of MSR value.\r | |
| 6275 | @param EDX Upper 32-bits of MSR value.\r | |
| 6276 | \r | |
| 6277 | <b>Example usage</b>\r | |
| 6278 | @code\r | |
| 6279 | UINT64 Msr;\r | |
| 6280 | \r | |
| 6281 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);\r | |
| 6282 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);\r | |
| 6283 | @endcode\r | |
| a73ab083 | 6284 | @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.\r |
| c67b579c MK |
6285 | **/\r |
| 6286 | #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r | |
| 6287 | \r | |
| 6288 | \r | |
| 6289 | /**\r | |
| 6290 | Package. Uncore C-box 17 perfmon box wide filter1.\r | |
| 6291 | \r | |
| 6292 | @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)\r | |
| 6293 | @param EAX Lower 32-bits of MSR value.\r | |
| 6294 | @param EDX Upper 32-bits of MSR value.\r | |
| 6295 | \r | |
| 6296 | <b>Example usage</b>\r | |
| 6297 | @code\r | |
| 6298 | UINT64 Msr;\r | |
| 6299 | \r | |
| 6300 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);\r | |
| 6301 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);\r | |
| 6302 | @endcode\r | |
| a73ab083 | 6303 | @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.\r |
| c67b579c MK |
6304 | **/\r |
| 6305 | #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r | |
| 6306 | \r | |
| 6307 | /**\r | |
| 6308 | Package. Uncore C-box 17 perfmon box wide status.\r | |
| 6309 | \r | |
| 6310 | @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)\r | |
| 6311 | @param EAX Lower 32-bits of MSR value.\r | |
| 6312 | @param EDX Upper 32-bits of MSR value.\r | |
| 6313 | \r | |
| 6314 | <b>Example usage</b>\r | |
| 6315 | @code\r | |
| 6316 | UINT64 Msr;\r | |
| 6317 | \r | |
| 6318 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);\r | |
| 6319 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);\r | |
| 6320 | @endcode\r | |
| a73ab083 | 6321 | @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.\r |
| c67b579c MK |
6322 | **/\r |
| 6323 | #define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r | |
| 6324 | \r | |
| 6325 | \r | |
| 6326 | /**\r | |
| 6327 | Package. Uncore C-box 17 perfmon counter n.\r | |
| 6328 | \r | |
| 6329 | @param ECX MSR_HASWELL_E_C17_PMON_CTRn\r | |
| 6330 | @param EAX Lower 32-bits of MSR value.\r | |
| 6331 | @param EDX Upper 32-bits of MSR value.\r | |
| 6332 | \r | |
| 6333 | <b>Example usage</b>\r | |
| 6334 | @code\r | |
| 6335 | UINT64 Msr;\r | |
| 6336 | \r | |
| 6337 | Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);\r | |
| 6338 | AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);\r | |
| 6339 | @endcode\r | |
| a73ab083 JF |
6340 | @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.\r |
| 6341 | MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.\r | |
| 6342 | MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.\r | |
| 6343 | MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.\r | |
| c67b579c MK |
6344 | @{\r |
| 6345 | **/\r | |
| 6346 | #define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r | |
| 6347 | #define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19\r | |
| 6348 | #define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A\r | |
| 6349 | #define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B\r | |
| 6350 | /// @}\r | |
| 6351 | \r | |
| 6352 | #endif\r |