2 MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.12.
24 #ifndef __HASWELL_E_MSR_H__
25 #define __HASWELL_E_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Haswell-E microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x3F \
46 Package. Configured State of Enabled Processor Core Count and Logical
47 Processor Count (RO) - After a Power-On RESET, enumerates factory
48 configuration of the number of processor cores and logical processors in the
49 physical package. - Following the sequence of (i) BIOS modified a
50 Configuration Mask which selects a subset of processor cores to be active
51 post RESET and (ii) a RESET event after the modification, enumerates the
52 current configuration of enabled processor core count and logical processor
53 count in the physical package.
55 @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
56 @param EAX Lower 32-bits of MSR value.
57 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
58 @param EDX Upper 32-bits of MSR value.
59 Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
63 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;
65 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);
67 @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
69 #define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035
72 MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
76 /// Individual bit fields
80 /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are
81 /// currently enabled (by either factory configuration or BIOS
82 /// configuration) in the physical package.
86 /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
87 /// are currently enabled (by either factory configuration or BIOS
88 /// configuration) in the physical package.
90 UINT32 Thread_Count
:16;
94 /// All bit fields as a 32-bit value
98 /// All bit fields as a 64-bit value
101 } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
;
105 Thread. A Hardware Assigned ID for the Logical Processor (RO).
107 @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
108 @param EAX Lower 32-bits of MSR value.
109 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
110 @param EDX Upper 32-bits of MSR value.
111 Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
115 MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;
117 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);
119 @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
121 #define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053
124 MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
128 /// Individual bit fields
132 /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific
133 /// numerical. value physically assigned to each logical processor. This
134 /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
135 /// a physical package.
137 UINT32 Logical_Processor_ID
:8;
142 /// All bit fields as a 32-bit value
146 /// All bit fields as a 64-bit value
149 } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
;
153 Core. C-State Configuration Control (R/W) Note: C-state values are processor
154 specific C-state code names, unrelated to MWAIT extension C-state parameters
155 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
157 @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
158 @param EAX Lower 32-bits of MSR value.
159 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
160 @param EDX Upper 32-bits of MSR value.
161 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
165 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
167 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
168 AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
170 @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
172 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2
175 MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
179 /// Individual bit fields
183 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
184 /// processor-specific C-state code name (consuming the least power) for
185 /// the package. The default is set as factory-configured package C-state
186 /// limit. The following C-state code name encodings are supported: 000b:
187 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
188 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
189 /// supported by the processor are available.
194 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
199 /// [Bit 15] CFG Lock (R/WO).
204 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
206 UINT32 C3AutoDemotion
:1;
208 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
210 UINT32 C1AutoDemotion
:1;
212 /// [Bit 27] Enable C3 Undemotion (R/W).
214 UINT32 C3Undemotion
:1;
216 /// [Bit 28] Enable C1 Undemotion (R/W).
218 UINT32 C1Undemotion
:1;
220 /// [Bit 29] Package C State Demotion Enable (R/W).
222 UINT32 CStateDemotion
:1;
224 /// [Bit 30] Package C State UnDemotion Enable (R/W).
226 UINT32 CStateUndemotion
:1;
231 /// All bit fields as a 32-bit value
235 /// All bit fields as a 64-bit value
238 } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
;
242 Thread. Global Machine Check Capability (R/O).
244 @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
245 @param EAX Lower 32-bits of MSR value.
246 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
247 @param EDX Upper 32-bits of MSR value.
248 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
252 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;
254 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
256 @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
258 #define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179
261 MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
265 /// Individual bit fields
269 /// [Bits 7:0] Count.
273 /// [Bit 8] MCG_CTL_P.
277 /// [Bit 9] MCG_EXT_P.
281 /// [Bit 10] MCP_CMCI_P.
285 /// [Bit 11] MCG_TES_P.
290 /// [Bits 23:16] MCG_EXT_CNT.
292 UINT32 MCG_EXT_CNT
:8;
294 /// [Bit 24] MCG_SER_P.
298 /// [Bit 25] MCG_EM_P.
302 /// [Bit 26] MCG_ELOG_P.
309 /// All bit fields as a 32-bit value
313 /// All bit fields as a 64-bit value
316 } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
;
320 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
321 Enhancement. Accessible only while in SMM.
323 @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
324 @param EAX Lower 32-bits of MSR value.
325 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
326 @param EDX Upper 32-bits of MSR value.
327 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
331 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;
333 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
334 AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
336 @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
338 #define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D
341 MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
345 /// Individual bit fields
351 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
352 /// SMM code access restriction is supported and a host-space interface
353 /// available to SMM handler.
355 UINT32 SMM_Code_Access_Chk
:1;
357 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
358 /// SMM long flow indicator is supported and a host-space interface
359 /// available to SMM handler.
361 UINT32 Long_Flow_Indication
:1;
365 /// All bit fields as a 64-bit value
368 } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
;
372 Package. MC Bank Error Configuration (R/W).
374 @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
375 @param EAX Lower 32-bits of MSR value.
376 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
377 @param EDX Upper 32-bits of MSR value.
378 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
382 MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;
384 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
385 AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
387 @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
389 #define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F
392 MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
396 /// Individual bit fields
401 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
402 /// to log additional info in bits 36:32.
404 UINT32 MemErrorLogEnable
:1;
409 /// All bit fields as a 32-bit value
413 /// All bit fields as a 64-bit value
416 } MSR_HASWELL_E_ERROR_CONTROL_REGISTER
;
420 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
421 RW if MSR_PLATFORM_INFO.[28] = 1.
423 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
424 @param EAX Lower 32-bits of MSR value.
425 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
426 @param EDX Upper 32-bits of MSR value.
427 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
431 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;
433 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
435 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
437 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD
440 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
444 /// Individual bit fields
448 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
449 /// limit of 1 core active.
453 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
454 /// limit of 2 core active.
458 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
459 /// limit of 3 core active.
463 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
464 /// limit of 4 core active.
468 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
469 /// limit of 5 core active.
473 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
474 /// limit of 6 core active.
478 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
479 /// limit of 7 core active.
483 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
484 /// limit of 8 core active.
489 /// All bit fields as a 64-bit value
492 } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
;
496 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
497 RW if MSR_PLATFORM_INFO.[28] = 1.
499 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
500 @param EAX Lower 32-bits of MSR value.
501 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
502 @param EDX Upper 32-bits of MSR value.
503 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
507 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;
509 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
511 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
513 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE
516 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
520 /// Individual bit fields
524 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
525 /// limit of 9 core active.
529 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
530 /// limit of 10 core active.
534 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
535 /// limit of 11 core active.
539 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
540 /// limit of 12 core active.
544 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
545 /// limit of 13 core active.
549 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
550 /// limit of 14 core active.
554 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
555 /// limit of 15 core active.
559 /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
560 /// limit of 16 core active.
565 /// All bit fields as a 64-bit value
568 } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
;
572 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
573 RW if MSR_PLATFORM_INFO.[28] = 1.
575 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
576 @param EAX Lower 32-bits of MSR value.
577 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
578 @param EDX Upper 32-bits of MSR value.
579 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
583 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;
585 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
587 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
589 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF
592 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
596 /// Individual bit fields
600 /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
601 /// limit of 17 core active.
605 /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
606 /// limit of 18 core active.
612 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
613 /// the processor uses override configuration specified in
614 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
615 /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
616 /// configuration (Default).
618 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
621 /// All bit fields as a 64-bit value
624 } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
;
628 Package. Unit Multipliers used in RAPL Interfaces (R/O).
630 @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
631 @param EAX Lower 32-bits of MSR value.
632 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
633 @param EDX Upper 32-bits of MSR value.
634 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
638 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;
640 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
642 @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
644 #define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606
647 MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
651 /// Individual bit fields
655 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
660 /// [Bits 12:8] Package. Energy Status Units Energy related information
661 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
662 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
665 UINT32 EnergyStatusUnits
:5;
668 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
676 /// All bit fields as a 32-bit value
680 /// All bit fields as a 64-bit value
683 } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
;
687 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
690 @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
691 @param EAX Lower 32-bits of MSR value.
692 @param EDX Upper 32-bits of MSR value.
698 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
699 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
701 @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
703 #define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618
707 Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.
709 @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
710 @param EAX Lower 32-bits of MSR value.
711 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
712 @param EDX Upper 32-bits of MSR value.
713 Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
717 MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;
719 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
721 @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
723 #define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
726 MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
730 /// Individual bit fields
734 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
735 /// to enable DRAM RAPL mode 0 (Direct VR).
741 /// All bit fields as a 32-bit value
745 /// All bit fields as a 64-bit value
748 } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER
;
752 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
755 @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
756 @param EAX Lower 32-bits of MSR value.
757 @param EDX Upper 32-bits of MSR value.
763 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
765 @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
767 #define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B
771 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
773 @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
774 @param EAX Lower 32-bits of MSR value.
775 @param EDX Upper 32-bits of MSR value.
781 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
782 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
784 @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
786 #define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C
790 Package. Configuration of PCIE PLL Relative to BCLK(R/W).
792 @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
793 @param EAX Lower 32-bits of MSR value.
794 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
795 @param EDX Upper 32-bits of MSR value.
796 Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
800 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;
802 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
803 AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);
805 @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
807 #define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E
810 MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
814 /// Individual bit fields
818 /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz
819 /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use
820 /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
825 /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
830 /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
831 /// before re-locking Gen2/Gen3 PLLs.
838 /// All bit fields as a 32-bit value
842 /// All bit fields as a 64-bit value
845 } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
;
849 Package. Reserved (R/O) Reads return 0.
851 @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
852 @param EAX Lower 32-bits of MSR value.
853 @param EDX Upper 32-bits of MSR value.
859 Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);
861 @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
863 #define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639
867 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
868 refers to processor core frequency).
870 @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
871 @param EAX Lower 32-bits of MSR value.
872 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
873 @param EDX Upper 32-bits of MSR value.
874 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
878 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
880 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
881 AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
883 @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
885 #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690
888 MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
892 /// Individual bit fields
896 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
897 /// reduced below the operating system request due to assertion of
898 /// external PROCHOT.
900 UINT32 PROCHOT_Status
:1;
902 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
903 /// operating system request due to a thermal event.
905 UINT32 ThermalStatus
:1;
907 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
908 /// reduced below the operating system request due to PBM limit.
910 UINT32 PowerBudgetManagementStatus
:1;
912 /// [Bit 3] Platform Configuration Services Status (R0) When set,
913 /// frequency is reduced below the operating system request due to PCS
916 UINT32 PlatformConfigurationServicesStatus
:1;
919 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
920 /// When set, frequency is reduced below the operating system request
921 /// because the processor has detected that utilization is low.
923 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
925 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
926 /// below the operating system request due to a thermal alert from the
927 /// Voltage Regulator.
929 UINT32 VRThermAlertStatus
:1;
932 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
933 /// reduced below the operating system request due to electrical design
934 /// point constraints (e.g. maximum electrical current consumption).
936 UINT32 ElectricalDesignPointStatus
:1;
939 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
940 /// below the operating system request due to Multi-Core Turbo limits.
942 UINT32 MultiCoreTurboStatus
:1;
945 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
946 /// below max non-turbo P1.
948 UINT32 FrequencyP1Status
:1;
950 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
951 /// set, frequency is reduced below max n-core turbo frequency.
953 UINT32 TurboFrequencyLimitingStatus
:1;
955 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
956 /// reduced below the operating system request.
958 UINT32 FrequencyLimitingStatus
:1;
960 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
961 /// has asserted since the log bit was last cleared. This log bit will
962 /// remain set until cleared by software writing 0.
964 UINT32 PROCHOT_Log
:1;
966 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
967 /// has asserted since the log bit was last cleared. This log bit will
968 /// remain set until cleared by software writing 0.
972 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
973 /// Status bit has asserted since the log bit was last cleared. This log
974 /// bit will remain set until cleared by software writing 0.
976 UINT32 PowerBudgetManagementLog
:1;
978 /// [Bit 19] Platform Configuration Services Log When set, indicates that
979 /// the PCS Status bit has asserted since the log bit was last cleared.
980 /// This log bit will remain set until cleared by software writing 0.
982 UINT32 PlatformConfigurationServicesLog
:1;
985 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
986 /// indicates that the AUBFC Status bit has asserted since the log bit was
987 /// last cleared. This log bit will remain set until cleared by software
990 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
992 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
993 /// Alert Status bit has asserted since the log bit was last cleared. This
994 /// log bit will remain set until cleared by software writing 0.
996 UINT32 VRThermAlertLog
:1;
999 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1000 /// Status bit has asserted since the log bit was last cleared. This log
1001 /// bit will remain set until cleared by software writing 0.
1003 UINT32 ElectricalDesignPointLog
:1;
1006 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
1007 /// Turbo Status bit has asserted since the log bit was last cleared. This
1008 /// log bit will remain set until cleared by software writing 0.
1010 UINT32 MultiCoreTurboLog
:1;
1013 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
1014 /// Frequency P1 Status bit has asserted since the log bit was last
1015 /// cleared. This log bit will remain set until cleared by software
1018 UINT32 CoreFrequencyP1Log
:1;
1020 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
1021 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
1022 /// has asserted since the log bit was last cleared. This log bit will
1023 /// remain set until cleared by software writing 0.
1025 UINT32 TurboFrequencyLimitingLog
:1;
1027 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
1028 /// Frequency Limiting Status bit has asserted since the log bit was last
1029 /// cleared. This log bit will remain set until cleared by software
1032 UINT32 CoreFrequencyLimitingLog
:1;
1033 UINT32 Reserved9
:32;
1036 /// All bit fields as a 32-bit value
1040 /// All bit fields as a 64-bit value
1043 } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
;
1047 THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
1048 ECX=0):EBX.RDT-M[bit 12] = 1.
1050 @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
1051 @param EAX Lower 32-bits of MSR value.
1052 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1053 @param EDX Upper 32-bits of MSR value.
1054 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1056 <b>Example usage</b>
1058 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;
1060 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
1061 AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
1063 @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
1065 #define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D
1068 MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
1072 /// Individual bit fields
1076 /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
1077 /// occupancy monitoring all other encoding reserved..
1080 UINT32 Reserved1
:24;
1082 /// [Bits 41:32] RMID (RW).
1085 UINT32 Reserved2
:22;
1088 /// All bit fields as a 64-bit value
1091 } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
;
1095 THREAD. Resource Association Register (R/W)..
1097 @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
1098 @param EAX Lower 32-bits of MSR value.
1099 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1100 @param EDX Upper 32-bits of MSR value.
1101 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1103 <b>Example usage</b>
1105 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;
1107 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
1108 AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
1110 @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
1112 #define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F
1115 MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
1119 /// Individual bit fields
1123 /// [Bits 9:0] RMID.
1126 UINT32 Reserved1
:22;
1127 UINT32 Reserved2
:32;
1130 /// All bit fields as a 32-bit value
1134 /// All bit fields as a 64-bit value
1137 } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER
;
1141 Package. Uncore perfmon per-socket global control.
1143 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
1144 @param EAX Lower 32-bits of MSR value.
1145 @param EDX Upper 32-bits of MSR value.
1147 <b>Example usage</b>
1151 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
1152 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
1154 @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1156 #define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700
1160 Package. Uncore perfmon per-socket global status.
1162 @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
1163 @param EAX Lower 32-bits of MSR value.
1164 @param EDX Upper 32-bits of MSR value.
1166 <b>Example usage</b>
1170 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
1171 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
1173 @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1175 #define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701
1179 Package. Uncore perfmon per-socket global configuration.
1181 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
1182 @param EAX Lower 32-bits of MSR value.
1183 @param EDX Upper 32-bits of MSR value.
1185 <b>Example usage</b>
1189 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
1190 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
1192 @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1194 #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702
1198 Package. Uncore U-box UCLK fixed counter control.
1200 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
1201 @param EAX Lower 32-bits of MSR value.
1202 @param EDX Upper 32-bits of MSR value.
1204 <b>Example usage</b>
1208 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
1209 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
1211 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
1213 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703
1217 Package. Uncore U-box UCLK fixed counter.
1219 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
1220 @param EAX Lower 32-bits of MSR value.
1221 @param EDX Upper 32-bits of MSR value.
1223 <b>Example usage</b>
1227 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
1228 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
1230 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
1232 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704
1236 Package. Uncore U-box perfmon event select for U-box counter 0.
1238 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
1239 @param EAX Lower 32-bits of MSR value.
1240 @param EDX Upper 32-bits of MSR value.
1242 <b>Example usage</b>
1246 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
1247 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
1249 @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
1251 #define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705
1255 Package. Uncore U-box perfmon event select for U-box counter 1.
1257 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
1258 @param EAX Lower 32-bits of MSR value.
1259 @param EDX Upper 32-bits of MSR value.
1261 <b>Example usage</b>
1265 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
1266 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
1268 @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
1270 #define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706
1274 Package. Uncore U-box perfmon U-box wide status.
1276 @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
1277 @param EAX Lower 32-bits of MSR value.
1278 @param EDX Upper 32-bits of MSR value.
1280 <b>Example usage</b>
1284 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
1285 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
1287 @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1289 #define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708
1293 Package. Uncore U-box perfmon counter 0.
1295 @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
1296 @param EAX Lower 32-bits of MSR value.
1297 @param EDX Upper 32-bits of MSR value.
1299 <b>Example usage</b>
1303 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
1304 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
1306 @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
1308 #define MSR_HASWELL_E_U_PMON_CTR0 0x00000709
1312 Package. Uncore U-box perfmon counter 1.
1314 @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
1315 @param EAX Lower 32-bits of MSR value.
1316 @param EDX Upper 32-bits of MSR value.
1318 <b>Example usage</b>
1322 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
1323 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
1325 @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
1327 #define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A
1331 Package. Uncore PCU perfmon for PCU-box-wide control.
1333 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
1334 @param EAX Lower 32-bits of MSR value.
1335 @param EDX Upper 32-bits of MSR value.
1337 <b>Example usage</b>
1341 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
1342 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
1344 @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
1346 #define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710
1350 Package. Uncore PCU perfmon event select for PCU counter 0.
1352 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
1353 @param EAX Lower 32-bits of MSR value.
1354 @param EDX Upper 32-bits of MSR value.
1356 <b>Example usage</b>
1360 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
1361 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
1363 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
1365 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711
1369 Package. Uncore PCU perfmon event select for PCU counter 1.
1371 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
1372 @param EAX Lower 32-bits of MSR value.
1373 @param EDX Upper 32-bits of MSR value.
1375 <b>Example usage</b>
1379 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
1380 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
1382 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
1384 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712
1388 Package. Uncore PCU perfmon event select for PCU counter 2.
1390 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
1391 @param EAX Lower 32-bits of MSR value.
1392 @param EDX Upper 32-bits of MSR value.
1394 <b>Example usage</b>
1398 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
1399 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
1401 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
1403 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713
1407 Package. Uncore PCU perfmon event select for PCU counter 3.
1409 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
1410 @param EAX Lower 32-bits of MSR value.
1411 @param EDX Upper 32-bits of MSR value.
1413 <b>Example usage</b>
1417 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
1418 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
1420 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
1422 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714
1426 Package. Uncore PCU perfmon box-wide filter.
1428 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
1429 @param EAX Lower 32-bits of MSR value.
1430 @param EDX Upper 32-bits of MSR value.
1432 <b>Example usage</b>
1436 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
1437 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
1439 @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
1441 #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715
1445 Package. Uncore PCU perfmon box wide status.
1447 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
1448 @param EAX Lower 32-bits of MSR value.
1449 @param EDX Upper 32-bits of MSR value.
1451 <b>Example usage</b>
1455 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
1456 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
1458 @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1460 #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716
1464 Package. Uncore PCU perfmon counter 0.
1466 @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
1467 @param EAX Lower 32-bits of MSR value.
1468 @param EDX Upper 32-bits of MSR value.
1470 <b>Example usage</b>
1474 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
1475 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
1477 @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
1479 #define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717
1483 Package. Uncore PCU perfmon counter 1.
1485 @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
1486 @param EAX Lower 32-bits of MSR value.
1487 @param EDX Upper 32-bits of MSR value.
1489 <b>Example usage</b>
1493 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
1494 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
1496 @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
1498 #define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718
1502 Package. Uncore PCU perfmon counter 2.
1504 @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
1505 @param EAX Lower 32-bits of MSR value.
1506 @param EDX Upper 32-bits of MSR value.
1508 <b>Example usage</b>
1512 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
1513 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
1515 @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
1517 #define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719
1521 Package. Uncore PCU perfmon counter 3.
1523 @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
1524 @param EAX Lower 32-bits of MSR value.
1525 @param EDX Upper 32-bits of MSR value.
1527 <b>Example usage</b>
1531 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
1532 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
1534 @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
1536 #define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A
1540 Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
1542 @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
1543 @param EAX Lower 32-bits of MSR value.
1544 @param EDX Upper 32-bits of MSR value.
1546 <b>Example usage</b>
1550 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
1551 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
1553 @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
1555 #define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720
1559 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
1561 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
1562 @param EAX Lower 32-bits of MSR value.
1563 @param EDX Upper 32-bits of MSR value.
1565 <b>Example usage</b>
1569 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
1570 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
1572 @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
1574 #define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721
1578 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
1580 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
1581 @param EAX Lower 32-bits of MSR value.
1582 @param EDX Upper 32-bits of MSR value.
1584 <b>Example usage</b>
1588 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
1589 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
1591 @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
1593 #define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722
1597 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
1599 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
1600 @param EAX Lower 32-bits of MSR value.
1601 @param EDX Upper 32-bits of MSR value.
1603 <b>Example usage</b>
1607 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
1608 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
1610 @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
1612 #define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723
1616 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
1618 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
1619 @param EAX Lower 32-bits of MSR value.
1620 @param EDX Upper 32-bits of MSR value.
1622 <b>Example usage</b>
1626 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
1627 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
1629 @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
1631 #define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724
1635 Package. Uncore SBo 0 perfmon box-wide filter.
1637 @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
1638 @param EAX Lower 32-bits of MSR value.
1639 @param EDX Upper 32-bits of MSR value.
1641 <b>Example usage</b>
1645 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
1646 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
1648 @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
1650 #define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725
1654 Package. Uncore SBo 0 perfmon counter 0.
1656 @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
1657 @param EAX Lower 32-bits of MSR value.
1658 @param EDX Upper 32-bits of MSR value.
1660 <b>Example usage</b>
1664 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
1665 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
1667 @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
1669 #define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726
1673 Package. Uncore SBo 0 perfmon counter 1.
1675 @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
1676 @param EAX Lower 32-bits of MSR value.
1677 @param EDX Upper 32-bits of MSR value.
1679 <b>Example usage</b>
1683 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
1684 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
1686 @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
1688 #define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727
1692 Package. Uncore SBo 0 perfmon counter 2.
1694 @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
1695 @param EAX Lower 32-bits of MSR value.
1696 @param EDX Upper 32-bits of MSR value.
1698 <b>Example usage</b>
1702 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
1703 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
1705 @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
1707 #define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728
1711 Package. Uncore SBo 0 perfmon counter 3.
1713 @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
1714 @param EAX Lower 32-bits of MSR value.
1715 @param EDX Upper 32-bits of MSR value.
1717 <b>Example usage</b>
1721 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
1722 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
1724 @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
1726 #define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729
1730 Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
1732 @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
1733 @param EAX Lower 32-bits of MSR value.
1734 @param EDX Upper 32-bits of MSR value.
1736 <b>Example usage</b>
1740 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
1741 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
1743 @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
1745 #define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A
1749 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
1751 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
1752 @param EAX Lower 32-bits of MSR value.
1753 @param EDX Upper 32-bits of MSR value.
1755 <b>Example usage</b>
1759 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
1760 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
1762 @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
1764 #define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B
1768 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
1770 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
1771 @param EAX Lower 32-bits of MSR value.
1772 @param EDX Upper 32-bits of MSR value.
1774 <b>Example usage</b>
1778 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
1779 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
1781 @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
1783 #define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C
1787 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
1789 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
1790 @param EAX Lower 32-bits of MSR value.
1791 @param EDX Upper 32-bits of MSR value.
1793 <b>Example usage</b>
1797 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
1798 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
1800 @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
1802 #define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D
1806 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
1808 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
1809 @param EAX Lower 32-bits of MSR value.
1810 @param EDX Upper 32-bits of MSR value.
1812 <b>Example usage</b>
1816 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
1817 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
1819 @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
1821 #define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E
1825 Package. Uncore SBo 1 perfmon box-wide filter.
1827 @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
1828 @param EAX Lower 32-bits of MSR value.
1829 @param EDX Upper 32-bits of MSR value.
1831 <b>Example usage</b>
1835 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
1836 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
1838 @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
1840 #define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F
1844 Package. Uncore SBo 1 perfmon counter 0.
1846 @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
1847 @param EAX Lower 32-bits of MSR value.
1848 @param EDX Upper 32-bits of MSR value.
1850 <b>Example usage</b>
1854 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
1855 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
1857 @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
1859 #define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730
1863 Package. Uncore SBo 1 perfmon counter 1.
1865 @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
1866 @param EAX Lower 32-bits of MSR value.
1867 @param EDX Upper 32-bits of MSR value.
1869 <b>Example usage</b>
1873 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
1874 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
1876 @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
1878 #define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731
1882 Package. Uncore SBo 1 perfmon counter 2.
1884 @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
1885 @param EAX Lower 32-bits of MSR value.
1886 @param EDX Upper 32-bits of MSR value.
1888 <b>Example usage</b>
1892 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
1893 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
1895 @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
1897 #define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732
1901 Package. Uncore SBo 1 perfmon counter 3.
1903 @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
1904 @param EAX Lower 32-bits of MSR value.
1905 @param EDX Upper 32-bits of MSR value.
1907 <b>Example usage</b>
1911 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
1912 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
1914 @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
1916 #define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733
1920 Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
1922 @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
1923 @param EAX Lower 32-bits of MSR value.
1924 @param EDX Upper 32-bits of MSR value.
1926 <b>Example usage</b>
1930 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
1931 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
1933 @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
1935 #define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734
1939 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
1941 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
1942 @param EAX Lower 32-bits of MSR value.
1943 @param EDX Upper 32-bits of MSR value.
1945 <b>Example usage</b>
1949 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
1950 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
1952 @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
1954 #define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735
1958 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
1960 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
1961 @param EAX Lower 32-bits of MSR value.
1962 @param EDX Upper 32-bits of MSR value.
1964 <b>Example usage</b>
1968 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
1969 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
1971 @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
1973 #define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736
1977 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
1979 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
1980 @param EAX Lower 32-bits of MSR value.
1981 @param EDX Upper 32-bits of MSR value.
1983 <b>Example usage</b>
1987 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
1988 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
1990 @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
1992 #define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737
1996 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
1998 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
1999 @param EAX Lower 32-bits of MSR value.
2000 @param EDX Upper 32-bits of MSR value.
2002 <b>Example usage</b>
2006 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
2007 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
2009 @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
2011 #define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738
2015 Package. Uncore SBo 2 perfmon box-wide filter.
2017 @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
2018 @param EAX Lower 32-bits of MSR value.
2019 @param EDX Upper 32-bits of MSR value.
2021 <b>Example usage</b>
2025 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
2026 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
2028 @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
2030 #define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739
2034 Package. Uncore SBo 2 perfmon counter 0.
2036 @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
2037 @param EAX Lower 32-bits of MSR value.
2038 @param EDX Upper 32-bits of MSR value.
2040 <b>Example usage</b>
2044 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
2045 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
2047 @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
2049 #define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A
2053 Package. Uncore SBo 2 perfmon counter 1.
2055 @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
2056 @param EAX Lower 32-bits of MSR value.
2057 @param EDX Upper 32-bits of MSR value.
2059 <b>Example usage</b>
2063 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
2064 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
2066 @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
2068 #define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B
2072 Package. Uncore SBo 2 perfmon counter 2.
2074 @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
2075 @param EAX Lower 32-bits of MSR value.
2076 @param EDX Upper 32-bits of MSR value.
2078 <b>Example usage</b>
2082 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
2083 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
2085 @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
2087 #define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C
2091 Package. Uncore SBo 2 perfmon counter 3.
2093 @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
2094 @param EAX Lower 32-bits of MSR value.
2095 @param EDX Upper 32-bits of MSR value.
2097 <b>Example usage</b>
2101 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
2102 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
2104 @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
2106 #define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D
2110 Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
2112 @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
2113 @param EAX Lower 32-bits of MSR value.
2114 @param EDX Upper 32-bits of MSR value.
2116 <b>Example usage</b>
2120 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
2121 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
2123 @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
2125 #define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E
2129 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
2131 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
2132 @param EAX Lower 32-bits of MSR value.
2133 @param EDX Upper 32-bits of MSR value.
2135 <b>Example usage</b>
2139 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
2140 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
2142 @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
2144 #define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F
2148 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
2150 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
2151 @param EAX Lower 32-bits of MSR value.
2152 @param EDX Upper 32-bits of MSR value.
2154 <b>Example usage</b>
2158 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
2159 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
2161 @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
2163 #define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740
2167 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
2169 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
2170 @param EAX Lower 32-bits of MSR value.
2171 @param EDX Upper 32-bits of MSR value.
2173 <b>Example usage</b>
2177 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
2178 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
2180 @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
2182 #define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741
2186 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
2188 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
2189 @param EAX Lower 32-bits of MSR value.
2190 @param EDX Upper 32-bits of MSR value.
2192 <b>Example usage</b>
2196 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
2197 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
2199 @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
2201 #define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742
2205 Package. Uncore SBo 3 perfmon box-wide filter.
2207 @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
2208 @param EAX Lower 32-bits of MSR value.
2209 @param EDX Upper 32-bits of MSR value.
2211 <b>Example usage</b>
2215 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
2216 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
2218 @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
2220 #define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743
2224 Package. Uncore SBo 3 perfmon counter 0.
2226 @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
2227 @param EAX Lower 32-bits of MSR value.
2228 @param EDX Upper 32-bits of MSR value.
2230 <b>Example usage</b>
2234 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
2235 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
2237 @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
2239 #define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744
2243 Package. Uncore SBo 3 perfmon counter 1.
2245 @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
2246 @param EAX Lower 32-bits of MSR value.
2247 @param EDX Upper 32-bits of MSR value.
2249 <b>Example usage</b>
2253 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
2254 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
2256 @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
2258 #define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745
2262 Package. Uncore SBo 3 perfmon counter 2.
2264 @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
2265 @param EAX Lower 32-bits of MSR value.
2266 @param EDX Upper 32-bits of MSR value.
2268 <b>Example usage</b>
2272 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
2273 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
2275 @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
2277 #define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746
2281 Package. Uncore SBo 3 perfmon counter 3.
2283 @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
2284 @param EAX Lower 32-bits of MSR value.
2285 @param EDX Upper 32-bits of MSR value.
2287 <b>Example usage</b>
2291 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
2292 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
2294 @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
2296 #define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747
2300 Package. Uncore C-box 0 perfmon for box-wide control.
2302 @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
2303 @param EAX Lower 32-bits of MSR value.
2304 @param EDX Upper 32-bits of MSR value.
2306 <b>Example usage</b>
2310 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
2311 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
2313 @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
2315 #define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00
2319 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
2321 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
2322 @param EAX Lower 32-bits of MSR value.
2323 @param EDX Upper 32-bits of MSR value.
2325 <b>Example usage</b>
2329 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
2330 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
2332 @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
2334 #define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01
2338 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
2340 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
2341 @param EAX Lower 32-bits of MSR value.
2342 @param EDX Upper 32-bits of MSR value.
2344 <b>Example usage</b>
2348 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
2349 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
2351 @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
2353 #define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02
2357 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
2359 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
2360 @param EAX Lower 32-bits of MSR value.
2361 @param EDX Upper 32-bits of MSR value.
2363 <b>Example usage</b>
2367 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
2368 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
2370 @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
2372 #define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03
2376 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
2378 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
2379 @param EAX Lower 32-bits of MSR value.
2380 @param EDX Upper 32-bits of MSR value.
2382 <b>Example usage</b>
2386 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
2387 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
2389 @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
2391 #define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04
2395 Package. Uncore C-box 0 perfmon box wide filter 0.
2397 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
2398 @param EAX Lower 32-bits of MSR value.
2399 @param EDX Upper 32-bits of MSR value.
2401 <b>Example usage</b>
2405 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
2406 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
2408 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
2410 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05
2414 Package. Uncore C-box 0 perfmon box wide filter 1.
2416 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
2417 @param EAX Lower 32-bits of MSR value.
2418 @param EDX Upper 32-bits of MSR value.
2420 <b>Example usage</b>
2424 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
2425 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
2427 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
2429 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06
2433 Package. Uncore C-box 0 perfmon box wide status.
2435 @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
2436 @param EAX Lower 32-bits of MSR value.
2437 @param EDX Upper 32-bits of MSR value.
2439 <b>Example usage</b>
2443 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
2444 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
2446 @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
2448 #define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07
2452 Package. Uncore C-box 0 perfmon counter 0.
2454 @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
2455 @param EAX Lower 32-bits of MSR value.
2456 @param EDX Upper 32-bits of MSR value.
2458 <b>Example usage</b>
2462 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
2463 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
2465 @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
2467 #define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08
2471 Package. Uncore C-box 0 perfmon counter 1.
2473 @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
2474 @param EAX Lower 32-bits of MSR value.
2475 @param EDX Upper 32-bits of MSR value.
2477 <b>Example usage</b>
2481 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
2482 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
2484 @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
2486 #define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09
2490 Package. Uncore C-box 0 perfmon counter 2.
2492 @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
2493 @param EAX Lower 32-bits of MSR value.
2494 @param EDX Upper 32-bits of MSR value.
2496 <b>Example usage</b>
2500 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
2501 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
2503 @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
2505 #define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A
2509 Package. Uncore C-box 0 perfmon counter 3.
2511 @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
2512 @param EAX Lower 32-bits of MSR value.
2513 @param EDX Upper 32-bits of MSR value.
2515 <b>Example usage</b>
2519 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
2520 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
2522 @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
2524 #define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B
2528 Package. Uncore C-box 1 perfmon for box-wide control.
2530 @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
2531 @param EAX Lower 32-bits of MSR value.
2532 @param EDX Upper 32-bits of MSR value.
2534 <b>Example usage</b>
2538 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
2539 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
2541 @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
2543 #define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10
2547 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
2549 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
2550 @param EAX Lower 32-bits of MSR value.
2551 @param EDX Upper 32-bits of MSR value.
2553 <b>Example usage</b>
2557 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
2558 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
2560 @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
2562 #define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11
2566 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
2568 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
2569 @param EAX Lower 32-bits of MSR value.
2570 @param EDX Upper 32-bits of MSR value.
2572 <b>Example usage</b>
2576 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
2577 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
2579 @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
2581 #define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12
2585 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
2587 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
2588 @param EAX Lower 32-bits of MSR value.
2589 @param EDX Upper 32-bits of MSR value.
2591 <b>Example usage</b>
2595 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
2596 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
2598 @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
2600 #define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13
2604 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
2606 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
2607 @param EAX Lower 32-bits of MSR value.
2608 @param EDX Upper 32-bits of MSR value.
2610 <b>Example usage</b>
2614 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
2615 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
2617 @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
2619 #define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14
2623 Package. Uncore C-box 1 perfmon box wide filter 0.
2625 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
2626 @param EAX Lower 32-bits of MSR value.
2627 @param EDX Upper 32-bits of MSR value.
2629 <b>Example usage</b>
2633 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
2634 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
2636 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
2638 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15
2642 Package. Uncore C-box 1 perfmon box wide filter1.
2644 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
2645 @param EAX Lower 32-bits of MSR value.
2646 @param EDX Upper 32-bits of MSR value.
2648 <b>Example usage</b>
2652 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
2653 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
2655 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
2657 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16
2661 Package. Uncore C-box 1 perfmon box wide status.
2663 @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
2664 @param EAX Lower 32-bits of MSR value.
2665 @param EDX Upper 32-bits of MSR value.
2667 <b>Example usage</b>
2671 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
2672 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
2674 @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
2676 #define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17
2680 Package. Uncore C-box 1 perfmon counter 0.
2682 @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
2683 @param EAX Lower 32-bits of MSR value.
2684 @param EDX Upper 32-bits of MSR value.
2686 <b>Example usage</b>
2690 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
2691 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
2693 @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
2695 #define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18
2699 Package. Uncore C-box 1 perfmon counter 1.
2701 @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
2702 @param EAX Lower 32-bits of MSR value.
2703 @param EDX Upper 32-bits of MSR value.
2705 <b>Example usage</b>
2709 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
2710 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
2712 @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
2714 #define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19
2718 Package. Uncore C-box 1 perfmon counter 2.
2720 @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
2721 @param EAX Lower 32-bits of MSR value.
2722 @param EDX Upper 32-bits of MSR value.
2724 <b>Example usage</b>
2728 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
2729 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
2731 @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
2733 #define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A
2737 Package. Uncore C-box 1 perfmon counter 3.
2739 @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
2740 @param EAX Lower 32-bits of MSR value.
2741 @param EDX Upper 32-bits of MSR value.
2743 <b>Example usage</b>
2747 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
2748 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
2750 @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
2752 #define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B
2756 Package. Uncore C-box 2 perfmon for box-wide control.
2758 @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
2759 @param EAX Lower 32-bits of MSR value.
2760 @param EDX Upper 32-bits of MSR value.
2762 <b>Example usage</b>
2766 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
2767 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
2769 @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
2771 #define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20
2775 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
2777 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
2778 @param EAX Lower 32-bits of MSR value.
2779 @param EDX Upper 32-bits of MSR value.
2781 <b>Example usage</b>
2785 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
2786 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
2788 @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
2790 #define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21
2794 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
2796 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
2797 @param EAX Lower 32-bits of MSR value.
2798 @param EDX Upper 32-bits of MSR value.
2800 <b>Example usage</b>
2804 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
2805 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
2807 @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
2809 #define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22
2813 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
2815 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
2816 @param EAX Lower 32-bits of MSR value.
2817 @param EDX Upper 32-bits of MSR value.
2819 <b>Example usage</b>
2823 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
2824 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
2826 @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
2828 #define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23
2832 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
2834 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
2835 @param EAX Lower 32-bits of MSR value.
2836 @param EDX Upper 32-bits of MSR value.
2838 <b>Example usage</b>
2842 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
2843 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
2845 @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
2847 #define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24
2851 Package. Uncore C-box 2 perfmon box wide filter 0.
2853 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
2854 @param EAX Lower 32-bits of MSR value.
2855 @param EDX Upper 32-bits of MSR value.
2857 <b>Example usage</b>
2861 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
2862 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
2864 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
2866 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25
2870 Package. Uncore C-box 2 perfmon box wide filter1.
2872 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
2873 @param EAX Lower 32-bits of MSR value.
2874 @param EDX Upper 32-bits of MSR value.
2876 <b>Example usage</b>
2880 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
2881 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
2883 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
2885 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26
2889 Package. Uncore C-box 2 perfmon box wide status.
2891 @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
2892 @param EAX Lower 32-bits of MSR value.
2893 @param EDX Upper 32-bits of MSR value.
2895 <b>Example usage</b>
2899 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
2900 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
2902 @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
2904 #define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27
2908 Package. Uncore C-box 2 perfmon counter 0.
2910 @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
2911 @param EAX Lower 32-bits of MSR value.
2912 @param EDX Upper 32-bits of MSR value.
2914 <b>Example usage</b>
2918 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
2919 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
2921 @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
2923 #define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28
2927 Package. Uncore C-box 2 perfmon counter 1.
2929 @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
2930 @param EAX Lower 32-bits of MSR value.
2931 @param EDX Upper 32-bits of MSR value.
2933 <b>Example usage</b>
2937 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
2938 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
2940 @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
2942 #define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29
2946 Package. Uncore C-box 2 perfmon counter 2.
2948 @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
2949 @param EAX Lower 32-bits of MSR value.
2950 @param EDX Upper 32-bits of MSR value.
2952 <b>Example usage</b>
2956 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
2957 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
2959 @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
2961 #define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A
2965 Package. Uncore C-box 2 perfmon counter 3.
2967 @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
2968 @param EAX Lower 32-bits of MSR value.
2969 @param EDX Upper 32-bits of MSR value.
2971 <b>Example usage</b>
2975 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
2976 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
2978 @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
2980 #define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B
2984 Package. Uncore C-box 3 perfmon for box-wide control.
2986 @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
2987 @param EAX Lower 32-bits of MSR value.
2988 @param EDX Upper 32-bits of MSR value.
2990 <b>Example usage</b>
2994 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
2995 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
2997 @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
2999 #define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30
3003 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3005 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
3006 @param EAX Lower 32-bits of MSR value.
3007 @param EDX Upper 32-bits of MSR value.
3009 <b>Example usage</b>
3013 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
3014 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
3016 @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
3018 #define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31
3022 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3024 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
3025 @param EAX Lower 32-bits of MSR value.
3026 @param EDX Upper 32-bits of MSR value.
3028 <b>Example usage</b>
3032 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
3033 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
3035 @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
3037 #define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32
3041 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3043 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
3044 @param EAX Lower 32-bits of MSR value.
3045 @param EDX Upper 32-bits of MSR value.
3047 <b>Example usage</b>
3051 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
3052 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
3054 @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
3056 #define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33
3060 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3062 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
3063 @param EAX Lower 32-bits of MSR value.
3064 @param EDX Upper 32-bits of MSR value.
3066 <b>Example usage</b>
3070 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
3071 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
3073 @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3075 #define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34
3079 Package. Uncore C-box 3 perfmon box wide filter 0.
3081 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
3082 @param EAX Lower 32-bits of MSR value.
3083 @param EDX Upper 32-bits of MSR value.
3085 <b>Example usage</b>
3089 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
3090 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
3092 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
3094 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35
3098 Package. Uncore C-box 3 perfmon box wide filter1.
3100 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
3101 @param EAX Lower 32-bits of MSR value.
3102 @param EDX Upper 32-bits of MSR value.
3104 <b>Example usage</b>
3108 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
3109 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
3111 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
3113 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36
3117 Package. Uncore C-box 3 perfmon box wide status.
3119 @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
3120 @param EAX Lower 32-bits of MSR value.
3121 @param EDX Upper 32-bits of MSR value.
3123 <b>Example usage</b>
3127 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
3128 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
3130 @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
3132 #define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37
3136 Package. Uncore C-box 3 perfmon counter 0.
3138 @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
3139 @param EAX Lower 32-bits of MSR value.
3140 @param EDX Upper 32-bits of MSR value.
3142 <b>Example usage</b>
3146 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
3147 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
3149 @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3151 #define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38
3155 Package. Uncore C-box 3 perfmon counter 1.
3157 @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
3158 @param EAX Lower 32-bits of MSR value.
3159 @param EDX Upper 32-bits of MSR value.
3161 <b>Example usage</b>
3165 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
3166 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
3168 @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3170 #define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39
3174 Package. Uncore C-box 3 perfmon counter 2.
3176 @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
3177 @param EAX Lower 32-bits of MSR value.
3178 @param EDX Upper 32-bits of MSR value.
3180 <b>Example usage</b>
3184 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
3185 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
3187 @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
3189 #define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A
3193 Package. Uncore C-box 3 perfmon counter 3.
3195 @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
3196 @param EAX Lower 32-bits of MSR value.
3197 @param EDX Upper 32-bits of MSR value.
3199 <b>Example usage</b>
3203 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
3204 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
3206 @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
3208 #define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B
3212 Package. Uncore C-box 4 perfmon for box-wide control.
3214 @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
3215 @param EAX Lower 32-bits of MSR value.
3216 @param EDX Upper 32-bits of MSR value.
3218 <b>Example usage</b>
3222 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
3223 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
3225 @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
3227 #define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40
3231 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
3233 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
3234 @param EAX Lower 32-bits of MSR value.
3235 @param EDX Upper 32-bits of MSR value.
3237 <b>Example usage</b>
3241 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
3242 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
3244 @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
3246 #define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41
3250 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
3252 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
3253 @param EAX Lower 32-bits of MSR value.
3254 @param EDX Upper 32-bits of MSR value.
3256 <b>Example usage</b>
3260 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
3261 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
3263 @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
3265 #define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42
3269 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
3271 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
3272 @param EAX Lower 32-bits of MSR value.
3273 @param EDX Upper 32-bits of MSR value.
3275 <b>Example usage</b>
3279 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
3280 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
3282 @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
3284 #define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43
3288 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
3290 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
3291 @param EAX Lower 32-bits of MSR value.
3292 @param EDX Upper 32-bits of MSR value.
3294 <b>Example usage</b>
3298 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
3299 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
3301 @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
3303 #define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44
3307 Package. Uncore C-box 4 perfmon box wide filter 0.
3309 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
3310 @param EAX Lower 32-bits of MSR value.
3311 @param EDX Upper 32-bits of MSR value.
3313 <b>Example usage</b>
3317 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
3318 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
3320 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
3322 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45
3326 Package. Uncore C-box 4 perfmon box wide filter1.
3328 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
3329 @param EAX Lower 32-bits of MSR value.
3330 @param EDX Upper 32-bits of MSR value.
3332 <b>Example usage</b>
3336 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
3337 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
3339 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
3341 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46
3345 Package. Uncore C-box 4 perfmon box wide status.
3347 @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
3348 @param EAX Lower 32-bits of MSR value.
3349 @param EDX Upper 32-bits of MSR value.
3351 <b>Example usage</b>
3355 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
3356 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
3358 @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
3360 #define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47
3364 Package. Uncore C-box 4 perfmon counter 0.
3366 @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
3367 @param EAX Lower 32-bits of MSR value.
3368 @param EDX Upper 32-bits of MSR value.
3370 <b>Example usage</b>
3374 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
3375 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
3377 @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
3379 #define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48
3383 Package. Uncore C-box 4 perfmon counter 1.
3385 @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
3386 @param EAX Lower 32-bits of MSR value.
3387 @param EDX Upper 32-bits of MSR value.
3389 <b>Example usage</b>
3393 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
3394 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
3396 @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
3398 #define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49
3402 Package. Uncore C-box 4 perfmon counter 2.
3404 @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
3405 @param EAX Lower 32-bits of MSR value.
3406 @param EDX Upper 32-bits of MSR value.
3408 <b>Example usage</b>
3412 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
3413 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
3415 @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
3417 #define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A
3421 Package. Uncore C-box 4 perfmon counter 3.
3423 @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
3424 @param EAX Lower 32-bits of MSR value.
3425 @param EDX Upper 32-bits of MSR value.
3427 <b>Example usage</b>
3431 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
3432 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
3434 @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
3436 #define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B
3440 Package. Uncore C-box 5 perfmon for box-wide control.
3442 @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
3443 @param EAX Lower 32-bits of MSR value.
3444 @param EDX Upper 32-bits of MSR value.
3446 <b>Example usage</b>
3450 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
3451 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
3453 @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
3455 #define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50
3459 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
3461 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
3462 @param EAX Lower 32-bits of MSR value.
3463 @param EDX Upper 32-bits of MSR value.
3465 <b>Example usage</b>
3469 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
3470 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
3472 @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
3474 #define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51
3478 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
3480 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
3481 @param EAX Lower 32-bits of MSR value.
3482 @param EDX Upper 32-bits of MSR value.
3484 <b>Example usage</b>
3488 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
3489 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
3491 @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
3493 #define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52
3497 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
3499 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
3500 @param EAX Lower 32-bits of MSR value.
3501 @param EDX Upper 32-bits of MSR value.
3503 <b>Example usage</b>
3507 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
3508 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
3510 @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
3512 #define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53
3516 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
3518 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
3519 @param EAX Lower 32-bits of MSR value.
3520 @param EDX Upper 32-bits of MSR value.
3522 <b>Example usage</b>
3526 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
3527 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
3529 @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
3531 #define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54
3535 Package. Uncore C-box 5 perfmon box wide filter 0.
3537 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
3538 @param EAX Lower 32-bits of MSR value.
3539 @param EDX Upper 32-bits of MSR value.
3541 <b>Example usage</b>
3545 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
3546 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
3548 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
3550 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55
3554 Package. Uncore C-box 5 perfmon box wide filter1.
3556 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
3557 @param EAX Lower 32-bits of MSR value.
3558 @param EDX Upper 32-bits of MSR value.
3560 <b>Example usage</b>
3564 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
3565 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
3567 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
3569 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56
3573 Package. Uncore C-box 5 perfmon box wide status.
3575 @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
3576 @param EAX Lower 32-bits of MSR value.
3577 @param EDX Upper 32-bits of MSR value.
3579 <b>Example usage</b>
3583 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
3584 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
3586 @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
3588 #define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57
3592 Package. Uncore C-box 5 perfmon counter 0.
3594 @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
3595 @param EAX Lower 32-bits of MSR value.
3596 @param EDX Upper 32-bits of MSR value.
3598 <b>Example usage</b>
3602 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
3603 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
3605 @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
3607 #define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58
3611 Package. Uncore C-box 5 perfmon counter 1.
3613 @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
3614 @param EAX Lower 32-bits of MSR value.
3615 @param EDX Upper 32-bits of MSR value.
3617 <b>Example usage</b>
3621 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
3622 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
3624 @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
3626 #define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59
3630 Package. Uncore C-box 5 perfmon counter 2.
3632 @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
3633 @param EAX Lower 32-bits of MSR value.
3634 @param EDX Upper 32-bits of MSR value.
3636 <b>Example usage</b>
3640 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
3641 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
3643 @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
3645 #define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A
3649 Package. Uncore C-box 5 perfmon counter 3.
3651 @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
3652 @param EAX Lower 32-bits of MSR value.
3653 @param EDX Upper 32-bits of MSR value.
3655 <b>Example usage</b>
3659 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
3660 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
3662 @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
3664 #define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B
3668 Package. Uncore C-box 6 perfmon for box-wide control.
3670 @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
3671 @param EAX Lower 32-bits of MSR value.
3672 @param EDX Upper 32-bits of MSR value.
3674 <b>Example usage</b>
3678 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
3679 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
3681 @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
3683 #define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60
3687 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
3689 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
3690 @param EAX Lower 32-bits of MSR value.
3691 @param EDX Upper 32-bits of MSR value.
3693 <b>Example usage</b>
3697 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
3698 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
3700 @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
3702 #define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61
3706 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
3708 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
3709 @param EAX Lower 32-bits of MSR value.
3710 @param EDX Upper 32-bits of MSR value.
3712 <b>Example usage</b>
3716 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
3717 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
3719 @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
3721 #define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62
3725 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
3727 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
3728 @param EAX Lower 32-bits of MSR value.
3729 @param EDX Upper 32-bits of MSR value.
3731 <b>Example usage</b>
3735 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
3736 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
3738 @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
3740 #define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63
3744 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
3746 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
3747 @param EAX Lower 32-bits of MSR value.
3748 @param EDX Upper 32-bits of MSR value.
3750 <b>Example usage</b>
3754 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
3755 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
3757 @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
3759 #define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64
3763 Package. Uncore C-box 6 perfmon box wide filter 0.
3765 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
3766 @param EAX Lower 32-bits of MSR value.
3767 @param EDX Upper 32-bits of MSR value.
3769 <b>Example usage</b>
3773 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
3774 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
3776 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
3778 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65
3782 Package. Uncore C-box 6 perfmon box wide filter1.
3784 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
3785 @param EAX Lower 32-bits of MSR value.
3786 @param EDX Upper 32-bits of MSR value.
3788 <b>Example usage</b>
3792 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
3793 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
3795 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
3797 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66
3801 Package. Uncore C-box 6 perfmon box wide status.
3803 @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
3804 @param EAX Lower 32-bits of MSR value.
3805 @param EDX Upper 32-bits of MSR value.
3807 <b>Example usage</b>
3811 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
3812 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
3814 @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
3816 #define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67
3820 Package. Uncore C-box 6 perfmon counter 0.
3822 @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
3823 @param EAX Lower 32-bits of MSR value.
3824 @param EDX Upper 32-bits of MSR value.
3826 <b>Example usage</b>
3830 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
3831 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
3833 @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
3835 #define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68
3839 Package. Uncore C-box 6 perfmon counter 1.
3841 @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
3842 @param EAX Lower 32-bits of MSR value.
3843 @param EDX Upper 32-bits of MSR value.
3845 <b>Example usage</b>
3849 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
3850 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
3852 @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
3854 #define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69
3858 Package. Uncore C-box 6 perfmon counter 2.
3860 @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
3861 @param EAX Lower 32-bits of MSR value.
3862 @param EDX Upper 32-bits of MSR value.
3864 <b>Example usage</b>
3868 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
3869 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
3871 @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
3873 #define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A
3877 Package. Uncore C-box 6 perfmon counter 3.
3879 @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
3880 @param EAX Lower 32-bits of MSR value.
3881 @param EDX Upper 32-bits of MSR value.
3883 <b>Example usage</b>
3887 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
3888 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
3890 @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
3892 #define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B
3896 Package. Uncore C-box 7 perfmon for box-wide control.
3898 @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
3899 @param EAX Lower 32-bits of MSR value.
3900 @param EDX Upper 32-bits of MSR value.
3902 <b>Example usage</b>
3906 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
3907 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
3909 @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
3911 #define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70
3915 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
3917 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
3918 @param EAX Lower 32-bits of MSR value.
3919 @param EDX Upper 32-bits of MSR value.
3921 <b>Example usage</b>
3925 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
3926 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
3928 @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
3930 #define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71
3934 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
3936 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
3937 @param EAX Lower 32-bits of MSR value.
3938 @param EDX Upper 32-bits of MSR value.
3940 <b>Example usage</b>
3944 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
3945 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
3947 @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
3949 #define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72
3953 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
3955 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
3956 @param EAX Lower 32-bits of MSR value.
3957 @param EDX Upper 32-bits of MSR value.
3959 <b>Example usage</b>
3963 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
3964 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
3966 @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
3968 #define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73
3972 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
3974 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
3975 @param EAX Lower 32-bits of MSR value.
3976 @param EDX Upper 32-bits of MSR value.
3978 <b>Example usage</b>
3982 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
3983 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
3985 @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
3987 #define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74
3991 Package. Uncore C-box 7 perfmon box wide filter 0.
3993 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
3994 @param EAX Lower 32-bits of MSR value.
3995 @param EDX Upper 32-bits of MSR value.
3997 <b>Example usage</b>
4001 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
4002 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
4004 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
4006 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75
4010 Package. Uncore C-box 7 perfmon box wide filter1.
4012 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
4013 @param EAX Lower 32-bits of MSR value.
4014 @param EDX Upper 32-bits of MSR value.
4016 <b>Example usage</b>
4020 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
4021 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
4023 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
4025 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76
4029 Package. Uncore C-box 7 perfmon box wide status.
4031 @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
4032 @param EAX Lower 32-bits of MSR value.
4033 @param EDX Upper 32-bits of MSR value.
4035 <b>Example usage</b>
4039 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
4040 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
4042 @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
4044 #define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77
4048 Package. Uncore C-box 7 perfmon counter 0.
4050 @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
4051 @param EAX Lower 32-bits of MSR value.
4052 @param EDX Upper 32-bits of MSR value.
4054 <b>Example usage</b>
4058 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
4059 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
4061 @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4063 #define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78
4067 Package. Uncore C-box 7 perfmon counter 1.
4069 @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
4070 @param EAX Lower 32-bits of MSR value.
4071 @param EDX Upper 32-bits of MSR value.
4073 <b>Example usage</b>
4077 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
4078 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
4080 @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4082 #define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79
4086 Package. Uncore C-box 7 perfmon counter 2.
4088 @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
4089 @param EAX Lower 32-bits of MSR value.
4090 @param EDX Upper 32-bits of MSR value.
4092 <b>Example usage</b>
4096 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
4097 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
4099 @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4101 #define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A
4105 Package. Uncore C-box 7 perfmon counter 3.
4107 @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
4108 @param EAX Lower 32-bits of MSR value.
4109 @param EDX Upper 32-bits of MSR value.
4111 <b>Example usage</b>
4115 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
4116 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
4118 @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4120 #define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B
4124 Package. Uncore C-box 8 perfmon local box wide control.
4126 @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
4127 @param EAX Lower 32-bits of MSR value.
4128 @param EDX Upper 32-bits of MSR value.
4130 <b>Example usage</b>
4134 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
4135 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
4137 @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
4139 #define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80
4143 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
4145 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
4146 @param EAX Lower 32-bits of MSR value.
4147 @param EDX Upper 32-bits of MSR value.
4149 <b>Example usage</b>
4153 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
4154 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
4156 @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
4158 #define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81
4162 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
4164 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
4165 @param EAX Lower 32-bits of MSR value.
4166 @param EDX Upper 32-bits of MSR value.
4168 <b>Example usage</b>
4172 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
4173 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
4175 @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
4177 #define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82
4181 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
4183 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
4184 @param EAX Lower 32-bits of MSR value.
4185 @param EDX Upper 32-bits of MSR value.
4187 <b>Example usage</b>
4191 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
4192 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
4194 @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
4196 #define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83
4200 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
4202 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
4203 @param EAX Lower 32-bits of MSR value.
4204 @param EDX Upper 32-bits of MSR value.
4206 <b>Example usage</b>
4210 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
4211 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
4213 @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
4215 #define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84
4219 Package. Uncore C-box 8 perfmon box wide filter0.
4221 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
4222 @param EAX Lower 32-bits of MSR value.
4223 @param EDX Upper 32-bits of MSR value.
4225 <b>Example usage</b>
4229 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
4230 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
4232 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
4234 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85
4238 Package. Uncore C-box 8 perfmon box wide filter1.
4240 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
4241 @param EAX Lower 32-bits of MSR value.
4242 @param EDX Upper 32-bits of MSR value.
4244 <b>Example usage</b>
4248 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
4249 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
4251 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
4253 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86
4257 Package. Uncore C-box 8 perfmon box wide status.
4259 @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
4260 @param EAX Lower 32-bits of MSR value.
4261 @param EDX Upper 32-bits of MSR value.
4263 <b>Example usage</b>
4267 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
4268 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
4270 @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
4272 #define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87
4276 Package. Uncore C-box 8 perfmon counter 0.
4278 @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
4279 @param EAX Lower 32-bits of MSR value.
4280 @param EDX Upper 32-bits of MSR value.
4282 <b>Example usage</b>
4286 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
4287 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
4289 @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
4291 #define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88
4295 Package. Uncore C-box 8 perfmon counter 1.
4297 @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
4298 @param EAX Lower 32-bits of MSR value.
4299 @param EDX Upper 32-bits of MSR value.
4301 <b>Example usage</b>
4305 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
4306 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
4308 @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
4310 #define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89
4314 Package. Uncore C-box 8 perfmon counter 2.
4316 @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
4317 @param EAX Lower 32-bits of MSR value.
4318 @param EDX Upper 32-bits of MSR value.
4320 <b>Example usage</b>
4324 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
4325 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
4327 @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
4329 #define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A
4333 Package. Uncore C-box 8 perfmon counter 3.
4335 @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
4336 @param EAX Lower 32-bits of MSR value.
4337 @param EDX Upper 32-bits of MSR value.
4339 <b>Example usage</b>
4343 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
4344 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
4346 @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
4348 #define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B
4352 Package. Uncore C-box 9 perfmon local box wide control.
4354 @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
4355 @param EAX Lower 32-bits of MSR value.
4356 @param EDX Upper 32-bits of MSR value.
4358 <b>Example usage</b>
4362 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
4363 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
4365 @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
4367 #define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90
4371 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
4373 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
4374 @param EAX Lower 32-bits of MSR value.
4375 @param EDX Upper 32-bits of MSR value.
4377 <b>Example usage</b>
4381 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
4382 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
4384 @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
4386 #define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91
4390 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
4392 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
4393 @param EAX Lower 32-bits of MSR value.
4394 @param EDX Upper 32-bits of MSR value.
4396 <b>Example usage</b>
4400 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
4401 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
4403 @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
4405 #define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92
4409 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
4411 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
4412 @param EAX Lower 32-bits of MSR value.
4413 @param EDX Upper 32-bits of MSR value.
4415 <b>Example usage</b>
4419 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
4420 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
4422 @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
4424 #define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93
4428 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
4430 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
4431 @param EAX Lower 32-bits of MSR value.
4432 @param EDX Upper 32-bits of MSR value.
4434 <b>Example usage</b>
4438 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
4439 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
4441 @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
4443 #define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94
4447 Package. Uncore C-box 9 perfmon box wide filter0.
4449 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
4450 @param EAX Lower 32-bits of MSR value.
4451 @param EDX Upper 32-bits of MSR value.
4453 <b>Example usage</b>
4457 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
4458 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
4460 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
4462 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95
4466 Package. Uncore C-box 9 perfmon box wide filter1.
4468 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
4469 @param EAX Lower 32-bits of MSR value.
4470 @param EDX Upper 32-bits of MSR value.
4472 <b>Example usage</b>
4476 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
4477 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
4479 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
4481 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96
4485 Package. Uncore C-box 9 perfmon box wide status.
4487 @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
4488 @param EAX Lower 32-bits of MSR value.
4489 @param EDX Upper 32-bits of MSR value.
4491 <b>Example usage</b>
4495 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
4496 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
4498 @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
4500 #define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97
4504 Package. Uncore C-box 9 perfmon counter 0.
4506 @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
4507 @param EAX Lower 32-bits of MSR value.
4508 @param EDX Upper 32-bits of MSR value.
4510 <b>Example usage</b>
4514 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
4515 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
4517 @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
4519 #define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98
4523 Package. Uncore C-box 9 perfmon counter 1.
4525 @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
4526 @param EAX Lower 32-bits of MSR value.
4527 @param EDX Upper 32-bits of MSR value.
4529 <b>Example usage</b>
4533 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
4534 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
4536 @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
4538 #define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99
4542 Package. Uncore C-box 9 perfmon counter 2.
4544 @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
4545 @param EAX Lower 32-bits of MSR value.
4546 @param EDX Upper 32-bits of MSR value.
4548 <b>Example usage</b>
4552 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
4553 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
4555 @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
4557 #define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A
4561 Package. Uncore C-box 9 perfmon counter 3.
4563 @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
4564 @param EAX Lower 32-bits of MSR value.
4565 @param EDX Upper 32-bits of MSR value.
4567 <b>Example usage</b>
4571 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
4572 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
4574 @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
4576 #define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B
4580 Package. Uncore C-box 10 perfmon local box wide control.
4582 @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
4583 @param EAX Lower 32-bits of MSR value.
4584 @param EDX Upper 32-bits of MSR value.
4586 <b>Example usage</b>
4590 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
4591 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
4593 @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
4595 #define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0
4599 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
4601 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
4602 @param EAX Lower 32-bits of MSR value.
4603 @param EDX Upper 32-bits of MSR value.
4605 <b>Example usage</b>
4609 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
4610 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
4612 @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
4614 #define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1
4618 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
4620 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
4621 @param EAX Lower 32-bits of MSR value.
4622 @param EDX Upper 32-bits of MSR value.
4624 <b>Example usage</b>
4628 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
4629 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
4631 @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
4633 #define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2
4637 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
4639 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
4640 @param EAX Lower 32-bits of MSR value.
4641 @param EDX Upper 32-bits of MSR value.
4643 <b>Example usage</b>
4647 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
4648 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
4650 @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
4652 #define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3
4656 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
4658 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
4659 @param EAX Lower 32-bits of MSR value.
4660 @param EDX Upper 32-bits of MSR value.
4662 <b>Example usage</b>
4666 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
4667 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
4669 @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
4671 #define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4
4675 Package. Uncore C-box 10 perfmon box wide filter0.
4677 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
4678 @param EAX Lower 32-bits of MSR value.
4679 @param EDX Upper 32-bits of MSR value.
4681 <b>Example usage</b>
4685 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
4686 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
4688 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
4690 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5
4694 Package. Uncore C-box 10 perfmon box wide filter1.
4696 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
4697 @param EAX Lower 32-bits of MSR value.
4698 @param EDX Upper 32-bits of MSR value.
4700 <b>Example usage</b>
4704 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
4705 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
4707 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
4709 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6
4713 Package. Uncore C-box 10 perfmon box wide status.
4715 @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
4716 @param EAX Lower 32-bits of MSR value.
4717 @param EDX Upper 32-bits of MSR value.
4719 <b>Example usage</b>
4723 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
4724 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
4726 @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
4728 #define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7
4732 Package. Uncore C-box 10 perfmon counter 0.
4734 @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
4735 @param EAX Lower 32-bits of MSR value.
4736 @param EDX Upper 32-bits of MSR value.
4738 <b>Example usage</b>
4742 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
4743 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
4745 @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
4747 #define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8
4751 Package. Uncore C-box 10 perfmon counter 1.
4753 @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
4754 @param EAX Lower 32-bits of MSR value.
4755 @param EDX Upper 32-bits of MSR value.
4757 <b>Example usage</b>
4761 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
4762 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
4764 @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
4766 #define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9
4770 Package. Uncore C-box 10 perfmon counter 2.
4772 @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
4773 @param EAX Lower 32-bits of MSR value.
4774 @param EDX Upper 32-bits of MSR value.
4776 <b>Example usage</b>
4780 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
4781 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
4783 @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
4785 #define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA
4789 Package. Uncore C-box 10 perfmon counter 3.
4791 @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
4792 @param EAX Lower 32-bits of MSR value.
4793 @param EDX Upper 32-bits of MSR value.
4795 <b>Example usage</b>
4799 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
4800 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
4802 @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
4804 #define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB
4808 Package. Uncore C-box 11 perfmon local box wide control.
4810 @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
4811 @param EAX Lower 32-bits of MSR value.
4812 @param EDX Upper 32-bits of MSR value.
4814 <b>Example usage</b>
4818 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
4819 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
4821 @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
4823 #define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0
4827 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
4829 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
4830 @param EAX Lower 32-bits of MSR value.
4831 @param EDX Upper 32-bits of MSR value.
4833 <b>Example usage</b>
4837 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
4838 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
4840 @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
4842 #define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1
4846 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
4848 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
4849 @param EAX Lower 32-bits of MSR value.
4850 @param EDX Upper 32-bits of MSR value.
4852 <b>Example usage</b>
4856 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
4857 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
4859 @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
4861 #define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2
4865 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
4867 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
4868 @param EAX Lower 32-bits of MSR value.
4869 @param EDX Upper 32-bits of MSR value.
4871 <b>Example usage</b>
4875 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
4876 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
4878 @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
4880 #define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3
4884 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
4886 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
4887 @param EAX Lower 32-bits of MSR value.
4888 @param EDX Upper 32-bits of MSR value.
4890 <b>Example usage</b>
4894 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
4895 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
4897 @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
4899 #define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4
4903 Package. Uncore C-box 11 perfmon box wide filter0.
4905 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
4906 @param EAX Lower 32-bits of MSR value.
4907 @param EDX Upper 32-bits of MSR value.
4909 <b>Example usage</b>
4913 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
4914 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
4916 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
4918 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5
4922 Package. Uncore C-box 11 perfmon box wide filter1.
4924 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
4925 @param EAX Lower 32-bits of MSR value.
4926 @param EDX Upper 32-bits of MSR value.
4928 <b>Example usage</b>
4932 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
4933 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
4935 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
4937 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6
4941 Package. Uncore C-box 11 perfmon box wide status.
4943 @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
4944 @param EAX Lower 32-bits of MSR value.
4945 @param EDX Upper 32-bits of MSR value.
4947 <b>Example usage</b>
4951 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
4952 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
4954 @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
4956 #define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7
4960 Package. Uncore C-box 11 perfmon counter 0.
4962 @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
4963 @param EAX Lower 32-bits of MSR value.
4964 @param EDX Upper 32-bits of MSR value.
4966 <b>Example usage</b>
4970 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
4971 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
4973 @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
4975 #define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8
4979 Package. Uncore C-box 11 perfmon counter 1.
4981 @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
4982 @param EAX Lower 32-bits of MSR value.
4983 @param EDX Upper 32-bits of MSR value.
4985 <b>Example usage</b>
4989 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
4990 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
4992 @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
4994 #define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9
4998 Package. Uncore C-box 11 perfmon counter 2.
5000 @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
5001 @param EAX Lower 32-bits of MSR value.
5002 @param EDX Upper 32-bits of MSR value.
5004 <b>Example usage</b>
5008 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
5009 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
5011 @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
5013 #define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA
5017 Package. Uncore C-box 11 perfmon counter 3.
5019 @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
5020 @param EAX Lower 32-bits of MSR value.
5021 @param EDX Upper 32-bits of MSR value.
5023 <b>Example usage</b>
5027 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
5028 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
5030 @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
5032 #define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB
5036 Package. Uncore C-box 12 perfmon local box wide control.
5038 @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
5039 @param EAX Lower 32-bits of MSR value.
5040 @param EDX Upper 32-bits of MSR value.
5042 <b>Example usage</b>
5046 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
5047 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
5049 @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
5051 #define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0
5055 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
5057 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
5058 @param EAX Lower 32-bits of MSR value.
5059 @param EDX Upper 32-bits of MSR value.
5061 <b>Example usage</b>
5065 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
5066 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
5068 @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
5070 #define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1
5074 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
5076 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
5077 @param EAX Lower 32-bits of MSR value.
5078 @param EDX Upper 32-bits of MSR value.
5080 <b>Example usage</b>
5084 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
5085 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
5087 @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
5089 #define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2
5093 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
5095 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
5096 @param EAX Lower 32-bits of MSR value.
5097 @param EDX Upper 32-bits of MSR value.
5099 <b>Example usage</b>
5103 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
5104 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
5106 @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
5108 #define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3
5112 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
5114 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
5115 @param EAX Lower 32-bits of MSR value.
5116 @param EDX Upper 32-bits of MSR value.
5118 <b>Example usage</b>
5122 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
5123 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
5125 @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
5127 #define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4
5131 Package. Uncore C-box 12 perfmon box wide filter0.
5133 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
5134 @param EAX Lower 32-bits of MSR value.
5135 @param EDX Upper 32-bits of MSR value.
5137 <b>Example usage</b>
5141 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
5142 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
5144 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
5146 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5
5150 Package. Uncore C-box 12 perfmon box wide filter1.
5152 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
5153 @param EAX Lower 32-bits of MSR value.
5154 @param EDX Upper 32-bits of MSR value.
5156 <b>Example usage</b>
5160 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
5161 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
5163 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
5165 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6
5169 Package. Uncore C-box 12 perfmon box wide status.
5171 @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
5172 @param EAX Lower 32-bits of MSR value.
5173 @param EDX Upper 32-bits of MSR value.
5175 <b>Example usage</b>
5179 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
5180 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
5182 @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
5184 #define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7
5188 Package. Uncore C-box 12 perfmon counter 0.
5190 @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
5191 @param EAX Lower 32-bits of MSR value.
5192 @param EDX Upper 32-bits of MSR value.
5194 <b>Example usage</b>
5198 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
5199 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
5201 @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
5203 #define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8
5207 Package. Uncore C-box 12 perfmon counter 1.
5209 @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
5210 @param EAX Lower 32-bits of MSR value.
5211 @param EDX Upper 32-bits of MSR value.
5213 <b>Example usage</b>
5217 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
5218 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
5220 @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
5222 #define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9
5226 Package. Uncore C-box 12 perfmon counter 2.
5228 @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
5229 @param EAX Lower 32-bits of MSR value.
5230 @param EDX Upper 32-bits of MSR value.
5232 <b>Example usage</b>
5236 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
5237 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
5239 @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
5241 #define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA
5245 Package. Uncore C-box 12 perfmon counter 3.
5247 @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
5248 @param EAX Lower 32-bits of MSR value.
5249 @param EDX Upper 32-bits of MSR value.
5251 <b>Example usage</b>
5255 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
5256 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
5258 @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
5260 #define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB
5264 Package. Uncore C-box 13 perfmon local box wide control.
5266 @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
5267 @param EAX Lower 32-bits of MSR value.
5268 @param EDX Upper 32-bits of MSR value.
5270 <b>Example usage</b>
5274 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
5275 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
5277 @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
5279 #define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0
5283 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
5285 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
5286 @param EAX Lower 32-bits of MSR value.
5287 @param EDX Upper 32-bits of MSR value.
5289 <b>Example usage</b>
5293 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
5294 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
5296 @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
5298 #define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1
5302 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
5304 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
5305 @param EAX Lower 32-bits of MSR value.
5306 @param EDX Upper 32-bits of MSR value.
5308 <b>Example usage</b>
5312 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
5313 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
5315 @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
5317 #define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2
5321 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
5323 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
5324 @param EAX Lower 32-bits of MSR value.
5325 @param EDX Upper 32-bits of MSR value.
5327 <b>Example usage</b>
5331 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
5332 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
5334 @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
5336 #define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3
5340 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
5342 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
5343 @param EAX Lower 32-bits of MSR value.
5344 @param EDX Upper 32-bits of MSR value.
5346 <b>Example usage</b>
5350 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
5351 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
5353 @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
5355 #define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4
5359 Package. Uncore C-box 13 perfmon box wide filter0.
5361 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
5362 @param EAX Lower 32-bits of MSR value.
5363 @param EDX Upper 32-bits of MSR value.
5365 <b>Example usage</b>
5369 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
5370 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
5372 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
5374 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5
5378 Package. Uncore C-box 13 perfmon box wide filter1.
5380 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
5381 @param EAX Lower 32-bits of MSR value.
5382 @param EDX Upper 32-bits of MSR value.
5384 <b>Example usage</b>
5388 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
5389 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
5391 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
5393 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6
5397 Package. Uncore C-box 13 perfmon box wide status.
5399 @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
5400 @param EAX Lower 32-bits of MSR value.
5401 @param EDX Upper 32-bits of MSR value.
5403 <b>Example usage</b>
5407 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
5408 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
5410 @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
5412 #define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7
5416 Package. Uncore C-box 13 perfmon counter 0.
5418 @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
5419 @param EAX Lower 32-bits of MSR value.
5420 @param EDX Upper 32-bits of MSR value.
5422 <b>Example usage</b>
5426 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
5427 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
5429 @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
5431 #define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8
5435 Package. Uncore C-box 13 perfmon counter 1.
5437 @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
5438 @param EAX Lower 32-bits of MSR value.
5439 @param EDX Upper 32-bits of MSR value.
5441 <b>Example usage</b>
5445 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
5446 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
5448 @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
5450 #define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9
5454 Package. Uncore C-box 13 perfmon counter 2.
5456 @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
5457 @param EAX Lower 32-bits of MSR value.
5458 @param EDX Upper 32-bits of MSR value.
5460 <b>Example usage</b>
5464 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
5465 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
5467 @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
5469 #define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA
5473 Package. Uncore C-box 13 perfmon counter 3.
5475 @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
5476 @param EAX Lower 32-bits of MSR value.
5477 @param EDX Upper 32-bits of MSR value.
5479 <b>Example usage</b>
5483 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
5484 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
5486 @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
5488 #define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB
5492 Package. Uncore C-box 14 perfmon local box wide control.
5494 @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
5495 @param EAX Lower 32-bits of MSR value.
5496 @param EDX Upper 32-bits of MSR value.
5498 <b>Example usage</b>
5502 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
5503 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
5505 @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
5507 #define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0
5511 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
5513 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
5514 @param EAX Lower 32-bits of MSR value.
5515 @param EDX Upper 32-bits of MSR value.
5517 <b>Example usage</b>
5521 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
5522 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
5524 @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
5526 #define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1
5530 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
5532 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
5533 @param EAX Lower 32-bits of MSR value.
5534 @param EDX Upper 32-bits of MSR value.
5536 <b>Example usage</b>
5540 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
5541 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
5543 @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
5545 #define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2
5549 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
5551 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
5552 @param EAX Lower 32-bits of MSR value.
5553 @param EDX Upper 32-bits of MSR value.
5555 <b>Example usage</b>
5559 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
5560 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
5562 @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
5564 #define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3
5568 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
5570 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
5571 @param EAX Lower 32-bits of MSR value.
5572 @param EDX Upper 32-bits of MSR value.
5574 <b>Example usage</b>
5578 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
5579 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
5581 @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
5583 #define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4
5587 Package. Uncore C-box 14 perfmon box wide filter0.
5589 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
5590 @param EAX Lower 32-bits of MSR value.
5591 @param EDX Upper 32-bits of MSR value.
5593 <b>Example usage</b>
5597 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
5598 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
5600 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
5602 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5
5606 Package. Uncore C-box 14 perfmon box wide filter1.
5608 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
5609 @param EAX Lower 32-bits of MSR value.
5610 @param EDX Upper 32-bits of MSR value.
5612 <b>Example usage</b>
5616 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
5617 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
5619 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
5621 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6
5625 Package. Uncore C-box 14 perfmon box wide status.
5627 @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
5628 @param EAX Lower 32-bits of MSR value.
5629 @param EDX Upper 32-bits of MSR value.
5631 <b>Example usage</b>
5635 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
5636 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
5638 @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
5640 #define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7
5644 Package. Uncore C-box 14 perfmon counter 0.
5646 @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
5647 @param EAX Lower 32-bits of MSR value.
5648 @param EDX Upper 32-bits of MSR value.
5650 <b>Example usage</b>
5654 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
5655 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
5657 @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
5659 #define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8
5663 Package. Uncore C-box 14 perfmon counter 1.
5665 @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
5666 @param EAX Lower 32-bits of MSR value.
5667 @param EDX Upper 32-bits of MSR value.
5669 <b>Example usage</b>
5673 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
5674 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
5676 @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
5678 #define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9
5682 Package. Uncore C-box 14 perfmon counter 2.
5684 @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
5685 @param EAX Lower 32-bits of MSR value.
5686 @param EDX Upper 32-bits of MSR value.
5688 <b>Example usage</b>
5692 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
5693 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
5695 @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
5697 #define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA
5701 Package. Uncore C-box 14 perfmon counter 3.
5703 @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
5704 @param EAX Lower 32-bits of MSR value.
5705 @param EDX Upper 32-bits of MSR value.
5707 <b>Example usage</b>
5711 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
5712 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
5714 @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
5716 #define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB
5720 Package. Uncore C-box 15 perfmon local box wide control.
5722 @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
5723 @param EAX Lower 32-bits of MSR value.
5724 @param EDX Upper 32-bits of MSR value.
5726 <b>Example usage</b>
5730 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
5731 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
5733 @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
5735 #define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0
5739 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
5741 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
5742 @param EAX Lower 32-bits of MSR value.
5743 @param EDX Upper 32-bits of MSR value.
5745 <b>Example usage</b>
5749 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
5750 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
5752 @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
5754 #define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1
5758 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
5760 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
5761 @param EAX Lower 32-bits of MSR value.
5762 @param EDX Upper 32-bits of MSR value.
5764 <b>Example usage</b>
5768 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
5769 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
5771 @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
5773 #define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2
5777 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
5779 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
5780 @param EAX Lower 32-bits of MSR value.
5781 @param EDX Upper 32-bits of MSR value.
5783 <b>Example usage</b>
5787 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
5788 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
5790 @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
5792 #define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3
5796 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
5798 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
5799 @param EAX Lower 32-bits of MSR value.
5800 @param EDX Upper 32-bits of MSR value.
5802 <b>Example usage</b>
5806 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
5807 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
5809 @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
5811 #define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4
5815 Package. Uncore C-box 15 perfmon box wide filter0.
5817 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
5818 @param EAX Lower 32-bits of MSR value.
5819 @param EDX Upper 32-bits of MSR value.
5821 <b>Example usage</b>
5825 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
5826 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
5828 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
5830 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5
5834 Package. Uncore C-box 15 perfmon box wide filter1.
5836 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
5837 @param EAX Lower 32-bits of MSR value.
5838 @param EDX Upper 32-bits of MSR value.
5840 <b>Example usage</b>
5844 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
5845 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
5847 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
5849 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6
5853 Package. Uncore C-box 15 perfmon box wide status.
5855 @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
5856 @param EAX Lower 32-bits of MSR value.
5857 @param EDX Upper 32-bits of MSR value.
5859 <b>Example usage</b>
5863 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
5864 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
5866 @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
5868 #define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7
5872 Package. Uncore C-box 15 perfmon counter 0.
5874 @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
5875 @param EAX Lower 32-bits of MSR value.
5876 @param EDX Upper 32-bits of MSR value.
5878 <b>Example usage</b>
5882 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
5883 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
5885 @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
5887 #define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8
5891 Package. Uncore C-box 15 perfmon counter 1.
5893 @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
5894 @param EAX Lower 32-bits of MSR value.
5895 @param EDX Upper 32-bits of MSR value.
5897 <b>Example usage</b>
5901 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
5902 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
5904 @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
5906 #define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9
5910 Package. Uncore C-box 15 perfmon counter 2.
5912 @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
5913 @param EAX Lower 32-bits of MSR value.
5914 @param EDX Upper 32-bits of MSR value.
5916 <b>Example usage</b>
5920 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
5921 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
5923 @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
5925 #define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA
5929 Package. Uncore C-box 15 perfmon counter 3.
5931 @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
5932 @param EAX Lower 32-bits of MSR value.
5933 @param EDX Upper 32-bits of MSR value.
5935 <b>Example usage</b>
5939 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
5940 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
5942 @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
5944 #define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB
5948 Package. Uncore C-box 16 perfmon for box-wide control.
5950 @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
5951 @param EAX Lower 32-bits of MSR value.
5952 @param EDX Upper 32-bits of MSR value.
5954 <b>Example usage</b>
5958 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
5959 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
5961 @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
5963 #define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00
5967 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
5969 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
5970 @param EAX Lower 32-bits of MSR value.
5971 @param EDX Upper 32-bits of MSR value.
5973 <b>Example usage</b>
5977 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
5978 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
5980 @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
5982 #define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01
5986 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
5988 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
5989 @param EAX Lower 32-bits of MSR value.
5990 @param EDX Upper 32-bits of MSR value.
5992 <b>Example usage</b>
5996 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
5997 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
5999 @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
6001 #define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02
6005 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
6007 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
6008 @param EAX Lower 32-bits of MSR value.
6009 @param EDX Upper 32-bits of MSR value.
6011 <b>Example usage</b>
6015 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
6016 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
6018 @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
6020 #define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03
6024 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
6026 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
6027 @param EAX Lower 32-bits of MSR value.
6028 @param EDX Upper 32-bits of MSR value.
6030 <b>Example usage</b>
6034 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
6035 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
6037 @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
6039 #define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04
6043 Package. Uncore C-box 16 perfmon box wide filter 0.
6045 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
6046 @param EAX Lower 32-bits of MSR value.
6047 @param EDX Upper 32-bits of MSR value.
6049 <b>Example usage</b>
6053 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
6054 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
6056 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
6058 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05
6062 Package. Uncore C-box 16 perfmon box wide filter 1.
6064 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
6065 @param EAX Lower 32-bits of MSR value.
6066 @param EDX Upper 32-bits of MSR value.
6068 <b>Example usage</b>
6072 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
6073 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
6075 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
6077 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06
6081 Package. Uncore C-box 16 perfmon box wide status.
6083 @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
6084 @param EAX Lower 32-bits of MSR value.
6085 @param EDX Upper 32-bits of MSR value.
6087 <b>Example usage</b>
6091 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
6092 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
6094 @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
6096 #define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07
6100 Package. Uncore C-box 16 perfmon counter 0.
6102 @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
6103 @param EAX Lower 32-bits of MSR value.
6104 @param EDX Upper 32-bits of MSR value.
6106 <b>Example usage</b>
6110 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
6111 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
6113 @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
6115 #define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08
6119 Package. Uncore C-box 16 perfmon counter 1.
6121 @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
6122 @param EAX Lower 32-bits of MSR value.
6123 @param EDX Upper 32-bits of MSR value.
6125 <b>Example usage</b>
6129 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
6130 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
6132 @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
6134 #define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09
6138 Package. Uncore C-box 16 perfmon counter 2.
6140 @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
6141 @param EAX Lower 32-bits of MSR value.
6142 @param EDX Upper 32-bits of MSR value.
6144 <b>Example usage</b>
6148 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
6149 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
6151 @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
6153 #define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A
6157 Package. Uncore C-box 16 perfmon counter 3.
6159 @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
6160 @param EAX Lower 32-bits of MSR value.
6161 @param EDX Upper 32-bits of MSR value.
6163 <b>Example usage</b>
6167 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
6168 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
6170 @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
6172 #define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B
6176 Package. Uncore C-box 17 perfmon for box-wide control.
6178 @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
6179 @param EAX Lower 32-bits of MSR value.
6180 @param EDX Upper 32-bits of MSR value.
6182 <b>Example usage</b>
6186 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
6187 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
6189 @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
6191 #define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10
6195 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
6197 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
6198 @param EAX Lower 32-bits of MSR value.
6199 @param EDX Upper 32-bits of MSR value.
6201 <b>Example usage</b>
6205 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
6206 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
6208 @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
6210 #define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11
6214 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
6216 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
6217 @param EAX Lower 32-bits of MSR value.
6218 @param EDX Upper 32-bits of MSR value.
6220 <b>Example usage</b>
6224 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
6225 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
6227 @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
6229 #define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12
6233 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
6235 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
6236 @param EAX Lower 32-bits of MSR value.
6237 @param EDX Upper 32-bits of MSR value.
6239 <b>Example usage</b>
6243 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
6244 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
6246 @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
6248 #define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13
6252 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
6254 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
6255 @param EAX Lower 32-bits of MSR value.
6256 @param EDX Upper 32-bits of MSR value.
6258 <b>Example usage</b>
6262 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
6263 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
6265 @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
6267 #define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14
6271 Package. Uncore C-box 17 perfmon box wide filter 0.
6273 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
6274 @param EAX Lower 32-bits of MSR value.
6275 @param EDX Upper 32-bits of MSR value.
6277 <b>Example usage</b>
6281 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
6282 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
6284 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
6286 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15
6290 Package. Uncore C-box 17 perfmon box wide filter1.
6292 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
6293 @param EAX Lower 32-bits of MSR value.
6294 @param EDX Upper 32-bits of MSR value.
6296 <b>Example usage</b>
6300 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
6301 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
6303 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
6305 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16
6308 Package. Uncore C-box 17 perfmon box wide status.
6310 @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
6311 @param EAX Lower 32-bits of MSR value.
6312 @param EDX Upper 32-bits of MSR value.
6314 <b>Example usage</b>
6318 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
6319 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
6321 @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
6323 #define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17
6327 Package. Uncore C-box 17 perfmon counter n.
6329 @param ECX MSR_HASWELL_E_C17_PMON_CTRn
6330 @param EAX Lower 32-bits of MSR value.
6331 @param EDX Upper 32-bits of MSR value.
6333 <b>Example usage</b>
6337 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
6338 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
6340 @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
6341 MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
6342 MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
6343 MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
6346 #define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18
6347 #define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19
6348 #define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A
6349 #define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B