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UefiCpuPkg/MtrrLib: Fix a MTRR calculation bug
[mirror_edk2.git] / UefiCpuPkg / Library / MtrrLib / MtrrLib.c
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e50466da 1/** @file\r
2 MTRR setting library\r
3\r
3143144b 4 @par Note:\r
81f56049
JF
5 Most of services in this library instance are suggested to be invoked by BSP only,\r
6 except for MtrrSetAllMtrrs() which is used to sync BSP's MTRR setting to APs.\r
7\r
5a6c5af6 8 Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc 9 This program and the accompanying materials\r
e50466da 10 are licensed and made available under the terms and conditions of the BSD License\r
11 which accompanies this distribution. The full text of the license may be found at\r
12 http://opensource.org/licenses/bsd-license.php\r
13\r
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
16\r
17**/\r
18\r
2bbd7e2f 19#include <Uefi.h>\r
3bb13d35
RN
20#include <Register/Cpuid.h>\r
21#include <Register/Msr.h>\r
22\r
e50466da 23#include <Library/MtrrLib.h>\r
24#include <Library/BaseLib.h>\r
25#include <Library/CpuLib.h>\r
26#include <Library/BaseMemoryLib.h>\r
27#include <Library/DebugLib.h>\r
28\r
eecad349
JF
29#define OR_SEED 0x0101010101010101ull\r
30#define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull\r
2bbd7e2f
RN
31#define MAX_WEIGHT MAX_UINT8\r
32#define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB)\r
8051302a 33#define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B);\r
2bbd7e2f 34\r
3143144b
RN
35#define M(x,y) ((x) * VertexCount + (y))\r
36#define O(x,y) ((y) * VertexCount + (x))\r
2bbd7e2f 37\r
c878cee4 38//\r
39// Context to save and restore when MTRRs are programmed\r
40//\r
41typedef struct {\r
42 UINTN Cr4;\r
43 BOOLEAN InterruptState;\r
44} MTRR_CONTEXT;\r
45\r
8051302a 46typedef struct {\r
2bbd7e2f
RN
47 UINT64 Address;\r
48 UINT64 Alignment;\r
8051302a 49 UINT64 Length;\r
57951033 50 MTRR_MEMORY_CACHE_TYPE Type : 7;\r
2bbd7e2f
RN
51\r
52 //\r
53 // Temprary use for calculating the best MTRR settings.\r
54 //\r
55 BOOLEAN Visited : 1;\r
56 UINT8 Weight;\r
57 UINT16 Previous;\r
58} MTRR_LIB_ADDRESS;\r
8051302a 59\r
e50466da 60//\r
61// This table defines the offset, base and length of the fixed MTRRs\r
62//\r
f877f300 63CONST FIXED_MTRR mMtrrLibFixedMtrrTable[] = {\r
e50466da 64 {\r
af838805 65 MSR_IA32_MTRR_FIX64K_00000,\r
e50466da 66 0,\r
67 SIZE_64KB\r
68 },\r
69 {\r
af838805 70 MSR_IA32_MTRR_FIX16K_80000,\r
e50466da 71 0x80000,\r
72 SIZE_16KB\r
73 },\r
74 {\r
af838805 75 MSR_IA32_MTRR_FIX16K_A0000,\r
e50466da 76 0xA0000,\r
77 SIZE_16KB\r
78 },\r
79 {\r
af838805 80 MSR_IA32_MTRR_FIX4K_C0000,\r
e50466da 81 0xC0000,\r
82 SIZE_4KB\r
83 },\r
84 {\r
af838805 85 MSR_IA32_MTRR_FIX4K_C8000,\r
e50466da 86 0xC8000,\r
87 SIZE_4KB\r
88 },\r
89 {\r
af838805 90 MSR_IA32_MTRR_FIX4K_D0000,\r
e50466da 91 0xD0000,\r
92 SIZE_4KB\r
93 },\r
94 {\r
af838805 95 MSR_IA32_MTRR_FIX4K_D8000,\r
e50466da 96 0xD8000,\r
97 SIZE_4KB\r
98 },\r
99 {\r
af838805 100 MSR_IA32_MTRR_FIX4K_E0000,\r
e50466da 101 0xE0000,\r
102 SIZE_4KB\r
103 },\r
104 {\r
af838805 105 MSR_IA32_MTRR_FIX4K_E8000,\r
e50466da 106 0xE8000,\r
107 SIZE_4KB\r
108 },\r
109 {\r
af838805 110 MSR_IA32_MTRR_FIX4K_F0000,\r
e50466da 111 0xF0000,\r
112 SIZE_4KB\r
113 },\r
114 {\r
af838805 115 MSR_IA32_MTRR_FIX4K_F8000,\r
e50466da 116 0xF8000,\r
117 SIZE_4KB\r
76b4cae3 118 }\r
e50466da 119};\r
120\r
f877f300 121//\r
122// Lookup table used to print MTRRs\r
123//\r
124GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {\r
125 "UC", // CacheUncacheable\r
126 "WC", // CacheWriteCombining\r
127 "R*", // Invalid\r
128 "R*", // Invalid\r
129 "WT", // CacheWriteThrough\r
130 "WP", // CacheWriteProtected\r
131 "WB", // CacheWriteBack\r
132 "R*" // Invalid\r
133};\r
134\r
2bbd7e2f
RN
135\r
136/**\r
137 Worker function prints all MTRRs for debugging.\r
138\r
139 If MtrrSetting is not NULL, print MTRR settings from input MTRR\r
140 settings buffer.\r
141 If MtrrSetting is NULL, print MTRR settings from MTRRs.\r
142\r
143 @param MtrrSetting A buffer holding all MTRRs content.\r
144**/\r
145VOID\r
146MtrrDebugPrintAllMtrrsWorker (\r
147 IN MTRR_SETTINGS *MtrrSetting\r
148 );\r
149\r
31b3597e
MK
150/**\r
151 Worker function returns the variable MTRR count for the CPU.\r
152\r
153 @return Variable MTRR count\r
154\r
155**/\r
156UINT32\r
157GetVariableMtrrCountWorker (\r
158 VOID\r
159 )\r
160{\r
386f5785 161 MSR_IA32_MTRRCAP_REGISTER MtrrCap;\r
31b3597e 162\r
386f5785 163 MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
2bbd7e2f 164 ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *) 0)->Mtrr));\r
386f5785 165 return MtrrCap.Bits.VCNT;\r
31b3597e
MK
166}\r
167\r
3b9be416
JY
168/**\r
169 Returns the variable MTRR count for the CPU.\r
170\r
171 @return Variable MTRR count\r
172\r
173**/\r
174UINT32\r
ed8dfd7b 175EFIAPI\r
3b9be416
JY
176GetVariableMtrrCount (\r
177 VOID\r
178 )\r
179{\r
947a573a 180 if (!IsMtrrSupported ()) {\r
181 return 0;\r
182 }\r
31b3597e 183 return GetVariableMtrrCountWorker ();\r
3b9be416
JY
184}\r
185\r
186/**\r
31b3597e 187 Worker function returns the firmware usable variable MTRR count for the CPU.\r
3b9be416
JY
188\r
189 @return Firmware usable variable MTRR count\r
190\r
191**/\r
192UINT32\r
31b3597e 193GetFirmwareVariableMtrrCountWorker (\r
3b9be416
JY
194 VOID\r
195 )\r
196{\r
947a573a 197 UINT32 VariableMtrrCount;\r
46309b11 198 UINT32 ReservedMtrrNumber;\r
947a573a 199\r
31b3597e 200 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
46309b11
JF
201 ReservedMtrrNumber = PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);\r
202 if (VariableMtrrCount < ReservedMtrrNumber) {\r
947a573a 203 return 0;\r
204 }\r
205\r
46309b11 206 return VariableMtrrCount - ReservedMtrrNumber;\r
3b9be416 207}\r
e50466da 208\r
31b3597e
MK
209/**\r
210 Returns the firmware usable variable MTRR count for the CPU.\r
211\r
212 @return Firmware usable variable MTRR count\r
213\r
214**/\r
215UINT32\r
216EFIAPI\r
217GetFirmwareVariableMtrrCount (\r
218 VOID\r
219 )\r
220{\r
221 if (!IsMtrrSupported ()) {\r
222 return 0;\r
223 }\r
224 return GetFirmwareVariableMtrrCountWorker ();\r
225}\r
226\r
227/**\r
228 Worker function returns the default MTRR cache type for the system.\r
229\r
5abd5ed4
MK
230 If MtrrSetting is not NULL, returns the default MTRR cache type from input\r
231 MTRR settings buffer.\r
232 If MtrrSetting is NULL, returns the default MTRR cache type from MSR.\r
233\r
234 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
235\r
31b3597e
MK
236 @return The default MTRR cache type.\r
237\r
238**/\r
239MTRR_MEMORY_CACHE_TYPE\r
240MtrrGetDefaultMemoryTypeWorker (\r
5abd5ed4 241 IN MTRR_SETTINGS *MtrrSetting\r
31b3597e
MK
242 )\r
243{\r
af838805
RN
244 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
245\r
5abd5ed4 246 if (MtrrSetting == NULL) {\r
af838805 247 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
5abd5ed4 248 } else {\r
af838805 249 DefType.Uint64 = MtrrSetting->MtrrDefType;\r
5abd5ed4 250 }\r
af838805
RN
251\r
252 return (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;\r
31b3597e
MK
253}\r
254\r
255\r
e50466da 256/**\r
257 Returns the default MTRR cache type for the system.\r
258\r
91ec7824 259 @return The default MTRR cache type.\r
e50466da 260\r
261**/\r
91ec7824 262MTRR_MEMORY_CACHE_TYPE\r
263EFIAPI\r
264MtrrGetDefaultMemoryType (\r
e50466da 265 VOID\r
91ec7824 266 )\r
e50466da 267{\r
91ec7824 268 if (!IsMtrrSupported ()) {\r
269 return CacheUncacheable;\r
270 }\r
5abd5ed4 271 return MtrrGetDefaultMemoryTypeWorker (NULL);\r
91ec7824 272}\r
e50466da 273\r
274/**\r
275 Preparation before programming MTRR.\r
276\r
277 This function will do some preparation for programming MTRRs:\r
278 disable cache, invalid cache and disable MTRR caching functionality\r
279\r
a5953380 280 @param[out] MtrrContext Pointer to context to save\r
e50466da 281\r
282**/\r
c878cee4 283VOID\r
b8f01599 284MtrrLibPreMtrrChange (\r
c878cee4 285 OUT MTRR_CONTEXT *MtrrContext\r
e50466da 286 )\r
287{\r
af838805 288 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
c878cee4 289 //\r
290 // Disable interrupts and save current interrupt state\r
291 //\r
292 MtrrContext->InterruptState = SaveAndDisableInterrupts();\r
76b4cae3 293\r
e50466da 294 //\r
295 // Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)\r
296 //\r
58b23d90 297 AsmDisableCache ();\r
298\r
e50466da 299 //\r
58b23d90 300 // Save original CR4 value and clear PGE flag (Bit 7)\r
e50466da 301 //\r
c878cee4 302 MtrrContext->Cr4 = AsmReadCr4 ();\r
303 AsmWriteCr4 (MtrrContext->Cr4 & (~BIT7));\r
58b23d90 304\r
e50466da 305 //\r
306 // Flush all TLBs\r
307 //\r
308 CpuFlushTlb ();\r
58b23d90 309\r
e50466da 310 //\r
76b4cae3 311 // Disable MTRRs\r
e50466da 312 //\r
af838805
RN
313 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
314 DefType.Bits.E = 0;\r
315 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);\r
e50466da 316}\r
317\r
e50466da 318/**\r
319 Cleaning up after programming MTRRs.\r
320\r
321 This function will do some clean up after programming MTRRs:\r
0779e5bf 322 Flush all TLBs, re-enable caching, restore CR4.\r
e50466da 323\r
a5953380 324 @param[in] MtrrContext Pointer to context to restore\r
e50466da 325\r
326**/\r
327VOID\r
b8f01599 328MtrrLibPostMtrrChangeEnableCache (\r
c878cee4 329 IN MTRR_CONTEXT *MtrrContext\r
e50466da 330 )\r
331{\r
e50466da 332 //\r
76b4cae3 333 // Flush all TLBs\r
e50466da 334 //\r
e50466da 335 CpuFlushTlb ();\r
336\r
337 //\r
338 // Enable Normal Mode caching CD=NW=0, CD(Bit30), NW(Bit29)\r
339 //\r
58b23d90 340 AsmEnableCache ();\r
e50466da 341\r
58b23d90 342 //\r
343 // Restore original CR4 value\r
344 //\r
c878cee4 345 AsmWriteCr4 (MtrrContext->Cr4);\r
76b4cae3 346\r
c878cee4 347 //\r
348 // Restore original interrupt state\r
349 //\r
350 SetInterruptState (MtrrContext->InterruptState);\r
e50466da 351}\r
352\r
0779e5bf 353/**\r
354 Cleaning up after programming MTRRs.\r
355\r
356 This function will do some clean up after programming MTRRs:\r
357 enable MTRR caching functionality, and enable cache\r
358\r
a5953380 359 @param[in] MtrrContext Pointer to context to restore\r
0779e5bf 360\r
361**/\r
362VOID\r
b8f01599 363MtrrLibPostMtrrChange (\r
c878cee4 364 IN MTRR_CONTEXT *MtrrContext\r
0779e5bf 365 )\r
366{\r
af838805 367 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
0779e5bf 368 //\r
369 // Enable Cache MTRR\r
370 //\r
af838805
RN
371 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
372 DefType.Bits.E = 1;\r
373 DefType.Bits.FE = 1;\r
374 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);\r
0779e5bf 375\r
b8f01599 376 MtrrLibPostMtrrChangeEnableCache (MtrrContext);\r
0779e5bf 377}\r
378\r
85b7f65b
MK
379/**\r
380 Worker function gets the content in fixed MTRRs\r
381\r
382 @param[out] FixedSettings A buffer to hold fixed MTRRs content.\r
383\r
384 @retval The pointer of FixedSettings\r
385\r
386**/\r
387MTRR_FIXED_SETTINGS*\r
388MtrrGetFixedMtrrWorker (\r
389 OUT MTRR_FIXED_SETTINGS *FixedSettings\r
390 )\r
391{\r
392 UINT32 Index;\r
393\r
394 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
395 FixedSettings->Mtrr[Index] =\r
396 AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
397 }\r
398\r
399 return FixedSettings;\r
400}\r
401\r
402\r
403/**\r
404 This function gets the content in fixed MTRRs\r
405\r
406 @param[out] FixedSettings A buffer to hold fixed MTRRs content.\r
407\r
408 @retval The pointer of FixedSettings\r
409\r
410**/\r
411MTRR_FIXED_SETTINGS*\r
412EFIAPI\r
413MtrrGetFixedMtrr (\r
414 OUT MTRR_FIXED_SETTINGS *FixedSettings\r
415 )\r
416{\r
417 if (!IsMtrrSupported ()) {\r
418 return FixedSettings;\r
419 }\r
420\r
421 return MtrrGetFixedMtrrWorker (FixedSettings);\r
422}\r
423\r
424\r
425/**\r
426 Worker function will get the raw value in variable MTRRs\r
427\r
5abd5ed4
MK
428 If MtrrSetting is not NULL, gets the variable MTRRs raw value from input\r
429 MTRR settings buffer.\r
430 If MtrrSetting is NULL, gets the variable MTRRs raw value from MTRRs.\r
431\r
432 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
433 @param[in] VariableMtrrCount Number of variable MTRRs.\r
85b7f65b
MK
434 @param[out] VariableSettings A buffer to hold variable MTRRs content.\r
435\r
436 @return The VariableSettings input pointer\r
437\r
438**/\r
439MTRR_VARIABLE_SETTINGS*\r
440MtrrGetVariableMtrrWorker (\r
5abd5ed4 441 IN MTRR_SETTINGS *MtrrSetting,\r
acf431e6 442 IN UINT32 VariableMtrrCount,\r
85b7f65b
MK
443 OUT MTRR_VARIABLE_SETTINGS *VariableSettings\r
444 )\r
445{\r
446 UINT32 Index;\r
85b7f65b 447\r
2bbd7e2f 448 ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr));\r
85b7f65b
MK
449\r
450 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
5abd5ed4 451 if (MtrrSetting == NULL) {\r
9c8c4478
RN
452 VariableSettings->Mtrr[Index].Mask = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1));\r
453 //\r
454 // Skip to read the Base MSR when the Mask.V is not set.\r
455 //\r
456 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
457 VariableSettings->Mtrr[Index].Base = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1));\r
458 }\r
5abd5ed4
MK
459 } else {\r
460 VariableSettings->Mtrr[Index].Base = MtrrSetting->Variables.Mtrr[Index].Base;\r
461 VariableSettings->Mtrr[Index].Mask = MtrrSetting->Variables.Mtrr[Index].Mask;\r
462 }\r
85b7f65b
MK
463 }\r
464\r
465 return VariableSettings;\r
466}\r
467\r
468/**\r
469 This function will get the raw value in variable MTRRs\r
470\r
471 @param[out] VariableSettings A buffer to hold variable MTRRs content.\r
472\r
473 @return The VariableSettings input pointer\r
474\r
475**/\r
476MTRR_VARIABLE_SETTINGS*\r
477EFIAPI\r
478MtrrGetVariableMtrr (\r
479 OUT MTRR_VARIABLE_SETTINGS *VariableSettings\r
480 )\r
481{\r
482 if (!IsMtrrSupported ()) {\r
483 return VariableSettings;\r
484 }\r
485\r
486 return MtrrGetVariableMtrrWorker (\r
5abd5ed4 487 NULL,\r
acf431e6 488 GetVariableMtrrCountWorker (),\r
85b7f65b
MK
489 VariableSettings\r
490 );\r
491}\r
e50466da 492\r
493/**\r
494 Programs fixed MTRRs registers.\r
495\r
94240f1b 496 @param[in] Type The memory type to set.\r
76b4cae3
MK
497 @param[in, out] Base The base address of memory range.\r
498 @param[in, out] Length The length of memory range.\r
5fbb5ade 499 @param[in, out] LastMsrIndex On input, the last index of the fixed MTRR MSR to program.\r
0f354122 500 On return, the current index of the fixed MTRR MSR to program.\r
5fbb5ade
RN
501 @param[out] ClearMask The bits to clear in the fixed MTRR MSR.\r
502 @param[out] OrMask The bits to set in the fixed MTRR MSR.\r
e50466da 503\r
504 @retval RETURN_SUCCESS The cache type was updated successfully\r
505 @retval RETURN_UNSUPPORTED The requested range or cache type was invalid\r
506 for the fixed MTRRs.\r
507\r
508**/\r
509RETURN_STATUS\r
94240f1b
RN
510MtrrLibProgramFixedMtrr (\r
511 IN MTRR_MEMORY_CACHE_TYPE Type,\r
512 IN OUT UINT64 *Base,\r
513 IN OUT UINT64 *Length,\r
5fbb5ade
RN
514 IN OUT UINT32 *LastMsrIndex,\r
515 OUT UINT64 *ClearMask,\r
516 OUT UINT64 *OrMask\r
e50466da 517 )\r
518{\r
5fbb5ade 519 UINT32 MsrIndex;\r
eecad349
JF
520 UINT32 LeftByteShift;\r
521 UINT32 RightByteShift;\r
07e88920 522 UINT64 SubLength;\r
e50466da 523\r
eecad349
JF
524 //\r
525 // Find the fixed MTRR index to be programmed\r
526 //\r
5fbb5ade
RN
527 for (MsrIndex = *LastMsrIndex + 1; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {\r
528 if ((*Base >= mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) &&\r
e50466da 529 (*Base <\r
530 (\r
5fbb5ade
RN
531 mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress +\r
532 (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length)\r
e50466da 533 )\r
534 )\r
535 ) {\r
536 break;\r
537 }\r
538 }\r
539\r
5fbb5ade 540 ASSERT (MsrIndex != ARRAY_SIZE (mMtrrLibFixedMtrrTable));\r
e50466da 541\r
542 //\r
eecad349 543 // Find the begin offset in fixed MTRR and calculate byte offset of left shift\r
e50466da 544 //\r
5fbb5ade
RN
545 if ((((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) % mMtrrLibFixedMtrrTable[MsrIndex].Length) != 0) {\r
546 //\r
547 // Base address should be aligned to the begin of a certain Fixed MTRR range.\r
548 //\r
e50466da 549 return RETURN_UNSUPPORTED;\r
550 }\r
5fbb5ade
RN
551 LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) / mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
552 ASSERT (LeftByteShift < 8);\r
e50466da 553\r
eecad349
JF
554 //\r
555 // Find the end offset in fixed MTRR and calculate byte offset of right shift\r
556 //\r
5fbb5ade 557 SubLength = mMtrrLibFixedMtrrTable[MsrIndex].Length * (8 - LeftByteShift);\r
eecad349
JF
558 if (*Length >= SubLength) {\r
559 RightByteShift = 0;\r
07e88920 560 } else {\r
5fbb5ade
RN
561 if (((UINT32)(*Length) % mMtrrLibFixedMtrrTable[MsrIndex].Length) != 0) {\r
562 //\r
563 // Length should be aligned to the end of a certain Fixed MTRR range.\r
564 //\r
eecad349
JF
565 return RETURN_UNSUPPORTED;\r
566 }\r
5fbb5ade 567 RightByteShift = 8 - LeftByteShift - (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
eecad349
JF
568 //\r
569 // Update SubLength by actual length\r
570 //\r
571 SubLength = *Length;\r
e50466da 572 }\r
573\r
5fbb5ade
RN
574 *ClearMask = CLEAR_SEED;\r
575 *OrMask = MultU64x32 (OR_SEED, (UINT32) Type);\r
eecad349
JF
576\r
577 if (LeftByteShift != 0) {\r
578 //\r
579 // Clear the low bits by LeftByteShift\r
580 //\r
5fbb5ade
RN
581 *ClearMask &= LShiftU64 (*ClearMask, LeftByteShift * 8);\r
582 *OrMask &= LShiftU64 (*OrMask, LeftByteShift * 8);\r
eecad349
JF
583 }\r
584\r
585 if (RightByteShift != 0) {\r
586 //\r
587 // Clear the high bits by RightByteShift\r
588 //\r
5fbb5ade
RN
589 *ClearMask &= RShiftU64 (*ClearMask, RightByteShift * 8);\r
590 *OrMask &= RShiftU64 (*OrMask, RightByteShift * 8);\r
e50466da 591 }\r
592\r
07e88920
JF
593 *Length -= SubLength;\r
594 *Base += SubLength;\r
595\r
5fbb5ade 596 *LastMsrIndex = MsrIndex;\r
fa25cf38 597\r
e50466da 598 return RETURN_SUCCESS;\r
599}\r
600\r
601\r
d0baed7d
MK
602/**\r
603 Worker function gets the attribute of variable MTRRs.\r
604\r
605 This function shadows the content of variable MTRRs into an\r
606 internal array: VariableMtrr.\r
607\r
10c361ad
RN
608 @param[in] VariableSettings The variable MTRR values to shadow\r
609 @param[in] VariableMtrrCount The number of variable MTRRs\r
610 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
611 @param[in] MtrrValidAddressMask The valid address mask for MTRR\r
612 @param[out] VariableMtrr The array to shadow variable MTRRs content\r
d0baed7d 613\r
10c361ad 614 @return Number of MTRRs which has been used.\r
d0baed7d
MK
615\r
616**/\r
617UINT32\r
618MtrrGetMemoryAttributeInVariableMtrrWorker (\r
619 IN MTRR_VARIABLE_SETTINGS *VariableSettings,\r
10c361ad 620 IN UINTN VariableMtrrCount,\r
d0baed7d
MK
621 IN UINT64 MtrrValidBitsMask,\r
622 IN UINT64 MtrrValidAddressMask,\r
623 OUT VARIABLE_MTRR *VariableMtrr\r
624 )\r
625{\r
626 UINTN Index;\r
627 UINT32 UsedMtrr;\r
628\r
2bbd7e2f 629 ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * ARRAY_SIZE (VariableSettings->Mtrr));\r
10c361ad 630 for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {\r
af838805 631 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
d0baed7d
MK
632 VariableMtrr[Index].Msr = (UINT32)Index;\r
633 VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);\r
2bbd7e2f
RN
634 VariableMtrr[Index].Length =\r
635 ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
d0baed7d
MK
636 VariableMtrr[Index].Type = (VariableSettings->Mtrr[Index].Base & 0x0ff);\r
637 VariableMtrr[Index].Valid = TRUE;\r
638 VariableMtrr[Index].Used = TRUE;\r
639 UsedMtrr++;\r
640 }\r
641 }\r
642 return UsedMtrr;\r
643}\r
644\r
2bbd7e2f
RN
645/**\r
646 Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.\r
647 One MTRR_MEMORY_RANGE element is created for each MTRR setting.\r
648 The routine doesn't remove the overlap or combine the near-by region.\r
649\r
650 @param[in] VariableSettings The variable MTRR values to shadow\r
651 @param[in] VariableMtrrCount The number of variable MTRRs\r
652 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
653 @param[in] MtrrValidAddressMask The valid address mask for MTRR\r
654 @param[out] VariableMtrr The array to shadow variable MTRRs content\r
655\r
656 @return Number of MTRRs which has been used.\r
657\r
658**/\r
659UINT32\r
660MtrrLibGetRawVariableRanges (\r
661 IN MTRR_VARIABLE_SETTINGS *VariableSettings,\r
662 IN UINTN VariableMtrrCount,\r
663 IN UINT64 MtrrValidBitsMask,\r
664 IN UINT64 MtrrValidAddressMask,\r
665 OUT MTRR_MEMORY_RANGE *VariableMtrr\r
666 )\r
667{\r
668 UINTN Index;\r
669 UINT32 UsedMtrr;\r
670\r
671 ZeroMem (VariableMtrr, sizeof (MTRR_MEMORY_RANGE) * ARRAY_SIZE (VariableSettings->Mtrr));\r
672 for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {\r
673 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
674 VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);\r
675 VariableMtrr[Index].Length =\r
676 ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
677 VariableMtrr[Index].Type = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff);\r
678 UsedMtrr++;\r
679 }\r
680 }\r
681 return UsedMtrr;\r
682}\r
d0baed7d 683\r
e50466da 684/**\r
76b4cae3 685 Gets the attribute of variable MTRRs.\r
e50466da 686\r
3ba736f3
JY
687 This function shadows the content of variable MTRRs into an\r
688 internal array: VariableMtrr.\r
e50466da 689\r
76b4cae3
MK
690 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
691 @param[in] MtrrValidAddressMask The valid address mask for MTRR\r
692 @param[out] VariableMtrr The array to shadow variable MTRRs content\r
e50466da 693\r
438f1766 694 @return The return value of this parameter indicates the\r
3ba736f3 695 number of MTRRs which has been used.\r
e50466da 696\r
697**/\r
3ba736f3 698UINT32\r
e50466da 699EFIAPI\r
700MtrrGetMemoryAttributeInVariableMtrr (\r
701 IN UINT64 MtrrValidBitsMask,\r
702 IN UINT64 MtrrValidAddressMask,\r
703 OUT VARIABLE_MTRR *VariableMtrr\r
704 )\r
705{\r
d0baed7d 706 MTRR_VARIABLE_SETTINGS VariableSettings;\r
3b9be416 707\r
947a573a 708 if (!IsMtrrSupported ()) {\r
709 return 0;\r
710 }\r
711\r
d0baed7d 712 MtrrGetVariableMtrrWorker (\r
5abd5ed4 713 NULL,\r
d0baed7d
MK
714 GetVariableMtrrCountWorker (),\r
715 &VariableSettings\r
716 );\r
e50466da 717\r
d0baed7d
MK
718 return MtrrGetMemoryAttributeInVariableMtrrWorker (\r
719 &VariableSettings,\r
720 GetFirmwareVariableMtrrCountWorker (),\r
721 MtrrValidBitsMask,\r
722 MtrrValidAddressMask,\r
723 VariableMtrr\r
724 );\r
e50466da 725}\r
726\r
e50466da 727/**\r
1416ecb4
RN
728 Return the biggest alignment (lowest set bit) of address.\r
729 The function is equivalent to: 1 << LowBitSet64 (Address).\r
e50466da 730\r
8051302a
RN
731 @param Address The address to return the alignment.\r
732 @param Alignment0 The alignment to return when Address is 0.\r
e50466da 733\r
8051302a 734 @return The least alignment of the Address.\r
e50466da 735**/\r
8051302a 736UINT64\r
1416ecb4 737MtrrLibBiggestAlignment (\r
8051302a
RN
738 UINT64 Address,\r
739 UINT64 Alignment0\r
740)\r
e50466da 741{\r
8051302a
RN
742 if (Address == 0) {\r
743 return Alignment0;\r
e50466da 744 }\r
745\r
1416ecb4 746 return Address & ((~Address) + 1);\r
e50466da 747}\r
748\r
e50466da 749/**\r
8051302a 750 Return whether the left MTRR type precedes the right MTRR type.\r
76b4cae3 751\r
8051302a 752 The MTRR type precedence rules are:\r
10c361ad
RN
753 1. UC precedes any other type\r
754 2. WT precedes WB\r
755 For further details, please refer the IA32 Software Developer's Manual,\r
756 Volume 3, Section "MTRR Precedences".\r
e50466da 757\r
8051302a
RN
758 @param Left The left MTRR type.\r
759 @param Right The right MTRR type.\r
e50466da 760\r
8051302a
RN
761 @retval TRUE Left precedes Right.\r
762 @retval FALSE Left doesn't precede Right.\r
e50466da 763**/\r
8051302a
RN
764BOOLEAN\r
765MtrrLibTypeLeftPrecedeRight (\r
766 IN MTRR_MEMORY_CACHE_TYPE Left,\r
767 IN MTRR_MEMORY_CACHE_TYPE Right\r
768)\r
e50466da 769{\r
8051302a 770 return (BOOLEAN) (Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack));\r
e50466da 771}\r
772\r
e50466da 773/**\r
774 Initializes the valid bits mask and valid address mask for MTRRs.\r
775\r
776 This function initializes the valid bits mask and valid address mask for MTRRs.\r
777\r
76b4cae3
MK
778 @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR\r
779 @param[out] MtrrValidAddressMask The valid address mask for the MTRR\r
e50466da 780\r
781**/\r
e50466da 782VOID\r
783MtrrLibInitializeMtrrMask (\r
784 OUT UINT64 *MtrrValidBitsMask,\r
785 OUT UINT64 *MtrrValidAddressMask\r
786 )\r
787{\r
012f4054
RN
788 UINT32 MaxExtendedFunction;\r
789 CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;\r
e50466da 790\r
e50466da 791\r
012f4054 792 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);\r
e50466da 793\r
012f4054
RN
794 if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
795 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);\r
e50466da 796 } else {\r
012f4054 797 VirPhyAddressSize.Bits.PhysicalAddressBits = 36;\r
e50466da 798 }\r
012f4054
RN
799\r
800 *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
801 *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;\r
e50466da 802}\r
803\r
804\r
805/**\r
76b4cae3 806 Determines the real attribute of a memory range.\r
e50466da 807\r
808 This function is to arbitrate the real attribute of the memory when\r
10c361ad 809 there are 2 MTRRs covers the same memory range. For further details,\r
e50466da 810 please refer the IA32 Software Developer's Manual, Volume 3,\r
10c361ad 811 Section "MTRR Precedences".\r
e50466da 812\r
76b4cae3
MK
813 @param[in] MtrrType1 The first kind of Memory type\r
814 @param[in] MtrrType2 The second kind of memory type\r
e50466da 815\r
816**/\r
10c361ad 817MTRR_MEMORY_CACHE_TYPE\r
b8f01599 818MtrrLibPrecedence (\r
10c361ad
RN
819 IN MTRR_MEMORY_CACHE_TYPE MtrrType1,\r
820 IN MTRR_MEMORY_CACHE_TYPE MtrrType2\r
e50466da 821 )\r
822{\r
10c361ad
RN
823 if (MtrrType1 == MtrrType2) {\r
824 return MtrrType1;\r
e50466da 825 }\r
826\r
10c361ad
RN
827 ASSERT (\r
828 MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2) ||\r
829 MtrrLibTypeLeftPrecedeRight (MtrrType2, MtrrType1)\r
830 );\r
831\r
832 if (MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2)) {\r
833 return MtrrType1;\r
834 } else {\r
835 return MtrrType2;\r
e50466da 836 }\r
e50466da 837}\r
838\r
e50466da 839/**\r
5abd5ed4 840 Worker function will get the memory cache type of the specific address.\r
e50466da 841\r
5abd5ed4
MK
842 If MtrrSetting is not NULL, gets the memory cache type from input\r
843 MTRR settings buffer.\r
844 If MtrrSetting is NULL, gets the memory cache type from MTRRs.\r
e50466da 845\r
5abd5ed4 846 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
85b7f65b
MK
847 @param[in] Address The specific address\r
848\r
849 @return Memory cache type of the specific address\r
e50466da 850\r
851**/\r
85b7f65b 852MTRR_MEMORY_CACHE_TYPE\r
5abd5ed4
MK
853MtrrGetMemoryAttributeByAddressWorker (\r
854 IN MTRR_SETTINGS *MtrrSetting,\r
85b7f65b 855 IN PHYSICAL_ADDRESS Address\r
e50466da 856 )\r
857{\r
10c361ad
RN
858 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
859 UINT64 FixedMtrr;\r
860 UINTN Index;\r
861 UINTN SubIndex;\r
862 MTRR_MEMORY_CACHE_TYPE MtrrType;\r
2bbd7e2f 863 MTRR_MEMORY_RANGE VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
10c361ad
RN
864 UINT64 MtrrValidBitsMask;\r
865 UINT64 MtrrValidAddressMask;\r
866 UINT32 VariableMtrrCount;\r
867 MTRR_VARIABLE_SETTINGS VariableSettings;\r
f877f300 868\r
e50466da 869 //\r
85b7f65b 870 // Check if MTRR is enabled, if not, return UC as attribute\r
e50466da 871 //\r
5abd5ed4 872 if (MtrrSetting == NULL) {\r
10c361ad 873 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
5abd5ed4 874 } else {\r
10c361ad 875 DefType.Uint64 = MtrrSetting->MtrrDefType;\r
5abd5ed4 876 }\r
e50466da 877\r
10c361ad 878 if (DefType.Bits.E == 0) {\r
85b7f65b 879 return CacheUncacheable;\r
e50466da 880 }\r
881\r
882 //\r
85b7f65b 883 // If address is less than 1M, then try to go through the fixed MTRR\r
e50466da 884 //\r
85b7f65b 885 if (Address < BASE_1MB) {\r
10c361ad 886 if (DefType.Bits.FE != 0) {\r
85b7f65b
MK
887 //\r
888 // Go through the fixed MTRR\r
889 //\r
890 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
10c361ad
RN
891 if (Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress &&\r
892 Address < mMtrrLibFixedMtrrTable[Index].BaseAddress +\r
893 (mMtrrLibFixedMtrrTable[Index].Length * 8)) {\r
894 SubIndex =\r
895 ((UINTN) Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) /\r
896 mMtrrLibFixedMtrrTable[Index].Length;\r
897 if (MtrrSetting == NULL) {\r
898 FixedMtrr = AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
899 } else {\r
900 FixedMtrr = MtrrSetting->Fixed.Mtrr[Index];\r
901 }\r
902 return (MTRR_MEMORY_CACHE_TYPE) (RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF);\r
903 }\r
85b7f65b 904 }\r
e50466da 905 }\r
906 }\r
d0baed7d 907\r
10c361ad 908 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
2bbd7e2f 909 ASSERT (VariableMtrrCount <= ARRAY_SIZE (MtrrSetting->Variables.Mtrr));\r
10c361ad 910 MtrrGetVariableMtrrWorker (MtrrSetting, VariableMtrrCount, &VariableSettings);\r
e50466da 911\r
10c361ad 912 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
2bbd7e2f 913 MtrrLibGetRawVariableRanges (\r
10c361ad
RN
914 &VariableSettings,\r
915 VariableMtrrCount,\r
916 MtrrValidBitsMask,\r
917 MtrrValidAddressMask,\r
918 VariableMtrr\r
919 );\r
d0baed7d 920\r
e50466da 921 //\r
85b7f65b 922 // Go through the variable MTRR\r
e50466da 923 //\r
10c361ad 924 MtrrType = CacheInvalid;\r
85b7f65b 925 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
2bbd7e2f 926 if (VariableMtrr[Index].Length != 0) {\r
85b7f65b 927 if (Address >= VariableMtrr[Index].BaseAddress &&\r
10c361ad
RN
928 Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length) {\r
929 if (MtrrType == CacheInvalid) {\r
930 MtrrType = (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type;\r
931 } else {\r
932 MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type);\r
933 }\r
85b7f65b
MK
934 }\r
935 }\r
e50466da 936 }\r
937\r
10c361ad
RN
938 //\r
939 // If there is no MTRR which covers the Address, use the default MTRR type.\r
940 //\r
941 if (MtrrType == CacheInvalid) {\r
942 MtrrType = (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;\r
943 }\r
944\r
945 return MtrrType;\r
85b7f65b
MK
946}\r
947\r
948\r
5abd5ed4
MK
949/**\r
950 This function will get the memory cache type of the specific address.\r
951\r
952 This function is mainly for debug purpose.\r
953\r
954 @param[in] Address The specific address\r
955\r
956 @return Memory cache type of the specific address\r
957\r
958**/\r
959MTRR_MEMORY_CACHE_TYPE\r
960EFIAPI\r
961MtrrGetMemoryAttribute (\r
962 IN PHYSICAL_ADDRESS Address\r
963 )\r
964{\r
965 if (!IsMtrrSupported ()) {\r
966 return CacheUncacheable;\r
967 }\r
968\r
969 return MtrrGetMemoryAttributeByAddressWorker (NULL, Address);\r
970}\r
971\r
8051302a
RN
972/**\r
973 Update the Ranges array to change the specified range identified by\r
974 BaseAddress and Length to Type.\r
975\r
976 @param Ranges Array holding memory type settings for all memory regions.\r
977 @param Capacity The maximum count of memory ranges the array can hold.\r
978 @param Count Return the new memory range count in the array.\r
979 @param BaseAddress The base address of the memory range to change type.\r
980 @param Length The length of the memory range to change type.\r
981 @param Type The new type of the specified memory range.\r
982\r
983 @retval RETURN_SUCCESS The type of the specified memory range is\r
984 changed successfully.\r
2bbd7e2f
RN
985 @retval RETURN_ALREADY_STARTED The type of the specified memory range equals\r
986 to the desired type.\r
8051302a
RN
987 @retval RETURN_OUT_OF_RESOURCES The new type set causes the count of memory\r
988 range exceeds capacity.\r
989**/\r
990RETURN_STATUS\r
991MtrrLibSetMemoryType (\r
2bbd7e2f
RN
992 IN MTRR_MEMORY_RANGE *Ranges,\r
993 IN UINTN Capacity,\r
994 IN OUT UINTN *Count,\r
8051302a
RN
995 IN UINT64 BaseAddress,\r
996 IN UINT64 Length,\r
997 IN MTRR_MEMORY_CACHE_TYPE Type\r
998 )\r
999{\r
2bbd7e2f 1000 UINTN Index;\r
8051302a
RN
1001 UINT64 Limit;\r
1002 UINT64 LengthLeft;\r
1003 UINT64 LengthRight;\r
2bbd7e2f
RN
1004 UINTN StartIndex;\r
1005 UINTN EndIndex;\r
1006 UINTN DeltaCount;\r
8051302a 1007\r
4ef6c385
RN
1008 LengthRight = 0;\r
1009 LengthLeft = 0;\r
8051302a
RN
1010 Limit = BaseAddress + Length;\r
1011 StartIndex = *Count;\r
1012 EndIndex = *Count;\r
1013 for (Index = 0; Index < *Count; Index++) {\r
1014 if ((StartIndex == *Count) &&\r
1015 (Ranges[Index].BaseAddress <= BaseAddress) &&\r
1016 (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)) {\r
1017 StartIndex = Index;\r
1018 LengthLeft = BaseAddress - Ranges[Index].BaseAddress;\r
1019 }\r
1020\r
1021 if ((EndIndex == *Count) &&\r
1022 (Ranges[Index].BaseAddress < Limit) &&\r
1023 (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length)) {\r
1024 EndIndex = Index;\r
1025 LengthRight = Ranges[Index].BaseAddress + Ranges[Index].Length - Limit;\r
1026 break;\r
1027 }\r
1028 }\r
1029\r
1030 ASSERT (StartIndex != *Count && EndIndex != *Count);\r
1031 if (StartIndex == EndIndex && Ranges[StartIndex].Type == Type) {\r
2bbd7e2f 1032 return RETURN_ALREADY_STARTED;\r
8051302a
RN
1033 }\r
1034\r
1035 //\r
1036 // The type change may cause merging with previous range or next range.\r
1037 // Update the StartIndex, EndIndex, BaseAddress, Length so that following\r
1038 // logic doesn't need to consider merging.\r
1039 //\r
1040 if (StartIndex != 0) {\r
1041 if (LengthLeft == 0 && Ranges[StartIndex - 1].Type == Type) {\r
1042 StartIndex--;\r
1043 Length += Ranges[StartIndex].Length;\r
1044 BaseAddress -= Ranges[StartIndex].Length;\r
1045 }\r
1046 }\r
1047 if (EndIndex != (*Count) - 1) {\r
1048 if (LengthRight == 0 && Ranges[EndIndex + 1].Type == Type) {\r
1049 EndIndex++;\r
1050 Length += Ranges[EndIndex].Length;\r
1051 }\r
1052 }\r
1053\r
1054 //\r
1055 // |- 0 -|- 1 -|- 2 -|- 3 -| StartIndex EndIndex DeltaCount Count (Count = 4)\r
1056 // |++++++++++++++++++| 0 3 1=3-0-2 3\r
1057 // |+++++++| 0 1 -1=1-0-2 5\r
1058 // |+| 0 0 -2=0-0-2 6\r
1059 // |+++| 0 0 -1=0-0-2+1 5\r
1060 //\r
1061 //\r
1062 DeltaCount = EndIndex - StartIndex - 2;\r
1063 if (LengthLeft == 0) {\r
1064 DeltaCount++;\r
1065 }\r
1066 if (LengthRight == 0) {\r
1067 DeltaCount++;\r
1068 }\r
1069 if (*Count - DeltaCount > Capacity) {\r
1070 return RETURN_OUT_OF_RESOURCES;\r
1071 }\r
1072\r
1073 //\r
1074 // Reserve (-DeltaCount) space\r
1075 //\r
1076 CopyMem (&Ranges[EndIndex + 1 - DeltaCount], &Ranges[EndIndex + 1], (*Count - EndIndex - 1) * sizeof (Ranges[0]));\r
1077 *Count -= DeltaCount;\r
1078\r
1079 if (LengthLeft != 0) {\r
1080 Ranges[StartIndex].Length = LengthLeft;\r
1081 StartIndex++;\r
1082 }\r
1083 if (LengthRight != 0) {\r
1084 Ranges[EndIndex - DeltaCount].BaseAddress = BaseAddress + Length;\r
1085 Ranges[EndIndex - DeltaCount].Length = LengthRight;\r
1086 Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type;\r
1087 }\r
1088 Ranges[StartIndex].BaseAddress = BaseAddress;\r
1089 Ranges[StartIndex].Length = Length;\r
1090 Ranges[StartIndex].Type = Type;\r
1091 return RETURN_SUCCESS;\r
1092}\r
1093\r
1094/**\r
2bbd7e2f 1095 Return the number of memory types in range [BaseAddress, BaseAddress + Length).\r
8051302a 1096\r
2bbd7e2f
RN
1097 @param Ranges Array holding memory type settings for all memory regions.\r
1098 @param RangeCount The count of memory ranges the array holds.\r
1099 @param BaseAddress Base address.\r
1100 @param Length Length.\r
1101 @param Types Return bit mask to indicate all memory types in the specified range.\r
8051302a 1102\r
2bbd7e2f 1103 @retval Number of memory types.\r
8051302a 1104**/\r
2bbd7e2f
RN
1105UINT8\r
1106MtrrLibGetNumberOfTypes (\r
1107 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
1108 IN UINTN RangeCount,\r
1109 IN UINT64 BaseAddress,\r
1110 IN UINT64 Length,\r
1111 IN OUT UINT8 *Types OPTIONAL\r
1112 )\r
1113{\r
1114 UINTN Index;\r
1115 UINT8 TypeCount;\r
1116 UINT8 LocalTypes;\r
1117\r
1118 TypeCount = 0;\r
1119 LocalTypes = 0;\r
1120 for (Index = 0; Index < RangeCount; Index++) {\r
1121 if ((Ranges[Index].BaseAddress <= BaseAddress) &&\r
1122 (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)\r
1123 ) {\r
1124 if ((LocalTypes & (1 << Ranges[Index].Type)) == 0) {\r
1125 LocalTypes |= (UINT8)(1 << Ranges[Index].Type);\r
1126 TypeCount++;\r
1127 }\r
1128\r
1129 if (BaseAddress + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
1130 Length -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress;\r
1131 BaseAddress = Ranges[Index].BaseAddress + Ranges[Index].Length;\r
1132 } else {\r
1133 break;\r
1134 }\r
1135 }\r
1136 }\r
1137\r
1138 if (Types != NULL) {\r
1139 *Types = LocalTypes;\r
1140 }\r
1141 return TypeCount;\r
1142}\r
8051302a
RN
1143\r
1144/**\r
3143144b
RN
1145 Calculate the least MTRR number from vertex Start to Stop and update\r
1146 the Previous of all vertices from Start to Stop is updated to reflect\r
2bbd7e2f
RN
1147 how the memory range is covered by MTRR.\r
1148\r
3143144b
RN
1149 @param VertexCount The count of vertices in the graph.\r
1150 @param Vertices Array holding all vertices.\r
1151 @param Weight 2-dimention array holding weights between vertices.\r
1152 @param Start Start vertex.\r
1153 @param Stop Stop vertex.\r
2bbd7e2f
RN
1154 @param IncludeOptional TRUE to count the optional weight.\r
1155**/\r
1156VOID\r
1157MtrrLibCalculateLeastMtrrs (\r
3143144b
RN
1158 IN UINT16 VertexCount,\r
1159 IN MTRR_LIB_ADDRESS *Vertices,\r
2bbd7e2f
RN
1160 IN OUT CONST UINT8 *Weight,\r
1161 IN UINT16 Start,\r
1162 IN UINT16 Stop,\r
1163 IN BOOLEAN IncludeOptional\r
1164 )\r
1165{\r
1166 UINT16 Index;\r
1167 UINT8 MinWeight;\r
1168 UINT16 MinI;\r
1169 UINT8 Mandatory;\r
1170 UINT8 Optional;\r
1171\r
1172 for (Index = Start; Index <= Stop; Index++) {\r
3143144b
RN
1173 Vertices[Index].Visited = FALSE;\r
1174 Vertices[Index].Previous = VertexCount;\r
2bbd7e2f 1175 Mandatory = Weight[M(Start,Index)];\r
3143144b 1176 Vertices[Index].Weight = Mandatory;\r
2bbd7e2f
RN
1177 if (Mandatory != MAX_WEIGHT) {\r
1178 Optional = IncludeOptional ? Weight[O(Start, Index)] : 0;\r
3143144b
RN
1179 Vertices[Index].Weight += Optional;\r
1180 ASSERT (Vertices[Index].Weight >= Optional);\r
2bbd7e2f
RN
1181 }\r
1182 }\r
8051302a 1183\r
2bbd7e2f
RN
1184 MinI = Start;\r
1185 MinWeight = 0;\r
3143144b 1186 while (!Vertices[Stop].Visited) {\r
2bbd7e2f 1187 //\r
3143144b 1188 // Update the weight from the shortest vertex to other unvisited vertices\r
2bbd7e2f
RN
1189 //\r
1190 for (Index = Start + 1; Index <= Stop; Index++) {\r
3143144b 1191 if (!Vertices[Index].Visited) {\r
2bbd7e2f
RN
1192 Mandatory = Weight[M(MinI, Index)];\r
1193 if (Mandatory != MAX_WEIGHT) {\r
1194 Optional = IncludeOptional ? Weight[O(MinI, Index)] : 0;\r
3143144b
RN
1195 if (MinWeight + Mandatory + Optional <= Vertices[Index].Weight) {\r
1196 Vertices[Index].Weight = MinWeight + Mandatory + Optional;\r
1197 Vertices[Index].Previous = MinI; // Previous is Start based.\r
2bbd7e2f
RN
1198 }\r
1199 }\r
1200 }\r
1201 }\r
8051302a 1202\r
2bbd7e2f 1203 //\r
3143144b 1204 // Find the shortest vertex from Start\r
2bbd7e2f 1205 //\r
3143144b 1206 MinI = VertexCount;\r
2bbd7e2f
RN
1207 MinWeight = MAX_WEIGHT;\r
1208 for (Index = Start + 1; Index <= Stop; Index++) {\r
3143144b 1209 if (!Vertices[Index].Visited && MinWeight > Vertices[Index].Weight) {\r
2bbd7e2f 1210 MinI = Index;\r
3143144b 1211 MinWeight = Vertices[Index].Weight;\r
2bbd7e2f
RN
1212 }\r
1213 }\r
8051302a 1214\r
2bbd7e2f 1215 //\r
3143144b 1216 // Mark the shortest vertex from Start as visited\r
2bbd7e2f 1217 //\r
3143144b 1218 Vertices[MinI].Visited = TRUE;\r
2bbd7e2f
RN
1219 }\r
1220}\r
1221\r
1222/**\r
1223 Append the MTRR setting to MTRR setting array.\r
1224\r
1225 @param Mtrrs Array holding all MTRR settings.\r
1226 @param MtrrCapacity Capacity of the MTRR array.\r
1227 @param MtrrCount The count of MTRR settings in array.\r
1228 @param BaseAddress Base address.\r
1229 @param Length Length.\r
1230 @param Type Memory type.\r
1231\r
1232 @retval RETURN_SUCCESS MTRR setting is appended to array.\r
1233 @retval RETURN_OUT_OF_RESOURCES Array is full.\r
8051302a
RN
1234**/\r
1235RETURN_STATUS\r
2bbd7e2f
RN
1236MtrrLibAppendVariableMtrr (\r
1237 IN OUT MTRR_MEMORY_RANGE *Mtrrs,\r
1238 IN UINT32 MtrrCapacity,\r
1239 IN OUT UINT32 *MtrrCount,\r
1240 IN UINT64 BaseAddress,\r
1241 IN UINT64 Length,\r
1242 IN MTRR_MEMORY_CACHE_TYPE Type\r
1243 )\r
1244{\r
1245 if (*MtrrCount == MtrrCapacity) {\r
1246 return RETURN_OUT_OF_RESOURCES;\r
1247 }\r
1248\r
1249 Mtrrs[*MtrrCount].BaseAddress = BaseAddress;\r
1250 Mtrrs[*MtrrCount].Length = Length;\r
1251 Mtrrs[*MtrrCount].Type = Type;\r
1252 (*MtrrCount)++;\r
1253 return RETURN_SUCCESS;\r
1254}\r
1255\r
1256/**\r
1257 Return the memory type that has the least precedence.\r
1258\r
1259 @param TypeBits Bit mask of memory type.\r
1260\r
1261 @retval Memory type that has the least precedence.\r
1262**/\r
1263MTRR_MEMORY_CACHE_TYPE\r
1264MtrrLibLowestType (\r
1265 IN UINT8 TypeBits\r
8051302a
RN
1266)\r
1267{\r
2bbd7e2f 1268 INT8 Type;\r
8051302a 1269\r
2bbd7e2f
RN
1270 ASSERT (TypeBits != 0);\r
1271 for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1);\r
1272 return (MTRR_MEMORY_CACHE_TYPE)Type;\r
1273}\r
8051302a 1274\r
2bbd7e2f
RN
1275/**\r
1276 Return TRUE when the Operand is exactly power of 2.\r
1277\r
1278 @retval TRUE Operand is exactly power of 2.\r
1279 @retval FALSE Operand is not power of 2.\r
1280**/\r
1281BOOLEAN\r
1282MtrrLibIsPowerOfTwo (\r
1283 IN UINT64 Operand\r
1284)\r
1285{\r
1286 ASSERT (Operand != 0);\r
1287 return (BOOLEAN) ((Operand & (Operand - 1)) == 0);\r
1288}\r
1289\r
1290/**\r
3143144b 1291 Calculate the subtractive path from vertex Start to Stop.\r
2bbd7e2f
RN
1292\r
1293 @param DefaultType Default memory type.\r
1294 @param A0 Alignment to use when base address is 0.\r
1295 @param Ranges Array holding memory type settings for all memory regions.\r
1296 @param RangeCount The count of memory ranges the array holds.\r
3143144b
RN
1297 @param VertexCount The count of vertices in the graph.\r
1298 @param Vertices Array holding all vertices.\r
1299 @param Weight 2-dimention array holding weights between vertices.\r
1300 @param Start Start vertex.\r
1301 @param Stop Stop vertex.\r
2bbd7e2f
RN
1302 @param Types Type bit mask of memory range from Start to Stop.\r
1303 @param TypeCount Number of different memory types from Start to Stop.\r
1304 @param Mtrrs Array holding all MTRR settings.\r
1305 @param MtrrCapacity Capacity of the MTRR array.\r
1306 @param MtrrCount The count of MTRR settings in array.\r
1307\r
1308 @retval RETURN_SUCCESS The subtractive path is calculated successfully.\r
1309 @retval RETURN_OUT_OF_RESOURCES The MTRR setting array is full.\r
1310\r
1311**/\r
1312RETURN_STATUS\r
1313MtrrLibCalculateSubtractivePath (\r
1314 IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
1315 IN UINT64 A0,\r
1316 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
1317 IN UINTN RangeCount,\r
3143144b
RN
1318 IN UINT16 VertexCount,\r
1319 IN MTRR_LIB_ADDRESS *Vertices,\r
2bbd7e2f
RN
1320 IN OUT UINT8 *Weight,\r
1321 IN UINT16 Start,\r
1322 IN UINT16 Stop,\r
1323 IN UINT8 Types,\r
1324 IN UINT8 TypeCount,\r
1325 IN OUT MTRR_MEMORY_RANGE *Mtrrs, OPTIONAL\r
1326 IN UINT32 MtrrCapacity, OPTIONAL\r
1327 IN OUT UINT32 *MtrrCount OPTIONAL\r
1328 )\r
1329{\r
1330 RETURN_STATUS Status;\r
1331 UINT64 Base;\r
1332 UINT64 Length;\r
1333 UINT8 PrecedentTypes;\r
1334 UINTN Index;\r
1335 UINT64 HBase;\r
1336 UINT64 HLength;\r
1337 UINT64 SubLength;\r
1338 UINT16 SubStart;\r
1339 UINT16 SubStop;\r
1340 UINT16 Cur;\r
1341 UINT16 Pre;\r
1342 MTRR_MEMORY_CACHE_TYPE LowestType;\r
1343 MTRR_MEMORY_CACHE_TYPE LowestPrecedentType;\r
1344\r
3143144b
RN
1345 Base = Vertices[Start].Address;\r
1346 Length = Vertices[Stop].Address - Base;\r
2bbd7e2f
RN
1347\r
1348 LowestType = MtrrLibLowestType (Types);\r
1349\r
1350 //\r
1351 // Clear the lowest type (highest bit) to get the precedent types\r
1352 //\r
1353 PrecedentTypes = ~(1 << LowestType) & Types;\r
1354 LowestPrecedentType = MtrrLibLowestType (PrecedentTypes);\r
1355\r
1356 if (Mtrrs == NULL) {\r
1357 Weight[M(Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1);\r
1358 Weight[O(Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0);\r
1359 }\r
1360\r
1361 // Add all high level ranges\r
1362 HBase = MAX_UINT64;\r
1363 HLength = 0;\r
1364 for (Index = 0; Index < RangeCount; Index++) {\r
1365 if (Length == 0) {\r
1366 break;\r
1367 }\r
1368 if ((Base < Ranges[Index].BaseAddress) || (Ranges[Index].BaseAddress + Ranges[Index].Length <= Base)) {\r
1369 continue;\r
8051302a
RN
1370 }\r
1371\r
1372 //\r
2bbd7e2f 1373 // Base is in the Range[Index]\r
8051302a 1374 //\r
2bbd7e2f
RN
1375 if (Base + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
1376 SubLength = Ranges[Index].BaseAddress + Ranges[Index].Length - Base;\r
1377 } else {\r
1378 SubLength = Length;\r
1379 }\r
1380 if (((1 << Ranges[Index].Type) & PrecedentTypes) != 0) {\r
1381 //\r
1382 // Meet a range whose types take precedence.\r
1383 // Update the [HBase, HBase + HLength) to include the range,\r
1384 // [HBase, HBase + HLength) may contain sub ranges with 2 different types, and both take precedence.\r
1385 //\r
1386 if (HBase == MAX_UINT64) {\r
1387 HBase = Base;\r
8051302a 1388 }\r
2bbd7e2f 1389 HLength += SubLength;\r
8051302a 1390 }\r
2bbd7e2f
RN
1391\r
1392 Base += SubLength;\r
1393 Length -= SubLength;\r
1394\r
1395 if (HLength == 0) {\r
1396 continue;\r
1397 }\r
1398\r
1399 if ((Ranges[Index].Type == LowestType) || (Length == 0)) { // meet low type or end\r
1400\r
1401 //\r
1402 // Add the MTRRs for each high priority type range\r
1403 // the range[HBase, HBase + HLength) contains only two types.\r
1404 // We might use positive or subtractive, depending on which way uses less MTRR\r
1405 //\r
1406 for (SubStart = Start; SubStart <= Stop; SubStart++) {\r
3143144b 1407 if (Vertices[SubStart].Address == HBase) {\r
2bbd7e2f
RN
1408 break;\r
1409 }\r
8051302a 1410 }\r
2bbd7e2f
RN
1411\r
1412 for (SubStop = SubStart; SubStop <= Stop; SubStop++) {\r
3143144b 1413 if (Vertices[SubStop].Address == HBase + HLength) {\r
2bbd7e2f
RN
1414 break;\r
1415 }\r
1416 }\r
3143144b
RN
1417 ASSERT (Vertices[SubStart].Address == HBase);\r
1418 ASSERT (Vertices[SubStop].Address == HBase + HLength);\r
2bbd7e2f
RN
1419\r
1420 if ((TypeCount == 2) || (SubStart == SubStop - 1)) {\r
1421 //\r
1422 // add subtractive MTRRs for [HBase, HBase + HLength)\r
1423 // [HBase, HBase + HLength) contains only one type.\r
1424 // while - loop is to split the range to MTRR - compliant aligned range.\r
1425 //\r
1426 if (Mtrrs == NULL) {\r
1427 Weight[M (Start, Stop)] += (UINT8)(SubStop - SubStart);\r
1428 } else {\r
1429 while (SubStart != SubStop) {\r
1430 Status = MtrrLibAppendVariableMtrr (\r
1431 Mtrrs, MtrrCapacity, MtrrCount,\r
57951033 1432 Vertices[SubStart].Address, Vertices[SubStart].Length, Vertices[SubStart].Type\r
2bbd7e2f
RN
1433 );\r
1434 if (RETURN_ERROR (Status)) {\r
1435 return Status;\r
1436 }\r
1437 SubStart++;\r
1438 }\r
1439 }\r
1440 } else {\r
1441 ASSERT (TypeCount == 3);\r
3143144b 1442 MtrrLibCalculateLeastMtrrs (VertexCount, Vertices, Weight, SubStart, SubStop, TRUE);\r
2bbd7e2f
RN
1443\r
1444 if (Mtrrs == NULL) {\r
3143144b 1445 Weight[M (Start, Stop)] += Vertices[SubStop].Weight;\r
2bbd7e2f
RN
1446 } else {\r
1447 // When we need to collect the optimal path from SubStart to SubStop\r
1448 while (SubStop != SubStart) {\r
1449 Cur = SubStop;\r
3143144b 1450 Pre = Vertices[Cur].Previous;\r
2bbd7e2f
RN
1451 SubStop = Pre;\r
1452\r
57951033 1453 if (Weight[M (Pre, Cur)] + Weight[O (Pre, Cur)] != 0) {\r
2bbd7e2f
RN
1454 Status = MtrrLibAppendVariableMtrr (\r
1455 Mtrrs, MtrrCapacity, MtrrCount,\r
57951033
RN
1456 Vertices[Pre].Address, Vertices[Cur].Address - Vertices[Pre].Address,\r
1457 (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type\r
2bbd7e2f
RN
1458 );\r
1459 if (RETURN_ERROR (Status)) {\r
1460 return Status;\r
1461 }\r
1462 }\r
1463 if (Pre != Cur - 1) {\r
1464 Status = MtrrLibCalculateSubtractivePath (\r
1465 DefaultType, A0,\r
1466 Ranges, RangeCount,\r
3143144b 1467 VertexCount, Vertices, Weight,\r
2bbd7e2f
RN
1468 Pre, Cur, PrecedentTypes, 2,\r
1469 Mtrrs, MtrrCapacity, MtrrCount\r
1470 );\r
1471 if (RETURN_ERROR (Status)) {\r
1472 return Status;\r
1473 }\r
1474 }\r
1475 }\r
1476 }\r
1477\r
1478 }\r
1479 //\r
1480 // Reset HBase, HLength\r
1481 //\r
1482 HBase = MAX_UINT64;\r
1483 HLength = 0;\r
8051302a 1484 }\r
8051302a 1485 }\r
2bbd7e2f 1486 return RETURN_SUCCESS;\r
8051302a
RN
1487}\r
1488\r
1489/**\r
2bbd7e2f
RN
1490 Calculate MTRR settings to cover the specified memory ranges.\r
1491\r
1492 @param DefaultType Default memory type.\r
1493 @param A0 Alignment to use when base address is 0.\r
1494 @param Ranges Memory range array holding the memory type\r
1495 settings for all memory address.\r
1496 @param RangeCount Count of memory ranges.\r
1497 @param Scratch A temporary scratch buffer that is used to perform the calculation.\r
1498 This is an optional parameter that may be NULL.\r
1499 @param ScratchSize Pointer to the size in bytes of the scratch buffer.\r
1500 It may be updated to the actual required size when the calculation\r
1501 needs more scratch buffer.\r
1502 @param Mtrrs Array holding all MTRR settings.\r
1503 @param MtrrCapacity Capacity of the MTRR array.\r
1504 @param MtrrCount The count of MTRR settings in array.\r
8051302a
RN
1505\r
1506 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.\r
1507 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.\r
2bbd7e2f 1508 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
8051302a
RN
1509**/\r
1510RETURN_STATUS\r
2bbd7e2f
RN
1511MtrrLibCalculateMtrrs (\r
1512 IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
1513 IN UINT64 A0,\r
1514 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
1515 IN UINTN RangeCount,\r
1516 IN VOID *Scratch,\r
1517 IN OUT UINTN *ScratchSize,\r
1518 IN OUT MTRR_MEMORY_RANGE *Mtrrs,\r
1519 IN UINT32 MtrrCapacity,\r
1520 IN OUT UINT32 *MtrrCount\r
1521 )\r
8051302a 1522{\r
2bbd7e2f
RN
1523 UINT64 Base0;\r
1524 UINT64 Base1;\r
1525 UINTN Index;\r
1526 UINT64 Base;\r
1527 UINT64 Length;\r
8051302a 1528 UINT64 Alignment;\r
2bbd7e2f 1529 UINT64 SubLength;\r
3143144b 1530 MTRR_LIB_ADDRESS *Vertices;\r
2bbd7e2f 1531 UINT8 *Weight;\r
3143144b
RN
1532 UINT32 VertexIndex;\r
1533 UINT32 VertexCount;\r
2bbd7e2f
RN
1534 UINTN RequiredScratchSize;\r
1535 UINT8 TypeCount;\r
1536 UINT16 Start;\r
1537 UINT16 Stop;\r
1538 UINT8 Type;\r
1539 RETURN_STATUS Status;\r
3ff1e898 1540\r
2bbd7e2f
RN
1541 Base0 = Ranges[0].BaseAddress;\r
1542 Base1 = Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length;\r
1543 MTRR_LIB_ASSERT_ALIGNED (Base0, Base1 - Base0);\r
8051302a 1544\r
2bbd7e2f 1545 //\r
3143144b 1546 // Count the number of vertices.\r
2bbd7e2f 1547 //\r
3143144b
RN
1548 Vertices = (MTRR_LIB_ADDRESS*)Scratch;\r
1549 for (VertexIndex = 0, Index = 0; Index < RangeCount; Index++) {\r
2bbd7e2f
RN
1550 Base = Ranges[Index].BaseAddress;\r
1551 Length = Ranges[Index].Length;\r
1552 while (Length != 0) {\r
1553 Alignment = MtrrLibBiggestAlignment (Base, A0);\r
1554 SubLength = Alignment;\r
1555 if (SubLength > Length) {\r
1556 SubLength = GetPowerOfTwo64 (Length);\r
1557 }\r
3143144b
RN
1558 if (VertexIndex < *ScratchSize / sizeof (*Vertices)) {\r
1559 Vertices[VertexIndex].Address = Base;\r
1560 Vertices[VertexIndex].Alignment = Alignment;\r
1561 Vertices[VertexIndex].Type = Ranges[Index].Type;\r
1562 Vertices[VertexIndex].Length = SubLength;\r
2bbd7e2f
RN
1563 }\r
1564 Base += SubLength;\r
1565 Length -= SubLength;\r
3143144b 1566 VertexIndex++;\r
2bbd7e2f 1567 }\r
8051302a 1568 }\r
2bbd7e2f 1569 //\r
3143144b 1570 // Vertices[VertexIndex] = Base1, so whole vertex count is (VertexIndex + 1).\r
2bbd7e2f 1571 //\r
3143144b 1572 VertexCount = VertexIndex + 1;\r
2bbd7e2f 1573 DEBUG ((\r
3143144b
RN
1574 DEBUG_CACHE, " Count of vertices (%016llx - %016llx) = %d\n",\r
1575 Ranges[0].BaseAddress, Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length, VertexCount\r
2bbd7e2f 1576 ));\r
3143144b 1577 ASSERT (VertexCount < MAX_UINT16);\r
8051302a 1578\r
3143144b 1579 RequiredScratchSize = VertexCount * sizeof (*Vertices) + VertexCount * VertexCount * sizeof (*Weight);\r
2bbd7e2f
RN
1580 if (*ScratchSize < RequiredScratchSize) {\r
1581 *ScratchSize = RequiredScratchSize;\r
1582 return RETURN_BUFFER_TOO_SMALL;\r
8051302a 1583 }\r
3143144b 1584 Vertices[VertexCount - 1].Address = Base1;\r
8051302a 1585\r
3143144b
RN
1586 Weight = (UINT8 *) &Vertices[VertexCount];\r
1587 for (VertexIndex = 0; VertexIndex < VertexCount; VertexIndex++) {\r
ffb4c72d
RN
1588 //\r
1589 // Set optional weight between vertices and self->self to 0\r
1590 //\r
3143144b 1591 SetMem (&Weight[M(VertexIndex, 0)], VertexIndex + 1, 0);\r
ffb4c72d 1592 //\r
3143144b 1593 // Set mandatory weight between vertices to MAX_WEIGHT\r
ffb4c72d 1594 //\r
3143144b 1595 SetMem (&Weight[M (VertexIndex, VertexIndex + 1)], VertexCount - VertexIndex - 1, MAX_WEIGHT);\r
ffb4c72d
RN
1596\r
1597 // Final result looks like:\r
1598 // 00 FF FF FF\r
1599 // 00 00 FF FF\r
1600 // 00 00 00 FF\r
1601 // 00 00 00 00\r
1602 }\r
1603\r
1604 //\r
1605 // Set mandatory weight and optional weight for adjacent vertices\r
1606 //\r
3143144b
RN
1607 for (VertexIndex = 0; VertexIndex < VertexCount - 1; VertexIndex++) {\r
1608 if (Vertices[VertexIndex].Type != DefaultType) {\r
1609 Weight[M (VertexIndex, VertexIndex + 1)] = 1;\r
1610 Weight[O (VertexIndex, VertexIndex + 1)] = 0;\r
ffb4c72d 1611 } else {\r
3143144b
RN
1612 Weight[M (VertexIndex, VertexIndex + 1)] = 0;\r
1613 Weight[O (VertexIndex, VertexIndex + 1)] = 1;\r
8051302a 1614 }\r
8051302a
RN
1615 }\r
1616\r
2bbd7e2f 1617 for (TypeCount = 2; TypeCount <= 3; TypeCount++) {\r
3143144b
RN
1618 for (Start = 0; Start < VertexCount; Start++) {\r
1619 for (Stop = Start + 2; Stop < VertexCount; Stop++) {\r
1620 ASSERT (Vertices[Stop].Address > Vertices[Start].Address);\r
1621 Length = Vertices[Stop].Address - Vertices[Start].Address;\r
1622 if (Length > Vertices[Start].Alignment) {\r
2bbd7e2f
RN
1623 //\r
1624 // Pickup a new Start when [Start, Stop) cannot be described by one MTRR.\r
1625 //\r
1626 break;\r
1627 }\r
1628 if ((Weight[M(Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) {\r
1629 if (MtrrLibGetNumberOfTypes (\r
3143144b 1630 Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type\r
2bbd7e2f
RN
1631 ) == TypeCount) {\r
1632 //\r
1633 // Update the Weight[Start, Stop] using subtractive path.\r
1634 //\r
1635 MtrrLibCalculateSubtractivePath (\r
1636 DefaultType, A0,\r
1637 Ranges, RangeCount,\r
3143144b 1638 (UINT16)VertexCount, Vertices, Weight,\r
2bbd7e2f
RN
1639 Start, Stop, Type, TypeCount,\r
1640 NULL, 0, NULL\r
1641 );\r
1642 } else if (TypeCount == 2) {\r
1643 //\r
1644 // Pick up a new Start when we expect 2-type range, but 3-type range is met.\r
1645 // Because no matter how Stop is increased, we always meet 3-type range.\r
1646 //\r
1647 break;\r
1648 }\r
1649 }\r
1650 }\r
1651 }\r
8051302a
RN
1652 }\r
1653\r
2bbd7e2f 1654 Status = RETURN_SUCCESS;\r
3143144b
RN
1655 MtrrLibCalculateLeastMtrrs ((UINT16) VertexCount, Vertices, Weight, 0, (UINT16) VertexCount - 1, FALSE);\r
1656 Stop = (UINT16) VertexCount - 1;\r
2bbd7e2f 1657 while (Stop != 0) {\r
3143144b 1658 Start = Vertices[Stop].Previous;\r
2bbd7e2f
RN
1659 TypeCount = MAX_UINT8;\r
1660 Type = 0;\r
1661 if (Weight[M(Start, Stop)] != 0) {\r
3143144b 1662 TypeCount = MtrrLibGetNumberOfTypes (Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type);\r
2bbd7e2f
RN
1663 Status = MtrrLibAppendVariableMtrr (\r
1664 Mtrrs, MtrrCapacity, MtrrCount,\r
3143144b 1665 Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address,\r
2bbd7e2f
RN
1666 MtrrLibLowestType (Type)\r
1667 );\r
1668 if (RETURN_ERROR (Status)) {\r
1669 break;\r
8051302a
RN
1670 }\r
1671 }\r
1672\r
2bbd7e2f
RN
1673 if (Start != Stop - 1) {\r
1674 //\r
1675 // substractive path\r
1676 //\r
1677 if (TypeCount == MAX_UINT8) {\r
1678 TypeCount = MtrrLibGetNumberOfTypes (\r
3143144b 1679 Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type\r
2bbd7e2f
RN
1680 );\r
1681 }\r
1682 Status = MtrrLibCalculateSubtractivePath (\r
1683 DefaultType, A0,\r
1684 Ranges, RangeCount,\r
3143144b 1685 (UINT16) VertexCount, Vertices, Weight, Start, Stop,\r
2bbd7e2f
RN
1686 Type, TypeCount,\r
1687 Mtrrs, MtrrCapacity, MtrrCount\r
1688 );\r
1689 if (RETURN_ERROR (Status)) {\r
1690 break;\r
1691 }\r
8051302a 1692 }\r
2bbd7e2f
RN
1693 Stop = Start;\r
1694 }\r
1695 return Status;\r
1696}\r
1697\r
8051302a 1698\r
2bbd7e2f 1699/**\r
57994d9c 1700 Apply the fixed MTRR settings to memory range array.\r
2bbd7e2f
RN
1701\r
1702 @param Fixed The fixed MTRR settings.\r
1703 @param Ranges Return the memory range array holding memory type\r
1704 settings for all memory address.\r
1705 @param RangeCapacity The capacity of memory range array.\r
1706 @param RangeCount Return the count of memory range.\r
1707\r
1708 @retval RETURN_SUCCESS The memory range array is returned successfully.\r
1709 @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.\r
1710**/\r
1711RETURN_STATUS\r
1712MtrrLibApplyFixedMtrrs (\r
1713 IN MTRR_FIXED_SETTINGS *Fixed,\r
1714 IN OUT MTRR_MEMORY_RANGE *Ranges,\r
1715 IN UINTN RangeCapacity,\r
1716 IN OUT UINTN *RangeCount\r
1717 )\r
1718{\r
1719 RETURN_STATUS Status;\r
1720 UINTN MsrIndex;\r
1721 UINTN Index;\r
1722 MTRR_MEMORY_CACHE_TYPE MemoryType;\r
1723 UINT64 Base;\r
1724\r
1725 Base = 0;\r
1726 for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {\r
1727 ASSERT (Base == mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress);\r
1728 for (Index = 0; Index < sizeof (UINT64); Index++) {\r
1729 MemoryType = (MTRR_MEMORY_CACHE_TYPE)((UINT8 *)(&Fixed->Mtrr[MsrIndex]))[Index];\r
1730 Status = MtrrLibSetMemoryType (\r
1731 Ranges, RangeCapacity, RangeCount, Base, mMtrrLibFixedMtrrTable[MsrIndex].Length, MemoryType\r
1732 );\r
1733 if (Status == RETURN_OUT_OF_RESOURCES) {\r
1734 return Status;\r
1735 }\r
1736 Base += mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
1737 }\r
8051302a 1738 }\r
2bbd7e2f 1739 ASSERT (Base == BASE_1MB);\r
8051302a
RN
1740 return RETURN_SUCCESS;\r
1741}\r
1742\r
1743/**\r
2bbd7e2f 1744 Apply the variable MTRR settings to memory range array.\r
8051302a 1745\r
8051302a
RN
1746 @param VariableMtrr The variable MTRR array.\r
1747 @param VariableMtrrCount The count of variable MTRRs.\r
2bbd7e2f 1748 @param Ranges Return the memory range array with new MTRR settings applied.\r
8051302a
RN
1749 @param RangeCapacity The capacity of memory range array.\r
1750 @param RangeCount Return the count of memory range.\r
1751\r
1752 @retval RETURN_SUCCESS The memory range array is returned successfully.\r
1753 @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.\r
1754**/\r
1755RETURN_STATUS\r
2bbd7e2f
RN
1756MtrrLibApplyVariableMtrrs (\r
1757 IN CONST MTRR_MEMORY_RANGE *VariableMtrr,\r
1758 IN UINT32 VariableMtrrCount,\r
1759 IN OUT MTRR_MEMORY_RANGE *Ranges,\r
1760 IN UINTN RangeCapacity,\r
1761 IN OUT UINTN *RangeCount\r
1762 )\r
8051302a
RN
1763{\r
1764 RETURN_STATUS Status;\r
1765 UINTN Index;\r
1766\r
1767 //\r
1768 // WT > WB\r
1769 // UC > *\r
1770 // UC > * (except WB, UC) > WB\r
1771 //\r
1772\r
8051302a
RN
1773 //\r
1774 // 1. Set WB\r
1775 //\r
1776 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
2bbd7e2f 1777 if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheWriteBack)) {\r
8051302a
RN
1778 Status = MtrrLibSetMemoryType (\r
1779 Ranges, RangeCapacity, RangeCount,\r
2bbd7e2f 1780 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
8051302a 1781 );\r
2bbd7e2f 1782 if (Status == RETURN_OUT_OF_RESOURCES) {\r
8051302a
RN
1783 return Status;\r
1784 }\r
1785 }\r
1786 }\r
1787\r
1788 //\r
1789 // 2. Set other types than WB or UC\r
1790 //\r
1791 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
3143144b 1792 if ((VariableMtrr[Index].Length != 0) &&\r
2bbd7e2f 1793 (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable)) {\r
8051302a 1794 Status = MtrrLibSetMemoryType (\r
2bbd7e2f
RN
1795 Ranges, RangeCapacity, RangeCount,\r
1796 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
1797 );\r
1798 if (Status == RETURN_OUT_OF_RESOURCES) {\r
8051302a
RN
1799 return Status;\r
1800 }\r
1801 }\r
1802 }\r
1803\r
1804 //\r
1805 // 3. Set UC\r
1806 //\r
1807 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
2bbd7e2f 1808 if (VariableMtrr[Index].Length != 0 && VariableMtrr[Index].Type == CacheUncacheable) {\r
8051302a 1809 Status = MtrrLibSetMemoryType (\r
2bbd7e2f
RN
1810 Ranges, RangeCapacity, RangeCount,\r
1811 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
1812 );\r
1813 if (Status == RETURN_OUT_OF_RESOURCES) {\r
8051302a
RN
1814 return Status;\r
1815 }\r
1816 }\r
1817 }\r
1818 return RETURN_SUCCESS;\r
1819}\r
16c2d37e 1820\r
85b7f65b 1821/**\r
2bbd7e2f 1822 Return the memory type bit mask that's compatible to first type in the Ranges.\r
85b7f65b 1823\r
2bbd7e2f
RN
1824 @param Ranges Memory range array holding the memory type\r
1825 settings for all memory address.\r
1826 @param RangeCount Count of memory ranges.\r
b970ed68 1827\r
2bbd7e2f
RN
1828 @return Compatible memory type bit mask.\r
1829**/\r
1830UINT8\r
1831MtrrLibGetCompatibleTypes (\r
1832 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
1833 IN UINTN RangeCount\r
1834 )\r
1835{\r
1836 ASSERT (RangeCount != 0);\r
1837\r
1838 switch (Ranges[0].Type) {\r
1839 case CacheWriteBack:\r
1840 case CacheWriteThrough:\r
1841 return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable);\r
1842 break;\r
1843\r
1844 case CacheWriteCombining:\r
1845 case CacheWriteProtected:\r
1846 return (1 << Ranges[0].Type) | (1 << CacheUncacheable);\r
1847 break;\r
1848\r
1849 case CacheUncacheable:\r
1850 if (RangeCount == 1) {\r
1851 return (1 << CacheUncacheable);\r
1852 }\r
1853 return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1);\r
1854 break;\r
85b7f65b 1855\r
2bbd7e2f
RN
1856 case CacheInvalid:\r
1857 default:\r
1858 ASSERT (FALSE);\r
1859 break;\r
1860 }\r
1861 return 0;\r
1862}\r
85b7f65b 1863\r
2bbd7e2f
RN
1864/**\r
1865 Overwrite the destination MTRR settings with the source MTRR settings.\r
1866 This routine is to make sure the modification to destination MTRR settings\r
1867 is as small as possible.\r
1868\r
1869 @param DstMtrrs Destination MTRR settings.\r
1870 @param DstMtrrCount Count of destination MTRR settings.\r
1871 @param SrcMtrrs Source MTRR settings.\r
1872 @param SrcMtrrCount Count of source MTRR settings.\r
1873 @param Modified Flag array to indicate which destination MTRR setting is modified.\r
85b7f65b 1874**/\r
2bbd7e2f
RN
1875VOID\r
1876MtrrLibMergeVariableMtrr (\r
1877 MTRR_MEMORY_RANGE *DstMtrrs,\r
1878 UINT32 DstMtrrCount,\r
1879 MTRR_MEMORY_RANGE *SrcMtrrs,\r
1880 UINT32 SrcMtrrCount,\r
1881 BOOLEAN *Modified\r
85b7f65b
MK
1882 )\r
1883{\r
2bbd7e2f
RN
1884 UINT32 DstIndex;\r
1885 UINT32 SrcIndex;\r
8051302a 1886\r
2bbd7e2f 1887 ASSERT (SrcMtrrCount <= DstMtrrCount);\r
8051302a 1888\r
2bbd7e2f
RN
1889 for (DstIndex = 0; DstIndex < DstMtrrCount; DstIndex++) {\r
1890 Modified[DstIndex] = FALSE;\r
85b7f65b 1891\r
2bbd7e2f
RN
1892 if (DstMtrrs[DstIndex].Length == 0) {\r
1893 continue;\r
1894 }\r
1895 for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {\r
1896 if (DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress &&\r
1897 DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length &&\r
1898 DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type) {\r
1899 break;\r
1900 }\r
1901 }\r
85b7f65b 1902\r
2bbd7e2f
RN
1903 if (SrcIndex == SrcMtrrCount) {\r
1904 //\r
1905 // Remove the one from DstMtrrs which is not in SrcMtrrs\r
1906 //\r
1907 DstMtrrs[DstIndex].Length = 0;\r
1908 Modified[DstIndex] = TRUE;\r
1909 } else {\r
1910 //\r
1911 // Remove the one from SrcMtrrs which is also in DstMtrrs\r
1912 //\r
1913 SrcMtrrs[SrcIndex].Length = 0;\r
1914 }\r
85b7f65b
MK
1915 }\r
1916\r
2bbd7e2f
RN
1917 //\r
1918 // Now valid MTRR only exists in either DstMtrrs or SrcMtrrs.\r
1919 // Merge MTRRs from SrcMtrrs to DstMtrrs\r
1920 //\r
1921 DstIndex = 0;\r
1922 for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {\r
1923 if (SrcMtrrs[SrcIndex].Length != 0) {\r
85b7f65b 1924\r
2bbd7e2f
RN
1925 //\r
1926 // Find the empty slot in DstMtrrs\r
1927 //\r
1928 while (DstIndex < DstMtrrCount) {\r
1929 if (DstMtrrs[DstIndex].Length == 0) {\r
1930 break;\r
1931 }\r
1932 DstIndex++;\r
1933 }\r
1934 ASSERT (DstIndex < DstMtrrCount);\r
1935 CopyMem (&DstMtrrs[DstIndex], &SrcMtrrs[SrcIndex], sizeof (SrcMtrrs[0]));\r
1936 Modified[DstIndex] = TRUE;\r
1937 }\r
85b7f65b 1938 }\r
2bbd7e2f
RN
1939}\r
1940\r
1941/**\r
1942 Calculate the variable MTRR settings for all memory ranges.\r
85b7f65b 1943\r
2bbd7e2f
RN
1944 @param DefaultType Default memory type.\r
1945 @param A0 Alignment to use when base address is 0.\r
1946 @param Ranges Memory range array holding the memory type\r
1947 settings for all memory address.\r
1948 @param RangeCount Count of memory ranges.\r
1949 @param Scratch Scratch buffer to be used in MTRR calculation.\r
1950 @param ScratchSize Pointer to the size of scratch buffer.\r
1951 @param VariableMtrr Array holding all MTRR settings.\r
1952 @param VariableMtrrCapacity Capacity of the MTRR array.\r
1953 @param VariableMtrrCount The count of MTRR settings in array.\r
1954\r
1955 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.\r
1956 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.\r
1957 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
1958 The required scratch buffer size is returned through ScratchSize.\r
1959**/\r
1960RETURN_STATUS\r
1961MtrrLibSetMemoryRanges (\r
1962 IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
1963 IN UINT64 A0,\r
1964 IN MTRR_MEMORY_RANGE *Ranges,\r
1965 IN UINTN RangeCount,\r
1966 IN VOID *Scratch,\r
1967 IN OUT UINTN *ScratchSize,\r
1968 OUT MTRR_MEMORY_RANGE *VariableMtrr,\r
1969 IN UINT32 VariableMtrrCapacity,\r
1970 OUT UINT32 *VariableMtrrCount\r
1971 )\r
1972{\r
1973 RETURN_STATUS Status;\r
1974 UINT32 Index;\r
1975 UINT64 Base0;\r
1976 UINT64 Base1;\r
1977 UINT64 Alignment;\r
1978 UINT8 CompatibleTypes;\r
1979 UINT64 Length;\r
1980 UINT32 End;\r
1981 UINTN ActualScratchSize;\r
1982 UINTN BiggestScratchSize;\r
1983\r
1984 *VariableMtrrCount = 0;\r
3143144b 1985\r
85b7f65b 1986 //\r
2bbd7e2f
RN
1987 // Since the whole ranges need multiple calls of MtrrLibCalculateMtrrs().\r
1988 // Each call needs different scratch buffer size.\r
1989 // When the provided scratch buffer size is not sufficient in any call,\r
1990 // set the GetActualScratchSize to TRUE, and following calls will only\r
1991 // calculate the actual scratch size for the caller.\r
85b7f65b 1992 //\r
2bbd7e2f
RN
1993 BiggestScratchSize = 0;\r
1994\r
1995 for (Index = 0; Index < RangeCount;) {\r
1996 Base0 = Ranges[Index].BaseAddress;\r
1997\r
1998 //\r
1999 // Full step is optimal\r
2000 //\r
2001 while (Index < RangeCount) {\r
2002 ASSERT (Ranges[Index].BaseAddress == Base0);\r
2003 Alignment = MtrrLibBiggestAlignment (Base0, A0);\r
2004 while (Base0 + Alignment <= Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
2005 if ((BiggestScratchSize <= *ScratchSize) && (Ranges[Index].Type != DefaultType)) {\r
2006 Status = MtrrLibAppendVariableMtrr (\r
2007 VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
2008 Base0, Alignment, Ranges[Index].Type\r
2009 );\r
2010 if (RETURN_ERROR (Status)) {\r
2011 return Status;\r
2012 }\r
2013 }\r
2014 Base0 += Alignment;\r
2015 Alignment = MtrrLibBiggestAlignment (Base0, A0);\r
fa25cf38 2016 }\r
2bbd7e2f
RN
2017\r
2018 //\r
2019 // Remove the above range from Ranges[Index]\r
2020 //\r
2021 Ranges[Index].Length -= Base0 - Ranges[Index].BaseAddress;\r
2022 Ranges[Index].BaseAddress = Base0;\r
2023 if (Ranges[Index].Length != 0) {\r
2024 break;\r
b970ed68 2025 } else {\r
2bbd7e2f 2026 Index++;\r
fa25cf38 2027 }\r
85b7f65b 2028 }\r
85b7f65b 2029\r
2bbd7e2f
RN
2030 if (Index == RangeCount) {\r
2031 break;\r
2032 }\r
2033\r
2034 //\r
2035 // Find continous ranges [Base0, Base1) which could be combined by MTRR.\r
2036 // Per SDM, the compatible types between[B0, B1) are:\r
2037 // UC, *\r
2038 // WB, WT\r
2039 // UC, WB, WT\r
2040 //\r
2041 CompatibleTypes = MtrrLibGetCompatibleTypes (&Ranges[Index], RangeCount - Index);\r
2042\r
2043 End = Index; // End points to last one that matches the CompatibleTypes.\r
2044 while (End + 1 < RangeCount) {\r
2045 if (((1 << Ranges[End + 1].Type) & CompatibleTypes) == 0) {\r
2046 break;\r
2047 }\r
2048 End++;\r
2049 }\r
2050 Alignment = MtrrLibBiggestAlignment (Base0, A0);\r
2051 Length = GetPowerOfTwo64 (Ranges[End].BaseAddress + Ranges[End].Length - Base0);\r
2052 Base1 = Base0 + MIN (Alignment, Length);\r
2053\r
2054 //\r
2055 // Base1 may not in Ranges[End]. Update End to the range Base1 belongs to.\r
2056 //\r
2057 End = Index;\r
2058 while (End + 1 < RangeCount) {\r
2059 if (Base1 <= Ranges[End + 1].BaseAddress) {\r
2060 break;\r
2061 }\r
2062 End++;\r
2063 }\r
2064\r
2065 Length = Ranges[End].Length;\r
2066 Ranges[End].Length = Base1 - Ranges[End].BaseAddress;\r
2067 ActualScratchSize = *ScratchSize;\r
2068 Status = MtrrLibCalculateMtrrs (\r
2069 DefaultType, A0,\r
2070 &Ranges[Index], End + 1 - Index,\r
2071 Scratch, &ActualScratchSize,\r
2072 VariableMtrr, VariableMtrrCapacity, VariableMtrrCount\r
2073 );\r
2074 if (Status == RETURN_BUFFER_TOO_SMALL) {\r
2075 BiggestScratchSize = MAX (BiggestScratchSize, ActualScratchSize);\r
fa25cf38 2076 //\r
2bbd7e2f
RN
2077 // Ignore this error, because we need to calculate the biggest\r
2078 // scratch buffer size.\r
fa25cf38 2079 //\r
2bbd7e2f
RN
2080 Status = RETURN_SUCCESS;\r
2081 }\r
2082 if (RETURN_ERROR (Status)) {\r
2083 return Status;\r
2084 }\r
2085\r
2086 if (Length != Ranges[End].Length) {\r
2087 Ranges[End].BaseAddress = Base1;\r
2088 Ranges[End].Length = Length - Ranges[End].Length;\r
2089 Index = End;\r
2090 } else {\r
2091 Index = End + 1;\r
fa25cf38 2092 }\r
85b7f65b
MK
2093 }\r
2094\r
2bbd7e2f
RN
2095 if (*ScratchSize < BiggestScratchSize) {\r
2096 *ScratchSize = BiggestScratchSize;\r
2097 return RETURN_BUFFER_TOO_SMALL;\r
2098 }\r
2099 return RETURN_SUCCESS;\r
2100}\r
85b7f65b 2101\r
2bbd7e2f
RN
2102/**\r
2103 Set the below-1MB memory attribute to fixed MTRR buffer.\r
2104 Modified flag array indicates which fixed MTRR is modified.\r
2105\r
2106 @param [in, out] FixedSettings Fixed MTRR buffer.\r
2107 @param [out] Modified Flag array indicating which MTRR is modified.\r
2108 @param [in] BaseAddress Base address.\r
2109 @param [in] Length Length.\r
2110 @param [in] Type Memory type.\r
2111\r
2112 @retval RETURN_SUCCESS The memory attribute is set successfully.\r
2113 @retval RETURN_UNSUPPORTED The requested range or cache type was invalid\r
2114 for the fixed MTRRs.\r
2115**/\r
2116RETURN_STATUS\r
2117MtrrLibSetBelow1MBMemoryAttribute (\r
2118 IN OUT MTRR_FIXED_SETTINGS *FixedSettings,\r
2119 OUT BOOLEAN *Modified,\r
2120 IN PHYSICAL_ADDRESS BaseAddress,\r
2121 IN UINT64 Length,\r
2122 IN MTRR_MEMORY_CACHE_TYPE Type\r
2123 )\r
2124{\r
2125 RETURN_STATUS Status;\r
2126 UINT32 MsrIndex;\r
2127 UINT64 ClearMask;\r
2128 UINT64 OrMask;\r
2129 UINT64 ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
2130 UINT64 OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
86cabbcf 2131 BOOLEAN LocalModified[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
2bbd7e2f
RN
2132\r
2133 ASSERT (BaseAddress < BASE_1MB);\r
2134\r
86cabbcf
RN
2135 SetMem (LocalModified, sizeof (LocalModified), FALSE);\r
2136\r
2137 //\r
2138 // (Value & ~0 | 0) still equals to (Value)\r
2139 //\r
e00e0dd7
RN
2140 SetMem (ClearMasks, sizeof (ClearMasks), 0);\r
2141 SetMem (OrMasks, sizeof (OrMasks), 0);\r
86cabbcf 2142\r
2bbd7e2f
RN
2143 MsrIndex = (UINT32)-1;\r
2144 while ((BaseAddress < BASE_1MB) && (Length != 0)) {\r
2145 Status = MtrrLibProgramFixedMtrr (Type, &BaseAddress, &Length, &MsrIndex, &ClearMask, &OrMask);\r
2146 if (RETURN_ERROR (Status)) {\r
2147 return Status;\r
2148 }\r
86cabbcf
RN
2149 ClearMasks[MsrIndex] = ClearMask;\r
2150 OrMasks[MsrIndex] = OrMask;\r
2151 Modified[MsrIndex] = TRUE;\r
2152 LocalModified[MsrIndex] = TRUE;\r
e50466da 2153 }\r
8051302a 2154\r
2bbd7e2f 2155 for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {\r
86cabbcf 2156 if (LocalModified[MsrIndex]) {\r
2bbd7e2f
RN
2157 FixedSettings->Mtrr[MsrIndex] = (FixedSettings->Mtrr[MsrIndex] & ~ClearMasks[MsrIndex]) | OrMasks[MsrIndex];\r
2158 }\r
2159 }\r
2160 return RETURN_SUCCESS;\r
2161}\r
2162\r
2163/**\r
2164 This function attempts to set the attributes into MTRR setting buffer for multiple memory ranges.\r
8051302a 2165\r
2bbd7e2f
RN
2166 @param[in, out] MtrrSetting MTRR setting buffer to be set.\r
2167 @param[in] Scratch A temporary scratch buffer that is used to perform the calculation.\r
2168 @param[in, out] ScratchSize Pointer to the size in bytes of the scratch buffer.\r
2169 It may be updated to the actual required size when the calculation\r
2170 needs more scratch buffer.\r
2171 @param[in] Ranges Pointer to an array of MTRR_MEMORY_RANGE.\r
2172 When range overlap happens, the last one takes higher priority.\r
2173 When the function returns, either all the attributes are set successfully,\r
2174 or none of them is set.\r
f6194f5a 2175 @param[in] RangeCount Count of MTRR_MEMORY_RANGE.\r
2bbd7e2f
RN
2176\r
2177 @retval RETURN_SUCCESS The attributes were set for all the memory ranges.\r
2178 @retval RETURN_INVALID_PARAMETER Length in any range is zero.\r
2179 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the\r
2180 memory resource range specified by BaseAddress and Length in any range.\r
2181 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource\r
2182 range specified by BaseAddress and Length in any range.\r
2183 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
2184 the memory resource ranges.\r
2185 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by\r
2186 BaseAddress and Length cannot be modified.\r
2187 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
2188**/\r
2189RETURN_STATUS\r
2190EFIAPI\r
2191MtrrSetMemoryAttributesInMtrrSettings (\r
2192 IN OUT MTRR_SETTINGS *MtrrSetting,\r
2193 IN VOID *Scratch,\r
2194 IN OUT UINTN *ScratchSize,\r
2195 IN CONST MTRR_MEMORY_RANGE *Ranges,\r
2196 IN UINTN RangeCount\r
2197 )\r
2198{\r
2199 RETURN_STATUS Status;\r
2200 UINT32 Index;\r
2201 UINT64 BaseAddress;\r
2202 UINT64 Length;\r
2203 BOOLEAN Above1MbExist;\r
2204\r
2205 UINT64 MtrrValidBitsMask;\r
2206 UINT64 MtrrValidAddressMask;\r
2207 MTRR_MEMORY_CACHE_TYPE DefaultType;\r
2208 MTRR_VARIABLE_SETTINGS VariableSettings;\r
2209 MTRR_MEMORY_RANGE WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2];\r
2210 UINTN WorkingRangeCount;\r
2211 BOOLEAN Modified;\r
2212 MTRR_VARIABLE_SETTING VariableSetting;\r
2213 UINT32 OriginalVariableMtrrCount;\r
2214 UINT32 FirmwareVariableMtrrCount;\r
2215 UINT32 WorkingVariableMtrrCount;\r
2216 MTRR_MEMORY_RANGE OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
2217 MTRR_MEMORY_RANGE WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
2218 BOOLEAN VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
2219\r
2220 BOOLEAN FixedSettingsModified[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
2221 MTRR_FIXED_SETTINGS WorkingFixedSettings;\r
2222\r
2223 MTRR_CONTEXT MtrrContext;\r
2224 BOOLEAN MtrrContextValid;\r
2225\r
5a6c5af6 2226 Status = RETURN_SUCCESS;\r
2bbd7e2f 2227 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
e50466da 2228\r
2229 //\r
2bbd7e2f 2230 // TRUE indicating the accordingly Variable setting needs modificaiton in OriginalVariableMtrr.\r
e50466da 2231 //\r
2bbd7e2f 2232 SetMem (VariableSettingModified, ARRAY_SIZE (VariableSettingModified), FALSE);\r
8051302a 2233 //\r
2bbd7e2f 2234 // TRUE indicating the accordingly Fixed setting needs modification in WorkingFixedSettings.\r
8051302a 2235 //\r
2bbd7e2f
RN
2236 SetMem (FixedSettingsModified, ARRAY_SIZE (FixedSettingsModified), FALSE);\r
2237\r
2238 //\r
2239 // TRUE indicating the caller requests to set variable MTRRs.\r
2240 //\r
2241 Above1MbExist = FALSE;\r
2242 OriginalVariableMtrrCount = 0;\r
e50466da 2243\r
5a6c5af6
RN
2244 //\r
2245 // 0. Dump the requests.\r
2246 //\r
2247 DEBUG_CODE (\r
2248 DEBUG ((DEBUG_CACHE, "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a",\r
2249 (MtrrSetting == NULL) ? "Hardware" : "Buffer", *ScratchSize,\r
2250 (RangeCount <= 1) ? "," : "\n"\r
2251 ));\r
2252 for (Index = 0; Index < RangeCount; Index++) {\r
2253 DEBUG ((DEBUG_CACHE, " %a: [%016lx, %016lx)\n",\r
2254 mMtrrMemoryCacheTypeShortName[MIN (Ranges[Index].Type, CacheInvalid)],\r
2255 Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length\r
2256 ));\r
2257 }\r
2258 );\r
2259\r
2bbd7e2f
RN
2260 //\r
2261 // 1. Validate the parameters.\r
2262 //\r
5a6c5af6
RN
2263 if (!IsMtrrSupported ()) {\r
2264 Status = RETURN_UNSUPPORTED;\r
2265 goto Exit;\r
2266 }\r
2267\r
8051302a 2268 for (Index = 0; Index < RangeCount; Index++) {\r
2bbd7e2f 2269 if (Ranges[Index].Length == 0) {\r
5a6c5af6
RN
2270 Status = RETURN_INVALID_PARAMETER;\r
2271 goto Exit;\r
2bbd7e2f
RN
2272 }\r
2273 if (((Ranges[Index].BaseAddress & ~MtrrValidAddressMask) != 0) ||\r
cee85c48
RN
2274 ((((Ranges[Index].BaseAddress + Ranges[Index].Length) & ~MtrrValidAddressMask) != 0) &&\r
2275 (Ranges[Index].BaseAddress + Ranges[Index].Length) != MtrrValidBitsMask + 1)\r
2bbd7e2f 2276 ) {\r
cee85c48
RN
2277 //\r
2278 // Either the BaseAddress or the Limit doesn't follow the alignment requirement.\r
2279 // Note: It's still valid if Limit doesn't follow the alignment requirement but equals to MAX Address.\r
2280 //\r
5a6c5af6
RN
2281 Status = RETURN_UNSUPPORTED;\r
2282 goto Exit;\r
2bbd7e2f
RN
2283 }\r
2284 if ((Ranges[Index].Type != CacheUncacheable) &&\r
2285 (Ranges[Index].Type != CacheWriteCombining) &&\r
2286 (Ranges[Index].Type != CacheWriteThrough) &&\r
2287 (Ranges[Index].Type != CacheWriteProtected) &&\r
2288 (Ranges[Index].Type != CacheWriteBack)) {\r
5a6c5af6
RN
2289 Status = RETURN_INVALID_PARAMETER;\r
2290 goto Exit;\r
2bbd7e2f
RN
2291 }\r
2292 if (Ranges[Index].BaseAddress + Ranges[Index].Length > BASE_1MB) {\r
2293 Above1MbExist = TRUE;\r
8051302a 2294 }\r
1a2ad6fc 2295 }\r
e50466da 2296\r
1a2ad6fc 2297 //\r
2bbd7e2f 2298 // 2. Apply the above-1MB memory attribute settings.\r
1a2ad6fc 2299 //\r
2bbd7e2f
RN
2300 if (Above1MbExist) {\r
2301 //\r
2302 // 2.1. Read all variable MTRRs and convert to Ranges.\r
2303 //\r
2304 OriginalVariableMtrrCount = GetVariableMtrrCountWorker ();\r
2305 MtrrGetVariableMtrrWorker (MtrrSetting, OriginalVariableMtrrCount, &VariableSettings);\r
2306 MtrrLibGetRawVariableRanges (\r
2307 &VariableSettings, OriginalVariableMtrrCount,\r
2308 MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableMtrr\r
2309 );\r
1a2ad6fc 2310\r
2bbd7e2f
RN
2311 DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting);\r
2312 WorkingRangeCount = 1;\r
2313 WorkingRanges[0].BaseAddress = 0;\r
2314 WorkingRanges[0].Length = MtrrValidBitsMask + 1;\r
2315 WorkingRanges[0].Type = DefaultType;\r
1a2ad6fc 2316\r
2bbd7e2f
RN
2317 Status = MtrrLibApplyVariableMtrrs (\r
2318 OriginalVariableMtrr, OriginalVariableMtrrCount,\r
2319 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount);\r
2320 ASSERT_RETURN_ERROR (Status);\r
1a2ad6fc 2321\r
2bbd7e2f
RN
2322 ASSERT (OriginalVariableMtrrCount >= PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs));\r
2323 FirmwareVariableMtrrCount = OriginalVariableMtrrCount - PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);\r
2324 ASSERT (WorkingRangeCount <= 2 * FirmwareVariableMtrrCount + 1);\r
1a2ad6fc 2325\r
8051302a 2326 //\r
2bbd7e2f 2327 // 2.2. Force [0, 1M) to UC, so that it doesn't impact subtraction algorithm.\r
8051302a 2328 //\r
2bbd7e2f
RN
2329 Status = MtrrLibSetMemoryType (\r
2330 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,\r
2331 0, SIZE_1MB, CacheUncacheable\r
2332 );\r
2333 ASSERT (Status != RETURN_OUT_OF_RESOURCES);\r
8051302a 2334\r
2bbd7e2f
RN
2335 //\r
2336 // 2.3. Apply the new memory attribute settings to Ranges.\r
2337 //\r
2338 Modified = FALSE;\r
2339 for (Index = 0; Index < RangeCount; Index++) {\r
2340 BaseAddress = Ranges[Index].BaseAddress;\r
2341 Length = Ranges[Index].Length;\r
2342 if (BaseAddress < BASE_1MB) {\r
2343 if (Length <= BASE_1MB - BaseAddress) {\r
2344 continue;\r
1a2ad6fc 2345 }\r
2bbd7e2f
RN
2346 Length -= BASE_1MB - BaseAddress;\r
2347 BaseAddress = BASE_1MB;\r
1a2ad6fc 2348 }\r
2bbd7e2f
RN
2349 Status = MtrrLibSetMemoryType (\r
2350 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,\r
2351 BaseAddress, Length, Ranges[Index].Type\r
2352 );\r
2353 if (Status == RETURN_ALREADY_STARTED) {\r
2354 Status = RETURN_SUCCESS;\r
2355 } else if (Status == RETURN_OUT_OF_RESOURCES) {\r
5a6c5af6 2356 goto Exit;\r
8051302a 2357 } else {\r
2bbd7e2f
RN
2358 ASSERT_RETURN_ERROR (Status);\r
2359 Modified = TRUE;\r
8051302a 2360 }\r
1a2ad6fc 2361 }\r
1a2ad6fc 2362\r
2bbd7e2f
RN
2363 if (Modified) {\r
2364 //\r
2365 // 2.4. Calculate the Variable MTRR settings based on the Ranges.\r
2366 // Buffer Too Small may be returned if the scratch buffer size is insufficient.\r
2367 //\r
2368 Status = MtrrLibSetMemoryRanges (\r
2369 DefaultType, LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)), WorkingRanges, WorkingRangeCount,\r
2370 Scratch, ScratchSize,\r
2371 WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &WorkingVariableMtrrCount\r
2372 );\r
2373 if (RETURN_ERROR (Status)) {\r
5a6c5af6 2374 goto Exit;\r
2bbd7e2f 2375 }\r
e50466da 2376\r
2bbd7e2f
RN
2377 //\r
2378 // 2.5. Remove the [0, 1MB) MTRR if it still exists (not merged with other range)\r
2379 //\r
2380 for (Index = 0; Index < WorkingVariableMtrrCount; Index++) {\r
2381 if (WorkingVariableMtrr[Index].BaseAddress == 0 && WorkingVariableMtrr[Index].Length == SIZE_1MB) {\r
2382 ASSERT (WorkingVariableMtrr[Index].Type == CacheUncacheable);\r
2383 WorkingVariableMtrrCount--;\r
2384 CopyMem (\r
2385 &WorkingVariableMtrr[Index], &WorkingVariableMtrr[Index + 1],\r
2386 (WorkingVariableMtrrCount - Index) * sizeof (WorkingVariableMtrr[0])\r
2387 );\r
2388 break;\r
c9b44921 2389 }\r
85b7f65b 2390 }\r
2bbd7e2f
RN
2391\r
2392 if (WorkingVariableMtrrCount > FirmwareVariableMtrrCount) {\r
5a6c5af6
RN
2393 Status = RETURN_OUT_OF_RESOURCES;\r
2394 goto Exit;\r
2bbd7e2f
RN
2395 }\r
2396\r
2397 //\r
2398 // 2.6. Merge the WorkingVariableMtrr to OriginalVariableMtrr\r
2399 // Make sure least modification is made to OriginalVariableMtrr.\r
2400 //\r
2401 MtrrLibMergeVariableMtrr (\r
2402 OriginalVariableMtrr, OriginalVariableMtrrCount,\r
2403 WorkingVariableMtrr, WorkingVariableMtrrCount,\r
2404 VariableSettingModified\r
2405 );\r
85b7f65b 2406 }\r
e50466da 2407 }\r
2408\r
8051302a 2409 //\r
2bbd7e2f 2410 // 3. Apply the below-1MB memory attribute settings.\r
8051302a 2411 //\r
86cabbcf 2412 ZeroMem (WorkingFixedSettings.Mtrr, sizeof (WorkingFixedSettings.Mtrr));\r
2bbd7e2f
RN
2413 for (Index = 0; Index < RangeCount; Index++) {\r
2414 if (Ranges[Index].BaseAddress >= BASE_1MB) {\r
2415 continue;\r
85b7f65b 2416 }\r
85b7f65b 2417\r
2bbd7e2f
RN
2418 Status = MtrrLibSetBelow1MBMemoryAttribute (\r
2419 &WorkingFixedSettings, FixedSettingsModified,\r
2420 Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type\r
2421 );\r
2422 if (RETURN_ERROR (Status)) {\r
5a6c5af6 2423 goto Exit;\r
2bbd7e2f 2424 }\r
8051302a 2425 }\r
fa25cf38 2426\r
8051302a 2427 MtrrContextValid = FALSE;\r
fa25cf38 2428 //\r
2bbd7e2f 2429 // 4. Write fixed MTRRs that have been modified\r
fa25cf38 2430 //\r
2bbd7e2f 2431 for (Index = 0; Index < ARRAY_SIZE (FixedSettingsModified); Index++) {\r
fa25cf38 2432 if (FixedSettingsModified[Index]) {\r
2bbd7e2f
RN
2433 if (MtrrSetting != NULL) {\r
2434 MtrrSetting->Fixed.Mtrr[Index] = WorkingFixedSettings.Mtrr[Index];\r
2435 } else {\r
2436 if (!MtrrContextValid) {\r
2437 MtrrLibPreMtrrChange (&MtrrContext);\r
2438 MtrrContextValid = TRUE;\r
2439 }\r
2440 AsmWriteMsr64 (\r
2441 mMtrrLibFixedMtrrTable[Index].Msr,\r
2442 WorkingFixedSettings.Mtrr[Index]\r
fa25cf38 2443 );\r
2bbd7e2f 2444 }\r
fa25cf38
MK
2445 }\r
2446 }\r
2447\r
b0fa5d29 2448 //\r
2bbd7e2f 2449 // 5. Write variable MTRRs that have been modified\r
b0fa5d29 2450 //\r
8051302a
RN
2451 for (Index = 0; Index < OriginalVariableMtrrCount; Index++) {\r
2452 if (VariableSettingModified[Index]) {\r
2bbd7e2f
RN
2453 if (OriginalVariableMtrr[Index].Length != 0) {\r
2454 VariableSetting.Base = (OriginalVariableMtrr[Index].BaseAddress & MtrrValidAddressMask)\r
2455 | (UINT8)OriginalVariableMtrr[Index].Type;\r
2456 VariableSetting.Mask = ((~(OriginalVariableMtrr[Index].Length - 1)) & MtrrValidAddressMask) | BIT11;\r
2457 } else {\r
2458 VariableSetting.Base = 0;\r
2459 VariableSetting.Mask = 0;\r
2460 }\r
2461 if (MtrrSetting != NULL) {\r
2462 CopyMem (&MtrrSetting->Variables.Mtrr[Index], &VariableSetting, sizeof (VariableSetting));\r
2463 } else {\r
2464 if (!MtrrContextValid) {\r
2465 MtrrLibPreMtrrChange (&MtrrContext);\r
2466 MtrrContextValid = TRUE;\r
2467 }\r
2468 AsmWriteMsr64 (\r
2469 MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),\r
2470 VariableSetting.Base\r
2471 );\r
2472 AsmWriteMsr64 (\r
2473 MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),\r
2474 VariableSetting.Mask\r
2475 );\r
b0fa5d29
MK
2476 }\r
2477 }\r
2478 }\r
2bbd7e2f
RN
2479\r
2480 if (MtrrSetting != NULL) {\r
2481 ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E = 1;\r
2482 ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.FE = 1;\r
2483 } else {\r
2484 if (MtrrContextValid) {\r
2485 MtrrLibPostMtrrChange (&MtrrContext);\r
2486 }\r
fa25cf38
MK
2487 }\r
2488\r
5a6c5af6
RN
2489Exit:\r
2490 DEBUG ((DEBUG_CACHE, " Result = %r\n", Status));\r
2491 if (!RETURN_ERROR (Status)) {\r
2492 MtrrDebugPrintAllMtrrsWorker (MtrrSetting);\r
2493 }\r
2494 return Status;\r
31b3597e 2495}\r
b970ed68
MK
2496\r
2497/**\r
2bbd7e2f 2498 This function attempts to set the attributes into MTRR setting buffer for a memory range.\r
b970ed68 2499\r
2bbd7e2f
RN
2500 @param[in, out] MtrrSetting MTRR setting buffer to be set.\r
2501 @param[in] BaseAddress The physical address that is the start address\r
2502 of a memory range.\r
2503 @param[in] Length The size in bytes of the memory range.\r
2504 @param[in] Attribute The bit mask of attributes to set for the\r
2505 memory range.\r
b970ed68 2506\r
2bbd7e2f 2507 @retval RETURN_SUCCESS The attributes were set for the memory range.\r
b970ed68 2508 @retval RETURN_INVALID_PARAMETER Length is zero.\r
2bbd7e2f
RN
2509 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the\r
2510 memory resource range specified by BaseAddress and Length.\r
2511 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource\r
2512 range specified by BaseAddress and Length.\r
2513 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by\r
2514 BaseAddress and Length cannot be modified.\r
2515 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
2516 the memory resource range.\r
2517 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
b970ed68
MK
2518**/\r
2519RETURN_STATUS\r
2520EFIAPI\r
2bbd7e2f
RN
2521MtrrSetMemoryAttributeInMtrrSettings (\r
2522 IN OUT MTRR_SETTINGS *MtrrSetting,\r
b970ed68
MK
2523 IN PHYSICAL_ADDRESS BaseAddress,\r
2524 IN UINT64 Length,\r
2525 IN MTRR_MEMORY_CACHE_TYPE Attribute\r
2526 )\r
2527{\r
2bbd7e2f
RN
2528 UINT8 Scratch[SCRATCH_BUFFER_SIZE];\r
2529 UINTN ScratchSize;\r
2530 MTRR_MEMORY_RANGE Range;\r
8051302a 2531\r
2bbd7e2f
RN
2532 Range.BaseAddress = BaseAddress;\r
2533 Range.Length = Length;\r
2534 Range.Type = Attribute;\r
2535 ScratchSize = sizeof (Scratch);\r
5a6c5af6 2536 return MtrrSetMemoryAttributesInMtrrSettings (MtrrSetting, Scratch, &ScratchSize, &Range, 1);\r
b970ed68
MK
2537}\r
2538\r
2539/**\r
2bbd7e2f 2540 This function attempts to set the attributes for a memory range.\r
b970ed68 2541\r
2bbd7e2f
RN
2542 @param[in] BaseAddress The physical address that is the start\r
2543 address of a memory range.\r
2544 @param[in] Length The size in bytes of the memory range.\r
2545 @param[in] Attributes The bit mask of attributes to set for the\r
2546 memory range.\r
b970ed68 2547\r
2bbd7e2f
RN
2548 @retval RETURN_SUCCESS The attributes were set for the memory\r
2549 range.\r
b970ed68 2550 @retval RETURN_INVALID_PARAMETER Length is zero.\r
2bbd7e2f
RN
2551 @retval RETURN_UNSUPPORTED The processor does not support one or\r
2552 more bytes of the memory resource range\r
2553 specified by BaseAddress and Length.\r
2554 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support\r
2555 for the memory resource range specified\r
2556 by BaseAddress and Length.\r
2557 @retval RETURN_ACCESS_DENIED The attributes for the memory resource\r
2558 range specified by BaseAddress and Length\r
2559 cannot be modified.\r
2560 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to\r
2561 modify the attributes of the memory\r
2562 resource range.\r
2563 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.\r
b970ed68
MK
2564**/\r
2565RETURN_STATUS\r
2566EFIAPI\r
2bbd7e2f 2567MtrrSetMemoryAttribute (\r
b970ed68
MK
2568 IN PHYSICAL_ADDRESS BaseAddress,\r
2569 IN UINT64 Length,\r
2570 IN MTRR_MEMORY_CACHE_TYPE Attribute\r
2571 )\r
2572{\r
2bbd7e2f 2573 return MtrrSetMemoryAttributeInMtrrSettings (NULL, BaseAddress, Length, Attribute);\r
b970ed68
MK
2574}\r
2575\r
e50466da 2576/**\r
2577 Worker function setting variable MTRRs\r
2578\r
76b4cae3 2579 @param[in] VariableSettings A buffer to hold variable MTRRs content.\r
e50466da 2580\r
2581**/\r
2582VOID\r
2583MtrrSetVariableMtrrWorker (\r
2584 IN MTRR_VARIABLE_SETTINGS *VariableSettings\r
2585 )\r
2586{\r
2587 UINT32 Index;\r
3b9be416 2588 UINT32 VariableMtrrCount;\r
e50466da 2589\r
acf431e6 2590 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
2bbd7e2f 2591 ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr));\r
5bdfa4e5 2592\r
3b9be416 2593 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
9c8c4478
RN
2594 //\r
2595 // Mask MSR is always updated since caller might need to invalidate the MSR pair.\r
2596 // Base MSR is skipped when Mask.V is not set.\r
2597 //\r
2598 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSettings->Mtrr[Index].Mask);\r
2599 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
2600 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSettings->Mtrr[Index].Base);\r
2601 }\r
e50466da 2602 }\r
2603}\r
2604\r
2605\r
2606/**\r
2607 This function sets variable MTRRs\r
2608\r
76b4cae3 2609 @param[in] VariableSettings A buffer to hold variable MTRRs content.\r
e50466da 2610\r
2611 @return The pointer of VariableSettings\r
2612\r
2613**/\r
2614MTRR_VARIABLE_SETTINGS*\r
2615EFIAPI\r
2616MtrrSetVariableMtrr (\r
2617 IN MTRR_VARIABLE_SETTINGS *VariableSettings\r
2618 )\r
2619{\r
c878cee4 2620 MTRR_CONTEXT MtrrContext;\r
e50466da 2621\r
947a573a 2622 if (!IsMtrrSupported ()) {\r
2623 return VariableSettings;\r
2624 }\r
2625\r
b8f01599 2626 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2627 MtrrSetVariableMtrrWorker (VariableSettings);\r
b8f01599 2628 MtrrLibPostMtrrChange (&MtrrContext);\r
e518b80d
MK
2629 MtrrDebugPrintAllMtrrs ();\r
2630\r
e50466da 2631 return VariableSettings;\r
2632}\r
2633\r
e50466da 2634/**\r
2635 Worker function setting fixed MTRRs\r
2636\r
acf431e6 2637 @param[in] FixedSettings A buffer to hold fixed MTRRs content.\r
e50466da 2638\r
2639**/\r
2640VOID\r
2641MtrrSetFixedMtrrWorker (\r
2642 IN MTRR_FIXED_SETTINGS *FixedSettings\r
2643 )\r
2644{\r
2645 UINT32 Index;\r
2646\r
2647 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
2648 AsmWriteMsr64 (\r
f877f300 2649 mMtrrLibFixedMtrrTable[Index].Msr,\r
e50466da 2650 FixedSettings->Mtrr[Index]\r
2651 );\r
2652 }\r
2653}\r
2654\r
2655\r
2656/**\r
2657 This function sets fixed MTRRs\r
2658\r
acf431e6 2659 @param[in] FixedSettings A buffer to hold fixed MTRRs content.\r
e50466da 2660\r
2661 @retval The pointer of FixedSettings\r
2662\r
2663**/\r
2664MTRR_FIXED_SETTINGS*\r
2665EFIAPI\r
2666MtrrSetFixedMtrr (\r
2667 IN MTRR_FIXED_SETTINGS *FixedSettings\r
2668 )\r
2669{\r
c878cee4 2670 MTRR_CONTEXT MtrrContext;\r
e50466da 2671\r
947a573a 2672 if (!IsMtrrSupported ()) {\r
2673 return FixedSettings;\r
2674 }\r
2675\r
b8f01599 2676 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2677 MtrrSetFixedMtrrWorker (FixedSettings);\r
b8f01599 2678 MtrrLibPostMtrrChange (&MtrrContext);\r
e518b80d 2679 MtrrDebugPrintAllMtrrs ();\r
e50466da 2680\r
2681 return FixedSettings;\r
2682}\r
2683\r
2684\r
2685/**\r
2686 This function gets the content in all MTRRs (variable and fixed)\r
2687\r
acf431e6 2688 @param[out] MtrrSetting A buffer to hold all MTRRs content.\r
e50466da 2689\r
2690 @retval the pointer of MtrrSetting\r
2691\r
2692**/\r
2693MTRR_SETTINGS *\r
2694EFIAPI\r
2695MtrrGetAllMtrrs (\r
2696 OUT MTRR_SETTINGS *MtrrSetting\r
2697 )\r
2698{\r
947a573a 2699 if (!IsMtrrSupported ()) {\r
2700 return MtrrSetting;\r
2701 }\r
2702\r
e50466da 2703 //\r
2704 // Get fixed MTRRs\r
2705 //\r
acf431e6 2706 MtrrGetFixedMtrrWorker (&MtrrSetting->Fixed);\r
e50466da 2707\r
2708 //\r
2709 // Get variable MTRRs\r
2710 //\r
acf431e6 2711 MtrrGetVariableMtrrWorker (\r
5abd5ed4 2712 NULL,\r
acf431e6
MK
2713 GetVariableMtrrCountWorker (),\r
2714 &MtrrSetting->Variables\r
2715 );\r
e50466da 2716\r
2717 //\r
2718 // Get MTRR_DEF_TYPE value\r
2719 //\r
af838805 2720 MtrrSetting->MtrrDefType = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
e50466da 2721\r
2722 return MtrrSetting;\r
2723}\r
2724\r
2725\r
2726/**\r
2727 This function sets all MTRRs (variable and fixed)\r
2728\r
76b4cae3 2729 @param[in] MtrrSetting A buffer holding all MTRRs content.\r
e50466da 2730\r
2731 @retval The pointer of MtrrSetting\r
2732\r
2733**/\r
2734MTRR_SETTINGS *\r
2735EFIAPI\r
2736MtrrSetAllMtrrs (\r
2737 IN MTRR_SETTINGS *MtrrSetting\r
2738 )\r
2739{\r
c878cee4 2740 MTRR_CONTEXT MtrrContext;\r
e50466da 2741\r
947a573a 2742 if (!IsMtrrSupported ()) {\r
2743 return MtrrSetting;\r
2744 }\r
2745\r
b8f01599 2746 MtrrLibPreMtrrChange (&MtrrContext);\r
e50466da 2747\r
2748 //\r
2749 // Set fixed MTRRs\r
2750 //\r
2751 MtrrSetFixedMtrrWorker (&MtrrSetting->Fixed);\r
2752\r
2753 //\r
2754 // Set variable MTRRs\r
2755 //\r
2756 MtrrSetVariableMtrrWorker (&MtrrSetting->Variables);\r
2757\r
2758 //\r
2759 // Set MTRR_DEF_TYPE value\r
2760 //\r
af838805 2761 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrSetting->MtrrDefType);\r
e50466da 2762\r
b8f01599 2763 MtrrLibPostMtrrChangeEnableCache (&MtrrContext);\r
e50466da 2764\r
2765 return MtrrSetting;\r
2766}\r
2767\r
e518b80d 2768\r
947a573a 2769/**\r
2770 Checks if MTRR is supported.\r
2771\r
2772 @retval TRUE MTRR is supported.\r
2773 @retval FALSE MTRR is not supported.\r
2774\r
2775**/\r
2776BOOLEAN\r
2777EFIAPI\r
2778IsMtrrSupported (\r
2779 VOID\r
2780 )\r
2781{\r
3bb13d35
RN
2782 CPUID_VERSION_INFO_EDX Edx;\r
2783 MSR_IA32_MTRRCAP_REGISTER MtrrCap;\r
947a573a 2784\r
2785 //\r
2786 // Check CPUID(1).EDX[12] for MTRR capability\r
2787 //\r
3bb13d35
RN
2788 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32);\r
2789 if (Edx.Bits.MTRR == 0) {\r
947a573a 2790 return FALSE;\r
2791 }\r
2792\r
2793 //\r
3bb13d35
RN
2794 // Check number of variable MTRRs and fixed MTRRs existence.\r
2795 // If number of variable MTRRs is zero, or fixed MTRRs do not\r
947a573a 2796 // exist, return false.\r
2797 //\r
3bb13d35
RN
2798 MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
2799 if ((MtrrCap.Bits.VCNT == 0) || (MtrrCap.Bits.FIX == 0)) {\r
947a573a 2800 return FALSE;\r
2801 }\r
947a573a 2802 return TRUE;\r
2803}\r
8051302a 2804\r
2bbd7e2f
RN
2805\r
2806/**\r
2807 Worker function prints all MTRRs for debugging.\r
2808\r
2809 If MtrrSetting is not NULL, print MTRR settings from input MTRR\r
2810 settings buffer.\r
2811 If MtrrSetting is NULL, print MTRR settings from MTRRs.\r
2812\r
2813 @param MtrrSetting A buffer holding all MTRRs content.\r
2814**/\r
2815VOID\r
2816MtrrDebugPrintAllMtrrsWorker (\r
2817 IN MTRR_SETTINGS *MtrrSetting\r
2818 )\r
2819{\r
2820 DEBUG_CODE (\r
2821 MTRR_SETTINGS LocalMtrrs;\r
2822 MTRR_SETTINGS *Mtrrs;\r
2823 UINTN Index;\r
2824 UINTN RangeCount;\r
2825 UINT64 MtrrValidBitsMask;\r
2826 UINT64 MtrrValidAddressMask;\r
1c29d038 2827 UINT32 VariableMtrrCount;\r
5a6c5af6 2828 BOOLEAN ContainVariableMtrr;\r
2bbd7e2f
RN
2829 MTRR_MEMORY_RANGE Ranges[\r
2830 ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1\r
2831 ];\r
2832 MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];\r
2833\r
2834 if (!IsMtrrSupported ()) {\r
2835 return;\r
2836 }\r
2837\r
1c29d038
RN
2838 VariableMtrrCount = GetVariableMtrrCountWorker ();\r
2839\r
2bbd7e2f
RN
2840 if (MtrrSetting != NULL) {\r
2841 Mtrrs = MtrrSetting;\r
2842 } else {\r
2843 MtrrGetAllMtrrs (&LocalMtrrs);\r
2844 Mtrrs = &LocalMtrrs;\r
2845 }\r
2846\r
2847 //\r
2848 // Dump RAW MTRR contents\r
2849 //\r
5a6c5af6
RN
2850 DEBUG ((DEBUG_CACHE, "MTRR Settings:\n"));\r
2851 DEBUG ((DEBUG_CACHE, "=============\n"));\r
2852 DEBUG ((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType));\r
2bbd7e2f 2853 for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) {\r
5a6c5af6 2854 DEBUG ((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index]));\r
2bbd7e2f 2855 }\r
5a6c5af6 2856 ContainVariableMtrr = FALSE;\r
1c29d038 2857 for (Index = 0; Index < VariableMtrrCount; Index++) {\r
9c8c4478 2858 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 0) {\r
2bbd7e2f
RN
2859 //\r
2860 // If mask is not valid, then do not display range\r
2861 //\r
2862 continue;\r
2863 }\r
5a6c5af6 2864 ContainVariableMtrr = TRUE;\r
2bbd7e2f
RN
2865 DEBUG ((DEBUG_CACHE, "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n",\r
2866 Index,\r
2867 Mtrrs->Variables.Mtrr[Index].Base,\r
2868 Mtrrs->Variables.Mtrr[Index].Mask\r
2869 ));\r
2870 }\r
5a6c5af6
RN
2871 if (!ContainVariableMtrr) {\r
2872 DEBUG ((DEBUG_CACHE, "Variable MTRR : None.\n"));\r
2873 }\r
2bbd7e2f
RN
2874 DEBUG((DEBUG_CACHE, "\n"));\r
2875\r
2876 //\r
2877 // Dump MTRR setting in ranges\r
2878 //\r
5a6c5af6 2879 DEBUG((DEBUG_CACHE, "Memory Ranges:\n"));\r
2bbd7e2f
RN
2880 DEBUG((DEBUG_CACHE, "====================================\n"));\r
2881 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
2882 Ranges[0].BaseAddress = 0;\r
2883 Ranges[0].Length = MtrrValidBitsMask + 1;\r
2884 Ranges[0].Type = MtrrGetDefaultMemoryTypeWorker (Mtrrs);\r
2885 RangeCount = 1;\r
2886\r
2887 MtrrLibGetRawVariableRanges (\r
1c29d038 2888 &Mtrrs->Variables, VariableMtrrCount,\r
2bbd7e2f
RN
2889 MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges\r
2890 );\r
2891 MtrrLibApplyVariableMtrrs (\r
1c29d038 2892 RawVariableRanges, VariableMtrrCount,\r
2bbd7e2f
RN
2893 Ranges, ARRAY_SIZE (Ranges), &RangeCount\r
2894 );\r
2895\r
2896 MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount);\r
2897\r
2898 for (Index = 0; Index < RangeCount; Index++) {\r
2899 DEBUG ((DEBUG_CACHE, "%a:%016lx-%016lx\n",\r
2900 mMtrrMemoryCacheTypeShortName[Ranges[Index].Type],\r
2901 Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - 1\r
2902 ));\r
2903 }\r
2904 );\r
2905}\r
2906\r
2907/**\r
2908 This function prints all MTRRs for debugging.\r
2909**/\r
2910VOID\r
2911EFIAPI\r
2912MtrrDebugPrintAllMtrrs (\r
2913 VOID\r
2914 )\r
2915{\r
2916 MtrrDebugPrintAllMtrrsWorker (NULL);\r
2917}\r