MdeModulePkg/metafile: Add PCD PcdCpuStackGuard
[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec
CommitLineData
7798fb83 1## @file UefiCpuPkg.dec\r
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2# This Package provides UEFI compatible CPU modules and libraries.\r
3#\r
7eee4e1e 4# Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>\r
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5#\r
6# This program and the accompanying materials are licensed and made available under\r
7# the terms and conditions of the BSD License which accompanies this distribution.\r
8# The full text of the license may be found at\r
9# http://opensource.org/licenses/bsd-license.php\r
10#\r
11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13#\r
14##\r
15\r
16[Defines]\r
17 DEC_SPECIFICATION = 0x00010005\r
18 PACKAGE_NAME = UefiCpuPkg\r
abae030a 19 PACKAGE_UNI_FILE = UefiCpuPkg.uni\r
7798fb83 20 PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23\r
93041972 21 PACKAGE_VERSION = 0.80\r
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22\r
23[Includes]\r
24 Include\r
25\r
26[LibraryClasses]\r
27 ## @libraryclass Defines some routines that are generic for IA32 family CPU\r
28 ## to be UEFI specification compliant.\r
29 ##\r
30 UefiCpuLib|Include/Library/UefiCpuLib.h\r
31\r
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32 ## @libraryclass Defines some routines that are used to register/manage/program\r
33 ## CPU features.\r
34 ##\r
245e98bf 35 RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r
548013c0 36\r
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37[LibraryClasses.IA32, LibraryClasses.X64]\r
38 ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
39 ##\r
40 MtrrLib|Include/Library/MtrrLib.h\r
41\r
42 ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r
43 ##\r
44 LocalApicLib|Include/Library/LocalApicLib.h\r
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45\r
46 ## @libraryclass Provides platform specific initialization functions in the SEC phase.\r
47 ##\r
48 PlatformSecLib|Include/Library/PlatformSecLib.h\r
529a5a86 49\r
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50 ## @libraryclass Public include file for the SMM CPU Platform Hook Library.\r
51 ##\r
52 SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h\r
529a5a86 53\r
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54 ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r
55 ##\r
56 SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r
57\r
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58 ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.\r
59 ##\r
60 MpInitLib|Include/Library/MpInitLib.h\r
61\r
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62[Guids]\r
63 gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
f7c11c53 64 gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
7798fb83 65\r
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66 ## Include/Guid/CpuFeaturesSetDone.h\r
67 gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
68\r
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69 ## Include/Guid/CpuFeaturesInitDone.h\r
70 gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
71\r
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72[Protocols]\r
73 ## Include/Protocol/SmmCpuService.h\r
74 gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
529a5a86 75\r
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76 ## Include/Protocol/SmMonitorInit.h\r
77 gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r
78\r
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79#\r
80# [Error.gUefiCpuPkgTokenSpaceGuid]\r
81# 0x80000001 | Invalid value provided.\r
82#\r
83\r
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84[PcdsFeatureFlag]\r
85 ## Indicates if SMM Profile will be enabled.\r
86 # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
1015fb3c 87 # It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).\r
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88 # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
89 # TRUE - SMM Profile will be enabled.<BR>\r
90 # FALSE - SMM Profile will be disabled.<BR>\r
91 # @Prompt Enable SMM Profile.\r
92 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109\r
93\r
94 ## Indicates if the SMM profile log buffer is a ring buffer.\r
95 # If disabled, no additional log can be done when the buffer is full.<BR><BR>\r
96 # TRUE - the SMM profile log buffer is a ring buffer.<BR>\r
97 # FALSE - the SMM profile log buffer is a normal buffer.<BR>\r
98 # @Prompt The SMM profile log buffer is a ring buffer.\r
99 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a\r
100\r
101 ## Indicates if SMM Startup AP in a blocking fashion.\r
102 # TRUE - SMM Startup AP in a blocking fashion.<BR>\r
103 # FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r
104 # @Prompt SMM Startup AP in a blocking fashion.\r
105 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r
106\r
107 ## Indicates if SMM Stack Guard will be enabled.\r
509f8425 108 # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r
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109 # TRUE - SMM Stack Guard will be enabled.<BR>\r
110 # FALSE - SMM Stack Guard will be disabled.<BR>\r
111 # @Prompt Enable SMM Stack Guard.\r
509f8425 112 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r
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113\r
114 ## Indicates if BSP election in SMM will be enabled.\r
115 # If enabled, a BSP will be dynamically elected among all processors in each SMI.\r
116 # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r
117 # TRUE - BSP election in SMM will be enabled.<BR>\r
118 # FALSE - BSP election in SMM will be disabled.<BR>\r
119 # @Prompt Enable BSP election in SMM.\r
120 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106\r
121\r
122 ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r
123 # TRUE - SMM CPU hot-plug will be enabled.<BR>\r
124 # FALSE - SMM CPU hot-plug will be disabled.<BR>\r
125 # @Prompt SMM CPU hot-plug.\r
126 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C\r
127\r
128 ## Indicates if SMM Debug will be enabled.\r
129 # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r
130 # TRUE - SMM Debug will be enabled.<BR>\r
131 # FALSE - SMM Debug will be disabled.<BR>\r
132 # @Prompt Enable SMM Debug.\r
133 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B\r
134\r
135 ## Indicates if lock SMM Feature Control MSR.<BR><BR>\r
136 # TRUE - SMM Feature Control MSR will be locked.<BR>\r
137 # FALSE - SMM Feature Control MSR will not be locked.<BR>\r
138 # @Prompt Lock SMM Feature Control MSR.\r
139 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
140\r
7798fb83 141[PcdsFixedAtBuild, PcdsPatchableInModule]\r
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142 ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
143 # @Prompt Configure base address of CPU Local APIC\r
abae030a 144 # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r
7798fb83 145 gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001\r
529a5a86 146\r
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147 ## Specifies delay value in microseconds after sending out an INIT IPI.\r
148 # @Prompt Configure delay value after send an INIT IPI\r
cf1eb6e6 149 gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r
529a5a86 150\r
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151 ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
152 ## aligns the address on a 4-KByte boundary.\r
153 # @Prompt Configure stack size for Application Processor (AP)\r
154 gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r
7798fb83 155\r
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156 ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r
157 # @Prompt Stack size in the temporary RAM.\r
158 gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r
159\r
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160 ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r
161 # @Prompt SMM profile data buffer size.\r
162 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r
163\r
164 ## Specifies stack size in bytes for each processor in SMM.\r
165 # @Prompt Processor stack size in SMM.\r
166 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
167\r
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168 ## Indicates if SMM Code Access Check is enabled.\r
169 # If enabled, the SMM handler cannot execute the code outside SMM regions.\r
170 # This PCD is suggested to TRUE in production image.<BR><BR>\r
171 # TRUE - SMM Code Access Check will be enabled.<BR>\r
172 # FALSE - SMM Code Access Check will be disabled.<BR>\r
173 # @Prompt SMM Code Access Check.\r
174 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r
175\r
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176 ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
177 # MTRRs reserved for OS use is 2.\r
178 # @Prompt Number of reserved variable MTRRs.\r
179 gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r
180\r
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181 ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r
182 # @Prompt STM exception stack size.\r
183 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r
184\r
185 ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r
186 # @Prompt MSEG size.\r
187 gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r
188\r
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189 ## Specifies the supported CPU features bit in array.\r
190 # @Prompt Supported CPU features.\r
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191 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r
192\r
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193 ## Specifies if CPU features will be initialized after SMM relocation.\r
194 # @Prompt If CPU features will be initialized after SMM relocation.\r
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195 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r
196\r
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197 ## Specifies if CPU features will be initialized during S3 resume.\r
198 # @Prompt If CPU features will be initialized during S3 resume.\r
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199 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
200\r
f79fcf45 201[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
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202 ## Specifies max supported number of Logical Processors.\r
203 # @Prompt Configure max supported number of Logical Processors\r
204 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
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205 ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
206 # @Prompt Timeout for the BSP to detect all APs for the first time.\r
207 gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
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208 ## Specifies the base address of the first microcode Patch in the microcode Region.\r
209 # @Prompt Microcode Region base address.\r
210 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
211 ## Specifies the size of the microcode Region.\r
212 # @Prompt Microcode Region size.\r
213 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
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214 ## Specifies the AP wait loop state during POST phase.\r
215 # The value is defined as below.<BR><BR>\r
216 # 1: Place AP in the Hlt-Loop state.<BR>\r
217 # 2: Place AP in the Mwait-Loop state.<BR>\r
218 # 3: Place AP in the Run-Loop state.<BR>\r
219 # @Prompt The AP wait loop state.\r
220 # @ValidRange 0x80000001 | 1 - 3\r
221 gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
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222 ## Specifies the AP target C-state for Mwait during POST phase.\r
223 # The default value 0 means C1 state.\r
224 # The value is defined as below.<BR><BR>\r
225 # @Prompt The specified AP target C-state for Mwait.\r
226 gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
f79fcf45 227\r
28b020b5 228 ## Indicates if SMM uses static page table.\r
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229 # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.\r
230 # This flag only impacts X64 build, because SMM always builds static page table for IA32.\r
231 # It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
232 # It could not be enabled also at the same time with heap guard feature for SMM\r
233 # (PcdHeapGuardPropertyMask in MdeModulePkg).<BR><BR>\r
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234 # TRUE - SMM uses static page table for all memory.<BR>\r
235 # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.<BR>\r
236 # @Prompt Use static page table for all memory in SMM.\r
237 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D\r
238\r
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239 ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
240 # @Prompt AP synchronization timeout value in SMM.\r
241 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
242\r
243 ## Indicates the CPU synchronization method used when processing an SMI.\r
244 # 0x00 - Traditional CPU synchronization method.<BR>\r
245 # 0x01 - Relaxed CPU synchronization method.<BR>\r
246 # @Prompt SMM CPU Synchronization Method.\r
247 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
248\r
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249 ## Specifies user's desired settings for enabling/disabling processor features.\r
250 # @Prompt User settings for enabling/disabling processor features.\r
251 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesUserConfiguration|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000017\r
252\r
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253 ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
254 # @Prompt The encoded values for target duty cycle modulation.\r
255 # @ValidRange 0x80000001 | 0 - 15\r
256 gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r
257\r
258 ## Indicates if the current boot is a power-on reset.<BR><BR>\r
259 # TRUE - Current boot is a power-on reset.<BR>\r
260 # FALSE - Current boot is not a power-on reset.<BR>\r
261 # @Prompt Current boot is a power-on reset.\r
262 gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
263\r
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264[PcdsDynamic, PcdsDynamicEx]\r
265 ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
266 # @Prompt The pointer to a CPU S3 data buffer.\r
267 # @ValidList 0x80000001 | 0\r
268 gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r
269\r
270 ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r
271 # @Prompt The pointer to CPU Hot Plug Data.\r
272 # @ValidList 0x80000001 | 0\r
273 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r
274\r
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275 ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r
276 # @Prompt Processor feature capabilities.\r
277 # @ValidList 0x80000001 | 0\r
278 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r
279\r
280 ## Specifies actual settings for processor features, each bit corresponding to a specific feature.\r
281 # @Prompt Actual processor feature settings.\r
282 # @ValidList 0x80000001 | 0\r
283 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
284\r
234d4c5f 285 ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
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286 # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
287 # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
288 # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
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289 # 0x0 - 4K.<BR>\r
290 # 0x1 - 8K.<BR>\r
291 # 0x2 - 16K.<BR>\r
292 # 0x3 - 32K.<BR>\r
293 # 0x4 - 64K.<BR>\r
294 # 0x5 - 128K.<BR>\r
295 # 0x6 - 256K.<BR>\r
296 # 0x7 - 512K.<BR>\r
297 # 0x8 - 1M.<BR>\r
298 # 0x9 - 2M.<BR>\r
299 # 0xA - 4M.<BR>\r
300 # 0xB - 8M.<BR>\r
301 # 0xC - 16M.<BR>\r
302 # 0xD - 32M.<BR>\r
303 # 0xE - 64M.<BR>\r
304 # 0xF - 128M.<BR>\r
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305 # @Prompt The memory size used for processor trace if processor trace is enabled.\r
306 # @ValidRange 0x80000001 | 0 - 0xF\r
307 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r
c7399a0c 308\r
234d4c5f 309 ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
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310 # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
311 # This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
312 # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
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313 # 0 - Single Range output scheme.<BR>\r
314 # 1 - ToPA(Table of physical address) scheme.<BR>\r
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315 # @Prompt The processor trace output scheme used when processor trace is enabled.\r
316 # @ValidRange 0x80000001 | 0 - 1\r
317 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
c7399a0c 318\r
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319[UserExtensions.TianoCore."ExtraFiles"]\r
320 UefiCpuPkgExtra.uni\r