ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
   6 #
   7 #    SPDX-License-Identifier: BSD-2-Clause-Patent
   8 #
   9 #**/
  10
  11 [Defines]
  12   DEC_SPECIFICATION              = 0x00010005
  13   PACKAGE_NAME                   = ArmPkg
  14   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  15   PACKAGE_VERSION                = 0.1
  16
  17 ################################################################################
  18 #
  19 # Include Section - list of Include Paths that are provided by this package.
  20 #                   Comments are used for Keywords and Module Types.
  21 #
  22 # Supported Module Types:
  23 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  24 #
  25 ################################################################################
  26 [Includes.common]
  27   Include                        # Root include for the package
  28
  29 [LibraryClasses.common]
  30   ArmLib|Include/Library/ArmLib.h
  31   ArmMmuLib|Include/Library/ArmMmuLib.h
  32   SemihostLib|Include/Library/Semihosting.h
  33   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  34   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  35   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  36   ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
  37   ArmSvcLib|Include/Library/ArmSvcLib.h
  38   OpteeLib|Include/Library/OpteeLib.h
  39   StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  40
  41 [Guids.common]
  42   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  43
  44   ## ARM MPCore table
  45   # Include/Guid/ArmMpCoreInfo.h
  46   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
  47
  48 [Protocols.common]
  49   ## Arm System Control and Management Interface(SCMI) Base protocol
  50   ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
  51   gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
  52
  53   ## Arm System Control and Management Interface(SCMI) Clock management protocol
  54   ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
  55   gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
  56   gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
  57
  58   ## Arm System Control and Management Interface(SCMI) Clock management protocol
  59   ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
  60   gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
  61
  62 [Ppis]
  63   ## Include/Ppi/ArmMpCoreInfo.h
  64   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
  65
  66 [PcdsFeatureFlag.common]
  67   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
  68
  69   # On ARM Architecture with the Security Extension, the address for the
  70   # Vector Table can be mapped anywhere in the memory map. It means we can
  71   # point the Exception Vector Table to its location in CpuDxe.
  72   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
  73   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
  74   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
  75   # it has been configured by the CPU DXE
  76   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
  77
  78   # Define if the GICv3 controller should use the GICv2 legacy
  79   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
  80
  81 [PcdsFeatureFlag.ARM]
  82   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
  83   # TRUE may be appropriate to fix performance problems if you don't care about
  84   # hardware coherency (i.e., no virtualization or cache coherent DMA)
  85   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
  86
  87 [PcdsFixedAtBuild.common]
  88   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
  89
  90   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
  91   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
  92   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
  93
  94   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
  95   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
  96
  97   #
  98   # ARM Secure Firmware PCDs
  99   #
 100   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
 101   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
 102   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
 103   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 104
 105   #
 106   # ARM Hypervisor Firmware PCDs
 107   #
 108   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 109   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 110   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 111   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 112
 113   # Use ClusterId + CoreId to identify the PrimaryCore
 114   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 115   # The Primary Core is ClusterId[0] & CoreId[0]
 116   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 117
 118   #
 119   # SMBIOS PCDs
 120   #
 121   gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
 122   gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
 123   gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
 124   gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
 125   gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
 126   gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
 127   gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
 128   gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
 129   gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
 130   gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
 131
 132   #
 133   # ARM L2x0 PCDs
 134   #
 135   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 136
 137   #
 138   # ARM Normal (or Non Secure) Firmware PCDs
 139   #
 140   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 141   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 142
 143   #
 144   # Value to add to a host address to obtain a device address, using
 145   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 146   # means we can rely on truncation on overflow to specify negative
 147   # offsets.
 148   #
 149   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 150
 151 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 152   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 153   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 154
 155 [PcdsFixedAtBuild.ARM]
 156   #
 157   # ARM Security Extension
 158   #
 159
 160   # Secure Configuration Register
 161   # - BIT0 : NS - Non Secure bit
 162   # - BIT1 : IRQ Handler
 163   # - BIT2 : FIQ Handler
 164   # - BIT3 : EA - External Abort
 165   # - BIT4 : FW - F bit writable
 166   # - BIT5 : AW - A bit writable
 167   # - BIT6 : nET - Not Early Termination
 168   # - BIT7 : SCD - Secure Monitor Call Disable
 169   # - BIT8 : HCE - Hyp Call enable
 170   # - BIT9 : SIF - Secure Instruction Fetch
 171   # 0x31 = NS | EA | FW
 172   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 173
 174   # By default we do not do a transition to non-secure mode
 175   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 176
 177   # Non Secure Access Control Register
 178   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 179   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 180   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 181   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 182   # 0xC00 = cp10 | cp11
 183   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 184
 185 [PcdsFixedAtBuild.AARCH64]
 186   #
 187   # AArch64 Security Extension
 188   #
 189
 190   # Secure Configuration Register
 191   # - BIT0 : NS - Non Secure bit
 192   # - BIT1 : IRQ Handler
 193   # - BIT2 : FIQ Handler
 194   # - BIT3 : EA - External Abort
 195   # - BIT4 : FW - F bit writable
 196   # - BIT5 : AW - A bit writable
 197   # - BIT6 : nET - Not Early Termination
 198   # - BIT7 : SCD - Secure Monitor Call Disable
 199   # - BIT8 : HCE - Hyp Call enable
 200   # - BIT9 : SIF - Secure Instruction Fetch
 201   # - BIT10: RW -  Register width control for lower exception levels
 202   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 203   # - BIT12: TWI - Trap WFI
 204   # - BIT13: TWE - Trap WFE
 205   # 0x501 = NS | HCE | RW
 206   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 207
 208   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 209   #        Mode Description              Bits
 210   # NS EL2 SP2 all interrupts disabled =  0x3c9
 211   # NS EL1 SP1 all interrupts disabled =  0x3c5
 212   # Other modes include using SP0 or switching to Aarch32, but these are
 213   # not currently supported.
 214   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 215
 216
 217 #
 218 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 219 # redefined when using UEFI in a context of virtual machine.
 220 #
 221 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 222
 223   # System Memory (DRAM): These PCDs define the region of in-built system memory
 224   # Some platforms can get DRAM extensions, these additional regions may be
 225   # declared to UEFI using separate resource descriptor HOBs
 226   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 227   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 228
 229   gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
 230   gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
 231
 232   gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
 233   gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
 234
 235 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 236   #
 237   # ARM Architectural Timer
 238   #
 239   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 240
 241   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 242   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 243   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 244   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 245   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 246
 247   #
 248   # ARM Generic Watchdog
 249   #
 250
 251   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 252   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 253   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 254
 255   #
 256   # ARM Generic Interrupt Controller
 257   #
 258   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 259   # Base address for the GIC Redistributor region that contains the boot CPU
 260   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 261   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 262   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 263
 264   #
 265   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 266   # Note that "IO" is just another MMIO range that simulates IO space; there
 267   # are no special instructions to access it.
 268   #
 269   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 270   # specific to their containing address spaces. In order to get the physical
 271   # address for the CPU, for a given access, the respective translation value
 272   # has to be added.
 273   #
 274   # The translations always have to be initialized like this, using UINT64:
 275   #
 276   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 277   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 278   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 279   #
 280   #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
 281   #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 282   #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 283   #
 284   # because (a) the target address space (ie. the cpu-physical space) is
 285   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 286   # arithmetic.
 287   #
 288   # Accordingly, the translation itself needs to be implemented as:
 289   #
 290   #   UINT64 UntranslatedIoAddress;     // input parameter
 291   #   UINT32 UntranslatedMmio32Address; // input parameter
 292   #   UINT64 UntranslatedMmio64Address; // input parameter
 293   #
 294   #   UINT64 TranslatedIoAddress;       // output parameter
 295   #   UINT64 TranslatedMmio32Address;   // output parameter
 296   #   UINT64 TranslatedMmio64Address;   // output parameter
 297   #
 298   #   TranslatedIoAddress     = UntranslatedIoAddress +
 299   #                             PcdPciIoTranslation;
 300   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 301   #                             PcdPciMmio32Translation;
 302   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 303   #                             PcdPciMmio64Translation;
 304   #
 305   #  The modular arithmetic performed in UINT64 ensures that the translation
 306   #  works correctly regardless of the relation between IoCpuBase and
 307   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 308   #  PcdPciMmio64Base.
 309   #
 310   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 311   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 312   gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052
 313   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 314   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 315   gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055
 316   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 317   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 318   gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058
 319
 320   #
 321   # Inclusive range of allowed PCI buses.
 322   #
 323   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 324   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A