projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 8bbf0f09 A |
1 | #/** @file\r |
| 2 | # ARM processor package.\r | |
| 3 | #\r | |
| d6ebcab7 | 4 | # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r |
| 38a00bae | 5 | # Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.\r |
| 8bbf0f09 | 6 | #\r |
| 4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 8bbf0f09 A |
8 | #\r |
| 9 | #**/\r | |
| 10 | \r | |
| 2ef2b01e A |
11 | [Defines]\r |
| 12 | DEC_SPECIFICATION = 0x00010005\r | |
| 13 | PACKAGE_NAME = ArmPkg\r | |
| 14 | PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r | |
| 15 | PACKAGE_VERSION = 0.1\r | |
| 16 | \r | |
| 17 | ################################################################################\r | |
| 18 | #\r | |
| 19 | # Include Section - list of Include Paths that are provided by this package.\r | |
| 20 | # Comments are used for Keywords and Module Types.\r | |
| 21 | #\r | |
| 22 | # Supported Module Types:\r | |
| 23 | # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r | |
| 24 | #\r | |
| 25 | ################################################################################\r | |
| 26 | [Includes.common]\r | |
| 27 | Include # Root include for the package\r | |
| 28 | \r | |
| 29 | [LibraryClasses.common]\r | |
| 8bbf0f09 | 30 | ArmLib|Include/Library/ArmLib.h\r |
| 12728e11 | 31 | ArmMmuLib|Include/Library/ArmMmuLib.h\r |
| 2ef2b01e | 32 | SemihostLib|Include/Library/Semihosting.h\r |
| 11c20f4e | 33 | DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r |
| 097bd461 | 34 | ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r |
| 8d13298b | 35 | ArmGicArchLib|Include/Library/ArmGicArchLib.h\r |
| 38a00bae | 36 | ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h\r |
| 4d163696 | 37 | ArmSvcLib|Include/Library/ArmSvcLib.h\r |
| d65b78f1 | 38 | OpteeLib|Include/Library/OpteeLib.h\r |
| eed947be | 39 | StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r |
| c32aaba9 | 40 | \r |
| 2ef2b01e A |
41 | [Guids.common]\r |
| 42 | gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r | |
| 43 | \r | |
| 44788bae | 44 | ## ARM MPCore table\r |
| 45 | # Include/Guid/ArmMpCoreInfo.h\r | |
| 46 | gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r | |
| 47 | \r | |
| 4f2494cf GP |
48 | [Protocols.common]\r |
| 49 | ## Arm System Control and Management Interface(SCMI) Base protocol\r | |
| 50 | ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r | |
| 51 | gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r | |
| 52 | \r | |
| 53 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r | |
| 54 | ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r | |
| 55 | gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r | |
| 559a07d8 | 56 | gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r |
| 4f2494cf GP |
57 | \r |
| 58 | ## Arm System Control and Management Interface(SCMI) Clock management protocol\r | |
| 59 | ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r | |
| 60 | gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r | |
| 61 | \r | |
| 44788bae | 62 | [Ppis]\r |
| 63 | ## Include/Ppi/ArmMpCoreInfo.h\r | |
| 64 | gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r | |
| 65 | \r | |
| 2ef2b01e A |
66 | [PcdsFeatureFlag.common]\r |
| 67 | gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r | |
| 68 | \r | |
| 1bfda055 | 69 | # On ARM Architecture with the Security Extension, the address for the\r |
| 70 | # Vector Table can be mapped anywhere in the memory map. It means we can\r | |
| 71 | # point the Exception Vector Table to its location in CpuDxe.\r | |
| f0bbcdf8 | 72 | # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)\r |
| 1bfda055 | 73 | gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022\r |
| eeec69c5 | 74 | # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before\r |
| 75 | # it has been configured by the CPU DXE\r | |
| 76 | gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r | |
| c32aaba9 | 77 | \r |
| f6d46e29 AB |
78 | # Define if the GICv3 controller should use the GICv2 legacy\r |
| 79 | gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r | |
| 80 | \r | |
| 65ceda91 AB |
81 | [PcdsFeatureFlag.ARM]\r |
| 82 | # Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r | |
| 83 | # TRUE may be appropriate to fix performance problems if you don't care about\r | |
| 84 | # hardware coherency (i.e., no virtualization or cache coherent DMA)\r | |
| 85 | gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043\r | |
| 86 | \r | |
| 2ef2b01e | 87 | [PcdsFixedAtBuild.common]\r |
| 12c5ae23 | 88 | gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006\r |
| 89 | \r | |
| 1bfda055 | 90 | # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.\r |
| 91 | # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r | |
| 92 | gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r | |
| 93 | \r | |
| f0bbcdf8 | 94 | gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r |
| 2ef2b01e | 95 | gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r |
| c32aaba9 | 96 | \r |
| 1bfda055 | 97 | #\r |
| 262a9b04 | 98 | # ARM Secure Firmware PCDs\r |
| 1bfda055 | 99 | #\r |
| bb5420bb | 100 | gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015\r |
| 1bfda055 | 101 | gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016\r |
| bb5420bb | 102 | gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F\r |
| 1ad14bc8 | 103 | gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030\r |
| 1bfda055 | 104 | \r |
| 7245b435 | 105 | #\r |
| 106 | # ARM Hypervisor Firmware PCDs\r | |
| c32aaba9 | 107 | #\r |
| 7245b435 | 108 | gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A\r |
| 109 | gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r | |
| 110 | gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r | |
| 111 | gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r | |
| d6dc67ba | 112 | \r |
| 0787bc61 | 113 | # Use ClusterId + CoreId to identify the PrimaryCore\r |
| 114 | gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r | |
| c32aaba9 | 115 | # The Primary Core is ClusterId[0] & CoreId[0]\r |
| 0787bc61 | 116 | gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037\r |
| 117 | \r | |
| 660d4faa RC |
118 | #\r |
| 119 | # SMBIOS PCDs\r | |
| 120 | #\r | |
| 121 | gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053\r | |
| 122 | gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054\r | |
| 123 | gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055\r | |
| 124 | gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056\r | |
| 125 | gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057\r | |
| 126 | gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071\r | |
| 127 | gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072\r | |
| 128 | gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073\r | |
| 129 | gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074\r | |
| 130 | gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075\r | |
| 131 | \r | |
| 1bfda055 | 132 | #\r |
| 133 | # ARM L2x0 PCDs\r | |
| 134 | #\r | |
| 135 | gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r | |
| c32aaba9 | 136 | \r |
| 523b5266 AB |
137 | #\r |
| 138 | # ARM Normal (or Non Secure) Firmware PCDs\r | |
| 139 | #\r | |
| 140 | gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r | |
| 141 | gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r | |
| 142 | \r | |
| bfe34275 AB |
143 | #\r |
| 144 | # Value to add to a host address to obtain a device address, using\r | |
| 145 | # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r | |
| 146 | # means we can rely on truncation on overflow to specify negative\r | |
| 147 | # offsets.\r | |
| 148 | #\r | |
| 149 | gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r | |
| 150 | \r | |
| 523b5266 AB |
151 | [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r |
| 152 | gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r | |
| 153 | gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r | |
| 387653a4 | 154 | \r |
| 155 | [PcdsFixedAtBuild.ARM]\r | |
| cc935544 OM |
156 | #\r |
| 157 | # ARM Security Extension\r | |
| 158 | #\r | |
| 159 | \r | |
| 160 | # Secure Configuration Register\r | |
| 161 | # - BIT0 : NS - Non Secure bit\r | |
| 162 | # - BIT1 : IRQ Handler\r | |
| 163 | # - BIT2 : FIQ Handler\r | |
| 164 | # - BIT3 : EA - External Abort\r | |
| 165 | # - BIT4 : FW - F bit writable\r | |
| 166 | # - BIT5 : AW - A bit writable\r | |
| 167 | # - BIT6 : nET - Not Early Termination\r | |
| 168 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
| 169 | # - BIT8 : HCE - Hyp Call enable\r | |
| 170 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
| 171 | # 0x31 = NS | EA | FW\r | |
| 172 | gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r | |
| 173 | \r | |
| 387653a4 | 174 | # By default we do not do a transition to non-secure mode\r |
| 175 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r | |
| 2425e1d4 | 176 | \r |
| d6dc67ba OM |
177 | # Non Secure Access Control Register\r |
| 178 | # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r | |
| 179 | # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r | |
| 180 | # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable\r | |
| 181 | # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable\r | |
| 182 | # 0xC00 = cp10 | cp11\r | |
| 183 | gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r | |
| 184 | \r | |
| 25402f5d | 185 | [PcdsFixedAtBuild.AARCH64]\r |
| cc935544 OM |
186 | #\r |
| 187 | # AArch64 Security Extension\r | |
| 188 | #\r | |
| 189 | \r | |
| 190 | # Secure Configuration Register\r | |
| 191 | # - BIT0 : NS - Non Secure bit\r | |
| 192 | # - BIT1 : IRQ Handler\r | |
| 193 | # - BIT2 : FIQ Handler\r | |
| 194 | # - BIT3 : EA - External Abort\r | |
| 195 | # - BIT4 : FW - F bit writable\r | |
| 196 | # - BIT5 : AW - A bit writable\r | |
| 197 | # - BIT6 : nET - Not Early Termination\r | |
| 198 | # - BIT7 : SCD - Secure Monitor Call Disable\r | |
| 199 | # - BIT8 : HCE - Hyp Call enable\r | |
| 200 | # - BIT9 : SIF - Secure Instruction Fetch\r | |
| 201 | # - BIT10: RW - Register width control for lower exception levels\r | |
| 202 | # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r | |
| 203 | # - BIT12: TWI - Trap WFI\r | |
| 204 | # - BIT13: TWE - Trap WFE\r | |
| 205 | # 0x501 = NS | HCE | RW\r | |
| 206 | gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r | |
| 207 | \r | |
| 25402f5d HL |
208 | # By default we do transition to EL2 non-secure mode with Stack for EL2.\r |
| 209 | # Mode Description Bits\r | |
| c32aaba9 OM |
210 | # NS EL2 SP2 all interrupts disabled = 0x3c9\r |
| 211 | # NS EL1 SP1 all interrupts disabled = 0x3c5\r | |
| 25402f5d HL |
212 | # Other modes include using SP0 or switching to Aarch32, but these are\r |
| 213 | # not currently supported.\r | |
| 214 | gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r | |
| e1e2e66c AB |
215 | \r |
| 216 | \r | |
| dc63be24 | 217 | #\r |
| 523b5266 AB |
218 | # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r |
| 219 | # redefined when using UEFI in a context of virtual machine.\r | |
| dc63be24 | 220 | #\r |
| 523b5266 AB |
221 | [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r |
| 222 | \r | |
| f8d7d6e1 | 223 | # System Memory (DRAM): These PCDs define the region of in-built system memory\r |
| 142fa386 AB |
224 | # Some platforms can get DRAM extensions, these additional regions may be\r |
| 225 | # declared to UEFI using separate resource descriptor HOBs\r | |
| f8d7d6e1 AB |
226 | gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r |
| 227 | gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r | |
| 228 | \r | |
| 767febf8 AG |
229 | gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r |
| 230 | gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r | |
| 231 | \r | |
| 660d4faa RC |
232 | gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058\r |
| 233 | gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059\r | |
| 234 | \r | |
| 523b5266 | 235 | [PcdsFixedAtBuild.common, PcdsDynamic.common]\r |
| e1e2e66c AB |
236 | #\r |
| 237 | # ARM Architectural Timer\r | |
| 238 | #\r | |
| 239 | gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034\r | |
| 240 | \r | |
| 241 | # ARM Architectural Timer Interrupt(GIC PPI) numbers\r | |
| 242 | gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035\r | |
| 243 | gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r | |
| 244 | gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r | |
| 245 | gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r | |
| dc63be24 | 246 | \r |
| 0b4d97a0 RC |
247 | #\r |
| 248 | # ARM Generic Watchdog\r | |
| 249 | #\r | |
| 250 | \r | |
| 7c609a14 A |
251 | gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r |
| 252 | gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r | |
| 0b4d97a0 RC |
253 | gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r |
| 254 | \r | |
| dc63be24 AB |
255 | #\r |
| 256 | # ARM Generic Interrupt Controller\r | |
| 257 | #\r | |
| 8a1f2378 | 258 | gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r |
| 919697ae | 259 | # Base address for the GIC Redistributor region that contains the boot CPU\r |
| 8a1f2378 DC |
260 | gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r |
| 261 | gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r | |
| dc63be24 | 262 | gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r |
| d7c06eb0 AB |
263 | \r |
| 264 | #\r | |
| 265 | # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r | |
| 266 | # Note that "IO" is just another MMIO range that simulates IO space; there\r | |
| 267 | # are no special instructions to access it.\r | |
| 268 | #\r | |
| 269 | # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r | |
| 270 | # specific to their containing address spaces. In order to get the physical\r | |
| 271 | # address for the CPU, for a given access, the respective translation value\r | |
| 272 | # has to be added.\r | |
| 273 | #\r | |
| 274 | # The translations always have to be initialized like this, using UINT64:\r | |
| 275 | #\r | |
| 276 | # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 277 | # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 278 | # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r | |
| 279 | #\r | |
| 280 | # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r | |
| 281 | # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r | |
| 282 | # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r | |
| 283 | #\r | |
| 284 | # because (a) the target address space (ie. the cpu-physical space) is\r | |
| 285 | # 64-bit, and (b) the translation values are meant as offsets for *modular*\r | |
| 286 | # arithmetic.\r | |
| 287 | #\r | |
| 288 | # Accordingly, the translation itself needs to be implemented as:\r | |
| 289 | #\r | |
| 290 | # UINT64 UntranslatedIoAddress; // input parameter\r | |
| 291 | # UINT32 UntranslatedMmio32Address; // input parameter\r | |
| 292 | # UINT64 UntranslatedMmio64Address; // input parameter\r | |
| 293 | #\r | |
| 294 | # UINT64 TranslatedIoAddress; // output parameter\r | |
| 295 | # UINT64 TranslatedMmio32Address; // output parameter\r | |
| 296 | # UINT64 TranslatedMmio64Address; // output parameter\r | |
| 297 | #\r | |
| 298 | # TranslatedIoAddress = UntranslatedIoAddress +\r | |
| 299 | # PcdPciIoTranslation;\r | |
| 300 | # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r | |
| 301 | # PcdPciMmio32Translation;\r | |
| 302 | # TranslatedMmio64Address = UntranslatedMmio64Address +\r | |
| 303 | # PcdPciMmio64Translation;\r | |
| 304 | #\r | |
| 305 | # The modular arithmetic performed in UINT64 ensures that the translation\r | |
| 306 | # works correctly regardless of the relation between IoCpuBase and\r | |
| 307 | # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r | |
| 308 | # PcdPciMmio64Base.\r | |
| 309 | #\r | |
| 310 | gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r | |
| 311 | gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r | |
| 312 | gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r | |
| 313 | gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r | |
| 314 | gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r | |
| 315 | gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r | |
| 316 | gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r | |
| 317 | gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r | |
| 318 | gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r | |
| 319 | \r | |
| 320 | #\r | |
| 321 | # Inclusive range of allowed PCI buses.\r | |
| 322 | #\r | |
| 323 | gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r | |
| 324 | gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r |