ArmPkg/ArmPkg.dec

   1 #/** @file
   2 # ARM processor package.
   3 #
   4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
   5 # Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
   6 #
   7 #    SPDX-License-Identifier: BSD-2-Clause-Patent
   8 #
   9 #**/
  10
  11 [Defines]
  12   DEC_SPECIFICATION              = 0x00010005
  13   PACKAGE_NAME                   = ArmPkg
  14   PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
  15   PACKAGE_VERSION                = 0.1
  16
  17 ################################################################################
  18 #
  19 # Include Section - list of Include Paths that are provided by this package.
  20 #                   Comments are used for Keywords and Module Types.
  21 #
  22 # Supported Module Types:
  23 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  24 #
  25 ################################################################################
  26 [Includes.common]
  27   Include                        # Root include for the package
  28
  29 [LibraryClasses.common]
  30   ##  @libraryclass  Convert Arm instructions to a human readable format.
  31   #
  32   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
  33
  34   ##  @libraryclass  Provides an interface to Arm generic counters.
  35   #
  36   ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
  37
  38   ##  @libraryclass  Provides an interface to initialize a
  39   #   Generic Interrupt Controller (GIC).
  40   #
  41   ArmGicArchLib|Include/Library/ArmGicArchLib.h
  42
  43   ##  @libraryclass  Provides a Generic Interrupt Controller (GIC)
  44   #   configuration interface.
  45   #
  46   ArmGicLib|Include/Library/ArmGicLib.h
  47
  48   ##  @libraryclass  Provides a HyperVisor Call (HVC) interface.
  49   #
  50   ArmHvcLib|Include/Library/ArmHvcLib.h
  51
  52   ##  @libraryclass  Provides an interface to Arm registers.
  53   #
  54   ArmLib|Include/Library/ArmLib.h
  55
  56   ##  @libraryclass  Provides a Mmu interface.
  57   #
  58   ArmMmuLib|Include/Library/ArmMmuLib.h
  59
  60   ##  @libraryclass  Provides a Mailbox Transport Layer (MTL) interface
  61   #   for the System Control and Management Interface (SCMI).
  62   #
  63   ArmMtlLib|Include/Library/ArmMtlLib.h
  64
  65   ##  @libraryclass  Provides a System Monitor Call (SMC) interface.
  66   #
  67   ArmSmcLib|Include/Library/ArmSmcLib.h
  68
  69   ##  @libraryclass  Provides a SuperVisor Call (SVC) interface.
  70   #
  71   ArmSvcLib|Include/Library/ArmSvcLib.h
  72
  73   ##  @libraryclass  Provides a default exception handler.
  74   #
  75   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
  76
  77   ##  @libraryclass  Provides an interface to query miscellaneous OEM
  78   #   information.
  79   #
  80   OemMiscLib|Include/Library/OemMiscLib.h
  81
  82   ##  @libraryclass  Provides an OpTee interface.
  83   #
  84   OpteeLib|Include/Library/OpteeLib.h
  85
  86   ##  @libraryclass  Provides a semihosting interface.
  87   #
  88   SemihostLib|Include/Library/SemihostLib.h
  89
  90   ##  @libraryclass  Provides an interface for a StandaloneMm Mmu.
  91   #
  92   StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
  93
  94 [Guids.common]
  95   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
  96
  97   ## ARM MPCore table
  98   # Include/Guid/ArmMpCoreInfo.h
  99   gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5,  {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
 100
 101 [Protocols.common]
 102   ## Arm System Control and Management Interface(SCMI) Base protocol
 103   ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
 104   gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
 105
 106   ## Arm System Control and Management Interface(SCMI) Clock management protocol
 107   ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
 108   gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
 109   gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
 110
 111   ## Arm System Control and Management Interface(SCMI) Clock management protocol
 112   ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
 113   gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
 114
 115 [Ppis]
 116   ## Include/Ppi/ArmMpCoreInfo.h
 117   gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
 118
 119 [PcdsFeatureFlag.common]
 120   gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
 121
 122   # On ARM Architecture with the Security Extension, the address for the
 123   # Vector Table can be mapped anywhere in the memory map. It means we can
 124   # point the Exception Vector Table to its location in CpuDxe.
 125   # By default we copy the Vector Table at  PcdGet64(PcdCpuVectorBaseAddress)
 126   gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
 127   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
 128   # it has been configured by the CPU DXE
 129   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
 130
 131   # Define if the GICv3 controller should use the GICv2 legacy
 132   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
 133
 134 [PcdsFeatureFlag.ARM]
 135   # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
 136   # TRUE may be appropriate to fix performance problems if you don't care about
 137   # hardware coherency (i.e., no virtualization or cache coherent DMA)
 138   gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
 139
 140 [PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
 141   ## Used to select method for requesting services from S-EL1.<BR><BR>
 142   #   TRUE  - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
 143   #   FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
 144   # @Prompt Enable FF-A support.
 145   gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
 146
 147 [PcdsFixedAtBuild.common]
 148   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 149
 150   # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file.
 151   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
 152   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
 153
 154   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
 155   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
 156
 157   #
 158   # ARM Secure Firmware PCDs
 159   #
 160   gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
 161   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
 162   gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
 163   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 164
 165   #
 166   # ARM Hypervisor Firmware PCDs
 167   #
 168   gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
 169   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
 170   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
 171   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
 172
 173   # Use ClusterId + CoreId to identify the PrimaryCore
 174   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
 175   # The Primary Core is ClusterId[0] & CoreId[0]
 176   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
 177
 178   #
 179   # SMBIOS PCDs
 180   #
 181   gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
 182   gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
 183   gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
 184   gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
 185   gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
 186   gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
 187   gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
 188   gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
 189   gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
 190   gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
 191
 192   #
 193   # ARM L2x0 PCDs
 194   #
 195   gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
 196
 197   #
 198   # ARM Normal (or Non Secure) Firmware PCDs
 199   #
 200   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
 201   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
 202
 203   #
 204   # Value to add to a host address to obtain a device address, using
 205   # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
 206   # means we can rely on truncation on overflow to specify negative
 207   # offsets.
 208   #
 209   gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
 210
 211 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
 212   gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
 213   gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
 214
 215 [PcdsFixedAtBuild.ARM]
 216   #
 217   # ARM Security Extension
 218   #
 219
 220   # Secure Configuration Register
 221   # - BIT0 : NS - Non Secure bit
 222   # - BIT1 : IRQ Handler
 223   # - BIT2 : FIQ Handler
 224   # - BIT3 : EA - External Abort
 225   # - BIT4 : FW - F bit writable
 226   # - BIT5 : AW - A bit writable
 227   # - BIT6 : nET - Not Early Termination
 228   # - BIT7 : SCD - Secure Monitor Call Disable
 229   # - BIT8 : HCE - Hyp Call enable
 230   # - BIT9 : SIF - Secure Instruction Fetch
 231   # 0x31 = NS | EA | FW
 232   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
 233
 234   # By default we do not do a transition to non-secure mode
 235   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 236
 237   # Non Secure Access Control Register
 238   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
 239   # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
 240   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
 241   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
 242   # 0xC00 = cp10 | cp11
 243   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
 244
 245 [PcdsFixedAtBuild.AARCH64]
 246   #
 247   # AArch64 Security Extension
 248   #
 249
 250   # Secure Configuration Register
 251   # - BIT0 : NS - Non Secure bit
 252   # - BIT1 : IRQ Handler
 253   # - BIT2 : FIQ Handler
 254   # - BIT3 : EA - External Abort
 255   # - BIT4 : FW - F bit writable
 256   # - BIT5 : AW - A bit writable
 257   # - BIT6 : nET - Not Early Termination
 258   # - BIT7 : SCD - Secure Monitor Call Disable
 259   # - BIT8 : HCE - Hyp Call enable
 260   # - BIT9 : SIF - Secure Instruction Fetch
 261   # - BIT10: RW -  Register width control for lower exception levels
 262   # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
 263   # - BIT12: TWI - Trap WFI
 264   # - BIT13: TWE - Trap WFE
 265   # 0x501 = NS | HCE | RW
 266   gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
 267
 268   # By default we do transition to EL2 non-secure mode with Stack for EL2.
 269   #        Mode Description              Bits
 270   # NS EL2 SP2 all interrupts disabled =  0x3c9
 271   # NS EL1 SP1 all interrupts disabled =  0x3c5
 272   # Other modes include using SP0 or switching to Aarch32, but these are
 273   # not currently supported.
 274   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
 275
 276
 277 #
 278 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
 279 # redefined when using UEFI in a context of virtual machine.
 280 #
 281 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 282
 283   # System Memory (DRAM): These PCDs define the region of in-built system memory
 284   # Some platforms can get DRAM extensions, these additional regions may be
 285   # declared to UEFI using separate resource descriptor HOBs
 286   gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
 287   gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 288
 289   gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
 290   gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
 291
 292   gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
 293   gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
 294
 295 [PcdsFixedAtBuild.common, PcdsDynamic.common]
 296   #
 297   # ARM Architectural Timer
 298   #
 299   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
 300
 301   # ARM Architectural Timer Interrupt(GIC PPI) numbers
 302   gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
 303   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 304   gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
 305   gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
 306
 307   #
 308   # ARM Generic Watchdog
 309   #
 310
 311   gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
 312   gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
 313   gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 314
 315   #
 316   # ARM Generic Interrupt Controller
 317   #
 318   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
 319   # Base address for the GIC Redistributor region that contains the boot CPU
 320   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
 321   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
 322   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
 323
 324   #
 325   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 326   # Note that "IO" is just another MMIO range that simulates IO space; there
 327   # are no special instructions to access it.
 328   #
 329   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 330   # specific to their containing address spaces. In order to get the physical
 331   # address for the CPU, for a given access, the respective translation value
 332   # has to be added.
 333   #
 334   # The translations always have to be initialized like this, using UINT64:
 335   #
 336   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 337   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 338   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 339   #
 340   #   gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
 341   #   gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 342   #   gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 343   #
 344   # because (a) the target address space (ie. the cpu-physical space) is
 345   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 346   # arithmetic.
 347   #
 348   # Accordingly, the translation itself needs to be implemented as:
 349   #
 350   #   UINT64 UntranslatedIoAddress;     // input parameter
 351   #   UINT32 UntranslatedMmio32Address; // input parameter
 352   #   UINT64 UntranslatedMmio64Address; // input parameter
 353   #
 354   #   UINT64 TranslatedIoAddress;       // output parameter
 355   #   UINT64 TranslatedMmio32Address;   // output parameter
 356   #   UINT64 TranslatedMmio64Address;   // output parameter
 357   #
 358   #   TranslatedIoAddress     = UntranslatedIoAddress +
 359   #                             gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
 360   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 361   #                             gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
 362   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 363   #                             gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
 364   #
 365   #  The modular arithmetic performed in UINT64 ensures that the translation
 366   #  works correctly regardless of the relation between IoCpuBase and
 367   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 368   #  PcdPciMmio64Base.
 369   #
 370   gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
 371   gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
 372   gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
 373   gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
 374   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
 375   gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
 376
 377   #
 378   # Inclusive range of allowed PCI buses.
 379   #
 380   gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
 381   gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A