ArmPkg/ArmLib: add support for reading the max physical address space size
[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h
1 /** @file
2
3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef __ARM_LIB__
17 #define __ARM_LIB__
18
19 #include <Uefi/UefiBaseType.h>
20
21 #ifdef MDE_CPU_ARM
22 #include <Chipset/ArmV7.h>
23 #elif defined(MDE_CPU_AARCH64)
24 #include <Chipset/AArch64.h>
25 #else
26 #error "Unknown chipset."
27 #endif
28
29 #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
30 EFI_MEMORY_WT | EFI_MEMORY_WB | \
31 EFI_MEMORY_UCE)
32
33 /**
34 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
35 *
36 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
37 * be used in Secure World to distinguished Secure to Non-Secure memory.
38 */
39 typedef enum {
40 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
41 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
42 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
43 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
44
45 // On some platforms, memory mapped flash region is designed as not supporting
46 // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
47 // need.
48 // Do NOT use below two attributes if you are not sure.
49 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
50 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,
51
52 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
53 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
54 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
55 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
56 } ARM_MEMORY_REGION_ATTRIBUTES;
57
58 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
59
60 typedef struct {
61 EFI_PHYSICAL_ADDRESS PhysicalBase;
62 EFI_VIRTUAL_ADDRESS VirtualBase;
63 UINT64 Length;
64 ARM_MEMORY_REGION_ATTRIBUTES Attributes;
65 } ARM_MEMORY_REGION_DESCRIPTOR;
66
67 typedef VOID (*CACHE_OPERATION)(VOID);
68 typedef VOID (*LINE_OPERATION)(UINTN);
69
70 //
71 // ARM Processor Mode
72 //
73 typedef enum {
74 ARM_PROCESSOR_MODE_USER = 0x10,
75 ARM_PROCESSOR_MODE_FIQ = 0x11,
76 ARM_PROCESSOR_MODE_IRQ = 0x12,
77 ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
78 ARM_PROCESSOR_MODE_ABORT = 0x17,
79 ARM_PROCESSOR_MODE_HYP = 0x1A,
80 ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
81 ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
82 ARM_PROCESSOR_MODE_MASK = 0x1F
83 } ARM_PROCESSOR_MODE;
84
85 //
86 // ARM Cpu IDs
87 //
88 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
89 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
90 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
91 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
92 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
93 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
94
95 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
96 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
97 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
98 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
99 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
100 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
101
102 //
103 // ARM MP Core IDs
104 //
105 #define ARM_CORE_AFF0 0xFF
106 #define ARM_CORE_AFF1 (0xFF << 8)
107 #define ARM_CORE_AFF2 (0xFF << 16)
108 #define ARM_CORE_AFF3 (0xFFULL << 32)
109
110 #define ARM_CORE_MASK ARM_CORE_AFF0
111 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
112 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
113 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
114 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
115 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
116
117 UINTN
118 EFIAPI
119 ArmDataCacheLineLength (
120 VOID
121 );
122
123 UINTN
124 EFIAPI
125 ArmInstructionCacheLineLength (
126 VOID
127 );
128
129 UINTN
130 EFIAPI
131 ArmCacheWritebackGranule (
132 VOID
133 );
134
135 UINTN
136 EFIAPI
137 ArmIsArchTimerImplemented (
138 VOID
139 );
140
141 UINTN
142 EFIAPI
143 ArmReadIdPfr0 (
144 VOID
145 );
146
147 UINTN
148 EFIAPI
149 ArmReadIdPfr1 (
150 VOID
151 );
152
153 UINTN
154 EFIAPI
155 ArmCacheInfo (
156 VOID
157 );
158
159 BOOLEAN
160 EFIAPI
161 ArmIsMpCore (
162 VOID
163 );
164
165 VOID
166 EFIAPI
167 ArmInvalidateDataCache (
168 VOID
169 );
170
171
172 VOID
173 EFIAPI
174 ArmCleanInvalidateDataCache (
175 VOID
176 );
177
178 VOID
179 EFIAPI
180 ArmCleanDataCache (
181 VOID
182 );
183
184 VOID
185 EFIAPI
186 ArmInvalidateInstructionCache (
187 VOID
188 );
189
190 VOID
191 EFIAPI
192 ArmInvalidateDataCacheEntryByMVA (
193 IN UINTN Address
194 );
195
196 VOID
197 EFIAPI
198 ArmCleanDataCacheEntryToPoUByMVA (
199 IN UINTN Address
200 );
201
202 VOID
203 EFIAPI
204 ArmInvalidateInstructionCacheEntryToPoUByMVA (
205 IN UINTN Address
206 );
207
208 VOID
209 EFIAPI
210 ArmCleanDataCacheEntryByMVA (
211 IN UINTN Address
212 );
213
214 VOID
215 EFIAPI
216 ArmCleanInvalidateDataCacheEntryByMVA (
217 IN UINTN Address
218 );
219
220 VOID
221 EFIAPI
222 ArmInvalidateDataCacheEntryBySetWay (
223 IN UINTN SetWayFormat
224 );
225
226 VOID
227 EFIAPI
228 ArmCleanDataCacheEntryBySetWay (
229 IN UINTN SetWayFormat
230 );
231
232 VOID
233 EFIAPI
234 ArmCleanInvalidateDataCacheEntryBySetWay (
235 IN UINTN SetWayFormat
236 );
237
238 VOID
239 EFIAPI
240 ArmEnableDataCache (
241 VOID
242 );
243
244 VOID
245 EFIAPI
246 ArmDisableDataCache (
247 VOID
248 );
249
250 VOID
251 EFIAPI
252 ArmEnableInstructionCache (
253 VOID
254 );
255
256 VOID
257 EFIAPI
258 ArmDisableInstructionCache (
259 VOID
260 );
261
262 VOID
263 EFIAPI
264 ArmEnableMmu (
265 VOID
266 );
267
268 VOID
269 EFIAPI
270 ArmDisableMmu (
271 VOID
272 );
273
274 VOID
275 EFIAPI
276 ArmEnableCachesAndMmu (
277 VOID
278 );
279
280 VOID
281 EFIAPI
282 ArmDisableCachesAndMmu (
283 VOID
284 );
285
286 VOID
287 EFIAPI
288 ArmEnableInterrupts (
289 VOID
290 );
291
292 UINTN
293 EFIAPI
294 ArmDisableInterrupts (
295 VOID
296 );
297
298 BOOLEAN
299 EFIAPI
300 ArmGetInterruptState (
301 VOID
302 );
303
304 VOID
305 EFIAPI
306 ArmEnableAsynchronousAbort (
307 VOID
308 );
309
310 UINTN
311 EFIAPI
312 ArmDisableAsynchronousAbort (
313 VOID
314 );
315
316 VOID
317 EFIAPI
318 ArmEnableIrq (
319 VOID
320 );
321
322 UINTN
323 EFIAPI
324 ArmDisableIrq (
325 VOID
326 );
327
328 VOID
329 EFIAPI
330 ArmEnableFiq (
331 VOID
332 );
333
334 UINTN
335 EFIAPI
336 ArmDisableFiq (
337 VOID
338 );
339
340 BOOLEAN
341 EFIAPI
342 ArmGetFiqState (
343 VOID
344 );
345
346 /**
347 * Invalidate Data and Instruction TLBs
348 */
349 VOID
350 EFIAPI
351 ArmInvalidateTlb (
352 VOID
353 );
354
355 VOID
356 EFIAPI
357 ArmUpdateTranslationTableEntry (
358 IN VOID *TranslationTableEntry,
359 IN VOID *Mva
360 );
361
362 VOID
363 EFIAPI
364 ArmSetDomainAccessControl (
365 IN UINT32 Domain
366 );
367
368 VOID
369 EFIAPI
370 ArmSetTTBR0 (
371 IN VOID *TranslationTableBase
372 );
373
374 VOID
375 EFIAPI
376 ArmSetTTBCR (
377 IN UINT32 Bits
378 );
379
380 VOID *
381 EFIAPI
382 ArmGetTTBR0BaseAddress (
383 VOID
384 );
385
386 BOOLEAN
387 EFIAPI
388 ArmMmuEnabled (
389 VOID
390 );
391
392 VOID
393 EFIAPI
394 ArmEnableBranchPrediction (
395 VOID
396 );
397
398 VOID
399 EFIAPI
400 ArmDisableBranchPrediction (
401 VOID
402 );
403
404 VOID
405 EFIAPI
406 ArmSetLowVectors (
407 VOID
408 );
409
410 VOID
411 EFIAPI
412 ArmSetHighVectors (
413 VOID
414 );
415
416 VOID
417 EFIAPI
418 ArmDataMemoryBarrier (
419 VOID
420 );
421
422 VOID
423 EFIAPI
424 ArmDataSynchronizationBarrier (
425 VOID
426 );
427
428 VOID
429 EFIAPI
430 ArmInstructionSynchronizationBarrier (
431 VOID
432 );
433
434 VOID
435 EFIAPI
436 ArmWriteVBar (
437 IN UINTN VectorBase
438 );
439
440 UINTN
441 EFIAPI
442 ArmReadVBar (
443 VOID
444 );
445
446 VOID
447 EFIAPI
448 ArmWriteAuxCr (
449 IN UINT32 Bit
450 );
451
452 UINT32
453 EFIAPI
454 ArmReadAuxCr (
455 VOID
456 );
457
458 VOID
459 EFIAPI
460 ArmSetAuxCrBit (
461 IN UINT32 Bits
462 );
463
464 VOID
465 EFIAPI
466 ArmUnsetAuxCrBit (
467 IN UINT32 Bits
468 );
469
470 VOID
471 EFIAPI
472 ArmCallSEV (
473 VOID
474 );
475
476 VOID
477 EFIAPI
478 ArmCallWFE (
479 VOID
480 );
481
482 VOID
483 EFIAPI
484 ArmCallWFI (
485
486 VOID
487 );
488
489 UINTN
490 EFIAPI
491 ArmReadMpidr (
492 VOID
493 );
494
495 UINTN
496 EFIAPI
497 ArmReadMidr (
498 VOID
499 );
500
501 UINT32
502 EFIAPI
503 ArmReadCpacr (
504 VOID
505 );
506
507 VOID
508 EFIAPI
509 ArmWriteCpacr (
510 IN UINT32 Access
511 );
512
513 VOID
514 EFIAPI
515 ArmEnableVFP (
516 VOID
517 );
518
519 /**
520 Get the Secure Configuration Register value
521
522 @return Value read from the Secure Configuration Register
523
524 **/
525 UINT32
526 EFIAPI
527 ArmReadScr (
528 VOID
529 );
530
531 /**
532 Set the Secure Configuration Register
533
534 @param Value Value to write to the Secure Configuration Register
535
536 **/
537 VOID
538 EFIAPI
539 ArmWriteScr (
540 IN UINT32 Value
541 );
542
543 UINT32
544 EFIAPI
545 ArmReadMVBar (
546 VOID
547 );
548
549 VOID
550 EFIAPI
551 ArmWriteMVBar (
552 IN UINT32 VectorMonitorBase
553 );
554
555 UINT32
556 EFIAPI
557 ArmReadSctlr (
558 VOID
559 );
560
561 VOID
562 EFIAPI
563 ArmWriteSctlr (
564 IN UINT32 Value
565 );
566
567 UINTN
568 EFIAPI
569 ArmReadHVBar (
570 VOID
571 );
572
573 VOID
574 EFIAPI
575 ArmWriteHVBar (
576 IN UINTN HypModeVectorBase
577 );
578
579
580 //
581 // Helper functions for accessing CPU ACTLR
582 //
583
584 UINTN
585 EFIAPI
586 ArmReadCpuActlr (
587 VOID
588 );
589
590 VOID
591 EFIAPI
592 ArmWriteCpuActlr (
593 IN UINTN Val
594 );
595
596 VOID
597 EFIAPI
598 ArmSetCpuActlrBit (
599 IN UINTN Bits
600 );
601
602 VOID
603 EFIAPI
604 ArmUnsetCpuActlrBit (
605 IN UINTN Bits
606 );
607
608 //
609 // Accessors for the architected generic timer registers
610 //
611
612 #define ARM_ARCH_TIMER_ENABLE (1 << 0)
613 #define ARM_ARCH_TIMER_IMASK (1 << 1)
614 #define ARM_ARCH_TIMER_ISTATUS (1 << 2)
615
616 UINTN
617 EFIAPI
618 ArmReadCntFrq (
619 VOID
620 );
621
622 VOID
623 EFIAPI
624 ArmWriteCntFrq (
625 UINTN FreqInHz
626 );
627
628 UINT64
629 EFIAPI
630 ArmReadCntPct (
631 VOID
632 );
633
634 UINTN
635 EFIAPI
636 ArmReadCntkCtl (
637 VOID
638 );
639
640 VOID
641 EFIAPI
642 ArmWriteCntkCtl (
643 UINTN Val
644 );
645
646 UINTN
647 EFIAPI
648 ArmReadCntpTval (
649 VOID
650 );
651
652 VOID
653 EFIAPI
654 ArmWriteCntpTval (
655 UINTN Val
656 );
657
658 UINTN
659 EFIAPI
660 ArmReadCntpCtl (
661 VOID
662 );
663
664 VOID
665 EFIAPI
666 ArmWriteCntpCtl (
667 UINTN Val
668 );
669
670 UINTN
671 EFIAPI
672 ArmReadCntvTval (
673 VOID
674 );
675
676 VOID
677 EFIAPI
678 ArmWriteCntvTval (
679 UINTN Val
680 );
681
682 UINTN
683 EFIAPI
684 ArmReadCntvCtl (
685 VOID
686 );
687
688 VOID
689 EFIAPI
690 ArmWriteCntvCtl (
691 UINTN Val
692 );
693
694 UINT64
695 EFIAPI
696 ArmReadCntvCt (
697 VOID
698 );
699
700 UINT64
701 EFIAPI
702 ArmReadCntpCval (
703 VOID
704 );
705
706 VOID
707 EFIAPI
708 ArmWriteCntpCval (
709 UINT64 Val
710 );
711
712 UINT64
713 EFIAPI
714 ArmReadCntvCval (
715 VOID
716 );
717
718 VOID
719 EFIAPI
720 ArmWriteCntvCval (
721 UINT64 Val
722 );
723
724 UINT64
725 EFIAPI
726 ArmReadCntvOff (
727 VOID
728 );
729
730 VOID
731 EFIAPI
732 ArmWriteCntvOff (
733 UINT64 Val
734 );
735
736 UINTN
737 EFIAPI
738 ArmGetPhysicalAddressBits (
739 VOID
740 );
741
742 #endif // __ARM_LIB__