ArmPlatformPkg/PrePeiCore/MainMPCore.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4 *
   5 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   6 *
   7 **/
   8
   9 #include <Library/ArmGicLib.h>
  10
  11 #include <Ppi/ArmMpCoreInfo.h>
  12
  13 #include "PrePeiCore.h"
  14
  15 /*
  16  * This is the main function for secondary cores. They loop around until a non Null value is written to
  17  * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
  18  * Note:The secondary cores, while executing secondary_main, assumes that:
  19  *      : SGI 0 is configured as Non-secure interrupt
  20  *      : Priority Mask is configured to allow SGI 0
  21  *      : Interrupt Distributor and CPU interfaces are enabled
  22  *
  23  */
  24 VOID
  25 EFIAPI
  26 SecondaryMain (
  27   IN UINTN MpId
  28   )
  29 {
  30   EFI_STATUS              Status;
  31   UINTN                   PpiListSize;
  32   UINTN                   PpiListCount;
  33   EFI_PEI_PPI_DESCRIPTOR  *PpiList;
  34   ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;
  35   UINTN                   Index;
  36   UINTN                   ArmCoreCount;
  37   ARM_CORE_INFO           *ArmCoreInfoTable;
  38   UINT32                  ClusterId;
  39   UINT32                  CoreId;
  40   VOID                    (*SecondaryStart)(VOID);
  41   UINTN                   SecondaryEntryAddr;
  42   UINTN                   AcknowledgeInterrupt;
  43   UINTN                   InterruptId;
  44
  45   ClusterId = GET_CLUSTER_ID(MpId);
  46   CoreId    = GET_CORE_ID(MpId);
  47
  48   // Get the gArmMpCoreInfoPpiGuid
  49   PpiListSize = 0;
  50   ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
  51   PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
  52   for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
  53     if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
  54       break;
  55     }
  56   }
  57
  58   // On MP Core Platform we must implement the ARM MP Core Info PPI
  59   ASSERT (Index != PpiListCount);
  60
  61   ArmMpCoreInfoPpi = PpiList->Ppi;
  62   ArmCoreCount = 0;
  63   Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
  64   ASSERT_EFI_ERROR (Status);
  65
  66   // Find the core in the ArmCoreTable
  67   for (Index = 0; Index < ArmCoreCount; Index++) {
  68     if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {
  69       break;
  70     }
  71   }
  72
  73   // The ARM Core Info Table must define every core
  74   ASSERT (Index != ArmCoreCount);
  75
  76   // Clear Secondary cores MailBox
  77   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
  78
  79   do {
  80     ArmCallWFI ();
  81
  82     // Read the Mailbox
  83     SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
  84
  85     // Acknowledge the interrupt and send End of Interrupt signal.
  86     AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);
  87     // Check if it is a valid interrupt ID
  88     if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {
  89       // Got a valid SGI number hence signal End of Interrupt
  90       ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
  91     }
  92   } while (SecondaryEntryAddr == 0);
  93
  94   // Jump to secondary core entry point.
  95   SecondaryStart = (VOID (*)())SecondaryEntryAddr;
  96   SecondaryStart();
  97
  98   // The secondaries shouldn't reach here
  99   ASSERT(FALSE);
 100 }
 101
 102 VOID
 103 EFIAPI
 104 PrimaryMain (
 105   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
 106   )
 107 {
 108   EFI_SEC_PEI_HAND_OFF        SecCoreData;
 109   UINTN                       PpiListSize;
 110   EFI_PEI_PPI_DESCRIPTOR      *PpiList;
 111   UINTN                       TemporaryRamBase;
 112   UINTN                       TemporaryRamSize;
 113
 114   CreatePpiList (&PpiListSize, &PpiList);
 115
 116   // Enable the GIC Distributor
 117   ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));
 118
 119   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
 120   if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
 121     // Sending SGI to all the Secondary CPU interfaces
 122     ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
 123   }
 124
 125   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
 126   // the base of the primary core stack
 127   PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);
 128   TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
 129   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
 130
 131   //
 132   // Bind this information into the SEC hand-off state
 133   // Note: this must be in sync with the stuff in the asm file
 134   // Note also:  HOBs (pei temp ram) MUST be above stack
 135   //
 136   SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
 137   SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
 138   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
 139   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
 140   SecCoreData.TemporaryRamSize       = TemporaryRamSize;
 141   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;
 142   SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
 143   SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
 144   SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
 145
 146   // Jump to PEI core entry point
 147   PeiCoreEntryPoint (&SecCoreData, PpiList);
 148 }