BeagleBoardPkg/Include/BeagleBoard.h

   1 /** @file
   2 *  Header defining the BeagleBoard constants (Base addresses, sizes, flags)
   3 *
   4 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   5 *
   6 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   7 *
   8 **/
   9
  10 #ifndef __BEAGLEBOARD_PLATFORM_H__
  11 #define __BEAGLEBOARD_PLATFORM_H__
  12
  13 // DDR attributes
  14 #define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
  15 #define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
  16
  17 // SoC registers. L3 interconnects
  18 #define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000
  19 #define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000
  20 #define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
  21
  22 // SoC registers. L4 interconnects
  23 #define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000
  24 #define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000
  25 #define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
  26
  27
  28 #if 0
  29 /*******************************************
  30 // Platform Memory Map
  31 *******************************************/
  32
  33 // Can be NOR, DOC, DRAM, SRAM
  34 #define ARM_EB_REMAP_BASE                     0x00000000
  35 #define ARM_EB_REMAP_SZ                       0x04000000
  36
  37 // Motherboard Peripheral and On-chip peripheral
  38 #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE     0x10000000
  39 #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ       0x00100000
  40 #define ARM_EB_BOARD_PERIPH_BASE              0x10000000
  41 //#define ARM_EB_CHIP_PERIPH_BASE             0x10020000
  42
  43 // SMC
  44 #define ARM_EB_SMC_BASE                       0x40000000
  45 #define ARM_EB_SMC_SZ                         0x20000000
  46
  47 // NOR Flash 1
  48 #define ARM_EB_SMB_NOR_BASE                   0x40000000
  49 #define ARM_EB_SMB_NOR_SZ                     0x04000000 /* 64 MB */
  50 // DOC Flash
  51 #define ARM_EB_SMB_DOC_BASE                   0x44000000
  52 #define ARM_EB_SMB_DOC_SZ                     0x04000000 /* 64 MB */
  53 // SRAM
  54 #define ARM_EB_SMB_SRAM_BASE                  0x48000000
  55 #define ARM_EB_SMB_SRAM_SZ                    0x02000000 /* 32 MB */
  56 // USB, Ethernet, VRAM
  57 #define ARM_EB_SMB_PERIPH_BASE                0x4E000000
  58 //#define ARM_EB_SMB_PERIPH_VRAM              0x4C000000
  59 #define ARM_EB_SMB_PERIPH_SZ                  0x02000000 /* 32 MB */
  60
  61 // DRAM
  62 #define ARM_EB_DRAM_BASE                      0x70000000
  63 #define ARM_EB_DRAM_SZ                        0x10000000
  64
  65 // Logic Tile
  66 #define ARM_EB_LOGIC_TILE_BASE                0xC0000000
  67 #define ARM_EB_LOGIC_TILE_SZ                  0x40000000
  68
  69 /*******************************************
  70 // Motherboard peripherals
  71 *******************************************/
  72
  73 // Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)
  74 #define ARM_EB_SYS_FLAGS_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
  75 #define ARM_EB_SYS_FLAGS_SET_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
  76 #define ARM_EB_SYS_FLAGS_CLR_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
  77 #define ARM_EB_SYS_FLAGS_NV_REG               (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
  78 #define ARM_EB_SYS_FLAGS_NV_SET_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
  79 #define ARM_EB_SYS_FLAGS_NV_CLR_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
  80 #define ARM_EB_SYS_CLCD                       (ARM_EB_BOARD_PERIPH_BASE + 0x00050)
  81 #define ARM_EB_SYS_PROCID0_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
  82 #define ARM_EB_SYS_PROCID1_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
  83 #define ARM_EB_SYS_CFGDATA_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
  84 #define ARM_EB_SYS_CFGCTRL_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
  85 #define ARM_EB_SYS_CFGSTAT_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
  86
  87 // SP810 Controller
  88 #define SP810_CTRL_BASE                       (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
  89
  90 // SYSTRCL Register
  91 #define ARM_EB_SYSCTRL                        0x10001000
  92
  93 // Uart0
  94 #define PL011_CONSOLE_UART_BASE               (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
  95 #define PL011_CONSOLE_UART_SPEED              115200
  96
  97 // SP804 Timer Bases
  98 #define SP804_TIMER0_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
  99 #define SP804_TIMER1_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
 100 #define SP804_TIMER2_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
 101 #define SP804_TIMER3_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
 102
 103 // PL301 RTC
 104 #define PL031_RTC_BASE                        (ARM_EB_BOARD_PERIPH_BASE + 0x17000)
 105
 106 // Dynamic Memory Controller Base
 107 #define ARM_EB_DMC_BASE                       0x10018000
 108
 109 // Static Memory Controller Base
 110 #define ARM_EB_SMC_CTRL_BASE                  0x10080000
 111
 112 #define PL111_CLCD_BASE                       0x10020000
 113 //TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption
 114 #define PL111_CLCD_VRAM_BASE                  0x78000000
 115
 116 #define ARM_EB_SYS_OSCCLK4                    0x1000001C
 117
 118
 119 /*// System Configuration Controller register Base addresses
 120 //#define ARM_EB_SYS_CFG_CTRL_BASE                0x100E2000
 121 #define ARM_EB_SYS_CFGRW0_REG                   0x100E2000
 122 #define ARM_EB_SYS_CFGRW1_REG                   0x100E2004
 123 #define ARM_EB_SYS_CFGRW2_REG                   0x100E2008
 124
 125 #define ARM_EB_CFGRW1_REMAP_NOR0                0
 126 #define ARM_EB_CFGRW1_REMAP_NOR1                (1 << 28)
 127 #define ARM_EB_CFGRW1_REMAP_EXT_AXI             (1 << 29)
 128 #define ARM_EB_CFGRW1_REMAP_DRAM                (1 << 30)
 129
 130 // PL301 Fast AXI Base Address
 131 #define ARM_EB_FAXI_BASE                        0x100E9000
 132
 133 // L2x0 Cache Controller Base Address
 134 //#define ARM_EB_L2x0_CTLR_BASE                   0x1E00A000*/
 135
 136
 137 // PL031 RTC - Other settings
 138 #define PL031_PPM_ACCURACY                      300000000
 139
 140 /*******************************************
 141 // Interrupt Map
 142 *******************************************/
 143
 144 // Timer Interrupts
 145 #define TIMER01_INTERRUPT_NUM                34
 146 #define TIMER23_INTERRUPT_NUM                35
 147
 148
 149 /*******************************************
 150 // EFI Memory Map in Permanent Memory (DRAM)
 151 *******************************************/
 152
 153 // This region is allocated at the bottom of the DRAM. It will be used
 154 // for fixed address allocations such as Vector Table
 155 #define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB
 156
 157 // This region is the memory declared to PEI as permanent memory for PEI
 158 // and DXE. EFI stacks and heaps will be declared in this region.
 159 #define ARM_EB_EFI_MEMORY_REGION_SZ             0x1000000
 160 #endif
 161
 162 typedef enum {
 163   REVISION_XM,
 164   REVISION_UNKNOWN0,
 165   REVISION_UNKNOWN1,
 166   REVISION_UNKNOWN2,
 167   REVISION_UNKNOWN3,
 168   REVISION_C4,
 169   REVISION_C123,
 170   REVISION_AB,
 171 } BEAGLEBOARD_REVISION;
 172
 173 #endif