MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

   1 /** @file
   2
   3   PCI Root Bridge Io Protocol code.
   4
   5 Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include "PciHostBridge.h"
  17 #include "PciRootBridge.h"
  18 #include "PciHostResource.h"
  19
  20 extern EDKII_IOMMU_PROTOCOL        *mIoMmuProtocol;
  21
  22 #define NO_MAPPING  (VOID *) (UINTN) -1
  23
  24 //
  25 // Lookup table for increment values based on transfer widths
  26 //
  27 UINT8 mInStride[] = {
  28   1, // EfiPciWidthUint8
  29   2, // EfiPciWidthUint16
  30   4, // EfiPciWidthUint32
  31   8, // EfiPciWidthUint64
  32   0, // EfiPciWidthFifoUint8
  33   0, // EfiPciWidthFifoUint16
  34   0, // EfiPciWidthFifoUint32
  35   0, // EfiPciWidthFifoUint64
  36   1, // EfiPciWidthFillUint8
  37   2, // EfiPciWidthFillUint16
  38   4, // EfiPciWidthFillUint32
  39   8  // EfiPciWidthFillUint64
  40 };
  41
  42 //
  43 // Lookup table for increment values based on transfer widths
  44 //
  45 UINT8 mOutStride[] = {
  46   1, // EfiPciWidthUint8
  47   2, // EfiPciWidthUint16
  48   4, // EfiPciWidthUint32
  49   8, // EfiPciWidthUint64
  50   1, // EfiPciWidthFifoUint8
  51   2, // EfiPciWidthFifoUint16
  52   4, // EfiPciWidthFifoUint32
  53   8, // EfiPciWidthFifoUint64
  54   0, // EfiPciWidthFillUint8
  55   0, // EfiPciWidthFillUint16
  56   0, // EfiPciWidthFillUint32
  57   0  // EfiPciWidthFillUint64
  58 };
  59
  60 /**
  61   Construct the Pci Root Bridge instance.
  62
  63   @param Bridge            The root bridge instance.
  64
  65   @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
  66           or NULL if creation fails.
  67 **/
  68 PCI_ROOT_BRIDGE_INSTANCE *
  69 CreateRootBridge (
  70   IN PCI_ROOT_BRIDGE       *Bridge
  71   )
  72 {
  73   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
  74   PCI_RESOURCE_TYPE        Index;
  75   CHAR16                   *DevicePathStr;
  76   PCI_ROOT_BRIDGE_APERTURE *Aperture;
  77
  78   DevicePathStr = NULL;
  79
  80   DEBUG ((EFI_D_INFO, "RootBridge: "));
  81   DEBUG ((EFI_D_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));
  82   DEBUG ((EFI_D_INFO, "  Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));
  83   DEBUG ((EFI_D_INFO, "    DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));
  84   DEBUG ((EFI_D_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));
  85   DEBUG ((EFI_D_INFO, "     AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,
  86           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
  87           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
  88           ));
  89   DEBUG ((
  90     EFI_D_INFO, "           Bus: %lx - %lx Translation=%lx\n",
  91     Bridge->Bus.Base, Bridge->Bus.Limit, Bridge->Bus.Translation
  92     ));
  93   //
  94   // Translation for bus is not supported.
  95   //
  96   ASSERT (Bridge->Bus.Translation == 0);
  97   if (Bridge->Bus.Translation != 0) {
  98     return NULL;
  99   }
 100
 101   DEBUG ((
 102     DEBUG_INFO, "            Io: %lx - %lx Translation=%lx\n",
 103     Bridge->Io.Base, Bridge->Io.Limit, Bridge->Io.Translation
 104     ));
 105   DEBUG ((
 106     DEBUG_INFO, "           Mem: %lx - %lx Translation=%lx\n",
 107     Bridge->Mem.Base, Bridge->Mem.Limit, Bridge->Mem.Translation
 108     ));
 109   DEBUG ((
 110     DEBUG_INFO, "    MemAbove4G: %lx - %lx Translation=%lx\n",
 111     Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit, Bridge->MemAbove4G.Translation
 112     ));
 113   DEBUG ((
 114     DEBUG_INFO, "          PMem: %lx - %lx Translation=%lx\n",
 115     Bridge->PMem.Base, Bridge->PMem.Limit, Bridge->PMem.Translation
 116     ));
 117   DEBUG ((
 118     DEBUG_INFO, "   PMemAbove4G: %lx - %lx Translation=%lx\n",
 119     Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit, Bridge->PMemAbove4G.Translation
 120     ));
 121
 122   //
 123   // Make sure Mem and MemAbove4G apertures are valid
 124   //
 125   if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
 126     ASSERT (Bridge->Mem.Limit < SIZE_4GB);
 127     if (Bridge->Mem.Limit >= SIZE_4GB) {
 128       return NULL;
 129     }
 130   }
 131   if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
 132     ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
 133     if (Bridge->MemAbove4G.Base < SIZE_4GB) {
 134       return NULL;
 135     }
 136   }
 137   if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
 138     ASSERT (Bridge->PMem.Limit < SIZE_4GB);
 139     if (Bridge->PMem.Limit >= SIZE_4GB) {
 140       return NULL;
 141     }
 142   }
 143   if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
 144     ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
 145     if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
 146       return NULL;
 147     }
 148   }
 149
 150   //
 151   // Ignore AllocationAttributes when resources were already assigned.
 152   //
 153   if (!Bridge->ResourceAssigned) {
 154     if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {
 155       //
 156       // If this bit is set, then the PCI Root Bridge does not
 157       // support separate windows for Non-prefetchable and Prefetchable
 158       // memory.
 159       //
 160       ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
 161       ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
 162       if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
 163           (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
 164           ) {
 165         return NULL;
 166       }
 167     }
 168
 169     if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {
 170       //
 171       // If this bit is not set, then the PCI Root Bridge does not support
 172       // 64 bit memory windows.
 173       //
 174       ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
 175       ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
 176       if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
 177           (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
 178           ) {
 179         return NULL;
 180       }
 181     }
 182   }
 183
 184   RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));
 185   ASSERT (RootBridge != NULL);
 186
 187   RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
 188   RootBridge->Supports = Bridge->Supports;
 189   RootBridge->Attributes = Bridge->Attributes;
 190   RootBridge->DmaAbove4G = Bridge->DmaAbove4G;
 191   RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;
 192   RootBridge->AllocationAttributes = Bridge->AllocationAttributes;
 193   RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);
 194   RootBridge->DevicePathStr = DevicePathStr;
 195   RootBridge->ConfigBuffer = AllocatePool (
 196     TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
 197     );
 198   ASSERT (RootBridge->ConfigBuffer != NULL);
 199   InitializeListHead (&RootBridge->Maps);
 200
 201   CopyMem (&RootBridge->Bus, &Bridge->Bus, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 202   CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 203   CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 204   CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 205   CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 206   CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 207
 208   for (Index = TypeIo; Index < TypeMax; Index++) {
 209     switch (Index) {
 210     case TypeBus:
 211       Aperture = &RootBridge->Bus;
 212       break;
 213     case TypeIo:
 214       Aperture = &RootBridge->Io;
 215       break;
 216     case TypeMem32:
 217       Aperture = &RootBridge->Mem;
 218       break;
 219     case TypeMem64:
 220       Aperture = &RootBridge->MemAbove4G;
 221       break;
 222     case TypePMem32:
 223       Aperture = &RootBridge->PMem;
 224       break;
 225     case TypePMem64:
 226       Aperture = &RootBridge->PMemAbove4G;
 227       break;
 228     default:
 229       ASSERT (FALSE);
 230       Aperture = NULL;
 231       break;
 232     }
 233     RootBridge->ResAllocNode[Index].Type     = Index;
 234     if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {
 235       //
 236       // Base in ResAllocNode is a host address, while Base in Aperture is a
 237       // device address.
 238       //
 239       RootBridge->ResAllocNode[Index].Base   = TO_HOST_ADDRESS (Aperture->Base,
 240         Aperture->Translation);
 241       RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;
 242       RootBridge->ResAllocNode[Index].Status = ResAllocated;
 243     } else {
 244       RootBridge->ResAllocNode[Index].Base   = 0;
 245       RootBridge->ResAllocNode[Index].Length = 0;
 246       RootBridge->ResAllocNode[Index].Status = ResNone;
 247     }
 248   }
 249
 250   RootBridge->RootBridgeIo.SegmentNumber  = Bridge->Segment;
 251   RootBridge->RootBridgeIo.PollMem        = RootBridgeIoPollMem;
 252   RootBridge->RootBridgeIo.PollIo         = RootBridgeIoPollIo;
 253   RootBridge->RootBridgeIo.Mem.Read       = RootBridgeIoMemRead;
 254   RootBridge->RootBridgeIo.Mem.Write      = RootBridgeIoMemWrite;
 255   RootBridge->RootBridgeIo.Io.Read        = RootBridgeIoIoRead;
 256   RootBridge->RootBridgeIo.Io.Write       = RootBridgeIoIoWrite;
 257   RootBridge->RootBridgeIo.CopyMem        = RootBridgeIoCopyMem;
 258   RootBridge->RootBridgeIo.Pci.Read       = RootBridgeIoPciRead;
 259   RootBridge->RootBridgeIo.Pci.Write      = RootBridgeIoPciWrite;
 260   RootBridge->RootBridgeIo.Map            = RootBridgeIoMap;
 261   RootBridge->RootBridgeIo.Unmap          = RootBridgeIoUnmap;
 262   RootBridge->RootBridgeIo.AllocateBuffer = RootBridgeIoAllocateBuffer;
 263   RootBridge->RootBridgeIo.FreeBuffer     = RootBridgeIoFreeBuffer;
 264   RootBridge->RootBridgeIo.Flush          = RootBridgeIoFlush;
 265   RootBridge->RootBridgeIo.GetAttributes  = RootBridgeIoGetAttributes;
 266   RootBridge->RootBridgeIo.SetAttributes  = RootBridgeIoSetAttributes;
 267   RootBridge->RootBridgeIo.Configuration  = RootBridgeIoConfiguration;
 268
 269   return RootBridge;
 270 }
 271
 272 /**
 273   Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
 274
 275   The I/O operations are carried out exactly as requested. The caller is
 276   responsible for satisfying any alignment and I/O width restrictions that a PI
 277   System on a platform might require. For example on some platforms, width
 278   requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
 279   hand, will be handled by the driver.
 280
 281   @param[in] This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 282
 283   @param[in] OperationType  I/O operation type: IO/MMIO/PCI.
 284
 285   @param[in] Width          Signifies the width of the I/O or Memory operation.
 286
 287   @param[in] Address        The base address of the I/O operation.
 288
 289   @param[in] Count          The number of I/O operations to perform. The number
 290                             of bytes moved is Width size * Count, starting at
 291                             Address.
 292
 293   @param[in] Buffer         For read operations, the destination buffer to
 294                             store the results. For write operations, the source
 295                             buffer from which to write data.
 296
 297   @retval EFI_SUCCESS            The parameters for this request pass the
 298                                  checks.
 299
 300   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
 301
 302   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 303
 304   @retval EFI_INVALID_PARAMETER  Address or Count is invalid.
 305
 306   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
 307
 308   @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
 309                                  and Count is not valid for this PI system.
 310 **/
 311 EFI_STATUS
 312 RootBridgeIoCheckParameter (
 313   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 314   IN OPERATION_TYPE                         OperationType,
 315   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 316   IN UINT64                                 Address,
 317   IN UINTN                                  Count,
 318   IN VOID                                   *Buffer
 319   )
 320 {
 321   PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;
 322   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  *PciRbAddr;
 323   UINT64                                       Base;
 324   UINT64                                       Limit;
 325   UINT32                                       Size;
 326   UINT64                                       Length;
 327
 328   //
 329   // Check to see if Buffer is NULL
 330   //
 331   if (Buffer == NULL) {
 332     return EFI_INVALID_PARAMETER;
 333   }
 334
 335   //
 336   // Check to see if Width is in the valid range
 337   //
 338   if ((UINT32) Width >= EfiPciWidthMaximum) {
 339     return EFI_INVALID_PARAMETER;
 340   }
 341
 342   //
 343   // For FIFO type, the device address won't increase during the access,
 344   // so treat Count as 1
 345   //
 346   if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
 347     Count = 1;
 348   }
 349
 350   Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
 351   Size  = 1 << Width;
 352
 353   //
 354   // Make sure (Count * Size) doesn't exceed MAX_UINT64
 355   //
 356   if (Count > DivU64x32 (MAX_UINT64, Size)) {
 357     return EFI_INVALID_PARAMETER;
 358   }
 359
 360   //
 361   // Check to see if Address is aligned
 362   //
 363   if ((Address & (Size - 1)) != 0) {
 364     return EFI_UNSUPPORTED;
 365   }
 366
 367   //
 368   // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64
 369   //
 370   Length = MultU64x32 (Count, Size);
 371   if (Address > MAX_UINT64 - Length) {
 372     return EFI_INVALID_PARAMETER;
 373   }
 374
 375   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 376
 377   //
 378   // Check to see if any address associated with this transfer exceeds the
 379   // maximum allowed address.  The maximum address implied by the parameters
 380   // passed in is Address + Size * Count.  If the following condition is met,
 381   // then the transfer is not supported.
 382   //
 383   //    Address + Size * Count > Limit + 1
 384   //
 385   // Since Limit can be the maximum integer value supported by the CPU and
 386   // Count can also be the maximum integer value supported by the CPU, this
 387   // range check must be adjusted to avoid all oveflow conditions.
 388   //
 389   if (OperationType == IoOperation) {
 390     //
 391     // Allow Legacy IO access
 392     //
 393     if (Address + Length <= 0x1000) {
 394       if ((RootBridge->Attributes & (
 395            EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
 396            EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
 397            EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0) {
 398         return EFI_SUCCESS;
 399       }
 400     }
 401     Base = RootBridge->Io.Base;
 402     Limit = RootBridge->Io.Limit;
 403   } else if (OperationType == MemOperation) {
 404     //
 405     // Allow Legacy MMIO access
 406     //
 407     if ((Address >= 0xA0000) && (Address + Length) <= 0xC0000) {
 408       if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {
 409         return EFI_SUCCESS;
 410       }
 411     }
 412     //
 413     // By comparing the Address against Limit we know which range to be used
 414     // for checking
 415     //
 416     if ((Address >= RootBridge->Mem.Base) && (Address + Length <= RootBridge->Mem.Limit + 1)) {
 417       Base  = RootBridge->Mem.Base;
 418       Limit = RootBridge->Mem.Limit;
 419     } else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= RootBridge->PMem.Limit + 1)) {
 420       Base  = RootBridge->PMem.Base;
 421       Limit = RootBridge->PMem.Limit;
 422     } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length <= RootBridge->MemAbove4G.Limit + 1)) {
 423       Base  = RootBridge->MemAbove4G.Base;
 424       Limit = RootBridge->MemAbove4G.Limit;
 425     } else {
 426       Base  = RootBridge->PMemAbove4G.Base;
 427       Limit = RootBridge->PMemAbove4G.Limit;
 428     }
 429   } else {
 430     PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
 431     if (PciRbAddr->Bus < RootBridge->Bus.Base ||
 432         PciRbAddr->Bus > RootBridge->Bus.Limit) {
 433       return EFI_INVALID_PARAMETER;
 434     }
 435
 436     if (PciRbAddr->Device > PCI_MAX_DEVICE ||
 437         PciRbAddr->Function > PCI_MAX_FUNC) {
 438       return EFI_INVALID_PARAMETER;
 439     }
 440
 441     if (PciRbAddr->ExtendedRegister != 0) {
 442       Address = PciRbAddr->ExtendedRegister;
 443     } else {
 444       Address = PciRbAddr->Register;
 445     }
 446     Base = 0;
 447     Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;
 448   }
 449
 450   if (Address < Base) {
 451       return EFI_INVALID_PARAMETER;
 452   }
 453
 454   if (Address + Length > Limit + 1) {
 455     return EFI_INVALID_PARAMETER;
 456   }
 457
 458   return EFI_SUCCESS;
 459 }
 460
 461 /**
 462   Use address to match apertures of memory type and then get the corresponding
 463   translation.
 464
 465   @param RootBridge              The root bridge instance.
 466   @param Address                 The address used to match aperture.
 467   @param Translation             Pointer containing the output translation.
 468
 469   @return EFI_SUCCESS            Get translation successfully.
 470   @return EFI_INVALID_PARAMETER  No matched memory aperture; the input Address
 471                                  must be invalid.
 472 **/
 473 EFI_STATUS
 474 RootBridgeIoGetMemTranslationByAddress (
 475   IN PCI_ROOT_BRIDGE_INSTANCE               *RootBridge,
 476   IN UINT64                                 Address,
 477   IN OUT UINT64                             *Translation
 478   )
 479 {
 480   if (Address >= RootBridge->Mem.Base && Address <= RootBridge->Mem.Limit) {
 481     *Translation = RootBridge->Mem.Translation;
 482   } else if (Address >= RootBridge->PMem.Base && Address <= RootBridge->PMem.Limit) {
 483     *Translation = RootBridge->PMem.Translation;
 484   } else if (Address >= RootBridge->MemAbove4G.Base && Address <= RootBridge->MemAbove4G.Limit) {
 485     *Translation = RootBridge->MemAbove4G.Translation;
 486   } else if (Address >= RootBridge->PMemAbove4G.Base && Address <= RootBridge->PMemAbove4G.Limit) {
 487     *Translation = RootBridge->PMemAbove4G.Translation;
 488   } else {
 489     return EFI_INVALID_PARAMETER;
 490   }
 491
 492   return EFI_SUCCESS;
 493 }
 494
 495 /**
 496   Return the result of (Multiplicand * Multiplier / Divisor).
 497
 498   @param Multiplicand A 64-bit unsigned value.
 499   @param Multiplier   A 64-bit unsigned value.
 500   @param Divisor      A 32-bit unsigned value.
 501   @param Remainder    A pointer to a 32-bit unsigned value. This parameter is
 502                       optional and may be NULL.
 503
 504   @return Multiplicand * Multiplier / Divisor.
 505 **/
 506 UINT64
 507 MultThenDivU64x64x32 (
 508   IN      UINT64                    Multiplicand,
 509   IN      UINT64                    Multiplier,
 510   IN      UINT32                    Divisor,
 511   OUT     UINT32                    *Remainder  OPTIONAL
 512   )
 513 {
 514   UINT64                            Uint64;
 515   UINT32                            LocalRemainder;
 516   UINT32                            Uint32;
 517   if (Multiplicand > DivU64x64Remainder (MAX_UINT64, Multiplier, NULL)) {
 518     //
 519     // Make sure Multiplicand is the bigger one.
 520     //
 521     if (Multiplicand < Multiplier) {
 522       Uint64       = Multiplicand;
 523       Multiplicand = Multiplier;
 524       Multiplier   = Uint64;
 525     }
 526     //
 527     // Because Multiplicand * Multiplier overflows,
 528     //   Multiplicand * Multiplier / Divisor
 529     // = (2 * Multiplicand' + 1) * Multiplier / Divisor
 530     // = 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divisor
 531     //
 532     Uint64 = MultThenDivU64x64x32 (RShiftU64 (Multiplicand, 1), Multiplier, Divisor, &LocalRemainder);
 533     Uint64 = LShiftU64 (Uint64, 1);
 534     Uint32 = 0;
 535     if ((Multiplicand & 0x1) == 1) {
 536       Uint64 += DivU64x32Remainder (Multiplier, Divisor, &Uint32);
 537     }
 538     return Uint64 + DivU64x32Remainder (Uint32 + LShiftU64 (LocalRemainder, 1), Divisor, Remainder);
 539   } else {
 540     return DivU64x32Remainder (MultU64x64 (Multiplicand, Multiplier), Divisor, Remainder);
 541   }
 542 }
 543
 544 /**
 545   Return the elapsed tick count from CurrentTick.
 546
 547   @param  CurrentTick  On input, the previous tick count.
 548                        On output, the current tick count.
 549   @param  StartTick    The value the performance counter starts with when it
 550                        rolls over.
 551   @param  EndTick      The value that the performance counter ends with before
 552                        it rolls over.
 553
 554   @return  The elapsed tick count from CurrentTick.
 555 **/
 556 UINT64
 557 GetElapsedTick (
 558   UINT64  *CurrentTick,
 559   UINT64  StartTick,
 560   UINT64  EndTick
 561   )
 562 {
 563   UINT64  PreviousTick;
 564
 565   PreviousTick = *CurrentTick;
 566   *CurrentTick = GetPerformanceCounter();
 567   if (StartTick < EndTick) {
 568     return *CurrentTick - PreviousTick;
 569   } else {
 570     return PreviousTick - *CurrentTick;
 571   }
 572 }
 573
 574 /**
 575   Polls an address in memory mapped I/O space until an exit condition is met,
 576   or a timeout occurs.
 577
 578   This function provides a standard way to poll a PCI memory location. A PCI
 579   memory read operation is performed at the PCI memory address specified by
 580   Address for the width specified by Width. The result of this PCI memory read
 581   operation is stored in Result. This PCI memory read operation is repeated
 582   until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
 583   is equal to Value.
 584
 585   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 586   @param[in]   Width     Signifies the width of the memory operations.
 587   @param[in]   Address   The base address of the memory operations. The caller
 588                          is responsible for aligning Address if required.
 589   @param[in]   Mask      Mask used for the polling criteria. Bytes above Width
 590                          in Mask are ignored. The bits in the bytes below Width
 591                          which are zero in Mask are ignored when polling the
 592                          memory address.
 593   @param[in]   Value     The comparison value used for the polling exit
 594                          criteria.
 595   @param[in]   Delay     The number of 100 ns units to poll. Note that timer
 596                          available may be of poorer granularity.
 597   @param[out]  Result    Pointer to the last value read from the memory
 598                          location.
 599
 600   @retval EFI_SUCCESS            The last data returned from the access matched
 601                                  the poll exit criteria.
 602   @retval EFI_INVALID_PARAMETER  Width is invalid.
 603   @retval EFI_INVALID_PARAMETER  Result is NULL.
 604   @retval EFI_TIMEOUT            Delay expired before a match occurred.
 605   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 606                                  lack of resources.
 607 **/
 608 EFI_STATUS
 609 EFIAPI
 610 RootBridgeIoPollMem (
 611   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 612   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 613   IN  UINT64                                 Address,
 614   IN  UINT64                                 Mask,
 615   IN  UINT64                                 Value,
 616   IN  UINT64                                 Delay,
 617   OUT UINT64                                 *Result
 618   )
 619 {
 620   EFI_STATUS  Status;
 621   UINT64      NumberOfTicks;
 622   UINT32      Remainder;
 623   UINT64      StartTick;
 624   UINT64      EndTick;
 625   UINT64      CurrentTick;
 626   UINT64      ElapsedTick;
 627   UINT64      Frequency;
 628
 629   if (Result == NULL) {
 630     return EFI_INVALID_PARAMETER;
 631   }
 632
 633   if ((UINT32)Width > EfiPciWidthUint64) {
 634     return EFI_INVALID_PARAMETER;
 635   }
 636
 637   //
 638   // No matter what, always do a single poll.
 639   //
 640   Status = This->Mem.Read (This, Width, Address, 1, Result);
 641   if (EFI_ERROR (Status)) {
 642     return Status;
 643   }
 644
 645   if ((*Result & Mask) == Value) {
 646     return EFI_SUCCESS;
 647   }
 648
 649   if (Delay == 0) {
 650     return EFI_SUCCESS;
 651
 652   } else {
 653     //
 654     // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
 655     //
 656     Frequency     = GetPerformanceCounterProperties (&StartTick, &EndTick);
 657     NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);
 658     if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
 659       NumberOfTicks++;
 660     }
 661     for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()
 662         ; ElapsedTick <= NumberOfTicks
 663         ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
 664         ) {
 665       Status = This->Mem.Read (This, Width, Address, 1, Result);
 666       if (EFI_ERROR (Status)) {
 667         return Status;
 668       }
 669
 670       if ((*Result & Mask) == Value) {
 671         return EFI_SUCCESS;
 672       }
 673     }
 674   }
 675   return EFI_TIMEOUT;
 676 }
 677
 678 /**
 679   Reads from the I/O space of a PCI Root Bridge. Returns when either the
 680   polling exit criteria is satisfied or after a defined duration.
 681
 682   This function provides a standard way to poll a PCI I/O location. A PCI I/O
 683   read operation is performed at the PCI I/O address specified by Address for
 684   the width specified by Width.
 685   The result of this PCI I/O read operation is stored in Result. This PCI I/O
 686   read operation is repeated until either a timeout of Delay 100 ns units has
 687   expired, or (Result & Mask) is equal to Value.
 688
 689   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 690   @param[in] Width     Signifies the width of the I/O operations.
 691   @param[in] Address   The base address of the I/O operations. The caller is
 692                        responsible for aligning Address if required.
 693   @param[in] Mask      Mask used for the polling criteria. Bytes above Width in
 694                        Mask are ignored. The bits in the bytes below Width
 695                        which are zero in Mask are ignored when polling the I/O
 696                        address.
 697   @param[in] Value     The comparison value used for the polling exit criteria.
 698   @param[in] Delay     The number of 100 ns units to poll. Note that timer
 699                        available may be of poorer granularity.
 700   @param[out] Result   Pointer to the last value read from the memory location.
 701
 702   @retval EFI_SUCCESS            The last data returned from the access matched
 703                                  the poll exit criteria.
 704   @retval EFI_INVALID_PARAMETER  Width is invalid.
 705   @retval EFI_INVALID_PARAMETER  Result is NULL.
 706   @retval EFI_TIMEOUT            Delay expired before a match occurred.
 707   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 708                                  lack of resources.
 709 **/
 710 EFI_STATUS
 711 EFIAPI
 712 RootBridgeIoPollIo (
 713   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 714   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 715   IN  UINT64                                 Address,
 716   IN  UINT64                                 Mask,
 717   IN  UINT64                                 Value,
 718   IN  UINT64                                 Delay,
 719   OUT UINT64                                 *Result
 720   )
 721 {
 722   EFI_STATUS  Status;
 723   UINT64      NumberOfTicks;
 724   UINT32      Remainder;
 725   UINT64      StartTick;
 726   UINT64      EndTick;
 727   UINT64      CurrentTick;
 728   UINT64      ElapsedTick;
 729   UINT64      Frequency;
 730
 731   //
 732   // No matter what, always do a single poll.
 733   //
 734
 735   if (Result == NULL) {
 736     return EFI_INVALID_PARAMETER;
 737   }
 738
 739   if ((UINT32)Width > EfiPciWidthUint64) {
 740     return EFI_INVALID_PARAMETER;
 741   }
 742
 743   Status = This->Io.Read (This, Width, Address, 1, Result);
 744   if (EFI_ERROR (Status)) {
 745     return Status;
 746   }
 747   if ((*Result & Mask) == Value) {
 748     return EFI_SUCCESS;
 749   }
 750
 751   if (Delay == 0) {
 752     return EFI_SUCCESS;
 753
 754   } else {
 755     //
 756     // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
 757     //
 758     Frequency     = GetPerformanceCounterProperties (&StartTick, &EndTick);
 759     NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS(1), &Remainder);
 760     if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
 761       NumberOfTicks++;
 762     }
 763     for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter()
 764         ; ElapsedTick <= NumberOfTicks
 765         ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
 766         ) {
 767       Status = This->Io.Read (This, Width, Address, 1, Result);
 768       if (EFI_ERROR (Status)) {
 769         return Status;
 770       }
 771
 772       if ((*Result & Mask) == Value) {
 773         return EFI_SUCCESS;
 774       }
 775     }
 776   }
 777   return EFI_TIMEOUT;
 778 }
 779
 780 /**
 781   Enables a PCI driver to access PCI controller registers in the PCI root
 782   bridge memory space.
 783
 784   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
 785   controller registers in the PCI root bridge memory space.
 786   The memory operations are carried out exactly as requested. The caller is
 787   responsible for satisfying any alignment and memory width restrictions that a
 788   PCI Root Bridge on a platform might require.
 789
 790   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 791   @param[in]   Width     Signifies the width of the memory operation.
 792   @param[in]   Address   The base address of the memory operation. The caller
 793                          is responsible for aligning the Address if required.
 794   @param[in]   Count     The number of memory operations to perform. Bytes
 795                          moved is Width size * Count, starting at Address.
 796   @param[out]  Buffer    For read operations, the destination buffer to store
 797                          the results. For write operations, the source buffer
 798                          to write data from.
 799
 800   @retval EFI_SUCCESS            The data was read from or written to the PCI
 801                                  root bridge.
 802   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
 803   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 804   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 805                                  lack of resources.
 806 **/
 807 EFI_STATUS
 808 EFIAPI
 809 RootBridgeIoMemRead (
 810   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 811   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 812   IN     UINT64                                 Address,
 813   IN     UINTN                                  Count,
 814   OUT    VOID                                   *Buffer
 815   )
 816 {
 817   EFI_STATUS                             Status;
 818   PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;
 819   UINT64                                 Translation;
 820
 821   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
 822                                        Count, Buffer);
 823   if (EFI_ERROR (Status)) {
 824     return Status;
 825   }
 826
 827   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 828   Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
 829   if (EFI_ERROR (Status)) {
 830     return Status;
 831   }
 832
 833   // Address passed to CpuIo->Mem.Read needs to be a host address instead of
 834   // device address.
 835   return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
 836       TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
 837 }
 838
 839 /**
 840   Enables a PCI driver to access PCI controller registers in the PCI root
 841   bridge memory space.
 842
 843   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
 844   controller registers in the PCI root bridge memory space.
 845   The memory operations are carried out exactly as requested. The caller is
 846   responsible for satisfying any alignment and memory width restrictions that a
 847   PCI Root Bridge on a platform might require.
 848
 849   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 850   @param[in]   Width     Signifies the width of the memory operation.
 851   @param[in]   Address   The base address of the memory operation. The caller
 852                          is responsible for aligning the Address if required.
 853   @param[in]   Count     The number of memory operations to perform. Bytes
 854                          moved is Width size * Count, starting at Address.
 855   @param[in]   Buffer    For read operations, the destination buffer to store
 856                          the results. For write operations, the source buffer
 857                          to write data from.
 858
 859   @retval EFI_SUCCESS            The data was read from or written to the PCI
 860                                  root bridge.
 861   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
 862   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 863   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 864                                  lack of resources.
 865 **/
 866 EFI_STATUS
 867 EFIAPI
 868 RootBridgeIoMemWrite (
 869   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 870   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 871   IN     UINT64                                 Address,
 872   IN     UINTN                                  Count,
 873   IN     VOID                                   *Buffer
 874   )
 875 {
 876   EFI_STATUS                             Status;
 877   PCI_ROOT_BRIDGE_INSTANCE               *RootBridge;
 878   UINT64                                 Translation;
 879
 880   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
 881                                        Count, Buffer);
 882   if (EFI_ERROR (Status)) {
 883     return Status;
 884   }
 885
 886   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 887   Status = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
 888   if (EFI_ERROR (Status)) {
 889     return Status;
 890   }
 891
 892   // Address passed to CpuIo->Mem.Write needs to be a host address instead of
 893   // device address.
 894   return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
 895       TO_HOST_ADDRESS (Address, Translation), Count, Buffer);
 896 }
 897
 898 /**
 899   Enables a PCI driver to access PCI controller registers in the PCI root
 900   bridge I/O space.
 901
 902   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 903   @param[in]   Width       Signifies the width of the memory operations.
 904   @param[in]   Address     The base address of the I/O operation. The caller is
 905                            responsible for aligning the Address if required.
 906   @param[in]   Count       The number of I/O operations to perform. Bytes moved
 907                            is Width size * Count, starting at Address.
 908   @param[out]  Buffer      For read operations, the destination buffer to store
 909                            the results. For write operations, the source buffer
 910                            to write data from.
 911
 912   @retval EFI_SUCCESS              The data was read from or written to the PCI
 913                                    root bridge.
 914   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
 915   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
 916   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a
 917                                    lack of resources.
 918 **/
 919 EFI_STATUS
 920 EFIAPI
 921 RootBridgeIoIoRead (
 922   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 923   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 924   IN     UINT64                                 Address,
 925   IN     UINTN                                  Count,
 926   OUT    VOID                                   *Buffer
 927   )
 928 {
 929   EFI_STATUS                                    Status;
 930   PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;
 931
 932   Status = RootBridgeIoCheckParameter (
 933              This, IoOperation, Width,
 934              Address, Count, Buffer
 935              );
 936   if (EFI_ERROR (Status)) {
 937     return Status;
 938   }
 939
 940   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 941
 942   // Address passed to CpuIo->Io.Read needs to be a host address instead of
 943   // device address.
 944   return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
 945       TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
 946 }
 947
 948 /**
 949   Enables a PCI driver to access PCI controller registers in the PCI root
 950   bridge I/O space.
 951
 952   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 953   @param[in]   Width       Signifies the width of the memory operations.
 954   @param[in]   Address     The base address of the I/O operation. The caller is
 955                            responsible for aligning the Address if required.
 956   @param[in]   Count       The number of I/O operations to perform. Bytes moved
 957                            is Width size * Count, starting at Address.
 958   @param[in]   Buffer      For read operations, the destination buffer to store
 959                            the results. For write operations, the source buffer
 960                            to write data from.
 961
 962   @retval EFI_SUCCESS              The data was read from or written to the PCI
 963                                    root bridge.
 964   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
 965   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
 966   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a
 967                                    lack of resources.
 968 **/
 969 EFI_STATUS
 970 EFIAPI
 971 RootBridgeIoIoWrite (
 972   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *This,
 973   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,
 974   IN       UINT64                                  Address,
 975   IN       UINTN                                   Count,
 976   IN       VOID                                    *Buffer
 977   )
 978 {
 979   EFI_STATUS                                    Status;
 980   PCI_ROOT_BRIDGE_INSTANCE                      *RootBridge;
 981
 982   Status = RootBridgeIoCheckParameter (
 983              This, IoOperation, Width,
 984              Address, Count, Buffer
 985              );
 986   if (EFI_ERROR (Status)) {
 987     return Status;
 988   }
 989
 990   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 991
 992   // Address passed to CpuIo->Io.Write needs to be a host address instead of
 993   // device address.
 994   return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
 995       TO_HOST_ADDRESS (Address, RootBridge->Io.Translation), Count, Buffer);
 996 }
 997
 998 /**
 999   Enables a PCI driver to copy one region of PCI root bridge memory space to
1000   another region of PCI root bridge memory space.
1001
1002   The CopyMem() function enables a PCI driver to copy one region of PCI root
1003   bridge memory space to another region of PCI root bridge memory space. This
1004   is especially useful for video scroll operation on a memory mapped video
1005   buffer.
1006   The memory operations are carried out exactly as requested. The caller is
1007   responsible for satisfying any alignment and memory width restrictions that a
1008   PCI root bridge on a platform might require.
1009
1010   @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1011                          instance.
1012   @param[in] Width       Signifies the width of the memory operations.
1013   @param[in] DestAddress The destination address of the memory operation. The
1014                          caller is responsible for aligning the DestAddress if
1015                          required.
1016   @param[in] SrcAddress  The source address of the memory operation. The caller
1017                          is responsible for aligning the SrcAddress if
1018                          required.
1019   @param[in] Count       The number of memory operations to perform. Bytes
1020                          moved is Width size * Count, starting at DestAddress
1021                          and SrcAddress.
1022
1023   @retval  EFI_SUCCESS             The data was copied from one memory region
1024                                    to another memory region.
1025   @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.
1026   @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a
1027                                    lack of resources.
1028 **/
1029 EFI_STATUS
1030 EFIAPI
1031 RootBridgeIoCopyMem (
1032   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,
1033   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,
1034   IN UINT64                                       DestAddress,
1035   IN UINT64                                       SrcAddress,
1036   IN UINTN                                        Count
1037   )
1038 {
1039   EFI_STATUS  Status;
1040   BOOLEAN     Forward;
1041   UINTN       Stride;
1042   UINTN       Index;
1043   UINT64      Result;
1044
1045   if ((UINT32) Width > EfiPciWidthUint64) {
1046     return EFI_INVALID_PARAMETER;
1047   }
1048
1049   if (DestAddress == SrcAddress) {
1050     return EFI_SUCCESS;
1051   }
1052
1053   Stride = (UINTN) (1 << Width);
1054
1055   Forward = TRUE;
1056   if ((DestAddress > SrcAddress) &&
1057       (DestAddress < (SrcAddress + Count * Stride))) {
1058     Forward = FALSE;
1059     SrcAddress = SrcAddress + (Count - 1) * Stride;
1060     DestAddress = DestAddress + (Count - 1) * Stride;
1061   }
1062
1063   for (Index = 0; Index < Count; Index++) {
1064     Status = RootBridgeIoMemRead (
1065                This,
1066                Width,
1067                SrcAddress,
1068                1,
1069                &Result
1070                );
1071     if (EFI_ERROR (Status)) {
1072       return Status;
1073     }
1074     Status = RootBridgeIoMemWrite (
1075                This,
1076                Width,
1077                DestAddress,
1078                1,
1079                &Result
1080                );
1081     if (EFI_ERROR (Status)) {
1082       return Status;
1083     }
1084     if (Forward) {
1085       SrcAddress += Stride;
1086       DestAddress += Stride;
1087     } else {
1088       SrcAddress -= Stride;
1089       DestAddress -= Stride;
1090     }
1091   }
1092   return EFI_SUCCESS;
1093 }
1094
1095
1096 /**
1097   PCI configuration space access.
1098
1099   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1100   @param Read     TRUE indicating it's a read operation.
1101   @param Width    Signifies the width of the memory operation.
1102   @param Address  The address within the PCI configuration space
1103                   for the PCI controller.
1104   @param Count    The number of PCI configuration operations
1105                   to perform.
1106   @param Buffer   The destination buffer to store the results.
1107
1108   @retval EFI_SUCCESS            The data was read/written from/to the PCI root bridge.
1109   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1110 **/
1111 EFI_STATUS
1112 EFIAPI
1113 RootBridgeIoPciAccess (
1114   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
1115   IN     BOOLEAN                               Read,
1116   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
1117   IN     UINT64                                Address,
1118   IN     UINTN                                 Count,
1119   IN OUT VOID                                  *Buffer
1120   )
1121 {
1122   EFI_STATUS                                   Status;
1123   PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;
1124   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  PciAddress;
1125   UINT8                                        *Uint8Buffer;
1126   UINT8                                        InStride;
1127   UINT8                                        OutStride;
1128   UINTN                                        Size;
1129
1130   Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
1131   if (EFI_ERROR (Status)) {
1132     return Status;
1133   }
1134
1135   //
1136   // Read Pci configuration space
1137   //
1138   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1139   CopyMem (&PciAddress, &Address, sizeof (PciAddress));
1140
1141   if (PciAddress.ExtendedRegister == 0) {
1142     PciAddress.ExtendedRegister = PciAddress.Register;
1143   }
1144
1145   Address = PCI_SEGMENT_LIB_ADDRESS (
1146               RootBridge->RootBridgeIo.SegmentNumber,
1147               PciAddress.Bus,
1148               PciAddress.Device,
1149               PciAddress.Function,
1150               PciAddress.ExtendedRegister
1151               );
1152
1153   //
1154   // Select loop based on the width of the transfer
1155   //
1156   InStride  = mInStride[Width];
1157   OutStride = mOutStride[Width];
1158   Size      = (UINTN) (1 << (Width & 0x03));
1159   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
1160     if (Read) {
1161       PciSegmentReadBuffer (Address, Size, Uint8Buffer);
1162     } else {
1163       PciSegmentWriteBuffer (Address, Size, Uint8Buffer);
1164     }
1165   }
1166   return EFI_SUCCESS;
1167 }
1168
1169 /**
1170   Allows read from PCI configuration space.
1171
1172   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1173   @param Width    Signifies the width of the memory operation.
1174   @param Address  The address within the PCI configuration space
1175                   for the PCI controller.
1176   @param Count    The number of PCI configuration operations
1177                   to perform.
1178   @param Buffer   The destination buffer to store the results.
1179
1180   @retval EFI_SUCCESS           The data was read from the PCI root bridge.
1181   @retval EFI_INVALID_PARAMETER Invalid parameters found.
1182 **/
1183 EFI_STATUS
1184 EFIAPI
1185 RootBridgeIoPciRead (
1186   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
1187   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
1188   IN     UINT64                                Address,
1189   IN     UINTN                                 Count,
1190   IN OUT VOID                                  *Buffer
1191   )
1192 {
1193   return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);
1194 }
1195
1196 /**
1197   Allows write to PCI configuration space.
1198
1199   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1200   @param Width    Signifies the width of the memory operation.
1201   @param Address  The address within the PCI configuration space
1202                   for the PCI controller.
1203   @param Count    The number of PCI configuration operations
1204                   to perform.
1205   @param Buffer   The source buffer to get the results.
1206
1207   @retval EFI_SUCCESS            The data was written to the PCI root bridge.
1208   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1209 **/
1210 EFI_STATUS
1211 EFIAPI
1212 RootBridgeIoPciWrite (
1213   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
1214   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
1215   IN     UINT64                                Address,
1216   IN     UINTN                                 Count,
1217   IN OUT VOID                                  *Buffer
1218   )
1219 {
1220   return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);
1221 }
1222
1223 /**
1224   Provides the PCI controller-specific address needed to access
1225   system memory for DMA.
1226
1227   @param This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1228   @param Operation      Indicate if the bus master is going to read or write
1229                         to system memory.
1230   @param HostAddress    The system memory address to map on the PCI controller.
1231   @param NumberOfBytes  On input the number of bytes to map.
1232                         On output the number of bytes that were mapped.
1233   @param DeviceAddress  The resulting map address for the bus master PCI
1234                         controller to use to access the system memory's HostAddress.
1235   @param Mapping        The value to pass to Unmap() when the bus master DMA
1236                         operation is complete.
1237
1238   @retval EFI_SUCCESS            Success.
1239   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1240   @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.
1241   @retval EFI_DEVICE_ERROR       The System hardware could not map the requested address.
1242   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to lack of resources.
1243 **/
1244 EFI_STATUS
1245 EFIAPI
1246 RootBridgeIoMap (
1247   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
1248   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
1249   IN     VOID                                       *HostAddress,
1250   IN OUT UINTN                                      *NumberOfBytes,
1251   OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
1252   OUT    VOID                                       **Mapping
1253   )
1254 {
1255   EFI_STATUS                                        Status;
1256   PCI_ROOT_BRIDGE_INSTANCE                          *RootBridge;
1257   EFI_PHYSICAL_ADDRESS                              PhysicalAddress;
1258   MAP_INFO                                          *MapInfo;
1259
1260   if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
1261       Mapping == NULL) {
1262     return EFI_INVALID_PARAMETER;
1263   }
1264
1265   //
1266   // Make sure that Operation is valid
1267   //
1268   if ((UINT32) Operation >= EfiPciOperationMaximum) {
1269     return EFI_INVALID_PARAMETER;
1270   }
1271
1272   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1273
1274   if (mIoMmuProtocol != NULL) {
1275     if (!RootBridge->DmaAbove4G) {
1276       //
1277       // Clear 64bit support
1278       //
1279       if (Operation > EfiPciOperationBusMasterCommonBuffer) {
1280         Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - EfiPciOperationBusMasterRead64);
1281       }
1282     }
1283     Status = mIoMmuProtocol->Map (
1284                                mIoMmuProtocol,
1285                                (EDKII_IOMMU_OPERATION) Operation,
1286                                HostAddress,
1287                                NumberOfBytes,
1288                                DeviceAddress,
1289                                Mapping
1290                                );
1291     return Status;
1292   }
1293
1294   PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
1295   if ((!RootBridge->DmaAbove4G ||
1296        (Operation != EfiPciOperationBusMasterRead64 &&
1297         Operation != EfiPciOperationBusMasterWrite64 &&
1298         Operation != EfiPciOperationBusMasterCommonBuffer64)) &&
1299       ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) {
1300
1301     //
1302     // If the root bridge or the device cannot handle performing DMA above
1303     // 4GB but any part of the DMA transfer being mapped is above 4GB, then
1304     // map the DMA transfer to a buffer below 4GB.
1305     //
1306
1307     if (Operation == EfiPciOperationBusMasterCommonBuffer ||
1308         Operation == EfiPciOperationBusMasterCommonBuffer64) {
1309       //
1310       // Common Buffer operations can not be remapped.  If the common buffer
1311       // if above 4GB, then it is not possible to generate a mapping, so return
1312       // an error.
1313       //
1314       return EFI_UNSUPPORTED;
1315     }
1316
1317     //
1318     // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1319     // called later.
1320     //
1321     MapInfo = AllocatePool (sizeof (MAP_INFO));
1322     if (MapInfo == NULL) {
1323       *NumberOfBytes = 0;
1324       return EFI_OUT_OF_RESOURCES;
1325     }
1326
1327     //
1328     // Initialize the MAP_INFO structure
1329     //
1330     MapInfo->Signature         = MAP_INFO_SIGNATURE;
1331     MapInfo->Operation         = Operation;
1332     MapInfo->NumberOfBytes     = *NumberOfBytes;
1333     MapInfo->NumberOfPages     = EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes);
1334     MapInfo->HostAddress       = PhysicalAddress;
1335     MapInfo->MappedHostAddress = SIZE_4GB - 1;
1336
1337     //
1338     // Allocate a buffer below 4GB to map the transfer to.
1339     //
1340     Status = gBS->AllocatePages (
1341                     AllocateMaxAddress,
1342                     EfiBootServicesData,
1343                     MapInfo->NumberOfPages,
1344                     &MapInfo->MappedHostAddress
1345                     );
1346     if (EFI_ERROR (Status)) {
1347       FreePool (MapInfo);
1348       *NumberOfBytes = 0;
1349       return Status;
1350     }
1351
1352     //
1353     // If this is a read operation from the Bus Master's point of view,
1354     // then copy the contents of the real buffer into the mapped buffer
1355     // so the Bus Master can read the contents of the real buffer.
1356     //
1357     if (Operation == EfiPciOperationBusMasterRead ||
1358         Operation == EfiPciOperationBusMasterRead64) {
1359       CopyMem (
1360         (VOID *) (UINTN) MapInfo->MappedHostAddress,
1361         (VOID *) (UINTN) MapInfo->HostAddress,
1362         MapInfo->NumberOfBytes
1363         );
1364     }
1365
1366     InsertTailList (&RootBridge->Maps, &MapInfo->Link);
1367
1368     //
1369     // The DeviceAddress is the address of the maped buffer below 4GB
1370     //
1371     *DeviceAddress = MapInfo->MappedHostAddress;
1372     //
1373     // Return a pointer to the MAP_INFO structure in Mapping
1374     //
1375     *Mapping       = MapInfo;
1376   } else {
1377     //
1378     // If the root bridge CAN handle performing DMA above 4GB or
1379     // the transfer is below 4GB, so the DeviceAddress is simply the
1380     // HostAddress
1381     //
1382     *DeviceAddress = PhysicalAddress;
1383     *Mapping       = NO_MAPPING;
1384   }
1385
1386   return EFI_SUCCESS;
1387 }
1388
1389 /**
1390   Completes the Map() operation and releases any corresponding resources.
1391
1392   The Unmap() function completes the Map() operation and releases any
1393   corresponding resources.
1394   If the operation was an EfiPciOperationBusMasterWrite or
1395   EfiPciOperationBusMasterWrite64, the data is committed to the target system
1396   memory.
1397   Any resources used for the mapping are freed.
1398
1399   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1400   @param[in] Mapping   The mapping value returned from Map().
1401
1402   @retval EFI_SUCCESS            The range was unmapped.
1403   @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().
1404   @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.
1405 **/
1406 EFI_STATUS
1407 EFIAPI
1408 RootBridgeIoUnmap (
1409   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1410   IN VOID                             *Mapping
1411   )
1412 {
1413   MAP_INFO                 *MapInfo;
1414   LIST_ENTRY               *Link;
1415   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
1416   EFI_STATUS                Status;
1417
1418   if (mIoMmuProtocol != NULL) {
1419     Status = mIoMmuProtocol->Unmap (
1420                                mIoMmuProtocol,
1421                                Mapping
1422                                );
1423     return Status;
1424   }
1425
1426   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1427
1428   //
1429   // See if the Map() operation associated with this Unmap() required a mapping
1430   // buffer. If a mapping buffer was not required, then this function simply
1431   // returns EFI_SUCCESS.
1432   //
1433   if (Mapping == NO_MAPPING) {
1434     return EFI_SUCCESS;
1435   }
1436
1437   MapInfo = NO_MAPPING;
1438   for (Link = GetFirstNode (&RootBridge->Maps)
1439        ; !IsNull (&RootBridge->Maps, Link)
1440        ; Link = GetNextNode (&RootBridge->Maps, Link)
1441        ) {
1442     MapInfo = MAP_INFO_FROM_LINK (Link);
1443     if (MapInfo == Mapping) {
1444       break;
1445     }
1446   }
1447   //
1448   // Mapping is not a valid value returned by Map()
1449   //
1450   if (MapInfo != Mapping) {
1451     return EFI_INVALID_PARAMETER;
1452   }
1453   RemoveEntryList (&MapInfo->Link);
1454
1455   //
1456   // If this is a write operation from the Bus Master's point of view,
1457   // then copy the contents of the mapped buffer into the real buffer
1458   // so the processor can read the contents of the real buffer.
1459   //
1460   if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
1461       MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
1462     CopyMem (
1463       (VOID *) (UINTN) MapInfo->HostAddress,
1464       (VOID *) (UINTN) MapInfo->MappedHostAddress,
1465       MapInfo->NumberOfBytes
1466       );
1467   }
1468
1469   //
1470   // Free the mapped buffer and the MAP_INFO structure.
1471   //
1472   gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);
1473   FreePool (Mapping);
1474   return EFI_SUCCESS;
1475 }
1476
1477 /**
1478   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1479   or EfiPciOperationBusMasterCommonBuffer64 mapping.
1480
1481   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1482   @param Type        This parameter is not used and must be ignored.
1483   @param MemoryType  The type of memory to allocate, EfiBootServicesData or
1484                      EfiRuntimeServicesData.
1485   @param Pages       The number of pages to allocate.
1486   @param HostAddress A pointer to store the base system memory address of the
1487                      allocated range.
1488   @param Attributes  The requested bit mask of attributes for the allocated
1489                      range. Only the attributes
1490                      EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1491                      EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1492                      EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1493                      function.
1494
1495   @retval EFI_SUCCESS            The requested memory pages were allocated.
1496   @retval EFI_INVALID_PARAMETER  MemoryType is invalid.
1497   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.
1498   @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal
1499                                  attribute bits are MEMORY_WRITE_COMBINE,
1500                                  MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1501   @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.
1502 **/
1503 EFI_STATUS
1504 EFIAPI
1505 RootBridgeIoAllocateBuffer (
1506   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1507   IN  EFI_ALLOCATE_TYPE                Type,
1508   IN  EFI_MEMORY_TYPE                  MemoryType,
1509   IN  UINTN                            Pages,
1510   OUT VOID                             **HostAddress,
1511   IN  UINT64                           Attributes
1512   )
1513 {
1514   EFI_STATUS                Status;
1515   EFI_PHYSICAL_ADDRESS      PhysicalAddress;
1516   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1517   EFI_ALLOCATE_TYPE         AllocateType;
1518
1519   //
1520   // Validate Attributes
1521   //
1522   if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {
1523     return EFI_UNSUPPORTED;
1524   }
1525
1526   //
1527   // Check for invalid inputs
1528   //
1529   if (HostAddress == NULL) {
1530     return EFI_INVALID_PARAMETER;
1531   }
1532
1533   //
1534   // The only valid memory types are EfiBootServicesData and
1535   // EfiRuntimeServicesData
1536   //
1537   if (MemoryType != EfiBootServicesData &&
1538       MemoryType != EfiRuntimeServicesData) {
1539     return EFI_INVALID_PARAMETER;
1540   }
1541
1542   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1543
1544   if (mIoMmuProtocol != NULL) {
1545     if (!RootBridge->DmaAbove4G) {
1546       //
1547       // Clear DUAL_ADDRESS_CYCLE
1548       //
1549       Attributes &= ~((UINT64) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
1550     }
1551     Status = mIoMmuProtocol->AllocateBuffer (
1552                                mIoMmuProtocol,
1553                                Type,
1554                                MemoryType,
1555                                Pages,
1556                                HostAddress,
1557                                Attributes
1558                                );
1559     return Status;
1560   }
1561
1562   AllocateType = AllocateAnyPages;
1563   if (!RootBridge->DmaAbove4G ||
1564       (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {
1565     //
1566     // Limit allocations to memory below 4GB
1567     //
1568     AllocateType    = AllocateMaxAddress;
1569     PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (SIZE_4GB - 1);
1570   }
1571   Status = gBS->AllocatePages (
1572                   AllocateType,
1573                   MemoryType,
1574                   Pages,
1575                   &PhysicalAddress
1576                   );
1577   if (!EFI_ERROR (Status)) {
1578     *HostAddress = (VOID *) (UINTN) PhysicalAddress;
1579   }
1580
1581   return Status;
1582 }
1583
1584 /**
1585   Frees memory that was allocated with AllocateBuffer().
1586
1587   The FreeBuffer() function frees memory that was allocated with
1588   AllocateBuffer().
1589
1590   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1591   @param Pages       The number of pages to free.
1592   @param HostAddress The base system memory address of the allocated range.
1593
1594   @retval EFI_SUCCESS            The requested memory pages were freed.
1595   @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and
1596                                  Pages was not allocated with AllocateBuffer().
1597 **/
1598 EFI_STATUS
1599 EFIAPI
1600 RootBridgeIoFreeBuffer (
1601   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1602   IN  UINTN                            Pages,
1603   OUT VOID                             *HostAddress
1604   )
1605 {
1606   EFI_STATUS                Status;
1607
1608   if (mIoMmuProtocol != NULL) {
1609     Status = mIoMmuProtocol->FreeBuffer (
1610                                mIoMmuProtocol,
1611                                Pages,
1612                                HostAddress
1613                                );
1614     return Status;
1615   }
1616
1617   return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);
1618 }
1619
1620 /**
1621   Flushes all PCI posted write transactions from a PCI host bridge to system
1622   memory.
1623
1624   The Flush() function flushes any PCI posted write transactions from a PCI
1625   host bridge to system memory. Posted write transactions are generated by PCI
1626   bus masters when they perform write transactions to target addresses in
1627   system memory.
1628   This function does not flush posted write transactions from any PCI bridges.
1629   A PCI controller specific action must be taken to guarantee that the posted
1630   write transactions have been flushed from the PCI controller and from all the
1631   PCI bridges into the PCI host bridge. This is typically done with a PCI read
1632   transaction from the PCI controller prior to calling Flush().
1633
1634   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1635
1636   @retval EFI_SUCCESS        The PCI posted write transactions were flushed
1637                              from the PCI host bridge to system memory.
1638   @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed
1639                              from the PCI host bridge due to a hardware error.
1640 **/
1641 EFI_STATUS
1642 EFIAPI
1643 RootBridgeIoFlush (
1644   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This
1645   )
1646 {
1647   return EFI_SUCCESS;
1648 }
1649
1650 /**
1651   Gets the attributes that a PCI root bridge supports setting with
1652   SetAttributes(), and the attributes that a PCI root bridge is currently
1653   using.
1654
1655   The GetAttributes() function returns the mask of attributes that this PCI
1656   root bridge supports and the mask of attributes that the PCI root bridge is
1657   currently using.
1658
1659   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1660   @param Supported   A pointer to the mask of attributes that this PCI root
1661                      bridge supports setting with SetAttributes().
1662   @param Attributes  A pointer to the mask of attributes that this PCI root
1663                      bridge is currently using.
1664
1665   @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes
1666                                  that the PCI root bridge supports is returned
1667                                  in Supports. If Attributes is not NULL, then
1668                                  the attributes that the PCI root bridge is
1669                                  currently using is returned in Attributes.
1670   @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1671 **/
1672 EFI_STATUS
1673 EFIAPI
1674 RootBridgeIoGetAttributes (
1675   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1676   OUT UINT64                           *Supported,
1677   OUT UINT64                           *Attributes
1678   )
1679 {
1680   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
1681
1682   if (Attributes == NULL && Supported == NULL) {
1683     return EFI_INVALID_PARAMETER;
1684   }
1685
1686   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1687   //
1688   // Set the return value for Supported and Attributes
1689   //
1690   if (Supported != NULL) {
1691     *Supported  = RootBridge->Supports;
1692   }
1693
1694   if (Attributes != NULL) {
1695     *Attributes = RootBridge->Attributes;
1696   }
1697
1698   return EFI_SUCCESS;
1699 }
1700
1701 /**
1702   Sets attributes for a resource range on a PCI root bridge.
1703
1704   The SetAttributes() function sets the attributes specified in Attributes for
1705   the PCI root bridge on the resource range specified by ResourceBase and
1706   ResourceLength. Since the granularity of setting these attributes may vary
1707   from resource type to resource type, and from platform to platform, the
1708   actual resource range and the one passed in by the caller may differ. As a
1709   result, this function may set the attributes specified by Attributes on a
1710   larger resource range than the caller requested. The actual range is returned
1711   in ResourceBase and ResourceLength. The caller is responsible for verifying
1712   that the actual range for which the attributes were set is acceptable.
1713
1714   @param This            A pointer to the
1715                          EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1716   @param Attributes      The mask of attributes to set. If the
1717                          attribute bit MEMORY_WRITE_COMBINE,
1718                          MEMORY_CACHED, or MEMORY_DISABLE is set,
1719                          then the resource range is specified by
1720                          ResourceBase and ResourceLength. If
1721                          MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1722                          MEMORY_DISABLE are not set, then
1723                          ResourceBase and ResourceLength are ignored,
1724                          and may be NULL.
1725   @param ResourceBase    A pointer to the base address of the
1726                          resource range to be modified by the
1727                          attributes specified by Attributes.
1728   @param ResourceLength  A pointer to the length of the resource
1729                                    range to be modified by the attributes
1730                                    specified by Attributes.
1731
1732   @retval  EFI_SUCCESS           The current configuration of this PCI root bridge
1733                                  was returned in Resources.
1734   @retval  EFI_UNSUPPORTED       The current configuration of this PCI root bridge
1735                                  could not be retrieved.
1736 **/
1737 EFI_STATUS
1738 EFIAPI
1739 RootBridgeIoSetAttributes (
1740   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1741   IN     UINT64                           Attributes,
1742   IN OUT UINT64                           *ResourceBase,
1743   IN OUT UINT64                           *ResourceLength
1744   )
1745 {
1746   PCI_ROOT_BRIDGE_INSTANCE            *RootBridge;
1747
1748   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1749
1750   if ((Attributes & (~RootBridge->Supports)) != 0) {
1751     return EFI_UNSUPPORTED;
1752   }
1753
1754   RootBridge->Attributes = Attributes;
1755   return EFI_SUCCESS;
1756 }
1757
1758 /**
1759   Retrieves the current resource settings of this PCI root bridge in the form
1760   of a set of ACPI resource descriptors.
1761
1762   There are only two resource descriptor types from the ACPI Specification that
1763   may be used to describe the current resources allocated to a PCI root bridge.
1764   These are the QWORD Address Space Descriptor, and the End Tag. The QWORD
1765   Address Space Descriptor can describe memory, I/O, and bus number ranges for
1766   dynamic or fixed resources. The configuration of a PCI root bridge is described
1767   with one or more QWORD Address Space Descriptors followed by an End Tag.
1768
1769   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1770   @param[out]  Resources   A pointer to the resource descriptors that
1771                            describe the current configuration of this PCI root
1772                            bridge. The storage for the resource
1773                            descriptors is allocated by this function. The
1774                            caller must treat the return buffer as read-only
1775                            data, and the buffer must not be freed by the
1776                            caller.
1777
1778   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge
1779                            was returned in Resources.
1780   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge
1781                            could not be retrieved.
1782 **/
1783 EFI_STATUS
1784 EFIAPI
1785 RootBridgeIoConfiguration (
1786   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *This,
1787   OUT VOID                                **Resources
1788   )
1789 {
1790   PCI_RESOURCE_TYPE                 Index;
1791   PCI_ROOT_BRIDGE_INSTANCE          *RootBridge;
1792   PCI_RES_NODE                      *ResAllocNode;
1793   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
1794   EFI_ACPI_END_TAG_DESCRIPTOR       *End;
1795
1796   //
1797   // Get this instance of the Root Bridge.
1798   //
1799   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1800   ZeroMem (
1801     RootBridge->ConfigBuffer,
1802     TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
1803     );
1804   Descriptor = RootBridge->ConfigBuffer;
1805   for (Index = TypeIo; Index < TypeMax; Index++) {
1806
1807     ResAllocNode = &RootBridge->ResAllocNode[Index];
1808
1809     if (ResAllocNode->Status != ResAllocated) {
1810       continue;
1811     }
1812
1813     Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1814     Descriptor->Len  = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1815     // According to UEFI 2.7, RootBridgeIo->Configuration should return address
1816     // range in CPU view (host address), and ResAllocNode->Base is already a CPU
1817     // view address (host address).
1818     Descriptor->AddrRangeMin  = ResAllocNode->Base;
1819     Descriptor->AddrRangeMax  = ResAllocNode->Base + ResAllocNode->Length - 1;
1820     Descriptor->AddrLen       = ResAllocNode->Length;
1821     Descriptor->AddrTranslationOffset = GetTranslationByResourceType (
1822       RootBridge,
1823       ResAllocNode->Type
1824       );
1825
1826     switch (ResAllocNode->Type) {
1827
1828     case TypeIo:
1829       Descriptor->ResType       = ACPI_ADDRESS_SPACE_TYPE_IO;
1830       break;
1831
1832     case TypePMem32:
1833       Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1834     case TypeMem32:
1835       Descriptor->ResType               = ACPI_ADDRESS_SPACE_TYPE_MEM;
1836       Descriptor->AddrSpaceGranularity  = 32;
1837       break;
1838
1839     case TypePMem64:
1840       Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1841     case TypeMem64:
1842       Descriptor->ResType               = ACPI_ADDRESS_SPACE_TYPE_MEM;
1843       Descriptor->AddrSpaceGranularity  = 64;
1844       break;
1845
1846     case TypeBus:
1847       Descriptor->ResType       = ACPI_ADDRESS_SPACE_TYPE_BUS;
1848       break;
1849
1850     default:
1851       break;
1852     }
1853
1854     Descriptor++;
1855   }
1856   //
1857   // Terminate the entries.
1858   //
1859   End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
1860   End->Desc     = ACPI_END_TAG_DESCRIPTOR;
1861   End->Checksum = 0x0;
1862
1863   *Resources = RootBridge->ConfigBuffer;
1864   return EFI_SUCCESS;
1865 }