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UefiCpuPkg/PiSmmCpuDxeSmm: Pre-allocate PROCEDURE_TOKEN buffer
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
5 4.20.
6
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
8
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
12
13 **/
14
15 #include "SdMmcPciHcDxe.h"
16
17 /**
18 Dump the content of SD/MMC host controller's Capability Register.
19
20 @param[in] Slot The slot number of the SD card to send the command to.
21 @param[in] Capability The buffer to store the capability data.
22
23 **/
24 VOID
25 DumpCapabilityReg (
26 IN UINT8 Slot,
27 IN SD_MMC_HC_SLOT_CAP *Capability
28 )
29 {
30 //
31 // Dump Capability Data
32 //
33 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
34 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
35 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
36 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
37 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
38 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
39 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
40 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " SlotType "));
49 if (Capability->SlotType == 0x00) {
50 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
51 } else if (Capability->SlotType == 0x01) {
52 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
53 } else if (Capability->SlotType == 0x02) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
55 } else {
56 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
57 }
58 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
59 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
60 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
65 if (Capability->TimerCount == 0) {
66 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
67 } else {
68 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
69 }
70 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
71 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
72 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
73 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
74 return;
75 }
76
77 /**
78 Read SlotInfo register from SD/MMC host controller pci config space.
79
80 @param[in] PciIo The PCI IO protocol instance.
81 @param[out] FirstBar The buffer to store the first BAR value.
82 @param[out] SlotNum The buffer to store the supported slot number.
83
84 @retval EFI_SUCCESS The operation succeeds.
85 @retval Others The operation fails.
86
87 **/
88 EFI_STATUS
89 EFIAPI
90 SdMmcHcGetSlotInfo (
91 IN EFI_PCI_IO_PROTOCOL *PciIo,
92 OUT UINT8 *FirstBar,
93 OUT UINT8 *SlotNum
94 )
95 {
96 EFI_STATUS Status;
97 SD_MMC_HC_SLOT_INFO SlotInfo;
98
99 Status = PciIo->Pci.Read (
100 PciIo,
101 EfiPciIoWidthUint8,
102 SD_MMC_HC_SLOT_OFFSET,
103 sizeof (SlotInfo),
104 &SlotInfo
105 );
106 if (EFI_ERROR (Status)) {
107 return Status;
108 }
109
110 *FirstBar = SlotInfo.FirstBar;
111 *SlotNum = SlotInfo.SlotNum + 1;
112 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
113 return EFI_SUCCESS;
114 }
115
116 /**
117 Read/Write specified SD/MMC host controller mmio register.
118
119 @param[in] PciIo The PCI IO protocol instance.
120 @param[in] BarIndex The BAR index of the standard PCI Configuration
121 header to use as the base address for the memory
122 operation to perform.
123 @param[in] Offset The offset within the selected BAR to start the
124 memory operation.
125 @param[in] Read A boolean to indicate it's read or write operation.
126 @param[in] Count The width of the mmio register in bytes.
127 Must be 1, 2 , 4 or 8 bytes.
128 @param[in, out] Data For read operations, the destination buffer to store
129 the results. For write operations, the source buffer
130 to write data from. The caller is responsible for
131 having ownership of the data buffer and ensuring its
132 size not less than Count bytes.
133
134 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
135 @retval EFI_SUCCESS The read/write operation succeeds.
136 @retval Others The read/write operation fails.
137
138 **/
139 EFI_STATUS
140 EFIAPI
141 SdMmcHcRwMmio (
142 IN EFI_PCI_IO_PROTOCOL *PciIo,
143 IN UINT8 BarIndex,
144 IN UINT32 Offset,
145 IN BOOLEAN Read,
146 IN UINT8 Count,
147 IN OUT VOID *Data
148 )
149 {
150 EFI_STATUS Status;
151 EFI_PCI_IO_PROTOCOL_WIDTH Width;
152
153 if ((PciIo == NULL) || (Data == NULL)) {
154 return EFI_INVALID_PARAMETER;
155 }
156
157 switch (Count) {
158 case 1:
159 Width = EfiPciIoWidthUint8;
160 break;
161 case 2:
162 Width = EfiPciIoWidthUint16;
163 Count = 1;
164 break;
165 case 4:
166 Width = EfiPciIoWidthUint32;
167 Count = 1;
168 break;
169 case 8:
170 Width = EfiPciIoWidthUint32;
171 Count = 2;
172 break;
173 default:
174 return EFI_INVALID_PARAMETER;
175 }
176
177 if (Read) {
178 Status = PciIo->Mem.Read (
179 PciIo,
180 Width,
181 BarIndex,
182 (UINT64) Offset,
183 Count,
184 Data
185 );
186 } else {
187 Status = PciIo->Mem.Write (
188 PciIo,
189 Width,
190 BarIndex,
191 (UINT64) Offset,
192 Count,
193 Data
194 );
195 }
196
197 return Status;
198 }
199
200 /**
201 Do OR operation with the value of the specified SD/MMC host controller mmio register.
202
203 @param[in] PciIo The PCI IO protocol instance.
204 @param[in] BarIndex The BAR index of the standard PCI Configuration
205 header to use as the base address for the memory
206 operation to perform.
207 @param[in] Offset The offset within the selected BAR to start the
208 memory operation.
209 @param[in] Count The width of the mmio register in bytes.
210 Must be 1, 2 , 4 or 8 bytes.
211 @param[in] OrData The pointer to the data used to do OR operation.
212 The caller is responsible for having ownership of
213 the data buffer and ensuring its size not less than
214 Count bytes.
215
216 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
217 @retval EFI_SUCCESS The OR operation succeeds.
218 @retval Others The OR operation fails.
219
220 **/
221 EFI_STATUS
222 EFIAPI
223 SdMmcHcOrMmio (
224 IN EFI_PCI_IO_PROTOCOL *PciIo,
225 IN UINT8 BarIndex,
226 IN UINT32 Offset,
227 IN UINT8 Count,
228 IN VOID *OrData
229 )
230 {
231 EFI_STATUS Status;
232 UINT64 Data;
233 UINT64 Or;
234
235 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
236 if (EFI_ERROR (Status)) {
237 return Status;
238 }
239
240 if (Count == 1) {
241 Or = *(UINT8*) OrData;
242 } else if (Count == 2) {
243 Or = *(UINT16*) OrData;
244 } else if (Count == 4) {
245 Or = *(UINT32*) OrData;
246 } else if (Count == 8) {
247 Or = *(UINT64*) OrData;
248 } else {
249 return EFI_INVALID_PARAMETER;
250 }
251
252 Data |= Or;
253 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
254
255 return Status;
256 }
257
258 /**
259 Do AND operation with the value of the specified SD/MMC host controller mmio register.
260
261 @param[in] PciIo The PCI IO protocol instance.
262 @param[in] BarIndex The BAR index of the standard PCI Configuration
263 header to use as the base address for the memory
264 operation to perform.
265 @param[in] Offset The offset within the selected BAR to start the
266 memory operation.
267 @param[in] Count The width of the mmio register in bytes.
268 Must be 1, 2 , 4 or 8 bytes.
269 @param[in] AndData The pointer to the data used to do AND operation.
270 The caller is responsible for having ownership of
271 the data buffer and ensuring its size not less than
272 Count bytes.
273
274 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
275 @retval EFI_SUCCESS The AND operation succeeds.
276 @retval Others The AND operation fails.
277
278 **/
279 EFI_STATUS
280 EFIAPI
281 SdMmcHcAndMmio (
282 IN EFI_PCI_IO_PROTOCOL *PciIo,
283 IN UINT8 BarIndex,
284 IN UINT32 Offset,
285 IN UINT8 Count,
286 IN VOID *AndData
287 )
288 {
289 EFI_STATUS Status;
290 UINT64 Data;
291 UINT64 And;
292
293 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
294 if (EFI_ERROR (Status)) {
295 return Status;
296 }
297
298 if (Count == 1) {
299 And = *(UINT8*) AndData;
300 } else if (Count == 2) {
301 And = *(UINT16*) AndData;
302 } else if (Count == 4) {
303 And = *(UINT32*) AndData;
304 } else if (Count == 8) {
305 And = *(UINT64*) AndData;
306 } else {
307 return EFI_INVALID_PARAMETER;
308 }
309
310 Data &= And;
311 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
312
313 return Status;
314 }
315
316 /**
317 Wait for the value of the specified MMIO register set to the test value.
318
319 @param[in] PciIo The PCI IO protocol instance.
320 @param[in] BarIndex The BAR index of the standard PCI Configuration
321 header to use as the base address for the memory
322 operation to perform.
323 @param[in] Offset The offset within the selected BAR to start the
324 memory operation.
325 @param[in] Count The width of the mmio register in bytes.
326 Must be 1, 2, 4 or 8 bytes.
327 @param[in] MaskValue The mask value of memory.
328 @param[in] TestValue The test value of memory.
329
330 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
331 @retval EFI_SUCCESS The MMIO register has expected value.
332 @retval Others The MMIO operation fails.
333
334 **/
335 EFI_STATUS
336 EFIAPI
337 SdMmcHcCheckMmioSet (
338 IN EFI_PCI_IO_PROTOCOL *PciIo,
339 IN UINT8 BarIndex,
340 IN UINT32 Offset,
341 IN UINT8 Count,
342 IN UINT64 MaskValue,
343 IN UINT64 TestValue
344 )
345 {
346 EFI_STATUS Status;
347 UINT64 Value;
348
349 //
350 // Access PCI MMIO space to see if the value is the tested one.
351 //
352 Value = 0;
353 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
354 if (EFI_ERROR (Status)) {
355 return Status;
356 }
357
358 Value &= MaskValue;
359
360 if (Value == TestValue) {
361 return EFI_SUCCESS;
362 }
363
364 return EFI_NOT_READY;
365 }
366
367 /**
368 Wait for the value of the specified MMIO register set to the test value.
369
370 @param[in] PciIo The PCI IO protocol instance.
371 @param[in] BarIndex The BAR index of the standard PCI Configuration
372 header to use as the base address for the memory
373 operation to perform.
374 @param[in] Offset The offset within the selected BAR to start the
375 memory operation.
376 @param[in] Count The width of the mmio register in bytes.
377 Must be 1, 2, 4 or 8 bytes.
378 @param[in] MaskValue The mask value of memory.
379 @param[in] TestValue The test value of memory.
380 @param[in] Timeout The time out value for wait memory set, uses 1
381 microsecond as a unit.
382
383 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
384 range.
385 @retval EFI_SUCCESS The MMIO register has expected value.
386 @retval Others The MMIO operation fails.
387
388 **/
389 EFI_STATUS
390 EFIAPI
391 SdMmcHcWaitMmioSet (
392 IN EFI_PCI_IO_PROTOCOL *PciIo,
393 IN UINT8 BarIndex,
394 IN UINT32 Offset,
395 IN UINT8 Count,
396 IN UINT64 MaskValue,
397 IN UINT64 TestValue,
398 IN UINT64 Timeout
399 )
400 {
401 EFI_STATUS Status;
402 BOOLEAN InfiniteWait;
403
404 if (Timeout == 0) {
405 InfiniteWait = TRUE;
406 } else {
407 InfiniteWait = FALSE;
408 }
409
410 while (InfiniteWait || (Timeout > 0)) {
411 Status = SdMmcHcCheckMmioSet (
412 PciIo,
413 BarIndex,
414 Offset,
415 Count,
416 MaskValue,
417 TestValue
418 );
419 if (Status != EFI_NOT_READY) {
420 return Status;
421 }
422
423 //
424 // Stall for 1 microsecond.
425 //
426 gBS->Stall (1);
427
428 Timeout--;
429 }
430
431 return EFI_TIMEOUT;
432 }
433
434 /**
435 Get the controller version information from the specified slot.
436
437 @param[in] PciIo The PCI IO protocol instance.
438 @param[in] Slot The slot number of the SD card to send the command to.
439 @param[out] Version The buffer to store the version information.
440
441 @retval EFI_SUCCESS The operation executes successfully.
442 @retval Others The operation fails.
443
444 **/
445 EFI_STATUS
446 SdMmcHcGetControllerVersion (
447 IN EFI_PCI_IO_PROTOCOL *PciIo,
448 IN UINT8 Slot,
449 OUT UINT16 *Version
450 )
451 {
452 EFI_STATUS Status;
453
454 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
455 if (EFI_ERROR (Status)) {
456 return Status;
457 }
458
459 *Version &= 0xFF;
460
461 return EFI_SUCCESS;
462 }
463
464 /**
465 Software reset the specified SD/MMC host controller and enable all interrupts.
466
467 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
468 @param[in] Slot The slot number of the SD card to send the command to.
469
470 @retval EFI_SUCCESS The software reset executes successfully.
471 @retval Others The software reset fails.
472
473 **/
474 EFI_STATUS
475 SdMmcHcReset (
476 IN SD_MMC_HC_PRIVATE_DATA *Private,
477 IN UINT8 Slot
478 )
479 {
480 EFI_STATUS Status;
481 UINT8 SwReset;
482 EFI_PCI_IO_PROTOCOL *PciIo;
483
484 //
485 // Notify the SD/MMC override protocol that we are about to reset
486 // the SD/MMC host controller.
487 //
488 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
489 Status = mOverride->NotifyPhase (
490 Private->ControllerHandle,
491 Slot,
492 EdkiiSdMmcResetPre,
493 NULL);
494 if (EFI_ERROR (Status)) {
495 DEBUG ((DEBUG_WARN,
496 "%a: SD/MMC pre reset notifier callback failed - %r\n",
497 __FUNCTION__, Status));
498 return Status;
499 }
500 }
501
502 PciIo = Private->PciIo;
503 SwReset = BIT0;
504 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
505
506 if (EFI_ERROR (Status)) {
507 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
508 return Status;
509 }
510
511 Status = SdMmcHcWaitMmioSet (
512 PciIo,
513 Slot,
514 SD_MMC_HC_SW_RST,
515 sizeof (SwReset),
516 BIT0,
517 0x00,
518 SD_MMC_HC_GENERIC_TIMEOUT
519 );
520 if (EFI_ERROR (Status)) {
521 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
522 return Status;
523 }
524
525 //
526 // Enable all interrupt after reset all.
527 //
528 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
529 if (EFI_ERROR (Status)) {
530 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
531 Status));
532 return Status;
533 }
534
535 //
536 // Notify the SD/MMC override protocol that we have just reset
537 // the SD/MMC host controller.
538 //
539 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
540 Status = mOverride->NotifyPhase (
541 Private->ControllerHandle,
542 Slot,
543 EdkiiSdMmcResetPost,
544 NULL);
545 if (EFI_ERROR (Status)) {
546 DEBUG ((DEBUG_WARN,
547 "%a: SD/MMC post reset notifier callback failed - %r\n",
548 __FUNCTION__, Status));
549 }
550 }
551
552 return Status;
553 }
554
555 /**
556 Set all interrupt status bits in Normal and Error Interrupt Status Enable
557 register.
558
559 @param[in] PciIo The PCI IO protocol instance.
560 @param[in] Slot The slot number of the SD card to send the command to.
561
562 @retval EFI_SUCCESS The operation executes successfully.
563 @retval Others The operation fails.
564
565 **/
566 EFI_STATUS
567 SdMmcHcEnableInterrupt (
568 IN EFI_PCI_IO_PROTOCOL *PciIo,
569 IN UINT8 Slot
570 )
571 {
572 EFI_STATUS Status;
573 UINT16 IntStatus;
574
575 //
576 // Enable all bits in Error Interrupt Status Enable Register
577 //
578 IntStatus = 0xFFFF;
579 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
580 if (EFI_ERROR (Status)) {
581 return Status;
582 }
583 //
584 // Enable all bits in Normal Interrupt Status Enable Register
585 //
586 IntStatus = 0xFFFF;
587 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
588
589 return Status;
590 }
591
592 /**
593 Get the capability data from the specified slot.
594
595 @param[in] PciIo The PCI IO protocol instance.
596 @param[in] Slot The slot number of the SD card to send the command to.
597 @param[out] Capability The buffer to store the capability data.
598
599 @retval EFI_SUCCESS The operation executes successfully.
600 @retval Others The operation fails.
601
602 **/
603 EFI_STATUS
604 SdMmcHcGetCapability (
605 IN EFI_PCI_IO_PROTOCOL *PciIo,
606 IN UINT8 Slot,
607 OUT SD_MMC_HC_SLOT_CAP *Capability
608 )
609 {
610 EFI_STATUS Status;
611 UINT64 Cap;
612
613 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
614 if (EFI_ERROR (Status)) {
615 return Status;
616 }
617
618 CopyMem (Capability, &Cap, sizeof (Cap));
619
620 return EFI_SUCCESS;
621 }
622
623 /**
624 Get the maximum current capability data from the specified slot.
625
626 @param[in] PciIo The PCI IO protocol instance.
627 @param[in] Slot The slot number of the SD card to send the command to.
628 @param[out] MaxCurrent The buffer to store the maximum current capability data.
629
630 @retval EFI_SUCCESS The operation executes successfully.
631 @retval Others The operation fails.
632
633 **/
634 EFI_STATUS
635 SdMmcHcGetMaxCurrent (
636 IN EFI_PCI_IO_PROTOCOL *PciIo,
637 IN UINT8 Slot,
638 OUT UINT64 *MaxCurrent
639 )
640 {
641 EFI_STATUS Status;
642
643 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
644
645 return Status;
646 }
647
648 /**
649 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
650 slot.
651
652 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
653
654 @param[in] PciIo The PCI IO protocol instance.
655 @param[in] Slot The slot number of the SD card to send the command to.
656 @param[out] MediaPresent The pointer to the media present boolean value.
657
658 @retval EFI_SUCCESS There is no media change happened.
659 @retval EFI_MEDIA_CHANGED There is media change happened.
660 @retval Others The detection fails.
661
662 **/
663 EFI_STATUS
664 SdMmcHcCardDetect (
665 IN EFI_PCI_IO_PROTOCOL *PciIo,
666 IN UINT8 Slot,
667 OUT BOOLEAN *MediaPresent
668 )
669 {
670 EFI_STATUS Status;
671 UINT16 Data;
672 UINT32 PresentState;
673
674 //
675 // Check Present State Register to see if there is a card presented.
676 //
677 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
678 if (EFI_ERROR (Status)) {
679 return Status;
680 }
681
682 if ((PresentState & BIT16) != 0) {
683 *MediaPresent = TRUE;
684 } else {
685 *MediaPresent = FALSE;
686 }
687
688 //
689 // Check Normal Interrupt Status Register
690 //
691 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
692 if (EFI_ERROR (Status)) {
693 return Status;
694 }
695
696 if ((Data & (BIT6 | BIT7)) != 0) {
697 //
698 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
699 //
700 Data &= BIT6 | BIT7;
701 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
702 if (EFI_ERROR (Status)) {
703 return Status;
704 }
705
706 return EFI_MEDIA_CHANGED;
707 }
708
709 return EFI_SUCCESS;
710 }
711
712 /**
713 Stop SD/MMC card clock.
714
715 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
716
717 @param[in] PciIo The PCI IO protocol instance.
718 @param[in] Slot The slot number of the SD card to send the command to.
719
720 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
721 @retval Others Fail to stop SD/MMC clock.
722
723 **/
724 EFI_STATUS
725 SdMmcHcStopClock (
726 IN EFI_PCI_IO_PROTOCOL *PciIo,
727 IN UINT8 Slot
728 )
729 {
730 EFI_STATUS Status;
731 UINT32 PresentState;
732 UINT16 ClockCtrl;
733
734 //
735 // Ensure no SD transactions are occurring on the SD Bus by
736 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
737 // in the Present State register to be 0.
738 //
739 Status = SdMmcHcWaitMmioSet (
740 PciIo,
741 Slot,
742 SD_MMC_HC_PRESENT_STATE,
743 sizeof (PresentState),
744 BIT0 | BIT1,
745 0,
746 SD_MMC_HC_GENERIC_TIMEOUT
747 );
748 if (EFI_ERROR (Status)) {
749 return Status;
750 }
751
752 //
753 // Set SD Clock Enable in the Clock Control register to 0
754 //
755 ClockCtrl = (UINT16)~BIT2;
756 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
757
758 return Status;
759 }
760
761 /**
762 SD/MMC card clock supply.
763
764 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
765
766 @param[in] PciIo The PCI IO protocol instance.
767 @param[in] Slot The slot number of the SD card to send the command to.
768 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
769 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
770 @param[in] ControllerVer The version of host controller.
771
772 @retval EFI_SUCCESS The clock is supplied successfully.
773 @retval Others The clock isn't supplied successfully.
774
775 **/
776 EFI_STATUS
777 SdMmcHcClockSupply (
778 IN EFI_PCI_IO_PROTOCOL *PciIo,
779 IN UINT8 Slot,
780 IN UINT64 ClockFreq,
781 IN UINT32 BaseClkFreq,
782 IN UINT16 ControllerVer
783 )
784 {
785 EFI_STATUS Status;
786 UINT32 SettingFreq;
787 UINT32 Divisor;
788 UINT32 Remainder;
789 UINT16 ClockCtrl;
790
791 //
792 // Calculate a divisor for SD clock frequency
793 //
794 ASSERT (BaseClkFreq != 0);
795
796 if (ClockFreq == 0) {
797 return EFI_INVALID_PARAMETER;
798 }
799
800 if (ClockFreq > (BaseClkFreq * 1000)) {
801 ClockFreq = BaseClkFreq * 1000;
802 }
803
804 //
805 // Calculate the divisor of base frequency.
806 //
807 Divisor = 0;
808 SettingFreq = BaseClkFreq * 1000;
809 while (ClockFreq < SettingFreq) {
810 Divisor++;
811
812 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
813 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
814 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
815 break;
816 }
817 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
818 SettingFreq ++;
819 }
820 }
821
822 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
823
824 //
825 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
826 //
827 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
828 (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {
829 ASSERT (Divisor <= 0x3FF);
830 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
831 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
832 (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {
833 //
834 // Only the most significant bit can be used as divisor.
835 //
836 if (((Divisor - 1) & Divisor) != 0) {
837 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
838 }
839 ASSERT (Divisor <= 0x80);
840 ClockCtrl = (Divisor & 0xFF) << 8;
841 } else {
842 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
843 return EFI_UNSUPPORTED;
844 }
845
846 //
847 // Stop bus clock at first
848 //
849 Status = SdMmcHcStopClock (PciIo, Slot);
850 if (EFI_ERROR (Status)) {
851 return Status;
852 }
853
854 //
855 // Supply clock frequency with specified divisor
856 //
857 ClockCtrl |= BIT0;
858 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
859 if (EFI_ERROR (Status)) {
860 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
861 return Status;
862 }
863
864 //
865 // Wait Internal Clock Stable in the Clock Control register to be 1
866 //
867 Status = SdMmcHcWaitMmioSet (
868 PciIo,
869 Slot,
870 SD_MMC_HC_CLOCK_CTRL,
871 sizeof (ClockCtrl),
872 BIT1,
873 BIT1,
874 SD_MMC_HC_GENERIC_TIMEOUT
875 );
876 if (EFI_ERROR (Status)) {
877 return Status;
878 }
879
880 //
881 // Set SD Clock Enable in the Clock Control register to 1
882 //
883 ClockCtrl = BIT2;
884 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
885
886 return Status;
887 }
888
889 /**
890 SD/MMC bus power control.
891
892 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
893
894 @param[in] PciIo The PCI IO protocol instance.
895 @param[in] Slot The slot number of the SD card to send the command to.
896 @param[in] PowerCtrl The value setting to the power control register.
897
898 @retval TRUE There is a SD/MMC card attached.
899 @retval FALSE There is no a SD/MMC card attached.
900
901 **/
902 EFI_STATUS
903 SdMmcHcPowerControl (
904 IN EFI_PCI_IO_PROTOCOL *PciIo,
905 IN UINT8 Slot,
906 IN UINT8 PowerCtrl
907 )
908 {
909 EFI_STATUS Status;
910
911 //
912 // Clr SD Bus Power
913 //
914 PowerCtrl &= (UINT8)~BIT0;
915 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
916 if (EFI_ERROR (Status)) {
917 return Status;
918 }
919
920 //
921 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
922 //
923 PowerCtrl |= BIT0;
924 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
925
926 return Status;
927 }
928
929 /**
930 Set the SD/MMC bus width.
931
932 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
933
934 @param[in] PciIo The PCI IO protocol instance.
935 @param[in] Slot The slot number of the SD card to send the command to.
936 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
937
938 @retval EFI_SUCCESS The bus width is set successfully.
939 @retval Others The bus width isn't set successfully.
940
941 **/
942 EFI_STATUS
943 SdMmcHcSetBusWidth (
944 IN EFI_PCI_IO_PROTOCOL *PciIo,
945 IN UINT8 Slot,
946 IN UINT16 BusWidth
947 )
948 {
949 EFI_STATUS Status;
950 UINT8 HostCtrl1;
951
952 if (BusWidth == 1) {
953 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
954 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
955 } else if (BusWidth == 4) {
956 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
957 if (EFI_ERROR (Status)) {
958 return Status;
959 }
960 HostCtrl1 |= BIT1;
961 HostCtrl1 &= (UINT8)~BIT5;
962 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
963 } else if (BusWidth == 8) {
964 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
965 if (EFI_ERROR (Status)) {
966 return Status;
967 }
968 HostCtrl1 &= (UINT8)~BIT1;
969 HostCtrl1 |= BIT5;
970 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
971 } else {
972 ASSERT (FALSE);
973 return EFI_INVALID_PARAMETER;
974 }
975
976 return Status;
977 }
978
979 /**
980 Configure V4 controller enhancements at initialization.
981
982 @param[in] PciIo The PCI IO protocol instance.
983 @param[in] Slot The slot number of the SD card to send the command to.
984 @param[in] Capability The capability of the slot.
985 @param[in] ControllerVer The version of host controller.
986
987 @retval EFI_SUCCESS The clock is supplied successfully.
988
989 **/
990 EFI_STATUS
991 SdMmcHcInitV4Enhancements (
992 IN EFI_PCI_IO_PROTOCOL *PciIo,
993 IN UINT8 Slot,
994 IN SD_MMC_HC_SLOT_CAP Capability,
995 IN UINT16 ControllerVer
996 )
997 {
998 EFI_STATUS Status;
999 UINT16 HostCtrl2;
1000
1001 //
1002 // Check if controller version V4 or higher
1003 //
1004 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1005 HostCtrl2 = SD_MMC_HC_V4_EN;
1006 //
1007 // Check if controller version V4.0
1008 //
1009 if (ControllerVer == SD_MMC_HC_CTRL_VER_400) {
1010 //
1011 // Check if 64bit support is available
1012 //
1013 if (Capability.SysBus64V3 != 0) {
1014 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1015 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1016 }
1017 }
1018 //
1019 // Check if controller version V4.10 or higher
1020 //
1021 else if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {
1022 //
1023 // Check if 64bit support is available
1024 //
1025 if (Capability.SysBus64V4 != 0) {
1026 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1027 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1028 }
1029 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
1030 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
1031 }
1032 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1033 if (EFI_ERROR (Status)) {
1034 return Status;
1035 }
1036 }
1037
1038 return EFI_SUCCESS;
1039 }
1040
1041 /**
1042 Supply SD/MMC card with lowest clock frequency at initialization.
1043
1044 @param[in] PciIo The PCI IO protocol instance.
1045 @param[in] Slot The slot number of the SD card to send the command to.
1046 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
1047 @param[in] ControllerVer The version of host controller.
1048
1049 @retval EFI_SUCCESS The clock is supplied successfully.
1050 @retval Others The clock isn't supplied successfully.
1051
1052 **/
1053 EFI_STATUS
1054 SdMmcHcInitClockFreq (
1055 IN EFI_PCI_IO_PROTOCOL *PciIo,
1056 IN UINT8 Slot,
1057 IN UINT32 BaseClkFreq,
1058 IN UINT16 ControllerVer
1059 )
1060 {
1061 EFI_STATUS Status;
1062 UINT32 InitFreq;
1063
1064 //
1065 // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
1066 // the Capability Register 1 can be zero, which means a need for obtaining
1067 // the clock frequency via another method. Fail in case it is not updated
1068 // by SW at this point.
1069 //
1070 if (BaseClkFreq == 0) {
1071 //
1072 // Don't support get Base Clock Frequency information via another method
1073 //
1074 return EFI_UNSUPPORTED;
1075 }
1076 //
1077 // Supply 400KHz clock frequency at initialization phase.
1078 //
1079 InitFreq = 400;
1080 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, ControllerVer);
1081 return Status;
1082 }
1083
1084 /**
1085 Supply SD/MMC card with maximum voltage at initialization.
1086
1087 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1088
1089 @param[in] PciIo The PCI IO protocol instance.
1090 @param[in] Slot The slot number of the SD card to send the command to.
1091 @param[in] Capability The capability of the slot.
1092
1093 @retval EFI_SUCCESS The voltage is supplied successfully.
1094 @retval Others The voltage isn't supplied successfully.
1095
1096 **/
1097 EFI_STATUS
1098 SdMmcHcInitPowerVoltage (
1099 IN EFI_PCI_IO_PROTOCOL *PciIo,
1100 IN UINT8 Slot,
1101 IN SD_MMC_HC_SLOT_CAP Capability
1102 )
1103 {
1104 EFI_STATUS Status;
1105 UINT8 MaxVoltage;
1106 UINT8 HostCtrl2;
1107
1108 //
1109 // Calculate supported maximum voltage according to SD Bus Voltage Select
1110 //
1111 if (Capability.Voltage33 != 0) {
1112 //
1113 // Support 3.3V
1114 //
1115 MaxVoltage = 0x0E;
1116 } else if (Capability.Voltage30 != 0) {
1117 //
1118 // Support 3.0V
1119 //
1120 MaxVoltage = 0x0C;
1121 } else if (Capability.Voltage18 != 0) {
1122 //
1123 // Support 1.8V
1124 //
1125 MaxVoltage = 0x0A;
1126 HostCtrl2 = BIT3;
1127 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1128 gBS->Stall (5000);
1129 if (EFI_ERROR (Status)) {
1130 return Status;
1131 }
1132 } else {
1133 ASSERT (FALSE);
1134 return EFI_DEVICE_ERROR;
1135 }
1136
1137 //
1138 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1139 //
1140 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1141
1142 return Status;
1143 }
1144
1145 /**
1146 Initialize the Timeout Control register with most conservative value at initialization.
1147
1148 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1149
1150 @param[in] PciIo The PCI IO protocol instance.
1151 @param[in] Slot The slot number of the SD card to send the command to.
1152
1153 @retval EFI_SUCCESS The timeout control register is configured successfully.
1154 @retval Others The timeout control register isn't configured successfully.
1155
1156 **/
1157 EFI_STATUS
1158 SdMmcHcInitTimeoutCtrl (
1159 IN EFI_PCI_IO_PROTOCOL *PciIo,
1160 IN UINT8 Slot
1161 )
1162 {
1163 EFI_STATUS Status;
1164 UINT8 Timeout;
1165
1166 Timeout = 0x0E;
1167 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1168
1169 return Status;
1170 }
1171
1172 /**
1173 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1174 at initialization.
1175
1176 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1177 @param[in] Slot The slot number of the SD card to send the command to.
1178
1179 @retval EFI_SUCCESS The host controller is initialized successfully.
1180 @retval Others The host controller isn't initialized successfully.
1181
1182 **/
1183 EFI_STATUS
1184 SdMmcHcInitHost (
1185 IN SD_MMC_HC_PRIVATE_DATA *Private,
1186 IN UINT8 Slot
1187 )
1188 {
1189 EFI_STATUS Status;
1190 EFI_PCI_IO_PROTOCOL *PciIo;
1191 SD_MMC_HC_SLOT_CAP Capability;
1192
1193 //
1194 // Notify the SD/MMC override protocol that we are about to initialize
1195 // the SD/MMC host controller.
1196 //
1197 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1198 Status = mOverride->NotifyPhase (
1199 Private->ControllerHandle,
1200 Slot,
1201 EdkiiSdMmcInitHostPre,
1202 NULL);
1203 if (EFI_ERROR (Status)) {
1204 DEBUG ((DEBUG_WARN,
1205 "%a: SD/MMC pre init notifier callback failed - %r\n",
1206 __FUNCTION__, Status));
1207 return Status;
1208 }
1209 }
1210
1211 PciIo = Private->PciIo;
1212 Capability = Private->Capability[Slot];
1213
1214 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
1215 if (EFI_ERROR (Status)) {
1216 return Status;
1217 }
1218
1219 Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
1220 if (EFI_ERROR (Status)) {
1221 return Status;
1222 }
1223
1224 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1225 if (EFI_ERROR (Status)) {
1226 return Status;
1227 }
1228
1229 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1230 if (EFI_ERROR (Status)) {
1231 return Status;
1232 }
1233
1234 //
1235 // Notify the SD/MMC override protocol that we are have just initialized
1236 // the SD/MMC host controller.
1237 //
1238 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1239 Status = mOverride->NotifyPhase (
1240 Private->ControllerHandle,
1241 Slot,
1242 EdkiiSdMmcInitHostPost,
1243 NULL);
1244 if (EFI_ERROR (Status)) {
1245 DEBUG ((DEBUG_WARN,
1246 "%a: SD/MMC post init notifier callback failed - %r\n",
1247 __FUNCTION__, Status));
1248 }
1249 }
1250 return Status;
1251 }
1252
1253 /**
1254 Set SD Host Controler control 2 registry according to selected speed.
1255
1256 @param[in] ControllerHandle The handle of the controller.
1257 @param[in] PciIo The PCI IO protocol instance.
1258 @param[in] Slot The slot number of the SD card to send the command to.
1259 @param[in] Timing The timing to select.
1260
1261 @retval EFI_SUCCESS The timing is set successfully.
1262 @retval Others The timing isn't set successfully.
1263 **/
1264 EFI_STATUS
1265 SdMmcHcUhsSignaling (
1266 IN EFI_HANDLE ControllerHandle,
1267 IN EFI_PCI_IO_PROTOCOL *PciIo,
1268 IN UINT8 Slot,
1269 IN SD_MMC_BUS_MODE Timing
1270 )
1271 {
1272 EFI_STATUS Status;
1273 UINT8 HostCtrl2;
1274
1275 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1276 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1277 if (EFI_ERROR (Status)) {
1278 return Status;
1279 }
1280
1281 switch (Timing) {
1282 case SdMmcUhsSdr12:
1283 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1284 break;
1285 case SdMmcUhsSdr25:
1286 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1287 break;
1288 case SdMmcUhsSdr50:
1289 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1290 break;
1291 case SdMmcUhsSdr104:
1292 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1293 break;
1294 case SdMmcUhsDdr50:
1295 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1296 break;
1297 case SdMmcMmcLegacy:
1298 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1299 break;
1300 case SdMmcMmcHsSdr:
1301 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1302 break;
1303 case SdMmcMmcHsDdr:
1304 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1305 break;
1306 case SdMmcMmcHs200:
1307 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1308 break;
1309 case SdMmcMmcHs400:
1310 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1311 break;
1312 default:
1313 HostCtrl2 = 0;
1314 break;
1315 }
1316 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1317 if (EFI_ERROR (Status)) {
1318 return Status;
1319 }
1320
1321 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1322 Status = mOverride->NotifyPhase (
1323 ControllerHandle,
1324 Slot,
1325 EdkiiSdMmcUhsSignaling,
1326 &Timing
1327 );
1328 if (EFI_ERROR (Status)) {
1329 DEBUG ((
1330 DEBUG_ERROR,
1331 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1332 __FUNCTION__,
1333 Status
1334 ));
1335 return Status;
1336 }
1337 }
1338
1339 return EFI_SUCCESS;
1340 }
1341
1342 /**
1343 Set driver strength in host controller.
1344
1345 @param[in] PciIo The PCI IO protocol instance.
1346 @param[in] SlotIndex The slot index of the card.
1347 @param[in] DriverStrength DriverStrength to set in the controller.
1348
1349 @retval EFI_SUCCESS Driver strength programmed successfully.
1350 @retval Others Failed to set driver strength.
1351 **/
1352 EFI_STATUS
1353 SdMmcSetDriverStrength (
1354 IN EFI_PCI_IO_PROTOCOL *PciIo,
1355 IN UINT8 SlotIndex,
1356 IN SD_DRIVER_STRENGTH_TYPE DriverStrength
1357 )
1358 {
1359 EFI_STATUS Status;
1360 UINT16 HostCtrl2;
1361
1362 if (DriverStrength == SdDriverStrengthIgnore) {
1363 return EFI_SUCCESS;
1364 }
1365
1366 HostCtrl2 = (UINT16)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
1367 Status = SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1368 if (EFI_ERROR (Status)) {
1369 return Status;
1370 }
1371
1372 HostCtrl2 = (DriverStrength << 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK;
1373 return SdMmcHcOrMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1374 }
1375
1376 /**
1377 Turn on/off LED.
1378
1379 @param[in] PciIo The PCI IO protocol instance.
1380 @param[in] Slot The slot number of the SD card to send the command to.
1381 @param[in] On The boolean to turn on/off LED.
1382
1383 @retval EFI_SUCCESS The LED is turned on/off successfully.
1384 @retval Others The LED isn't turned on/off successfully.
1385
1386 **/
1387 EFI_STATUS
1388 SdMmcHcLedOnOff (
1389 IN EFI_PCI_IO_PROTOCOL *PciIo,
1390 IN UINT8 Slot,
1391 IN BOOLEAN On
1392 )
1393 {
1394 EFI_STATUS Status;
1395 UINT8 HostCtrl1;
1396
1397 if (On) {
1398 HostCtrl1 = BIT0;
1399 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1400 } else {
1401 HostCtrl1 = (UINT8)~BIT0;
1402 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1403 }
1404
1405 return Status;
1406 }
1407
1408 /**
1409 Build ADMA descriptor table for transfer.
1410
1411 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1412
1413 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1414 @param[in] ControllerVer The version of host controller.
1415
1416 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1417 @retval Others The ADMA descriptor table isn't created successfully.
1418
1419 **/
1420 EFI_STATUS
1421 BuildAdmaDescTable (
1422 IN SD_MMC_HC_TRB *Trb,
1423 IN UINT16 ControllerVer
1424 )
1425 {
1426 EFI_PHYSICAL_ADDRESS Data;
1427 UINT64 DataLen;
1428 UINT64 Entries;
1429 UINT32 Index;
1430 UINT64 Remaining;
1431 UINT64 Address;
1432 UINTN TableSize;
1433 EFI_PCI_IO_PROTOCOL *PciIo;
1434 EFI_STATUS Status;
1435 UINTN Bytes;
1436 UINT32 AdmaMaxDataPerLine;
1437 UINT32 DescSize;
1438 VOID *AdmaDesc;
1439
1440 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
1441 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
1442 AdmaDesc = NULL;
1443
1444 Data = Trb->DataPhy;
1445 DataLen = Trb->DataLen;
1446 PciIo = Trb->Private->PciIo;
1447
1448 //
1449 // Check for valid ranges in 32bit ADMA Descriptor Table
1450 //
1451 if ((Trb->Mode == SdMmcAdma32bMode) &&
1452 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {
1453 return EFI_INVALID_PARAMETER;
1454 }
1455 //
1456 // Check address field alignment
1457 //
1458 if (Trb->Mode != SdMmcAdma32bMode) {
1459 //
1460 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1461 //
1462 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {
1463 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));
1464 }
1465 } else {
1466 //
1467 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1468 //
1469 if ((Data & (BIT0 | BIT1)) != 0) {
1470 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1471 }
1472 }
1473
1474 //
1475 // Configure 64b ADMA.
1476 //
1477 if (Trb->Mode == SdMmcAdma64bV3Mode) {
1478 DescSize = sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE);
1479 }else if (Trb->Mode == SdMmcAdma64bV4Mode) {
1480 DescSize = sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE);
1481 }
1482 //
1483 // Configure 26b data length.
1484 //
1485 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1486 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
1487 }
1488
1489 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
1490 TableSize = (UINTN)MultU64x32 (Entries, DescSize);
1491 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1492 Status = PciIo->AllocateBuffer (
1493 PciIo,
1494 AllocateAnyPages,
1495 EfiBootServicesData,
1496 EFI_SIZE_TO_PAGES (TableSize),
1497 (VOID **)&AdmaDesc,
1498 0
1499 );
1500 if (EFI_ERROR (Status)) {
1501 return EFI_OUT_OF_RESOURCES;
1502 }
1503 ZeroMem (AdmaDesc, TableSize);
1504 Bytes = TableSize;
1505 Status = PciIo->Map (
1506 PciIo,
1507 EfiPciIoOperationBusMasterCommonBuffer,
1508 AdmaDesc,
1509 &Bytes,
1510 &Trb->AdmaDescPhy,
1511 &Trb->AdmaMap
1512 );
1513
1514 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1515 //
1516 // Map error or unable to map the whole RFis buffer into a contiguous region.
1517 //
1518 PciIo->FreeBuffer (
1519 PciIo,
1520 EFI_SIZE_TO_PAGES (TableSize),
1521 AdmaDesc
1522 );
1523 return EFI_OUT_OF_RESOURCES;
1524 }
1525
1526 if ((Trb->Mode == SdMmcAdma32bMode) &&
1527 (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1528 //
1529 // The ADMA doesn't support 64bit addressing.
1530 //
1531 PciIo->Unmap (
1532 PciIo,
1533 Trb->AdmaMap
1534 );
1535 PciIo->FreeBuffer (
1536 PciIo,
1537 EFI_SIZE_TO_PAGES (TableSize),
1538 AdmaDesc
1539 );
1540 return EFI_DEVICE_ERROR;
1541 }
1542
1543 Remaining = DataLen;
1544 Address = Data;
1545 if (Trb->Mode == SdMmcAdma32bMode) {
1546 Trb->Adma32Desc = AdmaDesc;
1547 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1548 Trb->Adma64V3Desc = AdmaDesc;
1549 } else {
1550 Trb->Adma64V4Desc = AdmaDesc;
1551 }
1552
1553 for (Index = 0; Index < Entries; Index++) {
1554 if (Trb->Mode == SdMmcAdma32bMode) {
1555 if (Remaining <= AdmaMaxDataPerLine) {
1556 Trb->Adma32Desc[Index].Valid = 1;
1557 Trb->Adma32Desc[Index].Act = 2;
1558 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1559 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1560 }
1561 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1562 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1563 break;
1564 } else {
1565 Trb->Adma32Desc[Index].Valid = 1;
1566 Trb->Adma32Desc[Index].Act = 2;
1567 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1568 Trb->Adma32Desc[Index].UpperLength = 0;
1569 }
1570 Trb->Adma32Desc[Index].LowerLength = 0;
1571 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1572 }
1573 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1574 if (Remaining <= AdmaMaxDataPerLine) {
1575 Trb->Adma64V3Desc[Index].Valid = 1;
1576 Trb->Adma64V3Desc[Index].Act = 2;
1577 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1578 Trb->Adma64V3Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1579 }
1580 Trb->Adma64V3Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1581 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1582 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1583 break;
1584 } else {
1585 Trb->Adma64V3Desc[Index].Valid = 1;
1586 Trb->Adma64V3Desc[Index].Act = 2;
1587 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1588 Trb->Adma64V3Desc[Index].UpperLength = 0;
1589 }
1590 Trb->Adma64V3Desc[Index].LowerLength = 0;
1591 Trb->Adma64V3Desc[Index].LowerAddress = (UINT32)Address;
1592 Trb->Adma64V3Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1593 }
1594 } else {
1595 if (Remaining <= AdmaMaxDataPerLine) {
1596 Trb->Adma64V4Desc[Index].Valid = 1;
1597 Trb->Adma64V4Desc[Index].Act = 2;
1598 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1599 Trb->Adma64V4Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1600 }
1601 Trb->Adma64V4Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1602 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1603 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1604 break;
1605 } else {
1606 Trb->Adma64V4Desc[Index].Valid = 1;
1607 Trb->Adma64V4Desc[Index].Act = 2;
1608 if (Trb->AdmaLengthMode == SdMmcAdmaLen26b) {
1609 Trb->Adma64V4Desc[Index].UpperLength = 0;
1610 }
1611 Trb->Adma64V4Desc[Index].LowerLength = 0;
1612 Trb->Adma64V4Desc[Index].LowerAddress = (UINT32)Address;
1613 Trb->Adma64V4Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1614 }
1615 }
1616
1617 Remaining -= AdmaMaxDataPerLine;
1618 Address += AdmaMaxDataPerLine;
1619 }
1620
1621 //
1622 // Set the last descriptor line as end of descriptor table
1623 //
1624 if (Trb->Mode == SdMmcAdma32bMode) {
1625 Trb->Adma32Desc[Index].End = 1;
1626 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1627 Trb->Adma64V3Desc[Index].End = 1;
1628 } else {
1629 Trb->Adma64V4Desc[Index].End = 1;
1630 }
1631 return EFI_SUCCESS;
1632 }
1633
1634 /**
1635 Create a new TRB for the SD/MMC cmd request.
1636
1637 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1638 @param[in] Slot The slot number of the SD card to send the command to.
1639 @param[in] Packet A pointer to the SD command data structure.
1640 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1641 not NULL, then nonblocking I/O is performed, and Event
1642 will be signaled when the Packet completes.
1643
1644 @return Created Trb or NULL.
1645
1646 **/
1647 SD_MMC_HC_TRB *
1648 SdMmcCreateTrb (
1649 IN SD_MMC_HC_PRIVATE_DATA *Private,
1650 IN UINT8 Slot,
1651 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1652 IN EFI_EVENT Event
1653 )
1654 {
1655 SD_MMC_HC_TRB *Trb;
1656 EFI_STATUS Status;
1657 EFI_TPL OldTpl;
1658 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1659 EFI_PCI_IO_PROTOCOL *PciIo;
1660 UINTN MapLength;
1661
1662 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1663 if (Trb == NULL) {
1664 return NULL;
1665 }
1666
1667 Trb->Signature = SD_MMC_HC_TRB_SIG;
1668 Trb->Slot = Slot;
1669 Trb->BlockSize = 0x200;
1670 Trb->Packet = Packet;
1671 Trb->Event = Event;
1672 Trb->Started = FALSE;
1673 Trb->Timeout = Packet->Timeout;
1674 Trb->Private = Private;
1675
1676 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1677 Trb->Data = Packet->InDataBuffer;
1678 Trb->DataLen = Packet->InTransferLength;
1679 Trb->Read = TRUE;
1680 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1681 Trb->Data = Packet->OutDataBuffer;
1682 Trb->DataLen = Packet->OutTransferLength;
1683 Trb->Read = FALSE;
1684 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1685 Trb->Data = NULL;
1686 Trb->DataLen = 0;
1687 } else {
1688 goto Error;
1689 }
1690
1691 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1692 Trb->BlockSize = (UINT16)Trb->DataLen;
1693 }
1694
1695 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1696 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1697 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1698 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1699 Trb->Mode = SdMmcPioMode;
1700 } else {
1701 if (Trb->Read) {
1702 Flag = EfiPciIoOperationBusMasterWrite;
1703 } else {
1704 Flag = EfiPciIoOperationBusMasterRead;
1705 }
1706
1707 PciIo = Private->PciIo;
1708 if (Trb->DataLen != 0) {
1709 MapLength = Trb->DataLen;
1710 Status = PciIo->Map (
1711 PciIo,
1712 Flag,
1713 Trb->Data,
1714 &MapLength,
1715 &Trb->DataPhy,
1716 &Trb->DataMap
1717 );
1718 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1719 Status = EFI_BAD_BUFFER_SIZE;
1720 goto Error;
1721 }
1722 }
1723
1724 if (Trb->DataLen == 0) {
1725 Trb->Mode = SdMmcNoData;
1726 } else if (Private->Capability[Slot].Adma2 != 0) {
1727 Trb->Mode = SdMmcAdma32bMode;
1728 Trb->AdmaLengthMode = SdMmcAdmaLen16b;
1729 if ((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_300) &&
1730 (Private->Capability[Slot].SysBus64V3 == 1)) {
1731 Trb->Mode = SdMmcAdma64bV3Mode;
1732 } else if (((Private->ControllerVersion[Slot] == SD_MMC_HC_CTRL_VER_400) &&
1733 (Private->Capability[Slot].SysBus64V3 == 1)) ||
1734 ((Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) &&
1735 (Private->Capability[Slot].SysBus64V4 == 1))) {
1736 Trb->Mode = SdMmcAdma64bV4Mode;
1737 }
1738 if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {
1739 Trb->AdmaLengthMode = SdMmcAdmaLen26b;
1740 }
1741 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
1742 if (EFI_ERROR (Status)) {
1743 PciIo->Unmap (PciIo, Trb->DataMap);
1744 goto Error;
1745 }
1746 } else if (Private->Capability[Slot].Sdma != 0) {
1747 Trb->Mode = SdMmcSdmaMode;
1748 } else {
1749 Trb->Mode = SdMmcPioMode;
1750 }
1751 }
1752
1753 if (Event != NULL) {
1754 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1755 InsertTailList (&Private->Queue, &Trb->TrbList);
1756 gBS->RestoreTPL (OldTpl);
1757 }
1758
1759 return Trb;
1760
1761 Error:
1762 SdMmcFreeTrb (Trb);
1763 return NULL;
1764 }
1765
1766 /**
1767 Free the resource used by the TRB.
1768
1769 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1770
1771 **/
1772 VOID
1773 SdMmcFreeTrb (
1774 IN SD_MMC_HC_TRB *Trb
1775 )
1776 {
1777 EFI_PCI_IO_PROTOCOL *PciIo;
1778
1779 PciIo = Trb->Private->PciIo;
1780
1781 if (Trb->AdmaMap != NULL) {
1782 PciIo->Unmap (
1783 PciIo,
1784 Trb->AdmaMap
1785 );
1786 }
1787 if (Trb->Adma32Desc != NULL) {
1788 PciIo->FreeBuffer (
1789 PciIo,
1790 Trb->AdmaPages,
1791 Trb->Adma32Desc
1792 );
1793 }
1794 if (Trb->Adma64V3Desc != NULL) {
1795 PciIo->FreeBuffer (
1796 PciIo,
1797 Trb->AdmaPages,
1798 Trb->Adma64V3Desc
1799 );
1800 }
1801 if (Trb->Adma64V4Desc != NULL) {
1802 PciIo->FreeBuffer (
1803 PciIo,
1804 Trb->AdmaPages,
1805 Trb->Adma64V4Desc
1806 );
1807 }
1808 if (Trb->DataMap != NULL) {
1809 PciIo->Unmap (
1810 PciIo,
1811 Trb->DataMap
1812 );
1813 }
1814 FreePool (Trb);
1815 return;
1816 }
1817
1818 /**
1819 Check if the env is ready for execute specified TRB.
1820
1821 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1822 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1823
1824 @retval EFI_SUCCESS The env is ready for TRB execution.
1825 @retval EFI_NOT_READY The env is not ready for TRB execution.
1826 @retval Others Some erros happen.
1827
1828 **/
1829 EFI_STATUS
1830 SdMmcCheckTrbEnv (
1831 IN SD_MMC_HC_PRIVATE_DATA *Private,
1832 IN SD_MMC_HC_TRB *Trb
1833 )
1834 {
1835 EFI_STATUS Status;
1836 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1837 EFI_PCI_IO_PROTOCOL *PciIo;
1838 UINT32 PresentState;
1839
1840 Packet = Trb->Packet;
1841
1842 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1843 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1844 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1845 //
1846 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1847 // the Present State register to be 0
1848 //
1849 PresentState = BIT0 | BIT1;
1850 } else {
1851 //
1852 // Wait Command Inhibit (CMD) in the Present State register
1853 // to be 0
1854 //
1855 PresentState = BIT0;
1856 }
1857
1858 PciIo = Private->PciIo;
1859 Status = SdMmcHcCheckMmioSet (
1860 PciIo,
1861 Trb->Slot,
1862 SD_MMC_HC_PRESENT_STATE,
1863 sizeof (PresentState),
1864 PresentState,
1865 0
1866 );
1867
1868 return Status;
1869 }
1870
1871 /**
1872 Wait for the env to be ready for execute specified TRB.
1873
1874 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1875 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1876
1877 @retval EFI_SUCCESS The env is ready for TRB execution.
1878 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1879 @retval Others Some erros happen.
1880
1881 **/
1882 EFI_STATUS
1883 SdMmcWaitTrbEnv (
1884 IN SD_MMC_HC_PRIVATE_DATA *Private,
1885 IN SD_MMC_HC_TRB *Trb
1886 )
1887 {
1888 EFI_STATUS Status;
1889 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1890 UINT64 Timeout;
1891 BOOLEAN InfiniteWait;
1892
1893 //
1894 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1895 //
1896 Packet = Trb->Packet;
1897 Timeout = Packet->Timeout;
1898 if (Timeout == 0) {
1899 InfiniteWait = TRUE;
1900 } else {
1901 InfiniteWait = FALSE;
1902 }
1903
1904 while (InfiniteWait || (Timeout > 0)) {
1905 //
1906 // Check Trb execution result by reading Normal Interrupt Status register.
1907 //
1908 Status = SdMmcCheckTrbEnv (Private, Trb);
1909 if (Status != EFI_NOT_READY) {
1910 return Status;
1911 }
1912 //
1913 // Stall for 1 microsecond.
1914 //
1915 gBS->Stall (1);
1916
1917 Timeout--;
1918 }
1919
1920 return EFI_TIMEOUT;
1921 }
1922
1923 /**
1924 Execute the specified TRB.
1925
1926 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1927 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1928
1929 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1930 @retval Others Some erros happen when sending this request to the host controller.
1931
1932 **/
1933 EFI_STATUS
1934 SdMmcExecTrb (
1935 IN SD_MMC_HC_PRIVATE_DATA *Private,
1936 IN SD_MMC_HC_TRB *Trb
1937 )
1938 {
1939 EFI_STATUS Status;
1940 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1941 EFI_PCI_IO_PROTOCOL *PciIo;
1942 UINT16 Cmd;
1943 UINT16 IntStatus;
1944 UINT32 Argument;
1945 UINT32 BlkCount;
1946 UINT16 BlkSize;
1947 UINT16 TransMode;
1948 UINT8 HostCtrl1;
1949 UINT64 SdmaAddr;
1950 UINT64 AdmaAddr;
1951 BOOLEAN AddressingMode64;
1952
1953 AddressingMode64 = FALSE;
1954
1955 Packet = Trb->Packet;
1956 PciIo = Trb->Private->PciIo;
1957 //
1958 // Clear all bits in Error Interrupt Status Register
1959 //
1960 IntStatus = 0xFFFF;
1961 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1962 if (EFI_ERROR (Status)) {
1963 return Status;
1964 }
1965 //
1966 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1967 //
1968 IntStatus = 0xFF3F;
1969 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1970 if (EFI_ERROR (Status)) {
1971 return Status;
1972 }
1973
1974 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1975 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1976 SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_ADDR_EN);
1977 if (!EFI_ERROR (Status)) {
1978 AddressingMode64 = TRUE;
1979 }
1980 }
1981
1982 //
1983 // Set Host Control 1 register DMA Select field
1984 //
1985 if ((Trb->Mode == SdMmcAdma32bMode) ||
1986 (Trb->Mode == SdMmcAdma64bV4Mode)) {
1987 HostCtrl1 = BIT4;
1988 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1989 if (EFI_ERROR (Status)) {
1990 return Status;
1991 }
1992 } else if (Trb->Mode == SdMmcAdma64bV3Mode) {
1993 HostCtrl1 = BIT4|BIT3;
1994 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1995 if (EFI_ERROR (Status)) {
1996 return Status;
1997 }
1998 }
1999
2000 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
2001
2002 if (Trb->Mode == SdMmcSdmaMode) {
2003 if ((!AddressingMode64) &&
2004 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {
2005 return EFI_INVALID_PARAMETER;
2006 }
2007
2008 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;
2009
2010 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2011 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);
2012 } else {
2013 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);
2014 }
2015
2016 if (EFI_ERROR (Status)) {
2017 return Status;
2018 }
2019 } else if ((Trb->Mode == SdMmcAdma32bMode) ||
2020 (Trb->Mode == SdMmcAdma64bV3Mode) ||
2021 (Trb->Mode == SdMmcAdma64bV4Mode)) {
2022 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
2023 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
2024 if (EFI_ERROR (Status)) {
2025 return Status;
2026 }
2027 }
2028
2029 BlkSize = Trb->BlockSize;
2030 if (Trb->Mode == SdMmcSdmaMode) {
2031 //
2032 // Set SDMA boundary to be 512K bytes.
2033 //
2034 BlkSize |= 0x7000;
2035 }
2036
2037 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
2038 if (EFI_ERROR (Status)) {
2039 return Status;
2040 }
2041
2042 BlkCount = 0;
2043 if (Trb->Mode != SdMmcNoData) {
2044 //
2045 // Calcuate Block Count.
2046 //
2047 BlkCount = (Trb->DataLen / Trb->BlockSize);
2048 }
2049 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
2050 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
2051 } else {
2052 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
2053 }
2054 if (EFI_ERROR (Status)) {
2055 return Status;
2056 }
2057
2058 Argument = Packet->SdMmcCmdBlk->CommandArgument;
2059 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
2060 if (EFI_ERROR (Status)) {
2061 return Status;
2062 }
2063
2064 TransMode = 0;
2065 if (Trb->Mode != SdMmcNoData) {
2066 if (Trb->Mode != SdMmcPioMode) {
2067 TransMode |= BIT0;
2068 }
2069 if (Trb->Read) {
2070 TransMode |= BIT4;
2071 }
2072 if (BlkCount > 1) {
2073 TransMode |= BIT5 | BIT1;
2074 }
2075 //
2076 // Only SD memory card needs to use AUTO CMD12 feature.
2077 //
2078 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
2079 if (BlkCount > 1) {
2080 TransMode |= BIT2;
2081 }
2082 }
2083 }
2084
2085 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
2086 if (EFI_ERROR (Status)) {
2087 return Status;
2088 }
2089
2090 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
2091 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
2092 Cmd |= BIT5;
2093 }
2094 //
2095 // Convert ResponseType to value
2096 //
2097 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2098 switch (Packet->SdMmcCmdBlk->ResponseType) {
2099 case SdMmcResponseTypeR1:
2100 case SdMmcResponseTypeR5:
2101 case SdMmcResponseTypeR6:
2102 case SdMmcResponseTypeR7:
2103 Cmd |= (BIT1 | BIT3 | BIT4);
2104 break;
2105 case SdMmcResponseTypeR2:
2106 Cmd |= (BIT0 | BIT3);
2107 break;
2108 case SdMmcResponseTypeR3:
2109 case SdMmcResponseTypeR4:
2110 Cmd |= BIT1;
2111 break;
2112 case SdMmcResponseTypeR1b:
2113 case SdMmcResponseTypeR5b:
2114 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
2115 break;
2116 default:
2117 ASSERT (FALSE);
2118 break;
2119 }
2120 }
2121 //
2122 // Execute cmd
2123 //
2124 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
2125 return Status;
2126 }
2127
2128 /**
2129 Check the TRB execution result.
2130
2131 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2132 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2133
2134 @retval EFI_SUCCESS The TRB is executed successfully.
2135 @retval EFI_NOT_READY The TRB is not completed for execution.
2136 @retval Others Some erros happen when executing this request.
2137
2138 **/
2139 EFI_STATUS
2140 SdMmcCheckTrbResult (
2141 IN SD_MMC_HC_PRIVATE_DATA *Private,
2142 IN SD_MMC_HC_TRB *Trb
2143 )
2144 {
2145 EFI_STATUS Status;
2146 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2147 UINT16 IntStatus;
2148 UINT32 Response[4];
2149 UINT64 SdmaAddr;
2150 UINT8 Index;
2151 UINT8 SwReset;
2152 UINT32 PioLength;
2153
2154 SwReset = 0;
2155 Packet = Trb->Packet;
2156 //
2157 // Check Trb execution result by reading Normal Interrupt Status register.
2158 //
2159 Status = SdMmcHcRwMmio (
2160 Private->PciIo,
2161 Trb->Slot,
2162 SD_MMC_HC_NOR_INT_STS,
2163 TRUE,
2164 sizeof (IntStatus),
2165 &IntStatus
2166 );
2167 if (EFI_ERROR (Status)) {
2168 goto Done;
2169 }
2170 //
2171 // Check Transfer Complete bit is set or not.
2172 //
2173 if ((IntStatus & BIT1) == BIT1) {
2174 if ((IntStatus & BIT15) == BIT15) {
2175 //
2176 // Read Error Interrupt Status register to check if the error is
2177 // Data Timeout Error.
2178 // If yes, treat it as success as Transfer Complete has higher
2179 // priority than Data Timeout Error.
2180 //
2181 Status = SdMmcHcRwMmio (
2182 Private->PciIo,
2183 Trb->Slot,
2184 SD_MMC_HC_ERR_INT_STS,
2185 TRUE,
2186 sizeof (IntStatus),
2187 &IntStatus
2188 );
2189 if (!EFI_ERROR (Status)) {
2190 if ((IntStatus & BIT4) == BIT4) {
2191 Status = EFI_SUCCESS;
2192 } else {
2193 Status = EFI_DEVICE_ERROR;
2194 }
2195 }
2196 }
2197
2198 goto Done;
2199 }
2200 //
2201 // Check if there is a error happened during cmd execution.
2202 // If yes, then do error recovery procedure to follow SD Host Controller
2203 // Simplified Spec 3.0 section 3.10.1.
2204 //
2205 if ((IntStatus & BIT15) == BIT15) {
2206 Status = SdMmcHcRwMmio (
2207 Private->PciIo,
2208 Trb->Slot,
2209 SD_MMC_HC_ERR_INT_STS,
2210 TRUE,
2211 sizeof (IntStatus),
2212 &IntStatus
2213 );
2214 if (EFI_ERROR (Status)) {
2215 goto Done;
2216 }
2217 if ((IntStatus & 0x0F) != 0) {
2218 SwReset |= BIT1;
2219 }
2220 if ((IntStatus & 0xF0) != 0) {
2221 SwReset |= BIT2;
2222 }
2223
2224 Status = SdMmcHcRwMmio (
2225 Private->PciIo,
2226 Trb->Slot,
2227 SD_MMC_HC_SW_RST,
2228 FALSE,
2229 sizeof (SwReset),
2230 &SwReset
2231 );
2232 if (EFI_ERROR (Status)) {
2233 goto Done;
2234 }
2235 Status = SdMmcHcWaitMmioSet (
2236 Private->PciIo,
2237 Trb->Slot,
2238 SD_MMC_HC_SW_RST,
2239 sizeof (SwReset),
2240 0xFF,
2241 0,
2242 SD_MMC_HC_GENERIC_TIMEOUT
2243 );
2244 if (EFI_ERROR (Status)) {
2245 goto Done;
2246 }
2247
2248 Status = EFI_DEVICE_ERROR;
2249 goto Done;
2250 }
2251 //
2252 // Check if DMA interrupt is signalled for the SDMA transfer.
2253 //
2254 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
2255 //
2256 // Clear DMA interrupt bit.
2257 //
2258 IntStatus = BIT3;
2259 Status = SdMmcHcRwMmio (
2260 Private->PciIo,
2261 Trb->Slot,
2262 SD_MMC_HC_NOR_INT_STS,
2263 FALSE,
2264 sizeof (IntStatus),
2265 &IntStatus
2266 );
2267 if (EFI_ERROR (Status)) {
2268 goto Done;
2269 }
2270 //
2271 // Update SDMA Address register.
2272 //
2273 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
2274
2275 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2276 Status = SdMmcHcRwMmio (
2277 Private->PciIo,
2278 Trb->Slot,
2279 SD_MMC_HC_ADMA_SYS_ADDR,
2280 FALSE,
2281 sizeof (UINT64),
2282 &SdmaAddr
2283 );
2284 } else {
2285 Status = SdMmcHcRwMmio (
2286 Private->PciIo,
2287 Trb->Slot,
2288 SD_MMC_HC_SDMA_ADDR,
2289 FALSE,
2290 sizeof (UINT32),
2291 &SdmaAddr
2292 );
2293 }
2294
2295 if (EFI_ERROR (Status)) {
2296 goto Done;
2297 }
2298 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
2299 }
2300
2301 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
2302 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
2303 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
2304 if ((IntStatus & BIT0) == BIT0) {
2305 Status = EFI_SUCCESS;
2306 goto Done;
2307 }
2308 }
2309
2310 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
2311 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
2312 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
2313 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
2314 //
2315 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2316 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2317 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2318 //
2319 if ((IntStatus & BIT5) == BIT5) {
2320 //
2321 // Clear Buffer Read Ready interrupt at first.
2322 //
2323 IntStatus = BIT5;
2324 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2325 //
2326 // Read data out from Buffer Port register
2327 //
2328 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2329 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2330 }
2331 Status = EFI_SUCCESS;
2332 goto Done;
2333 }
2334 }
2335
2336 Status = EFI_NOT_READY;
2337 Done:
2338 //
2339 // Get response data when the cmd is executed successfully.
2340 //
2341 if (!EFI_ERROR (Status)) {
2342 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2343 for (Index = 0; Index < 4; Index++) {
2344 Status = SdMmcHcRwMmio (
2345 Private->PciIo,
2346 Trb->Slot,
2347 SD_MMC_HC_RESPONSE + Index * 4,
2348 TRUE,
2349 sizeof (UINT32),
2350 &Response[Index]
2351 );
2352 if (EFI_ERROR (Status)) {
2353 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2354 return Status;
2355 }
2356 }
2357 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2358 }
2359 }
2360
2361 if (Status != EFI_NOT_READY) {
2362 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2363 }
2364
2365 return Status;
2366 }
2367
2368 /**
2369 Wait for the TRB execution result.
2370
2371 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2372 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2373
2374 @retval EFI_SUCCESS The TRB is executed successfully.
2375 @retval Others Some erros happen when executing this request.
2376
2377 **/
2378 EFI_STATUS
2379 SdMmcWaitTrbResult (
2380 IN SD_MMC_HC_PRIVATE_DATA *Private,
2381 IN SD_MMC_HC_TRB *Trb
2382 )
2383 {
2384 EFI_STATUS Status;
2385 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2386 UINT64 Timeout;
2387 BOOLEAN InfiniteWait;
2388
2389 Packet = Trb->Packet;
2390 //
2391 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2392 //
2393 Timeout = Packet->Timeout;
2394 if (Timeout == 0) {
2395 InfiniteWait = TRUE;
2396 } else {
2397 InfiniteWait = FALSE;
2398 }
2399
2400 while (InfiniteWait || (Timeout > 0)) {
2401 //
2402 // Check Trb execution result by reading Normal Interrupt Status register.
2403 //
2404 Status = SdMmcCheckTrbResult (Private, Trb);
2405 if (Status != EFI_NOT_READY) {
2406 return Status;
2407 }
2408 //
2409 // Stall for 1 microsecond.
2410 //
2411 gBS->Stall (1);
2412
2413 Timeout--;
2414 }
2415
2416 return EFI_TIMEOUT;
2417 }
2418
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