MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 //
  16 // Include common header file for this module.
  17 //
  18 #include "CommonHeader.h"
  19
  20 /**
  21   Invalidates the entire instruction cache in cache coherency domain of the
  22   calling CPU.
  23
  24   Invalidates the entire instruction cache in cache coherency domain of the
  25   calling CPU.
  26
  27 **/
  28 VOID
  29 EFIAPI
  30 InvalidateInstructionCache (
  31   VOID
  32   )
  33 {
  34 }
  35
  36 /**
  37   Invalidates a range of instruction cache lines in the cache coherency domain
  38   of the calling CPU.
  39
  40   Invalidates the instruction cache lines specified by Address and Length. If
  41   Address is not aligned on a cache line boundary, then entire instruction
  42   cache line containing Address is invalidated. If Address + Length is not
  43   aligned on a cache line boundary, then the entire instruction cache line
  44   containing Address + Length -1 is invalidated. This function may choose to
  45   invalidate the entire instruction cache if that is more efficient than
  46   invalidating the specified range. If Length is 0, the no instruction cache
  47   lines are invalidated. Address is returned.
  48
  49   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  50
  51   @param  Address The base address of the instruction cache lines to
  52                   invalidate. If the CPU is in a physical addressing mode, then
  53                   Address is a physical address. If the CPU is in a virtual
  54                   addressing mode, then Address is a virtual address.
  55
  56   @param  Length  The number of bytes to invalidate from the instruction cache.
  57
  58   @return Address
  59
  60 **/
  61 VOID *
  62 EFIAPI
  63 InvalidateInstructionCacheRange (
  64   IN      VOID                      *Address,
  65   IN      UINTN                     Length
  66   )
  67 {
  68   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  69   return Address;
  70 }
  71
  72 /**
  73   Writes Back and Invalidates the entire data cache in cache coherency domain
  74   of the calling CPU.
  75
  76   Writes Back and Invalidates the entire data cache in cache coherency domain
  77   of the calling CPU. This function guarantees that all dirty cache lines are
  78   written back to system memory, and also invalidates all the data cache lines
  79   in the cache coherency domain of the calling CPU.
  80
  81 **/
  82 VOID
  83 EFIAPI
  84 WriteBackInvalidateDataCache (
  85   VOID
  86   )
  87 {
  88 }
  89
  90 /**
  91   Writes Back and Invalidates a range of data cache lines in the cache
  92   coherency domain of the calling CPU.
  93
  94   Writes Back and Invalidate the data cache lines specified by Address and
  95   Length. If Address is not aligned on a cache line boundary, then entire data
  96   cache line containing Address is written back and invalidated. If Address +
  97   Length is not aligned on a cache line boundary, then the entire data cache
  98   line containing Address + Length -1 is written back and invalidated. This
  99   function may choose to write back and invalidate the entire data cache if
 100   that is more efficient than writing back and invalidating the specified
 101   range. If Length is 0, the no data cache lines are written back and
 102   invalidated. Address is returned.
 103
 104   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 105
 106   @param  Address The base address of the data cache lines to write back and
 107                   invalidate. If the CPU is in a physical addressing mode, then
 108                   Address is a physical address. If the CPU is in a virtual
 109                   addressing mode, then Address is a virtual address.
 110   @param  Length  The number of bytes to write back and invalidate from the
 111                   data cache.
 112
 113   @return Address
 114
 115 **/
 116 VOID *
 117 EFIAPI
 118 WriteBackInvalidateDataCacheRange (
 119   IN      VOID                      *Address,
 120   IN      UINTN                     Length
 121   )
 122 {
 123   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 124   return Address;
 125 }
 126
 127 /**
 128   Writes Back the entire data cache in cache coherency domain of the calling
 129   CPU.
 130
 131   Writes Back the entire data cache in cache coherency domain of the calling
 132   CPU. This function guarantees that all dirty cache lines are written back to
 133   system memory. This function may also invalidate all the data cache lines in
 134   the cache coherency domain of the calling CPU.
 135
 136 **/
 137 VOID
 138 EFIAPI
 139 WriteBackDataCache (
 140   VOID
 141   )
 142 {
 143 }
 144
 145 /**
 146   Writes Back a range of data cache lines in the cache coherency domain of the
 147   calling CPU.
 148
 149   Writes Back the data cache lines specified by Address and Length. If Address
 150   is not aligned on a cache line boundary, then entire data cache line
 151   containing Address is written back. If Address + Length is not aligned on a
 152   cache line boundary, then the entire data cache line containing Address +
 153   Length -1 is written back. This function may choose to write back the entire
 154   data cache if that is more efficient than writing back the specified range.
 155   If Length is 0, the no data cache lines are written back. This function may
 156   also invalidate all the data cache lines in the specified range of the cache
 157   coherency domain of the calling CPU. Address is returned.
 158
 159   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 160
 161   @param  Address The base address of the data cache lines to write back. If
 162                   the CPU is in a physical addressing mode, then Address is a
 163                   physical address. If the CPU is in a virtual addressing
 164                   mode, then Address is a virtual address.
 165   @param  Length  The number of bytes to write back from the data cache.
 166
 167   @return Address
 168
 169 **/
 170 VOID *
 171 EFIAPI
 172 WriteBackDataCacheRange (
 173   IN      VOID                      *Address,
 174   IN      UINTN                     Length
 175   )
 176 {
 177   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 178   return Address;
 179 }
 180
 181 /**
 182   Invalidates the entire data cache in cache coherency domain of the calling
 183   CPU.
 184
 185   Invalidates the entire data cache in cache coherency domain of the calling
 186   CPU. This function must be used with care because dirty cache lines are not
 187   written back to system memory. It is typically used for cache diagnostics. If
 188   the CPU does not support invalidation of the entire data cache, then a write
 189   back and invalidate operation should be performed on the entire data cache.
 190
 191 **/
 192 VOID
 193 EFIAPI
 194 InvalidateDataCache (
 195   VOID
 196   )
 197 {
 198 }
 199
 200 /**
 201   Invalidates a range of data cache lines in the cache coherency domain of the
 202   calling CPU.
 203
 204   Invalidates the data cache lines specified by Address and Length. If Address
 205   is not aligned on a cache line boundary, then entire data cache line
 206   containing Address is invalidated. If Address + Length is not aligned on a
 207   cache line boundary, then the entire data cache line containing Address +
 208   Length -1 is invalidated. This function must never invalidate any cache lines
 209   outside the specified range. If Length is 0, the no data cache lines are
 210   invalidated. Address is returned. This function must be used with care
 211   because dirty cache lines are not written back to system memory. It is
 212   typically used for cache diagnostics. If the CPU does not support
 213   invalidation of a data cache range, then a write back and invalidate
 214   operation should be performed on the data cache range.
 215
 216   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 217
 218   @param  Address The base address of the data cache lines to invalidate. If
 219                   the CPU is in a physical addressing mode, then Address is a
 220                   physical address. If the CPU is in a virtual addressing mode,
 221                   then Address is a virtual address.
 222   @param  Length  The number of bytes to invalidate from the data cache.
 223
 224   @return Address
 225
 226 **/
 227 VOID *
 228 EFIAPI
 229 InvalidateDataCacheRange (
 230   IN      VOID                      *Address,
 231   IN      UINTN                     Length
 232   )
 233 {
 234   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 235   return Address;
 236 }