--- /dev/null
+#/** @file\r
+# Component description file for Base Cache Maintenance Library\r
+#\r
+# Cache Maintenance Library that uses Base Library services to maintain caches.\r
+# This library assumes there are no chipset dependencies required to maintain caches.\r
+# Copyright (c) 2007 - 2007, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BaseCacheMaintenanceLib\r
+ FILE_GUID = 123dd843-57c9-4158-8418-ce68b3944ce7\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = CacheMaintenanceLib \r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources.common]\r
+ CommonHeader.h\r
+\r
+[Sources.Ia32]\r
+ x86Cache.c\r
+\r
+[Sources.X64]\r
+ x86Cache.c\r
+\r
+[Sources.IPF]\r
+ IpfCache.c\r
+\r
+[Sources.EBC]\r
+ EbcCache.c\r
+\r
+\r
+################################################################################\r
+#\r
+# Includes Section - list of Include locations that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Includes]\r
+ $(WORKSPACE)/MdePkg\Include/Library\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
+\r
+################################################################################\r
+#\r
+# Library Class Section - list of Library Classes that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+\r
+[LibraryClasses.IA32]\r
+ BaseLib\r
+\r
+[LibraryClasses.X64]\r
+ BaseLib\r
+\r
+[LibraryClasses.IPF]\r
+ BaseLib\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">\r
+ <MsaHeader>\r
+ <ModuleName>BaseCacheMaintenanceLib</ModuleName>\r
+ <ModuleType>BASE</ModuleType>\r
+ <GuidValue>123dd843-57c9-4158-8418-ce68b3944ce7</GuidValue>\r
+ <Version>1.0</Version>\r
+ <Abstract>Component description file for Base Cache Maintenance Library</Abstract>\r
+ <Description>Cache Maintenance Library that uses Base Library services to maintain caches.
+ This library assumes there are no chipset dependencies required to maintain caches.</Description>\r
+ <Copyright>Copyright (c) 2006 - 2007, Intel Corporation</Copyright>\r
+ <License>All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
+ <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
+ </MsaHeader>\r
+ <ModuleDefinitions>\r
+ <SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>\r
+ <BinaryModule>false</BinaryModule>\r
+ <OutputFileBasename>BaseCacheMaintenanceLib</OutputFileBasename>\r
+ </ModuleDefinitions>\r
+ <LibraryClassDefinitions>\r
+ <LibraryClass Usage="ALWAYS_PRODUCED">\r
+ <Keyword>CacheMaintenanceLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED" SupArchList="IA32 X64 IPF">\r
+ <Keyword>BaseLib</Keyword>\r
+ </LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">\r
+ <Keyword>DebugLib</Keyword>\r
+ </LibraryClass>\r
+ </LibraryClassDefinitions>\r
+ <SourceFiles>\r
+ <Filename SupArchList="IA32">x86Cache.c</Filename>\r
+ <Filename SupArchList="X64">x86Cache.c</Filename>\r
+ <Filename SupArchList="EBC">EbcCache.c</Filename>\r
+ <Filename SupArchList="IPF">IpfCache.c</Filename>\r
+ </SourceFiles>\r
+ <PackageDependencies>\r
+ <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
+ </PackageDependencies>\r
+ <Externs>\r
+ <Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>\r
+ <Specification>EDK_RELEASE_VERSION 0x00020000</Specification>\r
+ </Externs>\r
+</ModuleSurfaceArea>
\ No newline at end of file
--- /dev/null
+/**@file\r
+ Common header file shared by all source files.\r
+\r
+ This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+ Copyright (c) 2007 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <Base.h>\r
+//\r
+// The protocols, PPI and GUID defintions for this module\r
+//\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Cache Maintenance Functions.\r
+\r
+ Copyright (c) 2006, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+ Invalidates the entire instruction cache in cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Invalidates the entire instruction cache in cache coherency domain of the\r
+ calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateInstructionCache (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ Invalidates a range of instruction cache lines in the cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Invalidates the instruction cache lines specified by Address and Length. If\r
+ Address is not aligned on a cache line boundary, then entire instruction\r
+ cache line containing Address is invalidated. If Address + Length is not\r
+ aligned on a cache line boundary, then the entire instruction cache line\r
+ containing Address + Length -1 is invalidated. This function may choose to\r
+ invalidate the entire instruction cache if that is more efficient than\r
+ invalidating the specified range. If Length is 0, the no instruction cache\r
+ lines are invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateInstructionCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+ return Address;\r
+}\r
+\r
+/**\r
+ Writes Back and Invalidates the entire data cache in cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Writes Back and Invalidates the entire data cache in cache coherency domain\r
+ of the calling CPU. This function guarantees that all dirty cache lines are\r
+ written back to system memory, and also invalidates all the data cache lines\r
+ in the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackInvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ Writes Back and Invalidates a range of data cache lines in the cache\r
+ coherency domain of the calling CPU.\r
+\r
+ Writes Back and Invalidate the data cache lines specified by Address and\r
+ Length. If Address is not aligned on a cache line boundary, then entire data\r
+ cache line containing Address is written back and invalidated. If Address +\r
+ Length is not aligned on a cache line boundary, then the entire data cache\r
+ line containing Address + Length -1 is written back and invalidated. This\r
+ function may choose to write back and invalidate the entire data cache if\r
+ that is more efficient than writing back and invalidating the specified\r
+ range. If Length is 0, the no data cache lines are written back and\r
+ invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to write back and\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+ @param Length The number of bytes to write back and invalidate from the\r
+ data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackInvalidateDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+ return Address;\r
+}\r
+\r
+/**\r
+ Writes Back the entire data cache in cache coherency domain of the calling\r
+ CPU.\r
+\r
+ Writes Back the entire data cache in cache coherency domain of the calling\r
+ CPU. This function guarantees that all dirty cache lines are written back to\r
+ system memory. This function may also invalidate all the data cache lines in\r
+ the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackDataCache (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ Writes Back a range of data cache lines in the cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Writes Back the data cache lines specified by Address and Length. If Address\r
+ is not aligned on a cache line boundary, then entire data cache line\r
+ containing Address is written back. If Address + Length is not aligned on a\r
+ cache line boundary, then the entire data cache line containing Address +\r
+ Length -1 is written back. This function may choose to write back the entire\r
+ data cache if that is more efficient than writing back the specified range.\r
+ If Length is 0, the no data cache lines are written back. This function may\r
+ also invalidate all the data cache lines in the specified range of the cache\r
+ coherency domain of the calling CPU. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to write back. If\r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing\r
+ mode, then Address is a virtual address.\r
+ @param Length The number of bytes to write back from the data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+ return Address;\r
+}\r
+\r
+/**\r
+ Invalidates the entire data cache in cache coherency domain of the calling\r
+ CPU.\r
+\r
+ Invalidates the entire data cache in cache coherency domain of the calling\r
+ CPU. This function must be used with care because dirty cache lines are not\r
+ written back to system memory. It is typically used for cache diagnostics. If\r
+ the CPU does not support invalidation of the entire data cache, then a write\r
+ back and invalidate operation should be performed on the entire data cache.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ Invalidates a range of data cache lines in the cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Invalidates the data cache lines specified by Address and Length. If Address\r
+ is not aligned on a cache line boundary, then entire data cache line\r
+ containing Address is invalidated. If Address + Length is not aligned on a\r
+ cache line boundary, then the entire data cache line containing Address +\r
+ Length -1 is invalidated. This function must never invalidate any cache lines\r
+ outside the specified range. If Length is 0, the no data cache lines are\r
+ invalidated. Address is returned. This function must be used with care\r
+ because dirty cache lines are not written back to system memory. It is\r
+ typically used for cache diagnostics. If the CPU does not support\r
+ invalidation of a data cache range, then a write back and invalidate\r
+ operation should be performed on the data cache range.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to invalidate. If\r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing mode,\r
+ then Address is a virtual address.\r
+ @param Length The number of bytes to invalidate from the data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+ return Address;\r
+}\r
--- /dev/null
+/** @file\r
+ Cache Maintenance Functions.\r
+\r
+ Copyright (c) 2006, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+ Invalidates the entire instruction cache in cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Invalidates the entire instruction cache in cache coherency domain of the\r
+ calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateInstructionCache (\r
+ VOID\r
+ )\r
+{\r
+ PalCallStatic (NULL, 1, 1, 1, 0);\r
+}\r
+\r
+/**\r
+ Invalidates a range of instruction cache lines in the cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Invalidates the instruction cache lines specified by Address and Length. If\r
+ Address is not aligned on a cache line boundary, then entire instruction\r
+ cache line containing Address is invalidated. If Address + Length is not\r
+ aligned on a cache line boundary, then the entire instruction cache line\r
+ containing Address + Length -1 is invalidated. This function may choose to\r
+ invalidate the entire instruction cache if that is more efficient than\r
+ invalidating the specified range. If Length is 0, the no instruction cache\r
+ lines are invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateInstructionCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ return IpfFlushCacheRange (Address, Length);\r
+}\r
+\r
+/**\r
+ Writes Back and Invalidates the entire data cache in cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Writes Back and Invalidates the entire data cache in cache coherency domain\r
+ of the calling CPU. This function guarantees that all dirty cache lines are\r
+ written back to system memory, and also invalidates all the data cache lines\r
+ in the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackInvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+ PalCallStatic (NULL, 1, 2, 1, 0);\r
+}\r
+\r
+/**\r
+ Writes Back and Invalidates a range of data cache lines in the cache\r
+ coherency domain of the calling CPU.\r
+\r
+ Writes Back and Invalidate the data cache lines specified by Address and\r
+ Length. If Address is not aligned on a cache line boundary, then entire data\r
+ cache line containing Address is written back and invalidated. If Address +\r
+ Length is not aligned on a cache line boundary, then the entire data cache\r
+ line containing Address + Length -1 is written back and invalidated. This\r
+ function may choose to write back and invalidate the entire data cache if\r
+ that is more efficient than writing back and invalidating the specified\r
+ range. If Length is 0, the no data cache lines are written back and\r
+ invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to write back and\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+ @param Length The number of bytes to write back and invalidate from the\r
+ data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackInvalidateDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+\r
+ return IpfFlushCacheRange (Address, Length);\r
+}\r
+\r
+/**\r
+ Writes Back the entire data cache in cache coherency domain of the calling\r
+ CPU.\r
+\r
+ Writes Back the entire data cache in cache coherency domain of the calling\r
+ CPU. This function guarantees that all dirty cache lines are written back to\r
+ system memory. This function may also invalidate all the data cache lines in\r
+ the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackDataCache (\r
+ VOID\r
+ )\r
+{\r
+ PalCallStatic (NULL, 1, 2, 0, 0);\r
+}\r
+\r
+/**\r
+ Writes Back a range of data cache lines in the cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Writes Back the data cache lines specified by Address and Length. If Address\r
+ is not aligned on a cache line boundary, then entire data cache line\r
+ containing Address is written back. If Address + Length is not aligned on a\r
+ cache line boundary, then the entire data cache line containing Address +\r
+ Length -1 is written back. This function may choose to write back the entire\r
+ data cache if that is more efficient than writing back the specified range.\r
+ If Length is 0, the no data cache lines are written back. This function may\r
+ also invalidate all the data cache lines in the specified range of the cache\r
+ coherency domain of the calling CPU. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to write back. If\r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing\r
+ mode, then Address is a virtual address.\r
+ @param Length The number of bytes to write back from the data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+\r
+ return IpfFlushCacheRange (Address, Length);\r
+}\r
+\r
+/**\r
+ Invalidates the entire data cache in cache coherency domain of the calling\r
+ CPU.\r
+\r
+ Invalidates the entire data cache in cache coherency domain of the calling\r
+ CPU. This function must be used with care because dirty cache lines are not\r
+ written back to system memory. It is typically used for cache diagnostics. If\r
+ the CPU does not support invalidation of the entire data cache, then a write\r
+ back and invalidate operation should be performed on the entire data cache.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+ WriteBackInvalidateDataCache ();\r
+}\r
+\r
+/**\r
+ Invalidates a range of data cache lines in the cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Invalidates the data cache lines specified by Address and Length. If Address\r
+ is not aligned on a cache line boundary, then entire data cache line\r
+ containing Address is invalidated. If Address + Length is not aligned on a\r
+ cache line boundary, then the entire data cache line containing Address +\r
+ Length -1 is invalidated. This function must never invalidate any cache lines\r
+ outside the specified range. If Length is 0, the no data cache lines are\r
+ invalidated. Address is returned. This function must be used with care\r
+ because dirty cache lines are not written back to system memory. It is\r
+ typically used for cache diagnostics. If the CPU does not support\r
+ invalidation of a data cache range, then a write back and invalidate\r
+ operation should be performed on the data cache range.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to invalidate. If\r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing mode,\r
+ then Address is a virtual address.\r
+ @param Length The number of bytes to invalidate from the data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ return IpfFlushCacheRange (Address, Length);\r
+}\r
--- /dev/null
+/** @file\r
+ Cache Maintenance Functions.\r
+\r
+ Copyright (c) 2006, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: x86Cache.c\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+//\r
+// This size must be at or below the smallest cache size possible among all\r
+// supported processors\r
+//\r
+#define CACHE_LINE_SIZE 0x20\r
+\r
+/**\r
+ Invalidates the entire instruction cache in cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Invalidates the entire instruction cache in cache coherency domain of the\r
+ calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateInstructionCache (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ Invalidates a range of instruction cache lines in the cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Invalidates the instruction cache lines specified by Address and Length. If\r
+ Address is not aligned on a cache line boundary, then entire instruction\r
+ cache line containing Address is invalidated. If Address + Length is not\r
+ aligned on a cache line boundary, then the entire instruction cache line\r
+ containing Address + Length -1 is invalidated. This function may choose to\r
+ invalidate the entire instruction cache if that is more efficient than\r
+ invalidating the specified range. If Length is 0, the no instruction cache\r
+ lines are invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the instruction cache lines to\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+\r
+ @param Length The number of bytes to invalidate from the instruction cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateInstructionCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+ return Address;\r
+}\r
+\r
+/**\r
+ Writes Back and Invalidates the entire data cache in cache coherency domain\r
+ of the calling CPU.\r
+\r
+ Writes Back and Invalidates the entire data cache in cache coherency domain\r
+ of the calling CPU. This function guarantees that all dirty cache lines are\r
+ written back to system memory, and also invalidates all the data cache lines\r
+ in the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackInvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+ AsmWbinvd ();\r
+}\r
+\r
+/**\r
+ Writes Back and Invalidates a range of data cache lines in the cache\r
+ coherency domain of the calling CPU.\r
+\r
+ Writes Back and Invalidate the data cache lines specified by Address and\r
+ Length. If Address is not aligned on a cache line boundary, then entire data\r
+ cache line containing Address is written back and invalidated. If Address +\r
+ Length is not aligned on a cache line boundary, then the entire data cache\r
+ line containing Address + Length -1 is written back and invalidated. This\r
+ function may choose to write back and invalidate the entire data cache if\r
+ that is more efficient than writing back and invalidating the specified\r
+ range. If Length is 0, the no data cache lines are written back and\r
+ invalidated. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to write back and\r
+ invalidate. If the CPU is in a physical addressing mode, then\r
+ Address is a physical address. If the CPU is in a virtual\r
+ addressing mode, then Address is a virtual address.\r
+ @param Length The number of bytes to write back and invalidate from the\r
+ data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackInvalidateDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINTN Start, End;\r
+\r
+ ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
+\r
+ if (Length == 0) {\r
+ return Address;\r
+ }\r
+\r
+ Start = (UINTN)Address;\r
+ End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);\r
+ Start &= ~(CACHE_LINE_SIZE - 1);\r
+\r
+ do {\r
+ Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;\r
+ } while (Start != End);\r
+ return Address;\r
+}\r
+\r
+/**\r
+ Writes Back the entire data cache in cache coherency domain of the calling\r
+ CPU.\r
+\r
+ Writes Back the entire data cache in cache coherency domain of the calling\r
+ CPU. This function guarantees that all dirty cache lines are written back to\r
+ system memory. This function may also invalidate all the data cache lines in\r
+ the cache coherency domain of the calling CPU.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBackDataCache (\r
+ VOID\r
+ )\r
+{\r
+ WriteBackInvalidateDataCache ();\r
+}\r
+\r
+/**\r
+ Writes Back a range of data cache lines in the cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Writes Back the data cache lines specified by Address and Length. If Address\r
+ is not aligned on a cache line boundary, then entire data cache line\r
+ containing Address is written back. If Address + Length is not aligned on a\r
+ cache line boundary, then the entire data cache line containing Address +\r
+ Length -1 is written back. This function may choose to write back the entire\r
+ data cache if that is more efficient than writing back the specified range.\r
+ If Length is 0, the no data cache lines are written back. This function may\r
+ also invalidate all the data cache lines in the specified range of the cache\r
+ coherency domain of the calling CPU. Address is returned.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to write back. If\r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing\r
+ mode, then Address is a virtual address.\r
+ @param Length The number of bytes to write back from the data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+WriteBackDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ return WriteBackInvalidateDataCacheRange (Address, Length);\r
+}\r
+\r
+/**\r
+ Invalidates the entire data cache in cache coherency domain of the calling\r
+ CPU.\r
+\r
+ Invalidates the entire data cache in cache coherency domain of the calling\r
+ CPU. This function must be used with care because dirty cache lines are not\r
+ written back to system memory. It is typically used for cache diagnostics. If\r
+ the CPU does not support invalidation of the entire data cache, then a write\r
+ back and invalidate operation should be performed on the entire data cache.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InvalidateDataCache (\r
+ VOID\r
+ )\r
+{\r
+ AsmInvd ();\r
+}\r
+\r
+/**\r
+ Invalidates a range of data cache lines in the cache coherency domain of the\r
+ calling CPU.\r
+\r
+ Invalidates the data cache lines specified by Address and Length. If Address\r
+ is not aligned on a cache line boundary, then entire data cache line\r
+ containing Address is invalidated. If Address + Length is not aligned on a\r
+ cache line boundary, then the entire data cache line containing Address +\r
+ Length -1 is invalidated. This function must never invalidate any cache lines\r
+ outside the specified range. If Length is 0, the no data cache lines are\r
+ invalidated. Address is returned. This function must be used with care\r
+ because dirty cache lines are not written back to system memory. It is\r
+ typically used for cache diagnostics. If the CPU does not support\r
+ invalidation of a data cache range, then a write back and invalidate\r
+ operation should be performed on the data cache range.\r
+\r
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+\r
+ @param Address The base address of the data cache lines to invalidate. If\r
+ the CPU is in a physical addressing mode, then Address is a\r
+ physical address. If the CPU is in a virtual addressing mode,\r
+ then Address is a virtual address.\r
+ @param Length The number of bytes to invalidate from the data cache.\r
+\r
+ @return Address\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+InvalidateDataCacheRange (\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ return WriteBackInvalidateDataCacheRange (Address, Length);\r
+}\r
--- /dev/null
+#/** @file\r
+# Component description file for NULL Debug Library\r
+#\r
+# Debug Library with empty functions.\r
+# Copyright (c) 2007 - 2007, Intel Corporation.\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BaseDebugLibNull\r
+ FILE_GUID = 9ba1d976-0624-41a3-8650-28165e8d9ae8\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = DebugLib \r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources.common]\r
+ DebugLib.c\r
+ CommonHeader.h\r
+\r
+\r
+################################################################################\r
+#\r
+# Includes Section - list of Include locations that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Includes]\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">\r
+ <MsaHeader>\r
+ <ModuleName>BaseDebugLibNull</ModuleName>\r
+ <ModuleType>BASE</ModuleType>\r
+ <GuidValue>9ba1d976-0624-41a3-8650-28165e8d9ae8</GuidValue>\r
+ <Version>1.0</Version>\r
+ <Abstract>Component description file for NULL Debug Library</Abstract>\r
+ <Description>Debug Library with empty functions.</Description>\r
+ <Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright>\r
+ <License>All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
+ <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>\r
+ </MsaHeader>\r
+ <ModuleDefinitions>\r
+ <SupportedArchitectures>IA32 X64 IPF EBC</SupportedArchitectures>\r
+ <BinaryModule>false</BinaryModule>\r
+ <OutputFileBasename>BaseDebugLibNull</OutputFileBasename>\r
+ </ModuleDefinitions>\r
+ <LibraryClassDefinitions>\r
+ <LibraryClass Usage="ALWAYS_PRODUCED">\r
+ <Keyword>DebugLib</Keyword>\r
+ </LibraryClass>\r
+ </LibraryClassDefinitions>\r
+ <SourceFiles>\r
+ <Filename>DebugLib.c</Filename>\r
+ </SourceFiles>\r
+ <PackageDependencies>\r
+ <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>\r
+ </PackageDependencies>\r
+ <Externs>\r
+ <Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>\r
+ <Specification>EDK_RELEASE_VERSION 0x00020000</Specification>\r
+ </Externs>\r
+</ModuleSurfaceArea>
\ No newline at end of file
--- /dev/null
+/**@file\r
+ Common header file shared by all source files.\r
+\r
+ This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+ Copyright (c) 2007 - 2007, Intel Corporation.\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <Base.h>\r
+//\r
+// The protocols, PPI and GUID defintions for this module\r
+//\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/DebugLib.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Base Debug Library that uses PrintLib to print messages to a memory buffer.\r
+\r
+ Copyright (c) 2006, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+\r
+ Prints a debug message to the debug output device if the specified error level is enabled.\r
+\r
+ If any bit in ErrorLevel is also set in PcdDebugPrintErrorLevel, then print \r
+ the message specified by Format and the associated variable argument list to \r
+ the debug output device.\r
+\r
+ If Format is NULL, then ASSERT().\r
+\r
+ @param ErrorLevel The error level of the debug message.\r
+ @param Format Format string for the debug message to print.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DebugPrint (\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ ...\r
+ )\r
+{\r
+}\r
+\r
+\r
+/**\r
+\r
+ Prints an assert message containing a filename, line number, and description. \r
+ This may be followed by a breakpoint or a dead loop.\r
+\r
+ Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n" \r
+ to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of \r
+ PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if \r
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then \r
+ CpuDeadLoop() is called. If neither of these bits are set, then this function \r
+ returns immediately after the message is printed to the debug output device.\r
+ DebugAssert() must actively prevent recusrsion. If DebugAssert() is called while\r
+ processing another DebugAssert(), then DebugAssert() must return immediately.\r
+\r
+ If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.\r
+\r
+ If Description is NULL, then a <Description> string of "(NULL) Description" is printed.\r
+\r
+ @param FileName Pointer to the name of the source file that generated the assert condition.\r
+ @param LineNumber The line number in the source file that generated the assert condition\r
+ @param Description Pointer to the description of the assert condition.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DebugAssert (\r
+ IN CONST CHAR8 *FileName,\r
+ IN UINTN LineNumber,\r
+ IN CONST CHAR8 *Description\r
+ )\r
+{\r
+}\r
+\r
+\r
+/**\r
+\r
+ Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
+\r
+ This function fills Length bytes of Buffer with the value specified by \r
+ PcdDebugClearMemoryValue, and returns Buffer.\r
+\r
+ If Buffer is NULL, then ASSERT().\r
+\r
+ If Length is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). \r
+\r
+ @param Buffer Pointer to the target buffer to fill with PcdDebugClearMemoryValue.\r
+ @param Length Number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue. \r
+\r
+ @return Buffer\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+DebugClearMemory (\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ return Buffer;\r
+}\r
+\r
+\r
+/**\r
+ \r
+ Returns TRUE if ASSERT() macros are enabled.\r
+\r
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of \r
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+DebugAssertEnabled (\r
+ VOID\r
+ )\r
+{\r
+ return FALSE;\r
+}\r
+\r
+\r
+/**\r
+ \r
+ Returns TRUE if DEBUG()macros are enabled.\r
+\r
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of \r
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+DebugPrintEnabled (\r
+ VOID\r
+ )\r
+{\r
+ return FALSE;\r
+}\r
+\r
+\r
+/**\r
+ \r
+ Returns TRUE if DEBUG_CODE()macros are enabled.\r
+\r
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of \r
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+DebugCodeEnabled (\r
+ VOID\r
+ )\r
+{\r
+ return FALSE;\r
+}\r
+\r
+\r
+/**\r
+ \r
+ Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.\r
+\r
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of \r
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+DebugClearMemoryEnabled (\r
+ VOID\r
+ )\r
+{\r
+ return FALSE;\r
+}\r
--- /dev/null
+#/** @file\r
+# Component description file for Intrinsic Base Io Library\r
+#\r
+# I/O Library that uses compiler intrinsics to perform IN and OUT instructions\r
+# for IA-32 and x64. It also performs direct memory access for MMIO services.\r
+# Copyright (c) 2007 - 2007, Intel Corporation.\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BaseIoLibIntrinsic\r
+ FILE_GUID = 926c9cd0-4bb8-479b-9ac4-8a2a23f85307\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = IoLib \r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources.common]\r
+ IoLibMmioBuffer.c\r
+ CommonHeader.h\r
+\r
+[Sources.Ia32]\r
+ IoHighLevel.c\r
+ IoLibGcc.c\r
+ IoLibMsc.c\r
+ IoLib.c\r
+\r
+[Sources.X64]\r
+ IoHighLevel.c\r
+ IoLibGcc.c\r
+ IoLibMsc.c\r
+ IoLib.c\r
+\r
+[Sources.IPF]\r
+ IoHighLevel.c\r
+ IoLibIpf.c\r
+\r
+\r
+################################################################################\r
+#\r
+# Includes Section - list of Include locations that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Includes]\r
+ $(WORKSPACE)/MdePkg\Include/Library\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
+\r
+################################################################################\r
+#\r
+# Library Class Section - list of Library Classes that are required for\r
+# this module.\r
+#\r
+################################################################################\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ BaseLib\r
+\r
+[LibraryClasses.IPF]\r
+ PcdLib\r
+\r
+\r
+################################################################################\r
+#\r
+# Pcd FIXED_AT_BUILD - list of PCDs that this module is coded for.\r
+#\r
+################################################################################\r
+\r
+[PcdsFixedAtBuild.IPF]\r
+ PcdIoBlockBaseAddressForIpf|gEfiMdePkgTokenSpaceGuid\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <MsaHeader>
+ <ModuleName>BaseIoLibIntrinsic</ModuleName>
+ <ModuleType>BASE</ModuleType>
+ <GuidValue>926c9cd0-4bb8-479b-9ac4-8a2a23f85307</GuidValue>
+ <Version>1.0</Version>
+ <Abstract>Component description file for Intrinsic Base Io Library</Abstract>
+ <Description>I/O Library that uses compiler intrinsics to perform IN and OUT instructions
+ for IA-32 and x64. It also performs direct memory access for MMIO services.</Description>
+ <Copyright>Copyright (c) 2006 - 2007, Intel Corporation.</Copyright>
+ <License>All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>
+ <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>
+ </MsaHeader>
+ <ModuleDefinitions>
+ <SupportedArchitectures>IA32 X64 IPF</SupportedArchitectures>
+ <BinaryModule>false</BinaryModule>
+ <OutputFileBasename>BaseIoLibIntrinsic</OutputFileBasename>
+ </ModuleDefinitions>
+ <LibraryClassDefinitions>
+ <LibraryClass Usage="ALWAYS_PRODUCED">
+ <Keyword>IoLib</Keyword>
+ </LibraryClass>
+ <LibraryClass Usage="ALWAYS_CONSUMED">
+ <Keyword>BaseLib</Keyword>
+ </LibraryClass>
+ <LibraryClass Usage="ALWAYS_CONSUMED">
+ <Keyword>DebugLib</Keyword>
+ </LibraryClass>
+ <LibraryClass Usage="ALWAYS_CONSUMED" SupArchList="IPF">
+ <Keyword>PcdLib</Keyword>
+ </LibraryClass>
+ </LibraryClassDefinitions>
+ <SourceFiles>
+ <Filename>IoLibMmioBuffer.c</Filename>
+ <Filename SupArchList="IA32">IoLib.c</Filename>
+ <Filename SupArchList="IA32" ToolChainFamily="MSFT">IoLibMsc.c</Filename>
+ <Filename SupArchList="IA32" ToolChainFamily="GCC">IoLibGcc.c</Filename>
+ <Filename SupArchList="IA32">IoHighLevel.c</Filename>
+ <Filename SupArchList="X64">IoLib.c</Filename>
+ <Filename SupArchList="X64" ToolChainFamily="MSFT">IoLibMsc.c</Filename>
+ <Filename SupArchList="X64" ToolChainFamily="GCC">IoLibGcc.c</Filename>
+ <Filename SupArchList="X64">IoHighLevel.c</Filename>
+ <Filename SupArchList="IPF">IoLibIpf.c</Filename>
+ <Filename SupArchList="IPF">IoHighLevel.c</Filename>
+ </SourceFiles>
+ <PackageDependencies>
+ <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>
+ </PackageDependencies>
+ <Externs>
+ <Specification>EFI_SPECIFICATION_VERSION 0x00020000</Specification>
+ <Specification>EDK_RELEASE_VERSION 0x00020000</Specification>
+ </Externs>
+ <PcdCoded>
+ <PcdEntry PcdItemType="FIXED_AT_BUILD" Usage="ALWAYS_CONSUMED" SupArchList="IPF">
+ <C_Name>PcdIoBlockBaseAddressForIpf</C_Name>
+ <TokenSpaceGuidCName>gEfiMdePkgTokenSpaceGuid</TokenSpaceGuidCName>
+ <DefaultValue>0x0ffffc000000</DefaultValue>
+ <HelpText>The base address of IPF IO Block</HelpText>
+ </PcdEntry>
+ </PcdCoded>
+</ModuleSurfaceArea>
--- /dev/null
+/**@file\r
+ Common header file shared by all source files.\r
+\r
+ This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+ Copyright (c) 2007 - 2007, Intel Corporation.\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <Base.h>\r
+//\r
+// The protocols, PPI and GUID defintions for this module\r
+//\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/IoLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ High-level Io/Mmio functions.\r
+\r
+ All assertions for bit field operations are handled bit field functions in the\r
+ Base Library.\r
+\r
+ Copyright (c) 2006, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: IoHighLevel.c\r
+\r
+ The following IoLib instances share the same version of this file:\r
+\r
+ BaseIoLibIntrinsic\r
+ DxeIoLibCpuIo\r
+ PeiIoLibCpuIo\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+ Reads an 8-bit I/O port, performs a bitwise inclusive OR, and writes the\r
+ result back to the 8-bit I/O port.\r
+\r
+ Reads the 8-bit I/O port specified by Port, performs a bitwise inclusive OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 8-bit I/O port specified by Port. The value written to the I/O\r
+ port is returned. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param OrData The value to OR with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoOr8 (\r
+ IN UINTN Port,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));\r
+}\r
+\r
+/**\r
+ Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back\r
+ to the 8-bit I/O port.\r
+\r
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, and writes the result to\r
+ the 8-bit I/O port specified by Port. The value written to the I/O port is\r
+ returned. This function must guarantee that all I/O read and write operations\r
+ are serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoAnd8 (\r
+ IN UINTN Port,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));\r
+}\r
+\r
+/**\r
+ Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise\r
+ inclusive OR, and writes the result back to the 8-bit I/O port.\r
+\r
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, performs a bitwise OR\r
+ between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 8-bit I/O port specified by Port. The value\r
+ written to the I/O port is returned. This function must guarantee that all\r
+ I/O read and write operations are serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoAndThenOr8 (\r
+ IN UINTN Port,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+ Reads a bit field of an I/O register.\r
+\r
+ Reads the bit field in an 8-bit I/O register. The bit field is specified by\r
+ the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldRead8 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to an I/O register.\r
+\r
+ Writes Value to the bit field of the I/O register. The bit field is specified\r
+ by the StartBit and the EndBit. All other bits in the destination I/O\r
+ register are preserved. The value written to the I/O port is returned. Extra\r
+ left bits in Value are stripped.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldWrite8 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ return IoWrite8 (\r
+ Port,\r
+ BitFieldWrite8 (IoRead8 (Port), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the\r
+ result back to the bit field in the 8-bit port.\r
+\r
+ Reads the 8-bit I/O port specified by Port, performs a bitwise inclusive OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 8-bit I/O port specified by Port. The value written to the I/O\r
+ port is returned. This function must guarantee that all I/O read and write\r
+ operations are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param OrData The value to OR with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldOr8 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return IoWrite8 (\r
+ Port,\r
+ BitFieldOr8 (IoRead8 (Port), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the\r
+ result back to the bit field in the 8-bit port.\r
+\r
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, and writes the result to\r
+ the 8-bit I/O port specified by Port. The value written to the I/O port is\r
+ returned. This function must guarantee that all I/O read and write operations\r
+ are serialized. Extra left bits in AndData are stripped.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldAnd8 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ return IoWrite8 (\r
+ Port,\r
+ BitFieldAnd8 (IoRead8 (Port), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
+ bitwise inclusive OR, and writes the result back to the bit field in the\r
+ 8-bit port.\r
+\r
+ Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed\r
+ by a bitwise inclusive OR between the read result and the value specified by\r
+ AndData, and writes the result to the 8-bit I/O port specified by Port. The\r
+ value written to the I/O port is returned. This function must guarantee that\r
+ all I/O read and write operations are serialized. Extra left bits in both\r
+ AndData and OrData are stripped.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoBitFieldAndThenOr8 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return IoWrite8 (\r
+ Port,\r
+ BitFieldAndThenOr8 (IoRead8 (Port), StartBit, EndBit, AndData, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port, performs a bitwise inclusive OR, and writes the\r
+ result back to the 16-bit I/O port.\r
+\r
+ Reads the 16-bit I/O port specified by Port, performs a bitwise inclusive OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 16-bit I/O port specified by Port. The value written to the I/O\r
+ port is returned. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param OrData The value to OR with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoOr16 (\r
+ IN UINTN Port,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));\r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back\r
+ to the 16-bit I/O port.\r
+\r
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, and writes the result to\r
+ the 16-bit I/O port specified by Port. The value written to the I/O port is\r
+ returned. This function must guarantee that all I/O read and write operations\r
+ are serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoAnd16 (\r
+ IN UINTN Port,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));\r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise\r
+ inclusive OR, and writes the result back to the 16-bit I/O port.\r
+\r
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, performs a bitwise OR\r
+ between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 16-bit I/O port specified by Port. The value\r
+ written to the I/O port is returned. This function must guarantee that all\r
+ I/O read and write operations are serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoAndThenOr16 (\r
+ IN UINTN Port,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+ Reads a bit field of an I/O register.\r
+\r
+ Reads the bit field in a 16-bit I/O register. The bit field is specified by\r
+ the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldRead16 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to an I/O register.\r
+\r
+ Writes Value to the bit field of the I/O register. The bit field is specified\r
+ by the StartBit and the EndBit. All other bits in the destination I/O\r
+ register are preserved. The value written to the I/O port is returned. Extra\r
+ left bits in Value are stripped.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldWrite16 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ return IoWrite16 (\r
+ Port,\r
+ BitFieldWrite16 (IoRead16 (Port), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the\r
+ result back to the bit field in the 16-bit port.\r
+\r
+ Reads the 16-bit I/O port specified by Port, performs a bitwise inclusive OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 16-bit I/O port specified by Port. The value written to the I/O\r
+ port is returned. This function must guarantee that all I/O read and write\r
+ operations are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param OrData The value to OR with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldOr16 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return IoWrite16 (\r
+ Port,\r
+ BitFieldOr16 (IoRead16 (Port), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the\r
+ result back to the bit field in the 16-bit port.\r
+\r
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, and writes the result to\r
+ the 16-bit I/O port specified by Port. The value written to the I/O port is\r
+ returned. This function must guarantee that all I/O read and write operations\r
+ are serialized. Extra left bits in AndData are stripped.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldAnd16 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ return IoWrite16 (\r
+ Port,\r
+ BitFieldAnd16 (IoRead16 (Port), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
+ bitwise inclusive OR, and writes the result back to the bit field in the\r
+ 16-bit port.\r
+\r
+ Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed\r
+ by a bitwise inclusive OR between the read result and the value specified by\r
+ AndData, and writes the result to the 16-bit I/O port specified by Port. The\r
+ value written to the I/O port is returned. This function must guarantee that\r
+ all I/O read and write operations are serialized. Extra left bits in both\r
+ AndData and OrData are stripped.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoBitFieldAndThenOr16 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return IoWrite16 (\r
+ Port,\r
+ BitFieldAndThenOr16 (IoRead16 (Port), StartBit, EndBit, AndData, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port, performs a bitwise inclusive OR, and writes the\r
+ result back to the 32-bit I/O port.\r
+\r
+ Reads the 32-bit I/O port specified by Port, performs a bitwise inclusive OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 32-bit I/O port specified by Port. The value written to the I/O\r
+ port is returned. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param OrData The value to OR with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoOr32 (\r
+ IN UINTN Port,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return IoWrite32 (Port, IoRead32 (Port) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back\r
+ to the 32-bit I/O port.\r
+\r
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, and writes the result to\r
+ the 32-bit I/O port specified by Port. The value written to the I/O port is\r
+ returned. This function must guarantee that all I/O read and write operations\r
+ are serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoAnd32 (\r
+ IN UINTN Port,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ return IoWrite32 (Port, IoRead32 (Port) & AndData);\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise\r
+ inclusive OR, and writes the result back to the 32-bit I/O port.\r
+\r
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, performs a bitwise OR\r
+ between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 32-bit I/O port specified by Port. The value\r
+ written to the I/O port is returned. This function must guarantee that all\r
+ I/O read and write operations are serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoAndThenOr32 (\r
+ IN UINTN Port,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of an I/O register.\r
+\r
+ Reads the bit field in a 32-bit I/O register. The bit field is specified by\r
+ the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldRead32 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to an I/O register.\r
+\r
+ Writes Value to the bit field of the I/O register. The bit field is specified\r
+ by the StartBit and the EndBit. All other bits in the destination I/O\r
+ register are preserved. The value written to the I/O port is returned. Extra\r
+ left bits in Value are stripped.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldWrite32 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ return IoWrite32 (\r
+ Port,\r
+ BitFieldWrite32 (IoRead32 (Port), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the\r
+ result back to the bit field in the 32-bit port.\r
+\r
+ Reads the 32-bit I/O port specified by Port, performs a bitwise inclusive OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 32-bit I/O port specified by Port. The value written to the I/O\r
+ port is returned. This function must guarantee that all I/O read and write\r
+ operations are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param OrData The value to OR with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldOr32 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return IoWrite32 (\r
+ Port,\r
+ BitFieldOr32 (IoRead32 (Port), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the\r
+ result back to the bit field in the 32-bit port.\r
+\r
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, and writes the result to\r
+ the 32-bit I/O port specified by Port. The value written to the I/O port is\r
+ returned. This function must guarantee that all I/O read and write operations\r
+ are serialized. Extra left bits in AndData are stripped.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldAnd32 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ return IoWrite32 (\r
+ Port,\r
+ BitFieldAnd32 (IoRead32 (Port), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
+ bitwise inclusive OR, and writes the result back to the bit field in the\r
+ 32-bit port.\r
+\r
+ Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed\r
+ by a bitwise inclusive OR between the read result and the value specified by\r
+ AndData, and writes the result to the 32-bit I/O port specified by Port. The\r
+ value written to the I/O port is returned. This function must guarantee that\r
+ all I/O read and write operations are serialized. Extra left bits in both\r
+ AndData and OrData are stripped.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoBitFieldAndThenOr32 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return IoWrite32 (\r
+ Port,\r
+ BitFieldAndThenOr32 (IoRead32 (Port), StartBit, EndBit, AndData, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 64-bit I/O port, performs a bitwise inclusive OR, and writes the\r
+ result back to the 64-bit I/O port.\r
+\r
+ Reads the 64-bit I/O port specified by Port, performs a bitwise inclusive OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 64-bit I/O port specified by Port. The value written to the I/O\r
+ port is returned. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param OrData The value to OR with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoOr64 (\r
+ IN UINTN Port,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return IoWrite64 (Port, IoRead64 (Port) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back\r
+ to the 64-bit I/O port.\r
+\r
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, and writes the result to\r
+ the 64-bit I/O port specified by Port. The value written to the I/O port is\r
+ returned. This function must guarantee that all I/O read and write operations\r
+ are serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoAnd64 (\r
+ IN UINTN Port,\r
+ IN UINT64 AndData\r
+ )\r
+{\r
+ return IoWrite64 (Port, IoRead64 (Port) & AndData);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise\r
+ inclusive OR, and writes the result back to the 64-bit I/O port.\r
+\r
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, performs a bitwise OR\r
+ between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 64-bit I/O port specified by Port. The value\r
+ written to the I/O port is returned. This function must guarantee that all\r
+ I/O read and write operations are serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoAndThenOr64 (\r
+ IN UINTN Port,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of an I/O register.\r
+\r
+ Reads the bit field in a 64-bit I/O register. The bit field is specified by\r
+ the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldRead64 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to an I/O register.\r
+\r
+ Writes Value to the bit field of the I/O register. The bit field is specified\r
+ by the StartBit and the EndBit. All other bits in the destination I/O\r
+ register are preserved. The value written to the I/O port is returned. Extra\r
+ left bits in Value are stripped.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldWrite64 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ return IoWrite64 (\r
+ Port,\r
+ BitFieldWrite64 (IoRead64 (Port), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the\r
+ result back to the bit field in the 64-bit port.\r
+\r
+ Reads the 64-bit I/O port specified by Port, performs a bitwise inclusive OR\r
+ between the read result and the value specified by OrData, and writes the\r
+ result to the 64-bit I/O port specified by Port. The value written to the I/O\r
+ port is returned. This function must guarantee that all I/O read and write\r
+ operations are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param OrData The value to OR with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldOr64 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return IoWrite64 (\r
+ Port,\r
+ BitFieldOr64 (IoRead64 (Port), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the\r
+ result back to the bit field in the 64-bit port.\r
+\r
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND between\r
+ the read result and the value specified by AndData, and writes the result to\r
+ the 64-bit I/O port specified by Port. The value written to the I/O port is\r
+ returned. This function must guarantee that all I/O read and write operations\r
+ are serialized. Extra left bits in AndData are stripped.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldAnd64 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
+ )\r
+{\r
+ return IoWrite64 (\r
+ Port,\r
+ BitFieldAnd64 (IoRead64 (Port), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit port, performs a bitwise AND followed by a\r
+ bitwise inclusive OR, and writes the result back to the bit field in the\r
+ 64-bit port.\r
+\r
+ Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed\r
+ by a bitwise inclusive OR between the read result and the value specified by\r
+ AndData, and writes the result to the 64-bit I/O port specified by Port. The\r
+ value written to the I/O port is returned. This function must guarantee that\r
+ all I/O read and write operations are serialized. Extra left bits in both\r
+ AndData and OrData are stripped.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with the read value from the I/O port.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoBitFieldAndThenOr64 (\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return IoWrite64 (\r
+ Port,\r
+ BitFieldAndThenOr64 (IoRead64 (Port), StartBit, EndBit, AndData, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads an 8-bit MMIO register, performs a bitwise inclusive OR, and writes the\r
+ result back to the 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise\r
+ inclusive OR between the read result and the value specified by OrData, and\r
+ writes the result to the 8-bit MMIO register specified by Address. The value\r
+ written to the MMIO register is returned. This function must guarantee that\r
+ all MMIO read and write operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param OrData The value to OR with the read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioOr8 (\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));\r
+}\r
+\r
+/**\r
+ Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result\r
+ back to the 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, and writes the\r
+ result to the 8-bit MMIO register specified by Address. The value written to\r
+ the MMIO register is returned. This function must guarantee that all MMIO\r
+ read and write operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param AndData The value to AND with the read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioAnd8 (\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));\r
+}\r
+\r
+/**\r
+ Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise\r
+ inclusive OR, and writes the result back to the 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, performs a\r
+ bitwise OR between the result of the AND operation and the value specified by\r
+ OrData, and writes the result to the 8-bit MMIO register specified by\r
+ Address. The value written to the MMIO register is returned. This function\r
+ must guarantee that all MMIO read and write operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+\r
+ @param Address The MMIO register to write.\r
+ @param AndData The value to AND with the read value from the MMIO register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioAndThenOr8 (\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+ Reads a bit field of a MMIO register.\r
+\r
+ Reads the bit field in an 8-bit MMIO register. The bit field is specified by\r
+ the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldRead8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a MMIO register.\r
+\r
+ Writes Value to the bit field of the MMIO register. The bit field is\r
+ specified by the StartBit and the EndBit. All other bits in the destination\r
+ MMIO register are preserved. The new value of the 8-bit register is returned.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldWrite8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ return MmioWrite8 (\r
+ Address,\r
+ BitFieldWrite8 (MmioRead8 (Address), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise\r
+ inclusive OR between the read result and the value specified by OrData, and\r
+ writes the result to the 8-bit MMIO register specified by Address. The value\r
+ written to the MMIO register is returned. This function must guarantee that\r
+ all MMIO read and write operations are serialized. Extra left bits in OrData\r
+ are stripped.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param OrData The value to OR with read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldOr8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return MmioWrite8 (\r
+ Address,\r
+ BitFieldOr8 (MmioRead8 (Address), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and\r
+ writes the result back to the bit field in the 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, and writes the\r
+ result to the 8-bit MMIO register specified by Address. The value written to\r
+ the MMIO register is returned. This function must guarantee that all MMIO\r
+ read and write operations are serialized. Extra left bits in AndData are\r
+ stripped.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldAnd8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ return MmioWrite8 (\r
+ Address,\r
+ BitFieldAnd8 (MmioRead8 (Address), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed\r
+ by a bitwise inclusive OR, and writes the result back to the bit field in the\r
+ 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address, performs a bitwise AND\r
+ followed by a bitwise inclusive OR between the read result and the value\r
+ specified by AndData, and writes the result to the 8-bit MMIO register\r
+ specified by Address. The value written to the MMIO register is returned.\r
+ This function must guarantee that all MMIO read and write operations are\r
+ serialized. Extra left bits in both AndData and OrData are stripped.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with read value from the MMIO register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioBitFieldAndThenOr8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ return MmioWrite8 (\r
+ Address,\r
+ BitFieldAndThenOr8 (MmioRead8 (Address), StartBit, EndBit, AndData, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 16-bit MMIO register, performs a bitwise inclusive OR, and writes the\r
+ result back to the 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise\r
+ inclusive OR between the read result and the value specified by OrData, and\r
+ writes the result to the 16-bit MMIO register specified by Address. The value\r
+ written to the MMIO register is returned. This function must guarantee that\r
+ all MMIO read and write operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param OrData The value to OR with the read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioOr16 (\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));\r
+}\r
+\r
+/**\r
+ Reads a 16-bit MMIO register, performs a bitwise AND, and writes the result\r
+ back to the 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, and writes the\r
+ result to the 16-bit MMIO register specified by Address. The value written to\r
+ the MMIO register is returned. This function must guarantee that all MMIO\r
+ read and write operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param AndData The value to AND with the read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioAnd16 (\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));\r
+}\r
+\r
+/**\r
+ Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise\r
+ inclusive OR, and writes the result back to the 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, performs a\r
+ bitwise OR between the result of the AND operation and the value specified by\r
+ OrData, and writes the result to the 16-bit MMIO register specified by\r
+ Address. The value written to the MMIO register is returned. This function\r
+ must guarantee that all MMIO read and write operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+\r
+ @param Address The MMIO register to write.\r
+ @param AndData The value to AND with the read value from the MMIO register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioAndThenOr16 (\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));\r
+}\r
+\r
+/**\r
+ Reads a bit field of a MMIO register.\r
+\r
+ Reads the bit field in a 16-bit MMIO register. The bit field is specified by\r
+ the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldRead16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a MMIO register.\r
+\r
+ Writes Value to the bit field of the MMIO register. The bit field is\r
+ specified by the StartBit and the EndBit. All other bits in the destination\r
+ MMIO register are preserved. The new value of the 16-bit register is returned.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldWrite16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ return MmioWrite16 (\r
+ Address,\r
+ BitFieldWrite16 (MmioRead16 (Address), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise\r
+ inclusive OR between the read result and the value specified by OrData, and\r
+ writes the result to the 16-bit MMIO register specified by Address. The value\r
+ written to the MMIO register is returned. This function must guarantee that\r
+ all MMIO read and write operations are serialized. Extra left bits in OrData\r
+ are stripped.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param OrData The value to OR with read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldOr16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return MmioWrite16 (\r
+ Address,\r
+ BitFieldOr16 (MmioRead16 (Address), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and\r
+ writes the result back to the bit field in the 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, and writes the\r
+ result to the 16-bit MMIO register specified by Address. The value written to\r
+ the MMIO register is returned. This function must guarantee that all MMIO\r
+ read and write operations are serialized. Extra left bits in AndData are\r
+ stripped.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldAnd16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ return MmioWrite16 (\r
+ Address,\r
+ BitFieldAnd16 (MmioRead16 (Address), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed\r
+ by a bitwise inclusive OR, and writes the result back to the bit field in the\r
+ 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address, performs a bitwise AND\r
+ followed by a bitwise inclusive OR between the read result and the value\r
+ specified by AndData, and writes the result to the 16-bit MMIO register\r
+ specified by Address. The value written to the MMIO register is returned.\r
+ This function must guarantee that all MMIO read and write operations are\r
+ serialized. Extra left bits in both AndData and OrData are stripped.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with read value from the MMIO register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioBitFieldAndThenOr16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ return MmioWrite16 (\r
+ Address,\r
+ BitFieldAndThenOr16 (MmioRead16 (Address), StartBit, EndBit, AndData, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 32-bit MMIO register, performs a bitwise inclusive OR, and writes the\r
+ result back to the 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise\r
+ inclusive OR between the read result and the value specified by OrData, and\r
+ writes the result to the 32-bit MMIO register specified by Address. The value\r
+ written to the MMIO register is returned. This function must guarantee that\r
+ all MMIO read and write operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param OrData The value to OR with the read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioOr32 (\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return MmioWrite32 (Address, MmioRead32 (Address) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a 32-bit MMIO register, performs a bitwise AND, and writes the result\r
+ back to the 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, and writes the\r
+ result to the 32-bit MMIO register specified by Address. The value written to\r
+ the MMIO register is returned. This function must guarantee that all MMIO\r
+ read and write operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param AndData The value to AND with the read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioAnd32 (\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ return MmioWrite32 (Address, MmioRead32 (Address) & AndData);\r
+}\r
+\r
+/**\r
+ Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise\r
+ inclusive OR, and writes the result back to the 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, performs a\r
+ bitwise OR between the result of the AND operation and the value specified by\r
+ OrData, and writes the result to the 32-bit MMIO register specified by\r
+ Address. The value written to the MMIO register is returned. This function\r
+ must guarantee that all MMIO read and write operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+\r
+ @param Address The MMIO register to write.\r
+ @param AndData The value to AND with the read value from the MMIO register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioAndThenOr32 (\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of a MMIO register.\r
+\r
+ Reads the bit field in a 32-bit MMIO register. The bit field is specified by\r
+ the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldRead32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a MMIO register.\r
+\r
+ Writes Value to the bit field of the MMIO register. The bit field is\r
+ specified by the StartBit and the EndBit. All other bits in the destination\r
+ MMIO register are preserved. The new value of the 32-bit register is returned.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldWrite32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ return MmioWrite32 (\r
+ Address,\r
+ BitFieldWrite32 (MmioRead32 (Address), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise\r
+ inclusive OR between the read result and the value specified by OrData, and\r
+ writes the result to the 32-bit MMIO register specified by Address. The value\r
+ written to the MMIO register is returned. This function must guarantee that\r
+ all MMIO read and write operations are serialized. Extra left bits in OrData\r
+ are stripped.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param OrData The value to OR with read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldOr32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return MmioWrite32 (\r
+ Address,\r
+ BitFieldOr32 (MmioRead32 (Address), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and\r
+ writes the result back to the bit field in the 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, and writes the\r
+ result to the 32-bit MMIO register specified by Address. The value written to\r
+ the MMIO register is returned. This function must guarantee that all MMIO\r
+ read and write operations are serialized. Extra left bits in AndData are\r
+ stripped.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldAnd32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ return MmioWrite32 (\r
+ Address,\r
+ BitFieldAnd32 (MmioRead32 (Address), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed\r
+ by a bitwise inclusive OR, and writes the result back to the bit field in the\r
+ 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address, performs a bitwise AND\r
+ followed by a bitwise inclusive OR between the read result and the value\r
+ specified by AndData, and writes the result to the 32-bit MMIO register\r
+ specified by Address. The value written to the MMIO register is returned.\r
+ This function must guarantee that all MMIO read and write operations are\r
+ serialized. Extra left bits in both AndData and OrData are stripped.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with read value from the MMIO register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioBitFieldAndThenOr32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ return MmioWrite32 (\r
+ Address,\r
+ BitFieldAndThenOr32 (MmioRead32 (Address), StartBit, EndBit, AndData, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MMIO register, performs a bitwise inclusive OR, and writes the\r
+ result back to the 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise\r
+ inclusive OR between the read result and the value specified by OrData, and\r
+ writes the result to the 64-bit MMIO register specified by Address. The value\r
+ written to the MMIO register is returned. This function must guarantee that\r
+ all MMIO read and write operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param OrData The value to OR with the read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioOr64 (\r
+ IN UINTN Address,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return MmioWrite64 (Address, MmioRead64 (Address) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MMIO register, performs a bitwise AND, and writes the result\r
+ back to the 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, and writes the\r
+ result to the 64-bit MMIO register specified by Address. The value written to\r
+ the MMIO register is returned. This function must guarantee that all MMIO\r
+ read and write operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param AndData The value to AND with the read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioAnd64 (\r
+ IN UINTN Address,\r
+ IN UINT64 AndData\r
+ )\r
+{\r
+ return MmioWrite64 (Address, MmioRead64 (Address) & AndData);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise\r
+ inclusive OR, and writes the result back to the 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, performs a\r
+ bitwise OR between the result of the AND operation and the value specified by\r
+ OrData, and writes the result to the 64-bit MMIO register specified by\r
+ Address. The value written to the MMIO register is returned. This function\r
+ must guarantee that all MMIO read and write operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+\r
+ @param Address The MMIO register to write.\r
+ @param AndData The value to AND with the read value from the MMIO register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioAndThenOr64 (\r
+ IN UINTN Address,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of a MMIO register.\r
+\r
+ Reads the bit field in a 64-bit MMIO register. The bit field is specified by\r
+ the StartBit and the EndBit. The value of the bit field is returned.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldRead64 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a MMIO register.\r
+\r
+ Writes Value to the bit field of the MMIO register. The bit field is\r
+ specified by the StartBit and the EndBit. All other bits in the destination\r
+ MMIO register are preserved. The new value of the 64-bit register is returned.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldWrite64 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ return MmioWrite64 (\r
+ Address,\r
+ BitFieldWrite64 (MmioRead64 (Address), StartBit, EndBit, Value)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise\r
+ inclusive OR between the read result and the value specified by OrData, and\r
+ writes the result to the 64-bit MMIO register specified by Address. The value\r
+ written to the MMIO register is returned. This function must guarantee that\r
+ all MMIO read and write operations are serialized. Extra left bits in OrData\r
+ are stripped.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param OrData The value to OR with read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldOr64 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return MmioWrite64 (\r
+ Address,\r
+ BitFieldOr64 (MmioRead64 (Address), StartBit, EndBit, OrData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and\r
+ writes the result back to the bit field in the 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
+ between the read result and the value specified by AndData, and writes the\r
+ result to the 64-bit MMIO register specified by Address. The value written to\r
+ the MMIO register is returned. This function must guarantee that all MMIO\r
+ read and write operations are serialized. Extra left bits in AndData are\r
+ stripped.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with read value from the MMIO register.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldAnd64 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
+ )\r
+{\r
+ return MmioWrite64 (\r
+ Address,\r
+ BitFieldAnd64 (MmioRead64 (Address), StartBit, EndBit, AndData)\r
+ );\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed\r
+ by a bitwise inclusive OR, and writes the result back to the bit field in the\r
+ 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address, performs a bitwise AND\r
+ followed by a bitwise inclusive OR between the read result and the value\r
+ specified by AndData, and writes the result to the 64-bit MMIO register\r
+ specified by Address. The value written to the MMIO register is returned.\r
+ This function must guarantee that all MMIO read and write operations are\r
+ serialized. Extra left bits in both AndData and OrData are stripped.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+ If StartBit is greater than 63, then ASSERT().\r
+ If EndBit is greater than 63, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address MMIO register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..63.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..63.\r
+ @param AndData The value to AND with read value from the MMIO register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioBitFieldAndThenOr64 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
+ )\r
+{\r
+ return MmioWrite64 (\r
+ Address,\r
+ BitFieldAndThenOr64 (MmioRead64 (Address), StartBit, EndBit, AndData, OrData)\r
+ );\r
+}\r
--- /dev/null
+/** @file\r
+ Common I/O Library routines.\r
+\r
+ Copyright (c) 2006, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: IoLib.c\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+ Reads a 64-bit I/O port.\r
+\r
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoRead64 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit I/O port.\r
+\r
+ Writes the 64-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoWrite64 (\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ I/O Library. This file has compiler specifics for GCC as there is no\r
+ ANSI C standard for doing IO.\r
+\r
+ GCC - uses EFIAPI assembler. __asm__ calls GAS. __volatile__ makes sure the\r
+ compiler puts the assembler in this exact location. The complex GNUC\r
+ operations are not optimzed. It would be possible to also write these\r
+ with EFIAPI assembler.\r
+\r
+ We don't advocate putting compiler specifics in libraries or drivers but there\r
+ is no other way to make this work.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: IoLibGcc.c\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+ Reads an 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioRead8 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ return *(volatile UINT8*)Address;\r
+}\r
+\r
+/**\r
+ Writes an 8-bit MMIO register.\r
+\r
+ Writes the 8-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioWrite8 (\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ return *(volatile UINT8*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioRead16 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT ((Address & 1) == 0);\r
+ return *(volatile UINT16*)Address;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit MMIO register.\r
+\r
+ Writes the 16-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioWrite16 (\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 1) == 0);\r
+ return *(volatile UINT16*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioRead32 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT ((Address & 3) == 0);\r
+ return *(volatile UINT32*)Address;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit MMIO register.\r
+\r
+ Writes the 32-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioWrite32 (\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 3) == 0);\r
+ return *(volatile UINT32*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioRead64 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ ASSERT ((Address & 7) == 0);\r
+ return *(volatile UINT64*)Address;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit MMIO register.\r
+\r
+ Writes the 64-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioWrite64 (\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 7) == 0);\r
+ return *(volatile UINT64*)Address = Value;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Reads an 8-bit I/O port.\r
+\r
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+__inline__\r
+UINT8\r
+EFIAPI\r
+IoRead8 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT8 Data;\r
+\r
+ __asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes an 8-bit I/O port.\r
+\r
+ Writes the 8-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+__inline__\r
+UINT8\r
+EFIAPI\r
+IoWrite8 (\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+ return Value;;\r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port.\r
+\r
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+__inline__\r
+UINT16\r
+EFIAPI\r
+IoRead16 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT16 Data;\r
+\r
+ ASSERT ((Port & 1) == 0);\r
+ __asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit I/O port.\r
+\r
+ Writes the 16-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+__inline__\r
+UINT16\r
+EFIAPI\r
+IoWrite16 (\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT ((Port & 1) == 0);\r
+ __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+ return Value;;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port.\r
+\r
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+__inline__\r
+UINT32\r
+EFIAPI\r
+IoRead32 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT32 Data;\r
+\r
+ ASSERT ((Port & 3) == 0);\r
+ __asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit I/O port.\r
+\r
+ Writes the 32-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+__inline__\r
+UINT32\r
+EFIAPI\r
+IoWrite32 (\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT ((Port & 3) == 0);\r
+ __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
+ return Value;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ Common I/O Library routines.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: IoLibIpf.c\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+#define MAP_PORT_BASE_TO_MEM(_Port) \\r
+ ((((_Port) & 0xfffc) << 10) | ((_Port) & 0x0fff))\r
+\r
+/**\r
+ Reads a 8-bit I/O port.\r
+\r
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoRead8 (\r
+ IN UINT64 Port\r
+ )\r
+{\r
+ UINT64 Address;\r
+\r
+ //\r
+ // Add the 64MB aligned IO Port space to the IO address\r
+ //\r
+ Address = MAP_PORT_BASE_TO_MEM (Port);\r
+ Address += PcdGet64(PcdIoBlockBaseAddressForIpf);\r
+\r
+ return MmioRead8 (Address);\r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port.\r
+\r
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoRead16 (\r
+ IN UINT64 Port\r
+ )\r
+{\r
+ UINT64 Address;\r
+\r
+ //\r
+ // Add the 64MB aligned IO Port space to the IO address\r
+ //\r
+ Address = MAP_PORT_BASE_TO_MEM (Port);\r
+ Address += PcdGet64(PcdIoBlockBaseAddressForIpf);\r
+\r
+ return MmioRead16 (Address);\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port.\r
+\r
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoRead32 (\r
+ IN UINT64 Port\r
+ )\r
+{\r
+ UINT64 Address;\r
+\r
+ //\r
+ // Add the 64MB aligned IO Port space to the IO address\r
+ //\r
+ Address = MAP_PORT_BASE_TO_MEM (Port);\r
+ Address += PcdGet64(PcdIoBlockBaseAddressForIpf);\r
+\r
+ return MmioRead32 (Address);\r
+}\r
+\r
+/**\r
+ Reads a 64-bit I/O port.\r
+\r
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoRead64 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Writes a 8-bit I/O port.\r
+\r
+ Writes the 8-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoWrite8 (\r
+ IN UINT64 Port,\r
+ IN UINT8 Data\r
+ )\r
+{\r
+ UINT64 Address;\r
+\r
+ //\r
+ // Add the 64MB aligned IO Port space to the IO address\r
+ //\r
+ Address = MAP_PORT_BASE_TO_MEM (Port);\r
+ Address += PcdGet64(PcdIoBlockBaseAddressForIpf);\r
+\r
+ return MmioWrite8 (Address, Data);\r
+}\r
+\r
+/**\r
+ Writes a 16-bit I/O port.\r
+\r
+ Writes the 16-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoWrite16 (\r
+ IN UINT64 Port,\r
+ IN UINT16 Data\r
+ )\r
+{\r
+ UINT64 Address;\r
+\r
+ //\r
+ // Add the 64MB aligned IO Port space to the IO address\r
+ //\r
+ Address = MAP_PORT_BASE_TO_MEM (Port);\r
+ Address += PcdGet64(PcdIoBlockBaseAddressForIpf);\r
+\r
+ return MmioWrite16 (Address, Data);\r
+}\r
+\r
+/**\r
+ Writes a 32-bit I/O port.\r
+\r
+ Writes the 32-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoWrite32 (\r
+ IN UINT64 Port,\r
+ IN UINT32 Data\r
+ )\r
+{\r
+ UINT64 Address;\r
+\r
+ //\r
+ // Add the 64MB aligned IO Port space to the IO address\r
+ //\r
+ Address = MAP_PORT_BASE_TO_MEM (Port);\r
+ Address += PcdGet64(PcdIoBlockBaseAddressForIpf);\r
+\r
+ return MmioWrite32 (Address, Data);\r
+}\r
+\r
+/**\r
+ Writes a 64-bit I/O port.\r
+\r
+ Writes the 64-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 64-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+IoWrite64 (\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT (FALSE);\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Reads a 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioRead8 (\r
+ IN UINT64 Address\r
+ )\r
+{\r
+ UINT8 Data;\r
+\r
+ Address |= BIT63;\r
+\r
+ MemoryFence ();\r
+ Data = *((volatile UINT8 *) Address);\r
+ MemoryFence ();\r
+\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Reads a 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioRead16 (\r
+ IN UINT64 Address\r
+ )\r
+{\r
+ UINT16 Data;\r
+\r
+ Address |= BIT63;\r
+\r
+ MemoryFence ();\r
+ Data = *((volatile UINT16 *) Address);\r
+ MemoryFence ();\r
+\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioRead32 (\r
+ IN UINT64 Address\r
+ )\r
+{\r
+ UINT32 Data;\r
+\r
+ Address |= BIT63;\r
+\r
+ MemoryFence ();\r
+ Data = *((volatile UINT32 *) Address);\r
+ MemoryFence ();\r
+\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioRead64 (\r
+ IN UINT64 Address\r
+ )\r
+{\r
+ UINT64 Data;\r
+\r
+ Address |= BIT63;\r
+\r
+ MemoryFence ();\r
+ Data = *((volatile UINT64 *) Address);\r
+ MemoryFence ();\r
+\r
+ return Data;\r
+\r
+}\r
+\r
+/**\r
+ Writes a 8-bit MMIO register.\r
+\r
+ Writes the 8-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Data The value to write to the MMIO register.\r
+\r
+ @return The value written the memory address.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioWrite8 (\r
+ IN UINT64 Address,\r
+ IN UINT8 Data\r
+ )\r
+{\r
+ Address |= BIT63;\r
+\r
+ MemoryFence ();\r
+ *((volatile UINT8 *) Address) = Data;\r
+ MemoryFence ();\r
+\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit MMIO register.\r
+\r
+ Writes the 16-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Data The value to write to the MMIO register.\r
+\r
+ @return The value written the memory address.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioWrite16 (\r
+ IN UINT64 Address,\r
+ IN UINT16 Data\r
+ )\r
+{\r
+ Address |= BIT63;\r
+\r
+ MemoryFence ();\r
+ *((volatile UINT16 *) Address) = Data;\r
+ MemoryFence ();\r
+\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit MMIO register.\r
+\r
+ Writes the 32-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Data The value to write to the MMIO register.\r
+\r
+ @return The value written the memory address.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioWrite32 (\r
+ IN UINT64 Address,\r
+ IN UINT32 Data\r
+ )\r
+{\r
+ Address |= BIT63;\r
+\r
+ MemoryFence ();\r
+ *((volatile UINT32 *) Address) = Data;\r
+ MemoryFence ();\r
+\r
+ return Data;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit MMIO register.\r
+\r
+ Writes the 64-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Data The value to write to the MMIO register.\r
+\r
+ @return The value written the memory address.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioWrite64 (\r
+ IN UINT64 Address,\r
+ IN UINT64 Data\r
+ )\r
+{\r
+ Address |= BIT63;\r
+\r
+ MemoryFence ();\r
+ *((volatile UINT64 *) Address) = Data;\r
+ MemoryFence ();\r
+\r
+ return Data;\r
+}\r
--- /dev/null
+/** @file\r
+ I/O Library MMIO Buffer Functions.\r
+\r
+ Copyright (c) 2007, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+ Copy data from MMIO region to system memory by using 8-bit access.\r
+\r
+ Copy data from MMIO region specified by starting address StartAddress \r
+ to system memory specified by Buffer by using 8-bit access. The total \r
+ number of byte to be copied is specified by Length. Buffer is returned.\r
+ \r
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). \r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+\r
+ @param StartAddress Starting address for the MMIO region to be copied from.\r
+ @param Length Size in bytes of the copy.\r
+ @param Buffer Pointer to a system memory buffer receiving the data read.\r
+\r
+ @return Buffer\r
+\r
+**/\r
+UINT8 *\r
+EFIAPI\r
+MmioReadBuffer8 (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer\r
+ )\r
+{\r
+ UINT8 *ReturnBuffer;\r
+\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ \r
+ ReturnBuffer = Buffer;\r
+ \r
+ while (Length--) {\r
+ *(Buffer++) = MmioRead8 (StartAddress++);\r
+ }\r
+\r
+ return ReturnBuffer;\r
+}\r
+\r
+/**\r
+ Copy data from MMIO region to system memory by using 16-bit access.\r
+\r
+ Copy data from MMIO region specified by starting address StartAddress \r
+ to system memory specified by Buffer by using 16-bit access. The total \r
+ number of byte to be copied is specified by Length. Buffer is returned.\r
+ \r
+ If StartAddress is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). \r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ If Length is not aligned on a 16-bit boundary, then ASSERT().\r
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param StartAddress Starting address for the MMIO region to be copied from.\r
+ @param Length Size in bytes of the copy.\r
+ @param Buffer Pointer to a system memory buffer receiving the data read.\r
+\r
+ @return Buffer\r
+\r
+**/\r
+UINT16 *\r
+EFIAPI\r
+MmioReadBuffer16 (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT16 *Buffer\r
+ )\r
+{\r
+ UINT16 *ReturnBuffer;\r
+\r
+ ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
+ \r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+ ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ \r
+ ReturnBuffer = Buffer;\r
+ \r
+ while (Length) {\r
+ *(Buffer++) = MmioRead16 (StartAddress);\r
+ StartAddress += sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
+ }\r
+\r
+ return ReturnBuffer;\r
+}\r
+\r
+/**\r
+ Copy data from MMIO region to system memory by using 32-bit access.\r
+\r
+ Copy data from MMIO region specified by starting address StartAddress \r
+ to system memory specified by Buffer by using 32-bit access. The total \r
+ number of byte to be copied is specified by Length. Buffer is returned.\r
+ \r
+ If StartAddress is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). \r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ If Length is not aligned on a 32-bit boundary, then ASSERT().\r
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param StartAddress Starting address for the MMIO region to be copied from.\r
+ @param Length Size in bytes of the copy.\r
+ @param Buffer Pointer to a system memory buffer receiving the data read.\r
+\r
+ @return Buffer\r
+\r
+**/\r
+UINT32 *\r
+EFIAPI\r
+MmioReadBuffer32 (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT32 *Buffer\r
+ )\r
+{\r
+ UINT32 *ReturnBuffer;\r
+\r
+ ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
+ \r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+ ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ \r
+ ReturnBuffer = Buffer;\r
+ \r
+ while (Length) {\r
+ *(Buffer++) = MmioRead32 (StartAddress);\r
+ StartAddress += sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
+ }\r
+\r
+ return ReturnBuffer;\r
+}\r
+\r
+/**\r
+ Copy data from MMIO region to system memory by using 64-bit access.\r
+\r
+ Copy data from MMIO region specified by starting address StartAddress \r
+ to system memory specified by Buffer by using 64-bit access. The total \r
+ number of byte to be copied is specified by Length. Buffer is returned.\r
+ \r
+ If StartAddress is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). \r
+ If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().\r
+\r
+ If Length is not aligned on a 64-bit boundary, then ASSERT().\r
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+ @param StartAddress Starting address for the MMIO region to be copied from.\r
+ @param Length Size in bytes of the copy.\r
+ @param Buffer Pointer to a system memory buffer receiving the data read.\r
+\r
+ @return Buffer\r
+\r
+**/\r
+UINT64 *\r
+EFIAPI\r
+MmioReadBuffer64 (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT64 *Buffer\r
+ )\r
+{\r
+ UINT64 *ReturnBuffer;\r
+\r
+ ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
+ \r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+ ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ \r
+ ReturnBuffer = Buffer;\r
+ \r
+ while (Length) {\r
+ *(Buffer++) = MmioRead64 (StartAddress);\r
+ StartAddress += sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
+ }\r
+\r
+ return ReturnBuffer;\r
+}\r
+\r
+\r
+/**\r
+ Copy data from system memory to MMIO region by using 8-bit access.\r
+\r
+ Copy data from system memory specified by Buffer to MMIO region specified \r
+ by starting address StartAddress by using 8-bit access. The total number \r
+ of byte to be copied is specified by Length. Buffer is returned.\r
+ \r
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). \r
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
+\r
+\r
+ @param StartAddress Starting address for the MMIO region to be copied to.\r
+ @param Length Size in bytes of the copy.\r
+ @param Buffer Pointer to a system memory buffer containing the data to write.\r
+\r
+ @return Size in bytes of the copy.\r
+\r
+**/\r
+UINT8 *\r
+EFIAPI\r
+MmioWriteBuffer8 (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT8 *Buffer\r
+ )\r
+{\r
+ VOID* ReturnBuffer;\r
+\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ \r
+ ReturnBuffer = (UINT8 *) Buffer;\r
+ \r
+ while (Length--) {\r
+ MmioWrite8 (StartAddress++, *(Buffer++));\r
+ }\r
+\r
+ return ReturnBuffer;\r
+ \r
+}\r
+\r
+/**\r
+ Copy data from system memory to MMIO region by using 16-bit access.\r
+\r
+ Copy data from system memory specified by Buffer to MMIO region specified \r
+ by starting address StartAddress by using 16-bit access. The total number \r
+ of byte to be copied is specified by Length. Length is returned.\r
+ \r
+ If StartAddress is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). \r
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
+\r
+ If Length is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ If Buffer is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param StartAddress Starting address for the MMIO region to be copied to.\r
+ @param Length Size in bytes of the copy.\r
+ @param Buffer Pointer to a system memory buffer containing the data to write.\r
+\r
+ @return Size in bytes of the copy.\r
+\r
+**/\r
+UINT16 *\r
+EFIAPI\r
+MmioWriteBuffer16 (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT16 *Buffer\r
+ )\r
+{\r
+ UINT16 *ReturnBuffer;\r
+\r
+ ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
+ \r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+ ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+\r
+ ReturnBuffer = (UINT16 *) Buffer;\r
+ \r
+ while (Length) {\r
+ MmioWrite16 (StartAddress, *(Buffer++));\r
+ \r
+ StartAddress += sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
+ }\r
+\r
+ return ReturnBuffer;\r
+}\r
+\r
+\r
+/**\r
+ Copy data from system memory to MMIO region by using 32-bit access.\r
+\r
+ Copy data from system memory specified by Buffer to MMIO region specified \r
+ by starting address StartAddress by using 32-bit access. The total number \r
+ of byte to be copied is specified by Length. Length is returned.\r
+ \r
+ If StartAddress is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). \r
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
+\r
+ If Length is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ If Buffer is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param StartAddress Starting address for the MMIO region to be copied to.\r
+ @param Length Size in bytes of the copy.\r
+ @param Buffer Pointer to a system memory buffer containing the data to write.\r
+\r
+ @return Size in bytes of the copy.\r
+\r
+**/\r
+UINT32 *\r
+EFIAPI\r
+MmioWriteBuffer32 (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT32 *Buffer\r
+ )\r
+{\r
+ UINT32 *ReturnBuffer;\r
+\r
+ ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
+ \r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+ ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+\r
+ ReturnBuffer = (UINT32 *) Buffer;\r
+ \r
+ while (Length) {\r
+ MmioWrite32 (StartAddress, *(Buffer++));\r
+ \r
+ StartAddress += sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
+ }\r
+\r
+ return ReturnBuffer;\r
+}\r
+\r
+/**\r
+ Copy data from system memory to MMIO region by using 64-bit access.\r
+\r
+ Copy data from system memory specified by Buffer to MMIO region specified \r
+ by starting address StartAddress by using 64-bit access. The total number \r
+ of byte to be copied is specified by Length. Length is returned.\r
+ \r
+ If StartAddress is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+ If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). \r
+ If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().\r
+\r
+ If Length is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+ If Buffer is not aligned on a 64-bit boundary, then ASSERT().\r
+\r
+ @param StartAddress Starting address for the MMIO region to be copied to.\r
+ @param Length Size in bytes of the copy.\r
+ @param Buffer Pointer to a system memory buffer containing the data to write.\r
+\r
+ @return Size in bytes of the copy.\r
+\r
+**/\r
+UINT64 *\r
+EFIAPI\r
+MmioWriteBuffer64 (\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT64 *Buffer\r
+ )\r
+{\r
+ UINT64 *ReturnBuffer;\r
+\r
+ ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
+ \r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+\r
+ ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+\r
+ ReturnBuffer = (UINT64 *) Buffer;\r
+ \r
+ while (Length) {\r
+ MmioWrite64 (StartAddress, *(Buffer++));\r
+ \r
+ StartAddress += sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
+ }\r
+\r
+ return ReturnBuffer;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ I/O Library. This file has compiler specifics for Microsft C as there is no\r
+ ANSI C standard for doing IO.\r
+\r
+ MSC - uses intrinsic functions and the optimize will remove the function call\r
+ overhead.\r
+\r
+ We don't advocate putting compiler specifics in libraries or drivers but there\r
+ is no other way to make this work.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: IoLibMsc.c\r
+\r
+**/\r
+\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+#include "CommonHeader.h"\r
+\r
+//\r
+// Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics\r
+//\r
+int _inp (unsigned short port);\r
+unsigned short _inpw (unsigned short port);\r
+unsigned long _inpd (unsigned short port);\r
+int _outp (unsigned short port, int databyte );\r
+unsigned short _outpw (unsigned short port, unsigned short dataword );\r
+unsigned long _outpd (unsigned short port, unsigned long dataword );\r
+void _ReadWriteBarrier (void);\r
+\r
+#pragma intrinsic(_inp)\r
+#pragma intrinsic(_inpw)\r
+#pragma intrinsic(_inpd)\r
+#pragma intrinsic(_outp)\r
+#pragma intrinsic(_outpw)\r
+#pragma intrinsic(_outpd)\r
+#pragma intrinsic(_ReadWriteBarrier)\r
+\r
+//\r
+// _ReadWriteBarrier() forces memory reads and writes to complete at the point\r
+// in the call. This is only a hint to the compiler and does emit code.\r
+// In past versions of the compiler, _ReadWriteBarrier was enforced only\r
+// locally and did not affect functions up the call tree. In Visual C++\r
+// 2005, _ReadWriteBarrier is enforced all the way up the call tree.\r
+//\r
+\r
+/**\r
+ Reads an 8-bit I/O port.\r
+\r
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoRead8 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT8 Value;\r
+\r
+ _ReadWriteBarrier ();\r
+ Value = (UINT8)_inp ((UINT16)Port);\r
+ _ReadWriteBarrier ();\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes an 8-bit I/O port.\r
+\r
+ Writes the 8-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+IoWrite8 (\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ _ReadWriteBarrier ();\r
+ (UINT8)_outp ((UINT16)Port, Value);\r
+ _ReadWriteBarrier ();\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 16-bit I/O port.\r
+\r
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoRead16 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT16 Value;\r
+\r
+ ASSERT ((Port & 1) == 0);\r
+ _ReadWriteBarrier ();\r
+ Value = _inpw ((UINT16)Port);\r
+ _ReadWriteBarrier ();\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit I/O port.\r
+\r
+ Writes the 16-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+IoWrite16 (\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT ((Port & 1) == 0);\r
+ _ReadWriteBarrier ();\r
+ _outpw ((UINT16)Port, Value);\r
+ _ReadWriteBarrier ();\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit I/O port.\r
+\r
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r
+ This function must guarantee that all I/O read and write operations are\r
+ serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoRead32 (\r
+ IN UINTN Port\r
+ )\r
+{\r
+ UINT32 Value;\r
+\r
+ ASSERT ((Port & 3) == 0);\r
+ _ReadWriteBarrier ();\r
+ Value = _inpd ((UINT16)Port);\r
+ _ReadWriteBarrier ();\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit I/O port.\r
+\r
+ Writes the 32-bit I/O port specified by Port with the value specified by Value\r
+ and returns Value. This function must guarantee that all I/O read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit I/O port operations are not supported, then ASSERT().\r
+\r
+ @param Port The I/O port to write.\r
+ @param Value The value to write to the I/O port.\r
+\r
+ @return The value written the I/O port.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+IoWrite32 (\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT ((Port & 3) == 0);\r
+ _ReadWriteBarrier ();\r
+ _outpd ((UINT16)Port, Value);\r
+ _ReadWriteBarrier ();\r
+ return Value;\r
+}\r
+\r
+\r
+/**\r
+ Reads an 8-bit MMIO register.\r
+\r
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioRead8 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT8 Value;\r
+\r
+ Value = *(volatile UINT8*)Address;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes an 8-bit MMIO register.\r
+\r
+ Writes the 8-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 8-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+MmioWrite8 (\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ return *(volatile UINT8*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 16-bit MMIO register.\r
+\r
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioRead16 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT16 Value;\r
+\r
+ ASSERT ((Address & 1) == 0);\r
+ Value = *(volatile UINT16*)Address;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes a 16-bit MMIO register.\r
+\r
+ Writes the 16-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 16-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+MmioWrite16 (\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 1) == 0);\r
+ return *(volatile UINT16*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 32-bit MMIO register.\r
+\r
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioRead32 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT32 Value;\r
+\r
+ ASSERT ((Address & 3) == 0);\r
+ Value = *(volatile UINT32*)Address;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes a 32-bit MMIO register.\r
+\r
+ Writes the 32-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 32-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+MmioWrite32 (\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 3) == 0);\r
+ return *(volatile UINT32*)Address = Value;\r
+}\r
+\r
+/**\r
+ Reads a 64-bit MMIO register.\r
+\r
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r
+ returned. This function must guarantee that all MMIO read and write\r
+ operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioRead64 (\r
+ IN UINTN Address\r
+ )\r
+{\r
+ UINT64 Value;\r
+\r
+ ASSERT ((Address & 7) == 0);\r
+ Value = *(volatile UINT64*)Address;\r
+ return Value;\r
+}\r
+\r
+/**\r
+ Writes a 64-bit MMIO register.\r
+\r
+ Writes the 64-bit MMIO register specified by Address with the value specified\r
+ by Value and returns Value. This function must guarantee that all MMIO read\r
+ and write operations are serialized.\r
+\r
+ If 64-bit MMIO register operations are not supported, then ASSERT().\r
+\r
+ @param Address The MMIO register to write.\r
+ @param Value The value to write to the MMIO register.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+MmioWrite64 (\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ ASSERT ((Address & 7) == 0);\r
+ return *(volatile UINT64*)Address = Value;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ Math worker functions.\r
+\r
+ Copyright (c) 2006, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//
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