SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt support
[mirror_edk2.git] / SecurityPkg / Tcg / Tcg2Smm / Tpm.asl
1 /** @file
2 The TPM2 definition block in ACPI table for TCG2 physical presence
3 and MemoryClear.
4
5 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
6 (c)Copyright 2016 HP Development Company, L.P.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 DefinitionBlock (
18 "Tpm.aml",
19 "SSDT",
20 2,
21 "INTEL ",
22 "Tpm2Tabl",
23 0x1000
24 )
25 {
26 Scope (\_SB)
27 {
28 Device (TPM)
29 {
30 //
31 // TCG2
32 //
33
34 //
35 // TAG for patching TPM2.0 _HID
36 //
37 Name (_HID, "NNNN0000")
38
39 Name (_CID, "MSFT0101")
40
41 //
42 // Readable name of this device, don't know if this way is correct yet
43 //
44 Name (_STR, Unicode ("TPM 2.0 Device"))
45
46 //
47 // Operational region for Smi port access
48 //
49 OperationRegion (SMIP, SystemIO, 0xB2, 1)
50 Field (SMIP, ByteAcc, NoLock, Preserve)
51 {
52 IOB2, 8
53 }
54
55 //
56 // Operational region for TPM access
57 //
58 OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)
59 Field (TPMR, AnyAcc, NoLock, Preserve)
60 {
61 ACC0, 8, // TPM_ACCESS_0
62 Offset(0x8),
63 INTE, 32, // TPM_INT_ENABLE_0
64 INTV, 8, // TPM_INT_VECTOR_0
65 Offset(0x10),
66 INTS, 32, // TPM_INT_STATUS_0
67 INTF, 32, // TPM_INTF_CAPABILITY_0
68 STS0, 32, // TPM_STS_0
69 Offset(0x24),
70 FIFO, 32, // TPM_DATA_FIFO_0
71 Offset(0x30),
72 TID0, 32, // TPM_INTERFACE_ID_0
73 // ignore the rest
74 }
75
76 //
77 // Operational region for TPM support, TPM Physical Presence and TPM Memory Clear
78 // Region Offset 0xFFFF0000 and Length 0xF0 will be fixed in C code.
79 //
80 OperationRegion (TNVS, SystemMemory, 0xFFFF0000, 0xF0)
81 Field (TNVS, AnyAcc, NoLock, Preserve)
82 {
83 PPIN, 8, // Software SMI for Physical Presence Interface
84 PPIP, 32, // Used for save physical presence paramter
85 PPRP, 32, // Physical Presence request operation response
86 PPRQ, 32, // Physical Presence request operation
87 PPRM, 32, // Physical Presence request operation parameter
88 LPPR, 32, // Last Physical Presence request operation
89 FRET, 32, // Physical Presence function return code
90 MCIN, 8, // Software SMI for Memory Clear Interface
91 MCIP, 32, // Used for save the Mor paramter
92 MORD, 32, // Memory Overwrite Request Data
93 MRET, 32, // Memory Overwrite function return code
94 UCRQ, 32 // Phyical Presence request operation to Get User Confirmation Status
95 }
96
97 Name(RESO, ResourceTemplate () {
98 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS)
99 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {12}
100 })
101
102 //
103 // Return the resource consumed by TPM device.
104 //
105 Method(_CRS,0,Serialized)
106 {
107 Return(RESO)
108 }
109
110 //
111 // Set resources consumed by the TPM device. This is used to
112 // assign an interrupt number to the device. The input byte stream
113 // has to be the same as returned by _CRS (according to ACPI spec).
114 //
115 Method(_SRS,1,Serialized)
116 {
117 //
118 // Update resource descriptor
119 // Use the field name to identify the offsets in the argument
120 // buffer and RESO buffer.
121 //
122 CreateDWordField(Arg0, ^IRQ._INT, IRQ0)
123 CreateDWordField(RESO, ^IRQ._INT, LIRQ)
124 Store(IRQ0, LIRQ)
125
126 CreateBitField(Arg0, ^IRQ._HE, ITRG)
127 CreateBitField(RESO, ^IRQ._HE, LTRG)
128 Store(ITRG, LTRG)
129
130 CreateBitField(Arg0, ^IRQ._LL, ILVL)
131 CreateBitField(RESO, ^IRQ._LL, LLVL)
132 Store(ILVL, LLVL)
133
134 //
135 // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest
136 // nibble.
137 // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active
138 // 1111 - FIFO interface as defined in TIS1.3 is active
139 //
140 If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {
141 //
142 // If FIFO interface, interrupt vector register is
143 // available. TCG PTP specification allows only
144 // values 1..15 in this field. For other interrupts
145 // the field should stay 0.
146 //
147 If (LLess (IRQ0, 16)) {
148 Store (And(IRQ0, 0xF), INTV)
149 }
150 //
151 // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4
152 // contains settings for interrupt polarity.
153 // The other bits of the byte enable individual interrupts.
154 // They should be all be zero, but to avoid changing the
155 // configuration, the other bits are be preserved.
156 // 00 - high level
157 // 01 - low level
158 // 10 - rising edge
159 // 11 - falling edge
160 //
161 // ACPI spec definitions:
162 // _HE: '1' is Edge, '0' is Level
163 // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)
164 //
165 If (LEqual (ITRG, 1)) {
166 Or(INTE, 0x00000010, INTE)
167 } Else {
168 And(INTE, 0xFFFFFFEF, INTE)
169 }
170 if (LEqual (ILVL, 0)) {
171 Or(INTE, 0x00000008, INTE)
172 } Else {
173 And(INTE, 0xFFFFFFF7, INTE)
174 }
175 }
176 }
177
178 //
179 // Possible resource settings.
180 // The format of the data has to follow the same format as
181 // _CRS (according to ACPI spec).
182 //
183 Name (_PRS, ResourceTemplate() {
184 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
185 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , SIRQ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
186 })
187
188 Method (PTS, 1, Serialized)
189 {
190 //
191 // Detect Sx state for MOR, only S4, S5 need to handle
192 //
193 If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))
194 {
195 //
196 // Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.
197 //
198 If (LNot (And (MORD, 0x10)))
199 {
200 //
201 // Triggle the SMI through ACPI _PTS method.
202 //
203 Store (0x02, MCIP)
204
205 //
206 // Triggle the SMI interrupt
207 //
208 Store (MCIN, IOB2)
209 }
210 }
211 Return (0)
212 }
213
214 Method (_STA, 0)
215 {
216 if (LEqual (ACC0, 0xff))
217 {
218 Return (0)
219 }
220 Return (0x0f)
221 }
222
223 //
224 // TCG Hardware Information
225 //
226 Method (HINF, 3, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj
227 {
228 //
229 // Switch by function index
230 //
231 Switch (ToInteger(Arg1))
232 {
233 Case (0)
234 {
235 //
236 // Standard query
237 //
238 Return (Buffer () {0x03})
239 }
240 Case (1)
241 {
242 //
243 // Return failure if no TPM present
244 //
245 Name(TPMV, Package () {0x01, Package () {0x2, 0x0}})
246 if (LEqual (_STA (), 0x00))
247 {
248 Return (Package () {0x00})
249 }
250
251 //
252 // Return TPM version
253 //
254 Return (TPMV)
255 }
256 Default {BreakPoint}
257 }
258 Return (Buffer () {0})
259 }
260
261 Name(TPM2, Package (0x02){
262 Zero,
263 Zero
264 })
265
266 Name(TPM3, Package (0x03){
267 Zero,
268 Zero,
269 Zero
270 })
271
272 //
273 // TCG Physical Presence Interface
274 //
275 Method (TPPI, 3, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj
276 {
277 //
278 // Switch by function index
279 //
280 Switch (ToInteger(Arg1))
281 {
282 Case (0)
283 {
284 //
285 // Standard query, supports function 1-8
286 //
287 Return (Buffer () {0xFF, 0x01})
288 }
289 Case (1)
290 {
291 //
292 // a) Get Physical Presence Interface Version
293 //
294 Return ("$PV")
295 }
296 Case (2)
297 {
298 //
299 // b) Submit TPM Operation Request to Pre-OS Environment
300 //
301
302 Store (DerefOf (Index (Arg2, 0x00)), PPRQ)
303 Store (0, PPRM)
304 Store (0x02, PPIP)
305
306 //
307 // Triggle the SMI interrupt
308 //
309 Store (PPIN, IOB2)
310 Return (FRET)
311
312
313 }
314 Case (3)
315 {
316 //
317 // c) Get Pending TPM Operation Requested By the OS
318 //
319
320 Store (PPRQ, Index (TPM2, 0x01))
321 Return (TPM2)
322 }
323 Case (4)
324 {
325 //
326 // d) Get Platform-Specific Action to Transition to Pre-OS Environment
327 //
328 Return (2)
329 }
330 Case (5)
331 {
332 //
333 // e) Return TPM Operation Response to OS Environment
334 //
335 Store (0x05, PPIP)
336
337 //
338 // Triggle the SMI interrupt
339 //
340 Store (PPIN, IOB2)
341
342 Store (LPPR, Index (TPM3, 0x01))
343 Store (PPRP, Index (TPM3, 0x02))
344
345 Return (TPM3)
346 }
347 Case (6)
348 {
349
350 //
351 // f) Submit preferred user language (Not implemented)
352 //
353
354 Return (3)
355
356 }
357 Case (7)
358 {
359 //
360 // g) Submit TPM Operation Request to Pre-OS Environment 2
361 //
362 Store (7, PPIP)
363 Store (DerefOf (Index (Arg2, 0x00)), PPRQ)
364 Store (0, PPRM)
365 If (LEqual (PPRQ, 23)) {
366 Store (DerefOf (Index (Arg2, 0x01)), PPRM)
367 }
368
369 //
370 // Triggle the SMI interrupt
371 //
372 Store (PPIN, IOB2)
373 Return (FRET)
374 }
375 Case (8)
376 {
377 //
378 // e) Get User Confirmation Status for Operation
379 //
380 Store (8, PPIP)
381 Store (DerefOf (Index (Arg2, 0x00)), UCRQ)
382
383 //
384 // Triggle the SMI interrupt
385 //
386 Store (PPIN, IOB2)
387
388 Return (FRET)
389 }
390
391 Default {BreakPoint}
392 }
393 Return (1)
394 }
395
396 Method (TMCI, 3, Serialized, 0, IntObj, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj
397 {
398 //
399 // Switch by function index
400 //
401 Switch (ToInteger (Arg1))
402 {
403 Case (0)
404 {
405 //
406 // Standard query, supports function 1-1
407 //
408 Return (Buffer () {0x03})
409 }
410 Case (1)
411 {
412 //
413 // Save the Operation Value of the Request to MORD (reserved memory)
414 //
415 Store (DerefOf (Index (Arg2, 0x00)), MORD)
416
417 //
418 // Triggle the SMI through ACPI _DSM method.
419 //
420 Store (0x01, MCIP)
421
422 //
423 // Triggle the SMI interrupt
424 //
425 Store (MCIN, IOB2)
426 Return (MRET)
427 }
428 Default {BreakPoint}
429 }
430 Return (1)
431 }
432
433 Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})
434 {
435
436 //
437 // TCG Hardware Information
438 //
439 If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))
440 {
441 Return (HINF (Arg1, Arg2, Arg3))
442 }
443
444 //
445 // TCG Physical Presence Interface
446 //
447 If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))
448 {
449 Return (TPPI (Arg1, Arg2, Arg3))
450 }
451
452 //
453 // TCG Memory Clear Interface
454 //
455 If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
456 {
457 Return (TMCI (Arg1, Arg2, Arg3))
458 }
459
460 Return (Buffer () {0})
461 }
462 }
463 }
464 }