2 MSR Definitions for Intel processors based on the Skylake microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.
24 #ifndef __SKYLAKE_MSR_H__
25 #define __SKYLAKE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Skylake microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x4E || \
42 DisplayModel == 0x5E \
47 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
48 RW if MSR_PLATFORM_INFO.[28] = 1.
50 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)
51 @param EAX Lower 32-bits of MSR value.
52 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
53 @param EDX Upper 32-bits of MSR value.
54 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
58 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;
60 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
62 @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
64 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD
67 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
71 /// Individual bit fields
75 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
76 /// limit of 1 core active.
80 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
81 /// limit of 2 core active.
85 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
86 /// limit of 3 core active.
90 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
91 /// limit of 4 core active.
97 /// All bit fields as a 32-bit value
101 /// All bit fields as a 64-bit value
104 } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER
;
108 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)
109 that points to the MSR containing the most recent branch record.
111 @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)
112 @param EAX Lower 32-bits of MSR value.
113 @param EDX Upper 32-bits of MSR value.
119 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
120 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
122 @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
124 #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
128 Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
129 an 128-bit external entropy value for key derivation of an enclave.
131 @param ECX MSR_SKYLAKE_SGXOWNER0 (0x00000300)
132 @param EAX Lower 32-bits of MSR value.
133 @param EDX Upper 32-bits of MSR value.
139 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
141 @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
143 #define MSR_SKYLAKE_SGXOWNER0 0x00000300
147 Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
148 an 128-bit external entropy value for key derivation of an enclave.
150 @param ECX MSR_SKYLAKE_SGXOWNER1 (0x00000301)
151 @param EAX Lower 32-bits of MSR value.
152 @param EDX Upper 32-bits of MSR value.
158 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
160 @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
162 #define MSR_SKYLAKE_SGXOWNER1 0x00000301
166 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
169 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
170 @param EAX Lower 32-bits of MSR value.
171 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
172 @param EDX Upper 32-bits of MSR value.
173 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
177 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
179 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);
180 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
182 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
184 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E
187 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS
191 /// Individual bit fields
195 /// [Bit 0] Thread. Ovf_PMC0.
199 /// [Bit 1] Thread. Ovf_PMC1.
203 /// [Bit 2] Thread. Ovf_PMC2.
207 /// [Bit 3] Thread. Ovf_PMC3.
211 /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
215 /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
219 /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
223 /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
228 /// [Bit 32] Thread. Ovf_FixedCtr0.
230 UINT32 Ovf_FixedCtr0
:1;
232 /// [Bit 33] Thread. Ovf_FixedCtr1.
234 UINT32 Ovf_FixedCtr1
:1;
236 /// [Bit 34] Thread. Ovf_FixedCtr2.
238 UINT32 Ovf_FixedCtr2
:1;
241 /// [Bit 55] Thread. Trace_ToPA_PMI.
243 UINT32 Trace_ToPA_PMI
:1;
246 /// [Bit 58] Thread. LBR_Frz.
250 /// [Bit 59] Thread. CTR_Frz.
254 /// [Bit 60] Thread. ASCI.
258 /// [Bit 61] Thread. Ovf_Uncore.
262 /// [Bit 62] Thread. Ovf_BufDSSAVE.
264 UINT32 Ovf_BufDSSAVE
:1;
266 /// [Bit 63] Thread. CondChgd.
271 /// All bit fields as a 64-bit value
274 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER
;
278 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
281 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
282 @param EAX Lower 32-bits of MSR value.
283 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
284 @param EDX Upper 32-bits of MSR value.
285 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
289 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
291 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
292 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
294 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
296 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
299 MSR information returned for MSR index
300 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET
304 /// Individual bit fields
308 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
312 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
316 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
320 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
324 /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
328 /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
332 /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
336 /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
341 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
343 UINT32 Ovf_FixedCtr0
:1;
345 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
347 UINT32 Ovf_FixedCtr1
:1;
349 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
351 UINT32 Ovf_FixedCtr2
:1;
354 /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.
356 UINT32 Trace_ToPA_PMI
:1;
359 /// [Bit 58] Thread. Set 1 to clear LBR_Frz.
363 /// [Bit 59] Thread. Set 1 to clear CTR_Frz.
367 /// [Bit 60] Thread. Set 1 to clear ASCI.
371 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
375 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
377 UINT32 Ovf_BufDSSAVE
:1;
379 /// [Bit 63] Thread. Set 1 to clear CondChgd.
384 /// All bit fields as a 64-bit value
387 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
391 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
394 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
395 @param EAX Lower 32-bits of MSR value.
396 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
397 @param EDX Upper 32-bits of MSR value.
398 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
402 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
404 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
405 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
407 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
409 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
412 MSR information returned for MSR index
413 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET
417 /// Individual bit fields
421 /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.
425 /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.
429 /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.
433 /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.
437 /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).
441 /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).
445 /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).
449 /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).
454 /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.
456 UINT32 Ovf_FixedCtr0
:1;
458 /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.
460 UINT32 Ovf_FixedCtr1
:1;
462 /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.
464 UINT32 Ovf_FixedCtr2
:1;
467 /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.
469 UINT32 Trace_ToPA_PMI
:1;
472 /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.
476 /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.
480 /// [Bit 60] Thread. Set 1 to cause ASCI = 1.
484 /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.
488 /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.
490 UINT32 Ovf_BufDSSAVE
:1;
494 /// All bit fields as a 64-bit value
497 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
501 Thread. FrontEnd Precise Event Condition Select (R/W).
503 @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)
504 @param EAX Lower 32-bits of MSR value.
505 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
506 @param EDX Upper 32-bits of MSR value.
507 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
511 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;
513 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
514 AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
516 @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.
518 #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7
521 MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND
525 /// Individual bit fields
529 /// [Bits 2:0] Event Code Select.
531 UINT32 EventCodeSelect
:3;
534 /// [Bit 4] Event Code Select High.
536 UINT32 EventCodeSelectHigh
:1;
539 /// [Bits 19:8] IDQ_Bubble_Length Specifier.
541 UINT32 IDQ_Bubble_Length
:12;
543 /// [Bits 22:20] IDQ_Bubble_Width Specifier.
545 UINT32 IDQ_Bubble_Width
:3;
550 /// All bit fields as a 32-bit value
554 /// All bit fields as a 64-bit value
557 } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
;
561 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
564 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
565 @param EAX Lower 32-bits of MSR value.
566 @param EDX Upper 32-bits of MSR value.
572 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
574 @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
576 #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
580 Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both
581 platform vendor hardware implementation and BIOS enablement support it. This
582 MSR will read 0 if not valid.
584 @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)
585 @param EAX Lower 32-bits of MSR value.
586 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
587 @param EDX Upper 32-bits of MSR value.
588 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
592 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;
594 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
596 @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.
598 #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D
601 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER
605 /// Individual bit fields
609 /// [Bits 31:0] Total energy consumed by all devices in the platform that
610 /// receive power from integrated power delivery mechanism, Included
611 /// platform devices are processor cores, SOC, memory, add-on or
612 /// peripheral devices that get powered directly from the platform power
613 /// delivery means. The energy units are specified in the
614 /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
616 UINT32 TotalEnergy
:32;
620 /// All bit fields as a 32-bit value
624 /// All bit fields as a 64-bit value
627 } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
;
631 Thread. Productive Performance Count. (R/O). Hardware's view of workload
632 scalability. See Section 14.4.5.1.
634 @param ECX MSR_SKYLAKE_PPERF (0x0000064E)
635 @param EAX Lower 32-bits of MSR value.
636 @param EDX Upper 32-bits of MSR value.
642 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
644 @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.
646 #define MSR_SKYLAKE_PPERF 0x0000064E
650 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
651 refers to processor core frequency).
653 @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)
654 @param EAX Lower 32-bits of MSR value.
655 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
656 @param EDX Upper 32-bits of MSR value.
657 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
661 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
663 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);
664 AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
666 @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
668 #define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F
671 MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS
675 /// Individual bit fields
679 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
680 /// operating system request due to assertion of external PROCHOT.
682 UINT32 PROCHOT_Status
:1;
684 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
685 /// operating system request due to a thermal event.
687 UINT32 ThermalStatus
:1;
690 /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is
691 /// reduced below the operating system request due to residency state
692 /// regulation limit.
694 UINT32 ResidencyStateRegulationStatus
:1;
696 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
697 /// is reduced below the operating system request due to Running Average
698 /// Thermal Limit (RATL).
700 UINT32 RunningAverageThermalLimitStatus
:1;
702 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
703 /// below the operating system request due to a thermal alert from a
704 /// processor Voltage Regulator (VR).
706 UINT32 VRThermAlertStatus
:1;
708 /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is
709 /// reduced below the operating system request due to VR thermal design
712 UINT32 VRThermDesignCurrentStatus
:1;
714 /// [Bit 8] Other Status (R0) When set, frequency is reduced below the
715 /// operating system request due to electrical or other constraints.
717 UINT32 OtherStatus
:1;
720 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
721 /// set, frequency is reduced below the operating system request due to
722 /// package/platform-level power limiting PL1.
726 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
727 /// set, frequency is reduced below the operating system request due to
728 /// package/platform-level power limiting PL2/PL3.
732 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
733 /// below the operating system request due to multi-core turbo limits.
735 UINT32 MaxTurboLimitStatus
:1;
737 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
738 /// is reduced below the operating system request due to Turbo transition
739 /// attenuation. This prevents performance degradation due to frequent
740 /// operating ratio changes.
742 UINT32 TurboTransitionAttenuationStatus
:1;
745 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
746 /// has asserted since the log bit was last cleared. This log bit will
747 /// remain set until cleared by software writing 0.
749 UINT32 PROCHOT_Log
:1;
751 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
752 /// has asserted since the log bit was last cleared. This log bit will
753 /// remain set until cleared by software writing 0.
758 /// [Bit 20] Residency State Regulation Log When set, indicates that the
759 /// Residency State Regulation Status bit has asserted since the log bit
760 /// was last cleared. This log bit will remain set until cleared by
761 /// software writing 0.
763 UINT32 ResidencyStateRegulationLog
:1;
765 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
766 /// the RATL Status bit has asserted since the log bit was last cleared.
767 /// This log bit will remain set until cleared by software writing 0.
769 UINT32 RunningAverageThermalLimitLog
:1;
771 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
772 /// Alert Status bit has asserted since the log bit was last cleared. This
773 /// log bit will remain set until cleared by software writing 0.
775 UINT32 VRThermAlertLog
:1;
777 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
778 /// VR TDC Status bit has asserted since the log bit was last cleared.
779 /// This log bit will remain set until cleared by software writing 0.
781 UINT32 VRThermalDesignCurrentLog
:1;
783 /// [Bit 24] Other Log When set, indicates that the Other Status bit has
784 /// asserted since the log bit was last cleared. This log bit will remain
785 /// set until cleared by software writing 0.
790 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
791 /// indicates that the Package or Platform Level PL1 Power Limiting Status
792 /// bit has asserted since the log bit was last cleared. This log bit will
793 /// remain set until cleared by software writing 0.
797 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
798 /// indicates that the Package or Platform Level PL2/PL3 Power Limiting
799 /// Status bit has asserted since the log bit was last cleared. This log
800 /// bit will remain set until cleared by software writing 0.
804 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
805 /// Limit Status bit has asserted since the log bit was last cleared. This
806 /// log bit will remain set until cleared by software writing 0.
808 UINT32 MaxTurboLimitLog
:1;
810 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
811 /// Turbo Transition Attenuation Status bit has asserted since the log bit
812 /// was last cleared. This log bit will remain set until cleared by
813 /// software writing 0.
815 UINT32 TurboTransitionAttenuationLog
:1;
820 /// All bit fields as a 32-bit value
824 /// All bit fields as a 64-bit value
827 } MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
;
831 Package. HDC Configuration (R/W)..
833 @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
834 @param EAX Lower 32-bits of MSR value.
835 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
836 @param EDX Upper 32-bits of MSR value.
837 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
841 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;
843 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
844 AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
846 @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.
848 #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652
851 MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG
855 /// Individual bit fields
859 /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for
860 /// MSR_PKG_HDC_DEEP_RESIDENCY.
862 UINT32 PKG_Cx_Monitor
:3;
867 /// All bit fields as a 32-bit value
871 /// All bit fields as a 64-bit value
874 } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
;
878 Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.
880 @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)
881 @param EAX Lower 32-bits of MSR value.
882 @param EDX Upper 32-bits of MSR value.
888 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
890 @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.
892 #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653
896 Package. Accumulate the cycles the package was in C2 state and at least one
897 logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.
899 @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)
900 @param EAX Lower 32-bits of MSR value.
901 @param EDX Upper 32-bits of MSR value.
907 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
909 @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.
911 #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655
915 Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.
917 @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)
918 @param EAX Lower 32-bits of MSR value.
919 @param EDX Upper 32-bits of MSR value.
925 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
927 @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.
929 #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656
933 Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate
934 as the TSC. The increment each cycle is weighted by the number of processor
935 cores in the package that reside in C0. If N cores are simultaneously in C0,
936 then each cycle the counter increments by N.
938 @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)
939 @param EAX Lower 32-bits of MSR value.
940 @param EDX Upper 32-bits of MSR value.
946 Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
948 @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.
950 #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658
954 Package. Any Core C0 Residency. (R/O). Increment at the same rate as the
955 TSC. The increment each cycle is one if any processor core in the package is
958 @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)
959 @param EAX Lower 32-bits of MSR value.
960 @param EDX Upper 32-bits of MSR value.
966 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
968 @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.
970 #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659
974 Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate
975 as the TSC. The increment each cycle is one if any processor graphic
976 device's compute engines are in C0.
978 @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)
979 @param EAX Lower 32-bits of MSR value.
980 @param EDX Upper 32-bits of MSR value.
986 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
988 @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.
990 #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A
994 Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment
995 at the same rate as the TSC. The increment each cycle is one if at least one
996 compute engine of the processor graphics is in C0 and at least one processor
997 core in the package is also in C0.
999 @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)
1000 @param EAX Lower 32-bits of MSR value.
1001 @param EDX Upper 32-bits of MSR value.
1003 <b>Example usage</b>
1007 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
1009 @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.
1011 #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B
1015 Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to
1016 limit power consumption of the platform devices to the specified values. The
1017 Long Duration power consumption is specified via Platform_Power_Limit_1 and
1018 Platform_Power_Limit_1_Time. The Short Duration power consumption limit is
1019 specified via the Platform_Power_Limit_2 with duration chosen by the
1020 processor. The processor implements an exponential-weighted algorithm in the
1021 placement of the time windows.
1023 @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)
1024 @param EAX Lower 32-bits of MSR value.
1025 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
1026 @param EDX Upper 32-bits of MSR value.
1027 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
1029 <b>Example usage</b>
1031 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;
1033 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
1034 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
1036 @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.
1038 #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C
1041 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT
1045 /// Individual bit fields
1049 /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which
1050 /// the platform must not exceed over a time window as specified by
1051 /// Power_Limit_1_TIME field. The default value is the Thermal Design
1052 /// Power (TDP) and varies with product skus. The unit is specified in
1053 /// MSR_RAPLPOWER_UNIT.
1055 UINT32 PlatformPowerLimit1
:15;
1057 /// [Bit 15] Enable Platform Power Limit #1. When set, enables the
1058 /// processor to apply control policy such that the platform power does
1059 /// not exceed Platform Power limit #1 over the time window specified by
1060 /// Power Limit #1 Time Window.
1062 UINT32 EnablePlatformPowerLimit1
:1;
1064 /// [Bit 16] Platform Clamping Limitation #1. When set, allows the
1065 /// processor to go below the OS requested P states in order to maintain
1066 /// the power below specified Platform Power Limit #1 value. This bit is
1067 /// writeable only when CPUID (EAX=6):EAX[4] is set.
1069 UINT32 PlatformClampingLimitation1
:1;
1071 /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the
1072 /// duration of the time window over which Platform Power Limit 1 value
1073 /// should be maintained for sustained long duration. This field is made
1074 /// up of two numbers from the following equation: Time Window = (float)
1075 /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =
1076 /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is
1077 /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,
1078 /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].
1083 /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which
1084 /// the platform must not exceed over the Short Duration time window
1085 /// chosen by the processor. The recommended default value is 1.25 times
1086 /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).
1088 UINT32 PlatformPowerLimit2
:15;
1090 /// [Bit 47] Enable Platform Power Limit #2. When set, enables the
1091 /// processor to apply control policy such that the platform power does
1092 /// not exceed Platform Power limit #2 over the Short Duration time window.
1094 UINT32 EnablePlatformPowerLimit2
:1;
1096 /// [Bit 48] Platform Clamping Limitation #2. When set, allows the
1097 /// processor to go below the OS requested P states in order to maintain
1098 /// the power below specified Platform Power Limit #2 value.
1100 UINT32 PlatformClampingLimitation2
:1;
1101 UINT32 Reserved2
:14;
1103 /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR
1104 /// until system RESET.
1109 /// All bit fields as a 64-bit value
1112 } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
;
1116 Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last
1117 branch record registers on the last branch record stack. This part of the
1118 stack contains pointers to the source instruction. See also: - Last Branch
1119 Record Stack TOS at 1C9H - Section 17.10.
1121 @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
1122 @param EAX Lower 32-bits of MSR value.
1123 @param EDX Upper 32-bits of MSR value.
1125 <b>Example usage</b>
1129 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
1130 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
1132 @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
1133 MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
1134 MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
1135 MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
1136 MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
1137 MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
1138 MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
1139 MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
1140 MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
1141 MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
1142 MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
1143 MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
1144 MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
1145 MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
1146 MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
1147 MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
1150 #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690
1151 #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691
1152 #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692
1153 #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693
1154 #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694
1155 #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695
1156 #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696
1157 #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697
1158 #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698
1159 #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699
1160 #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A
1161 #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B
1162 #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C
1163 #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D
1164 #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E
1165 #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F
1170 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
1171 (frequency refers to processor graphics frequency).
1173 @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
1174 @param EAX Lower 32-bits of MSR value.
1175 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1176 @param EDX Upper 32-bits of MSR value.
1177 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1179 <b>Example usage</b>
1181 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
1183 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);
1184 AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
1186 @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
1188 #define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1191 MSR information returned for MSR index
1192 #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS
1196 /// Individual bit fields
1200 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
1201 /// assertion of external PROCHOT.
1203 UINT32 PROCHOT_Status
:1;
1205 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
1208 UINT32 ThermalStatus
:1;
1211 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
1212 /// is reduced due to running average thermal limit.
1214 UINT32 RunningAverageThermalLimitStatus
:1;
1216 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
1217 /// to a thermal alert from a processor Voltage Regulator.
1219 UINT32 VRThermAlertStatus
:1;
1221 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
1222 /// reduced due to VR TDC limit.
1224 UINT32 VRThermalDesignCurrentStatus
:1;
1226 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
1227 /// electrical or other constraints.
1229 UINT32 OtherStatus
:1;
1232 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
1233 /// set, frequency is reduced due to package/platform-level power limiting
1238 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
1239 /// set, frequency is reduced due to package/platform-level power limiting
1244 /// [Bit 12] Inefficient Operation Status (R0) When set, processor
1245 /// graphics frequency is operating below target frequency.
1247 UINT32 InefficientOperationStatus
:1;
1250 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1251 /// has asserted since the log bit was last cleared. This log bit will
1252 /// remain set until cleared by software writing 0.
1254 UINT32 PROCHOT_Log
:1;
1256 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1257 /// has asserted since the log bit was last cleared. This log bit will
1258 /// remain set until cleared by software writing 0.
1260 UINT32 ThermalLog
:1;
1263 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
1264 /// the RATL Status bit has asserted since the log bit was last cleared.
1265 /// This log bit will remain set until cleared by software writing 0.
1267 UINT32 RunningAverageThermalLimitLog
:1;
1269 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1270 /// Alert Status bit has asserted since the log bit was last cleared. This
1271 /// log bit will remain set until cleared by software writing 0.
1273 UINT32 VRThermAlertLog
:1;
1275 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
1276 /// VR Therm Alert Status bit has asserted since the log bit was last
1277 /// cleared. This log bit will remain set until cleared by software
1280 UINT32 VRThermalDesignCurrentLog
:1;
1282 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has
1283 /// asserted since the log bit was last cleared. This log bit will remain
1284 /// set until cleared by software writing 0.
1289 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
1290 /// indicates that the Package/Platform Level PL1 Power Limiting Status
1291 /// bit has asserted since the log bit was last cleared. This log bit will
1292 /// remain set until cleared by software writing 0.
1296 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
1297 /// indicates that the Package/Platform Level PL2 Power Limiting Status
1298 /// bit has asserted since the log bit was last cleared. This log bit will
1299 /// remain set until cleared by software writing 0.
1303 /// [Bit 28] Inefficient Operation Log When set, indicates that the
1304 /// Inefficient Operation Status bit has asserted since the log bit was
1305 /// last cleared. This log bit will remain set until cleared by software
1308 UINT32 InefficientOperationLog
:1;
1310 UINT32 Reserved7
:32;
1313 /// All bit fields as a 32-bit value
1317 /// All bit fields as a 64-bit value
1320 } MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
;
1324 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
1325 (frequency refers to ring interconnect in the uncore).
1327 @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)
1328 @param EAX Lower 32-bits of MSR value.
1329 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
1330 @param EDX Upper 32-bits of MSR value.
1331 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
1333 <b>Example usage</b>
1335 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;
1337 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);
1338 AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);
1340 @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
1342 #define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1
1345 MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS
1349 /// Individual bit fields
1353 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
1354 /// assertion of external PROCHOT.
1356 UINT32 PROCHOT_Status
:1;
1358 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
1361 UINT32 ThermalStatus
:1;
1364 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
1365 /// is reduced due to running average thermal limit.
1367 UINT32 RunningAverageThermalLimitStatus
:1;
1369 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
1370 /// to a thermal alert from a processor Voltage Regulator.
1372 UINT32 VRThermAlertStatus
:1;
1374 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
1375 /// reduced due to VR TDC limit.
1377 UINT32 VRThermalDesignCurrentStatus
:1;
1379 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
1380 /// electrical or other constraints.
1382 UINT32 OtherStatus
:1;
1385 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
1386 /// set, frequency is reduced due to package/Platform-level power limiting
1391 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
1392 /// set, frequency is reduced due to package/Platform-level power limiting
1398 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1399 /// has asserted since the log bit was last cleared. This log bit will
1400 /// remain set until cleared by software writing 0.
1402 UINT32 PROCHOT_Log
:1;
1404 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1405 /// has asserted since the log bit was last cleared. This log bit will
1406 /// remain set until cleared by software writing 0.
1408 UINT32 ThermalLog
:1;
1411 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
1412 /// the RATL Status bit has asserted since the log bit was last cleared.
1413 /// This log bit will remain set until cleared by software writing 0.
1415 UINT32 RunningAverageThermalLimitLog
:1;
1417 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1418 /// Alert Status bit has asserted since the log bit was last cleared. This
1419 /// log bit will remain set until cleared by software writing 0.
1421 UINT32 VRThermAlertLog
:1;
1423 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
1424 /// VR Therm Alert Status bit has asserted since the log bit was last
1425 /// cleared. This log bit will remain set until cleared by software
1428 UINT32 VRThermalDesignCurrentLog
:1;
1430 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has
1431 /// asserted since the log bit was last cleared. This log bit will remain
1432 /// set until cleared by software writing 0.
1437 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
1438 /// indicates that the Package/Platform Level PL1 Power Limiting Status
1439 /// bit has asserted since the log bit was last cleared. This log bit will
1440 /// remain set until cleared by software writing 0.
1444 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
1445 /// indicates that the Package/Platform Level PL2 Power Limiting Status
1446 /// bit has asserted since the log bit was last cleared. This log bit will
1447 /// remain set until cleared by software writing 0.
1451 UINT32 Reserved7
:32;
1454 /// All bit fields as a 32-bit value
1458 /// All bit fields as a 64-bit value
1461 } MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
;
1465 Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch
1466 record registers on the last branch record stack. This part of the stack
1467 contains pointers to the destination instruction. See also: - Last Branch
1468 Record Stack TOS at 1C9H - Section 17.10.
1470 @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP
1471 @param EAX Lower 32-bits of MSR value.
1472 @param EDX Upper 32-bits of MSR value.
1474 <b>Example usage</b>
1478 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
1479 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
1481 @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
1482 MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
1483 MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
1484 MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
1485 MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
1486 MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
1487 MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
1488 MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
1489 MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
1490 MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
1491 MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
1492 MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
1493 MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
1494 MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
1495 MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
1496 MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
1499 #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0
1500 #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1
1501 #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2
1502 #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3
1503 #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4
1504 #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5
1505 #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6
1506 #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7
1507 #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8
1508 #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9
1509 #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA
1510 #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB
1511 #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC
1512 #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD
1513 #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE
1514 #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF
1519 Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet
1520 of last branch record registers on the last branch record stack. This part
1521 of the stack contains flag, TSX-related and elapsed cycle information. See
1522 also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR
1525 @param ECX MSR_SKYLAKE_LBR_INFO_n
1526 @param EAX Lower 32-bits of MSR value.
1527 @param EDX Upper 32-bits of MSR value.
1529 <b>Example usage</b>
1533 Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
1534 AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
1536 @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.
1537 MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.
1538 MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.
1539 MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.
1540 MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.
1541 MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.
1542 MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.
1543 MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.
1544 MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.
1545 MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.
1546 MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.
1547 MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.
1548 MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.
1549 MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.
1550 MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.
1551 MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.
1552 MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.
1553 MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.
1554 MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.
1555 MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.
1556 MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.
1557 MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.
1558 MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.
1559 MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.
1560 MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.
1561 MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.
1562 MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.
1563 MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.
1564 MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.
1565 MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.
1566 MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.
1567 MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.
1570 #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0
1571 #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1
1572 #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2
1573 #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3
1574 #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4
1575 #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5
1576 #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6
1577 #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7
1578 #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8
1579 #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9
1580 #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA
1581 #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB
1582 #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC
1583 #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD
1584 #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE
1585 #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF
1586 #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0
1587 #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1
1588 #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2
1589 #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3
1590 #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4
1591 #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5
1592 #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6
1593 #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7
1594 #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8
1595 #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9
1596 #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA
1597 #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB
1598 #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC
1599 #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD
1600 #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE
1601 #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF
1606 Package. Uncore fixed counter control (R/W).
1608 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)
1609 @param EAX Lower 32-bits of MSR value.
1610 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
1611 @param EDX Upper 32-bits of MSR value.
1612 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
1614 <b>Example usage</b>
1616 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
1618 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);
1619 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
1621 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
1623 #define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394
1626 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL
1630 /// Individual bit fields
1633 UINT32 Reserved1
:20;
1635 /// [Bit 20] Enable overflow propagation.
1637 UINT32 EnableOverflow
:1;
1640 /// [Bit 22] Enable counting.
1642 UINT32 EnableCounting
:1;
1644 UINT32 Reserved4
:32;
1647 /// All bit fields as a 32-bit value
1651 /// All bit fields as a 64-bit value
1654 } MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
;
1658 Package. Uncore fixed counter.
1660 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)
1661 @param EAX Lower 32-bits of MSR value.
1662 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
1663 @param EDX Upper 32-bits of MSR value.
1664 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
1666 <b>Example usage</b>
1668 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;
1670 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);
1671 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);
1673 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
1675 #define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395
1678 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR
1682 /// Individual bit fields
1686 /// [Bits 31:0] Current count.
1688 UINT32 CurrentCount
:32;
1690 /// [Bits 43:32] Current count.
1692 UINT32 CurrentCountHi
:12;
1696 /// All bit fields as a 64-bit value
1699 } MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
;
1703 Package. Uncore C-Box configuration information (R/O).
1705 @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)
1706 @param EAX Lower 32-bits of MSR value.
1707 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
1708 @param EDX Upper 32-bits of MSR value.
1709 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
1711 <b>Example usage</b>
1713 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;
1715 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);
1717 @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
1719 #define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396
1722 MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG
1726 /// Individual bit fields
1730 /// [Bits 3:0] Specifies the number of C-Box units with programmable
1731 /// counters (including processor cores and processor graphics),.
1734 UINT32 Reserved1
:28;
1735 UINT32 Reserved2
:32;
1738 /// All bit fields as a 32-bit value
1742 /// All bit fields as a 64-bit value
1745 } MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER
;
1749 Package. Uncore Arb unit, performance counter 0.
1751 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)
1752 @param EAX Lower 32-bits of MSR value.
1753 @param EDX Upper 32-bits of MSR value.
1755 <b>Example usage</b>
1759 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);
1760 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);
1762 @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
1764 #define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0
1768 Package. Uncore Arb unit, performance counter 1.
1770 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)
1771 @param EAX Lower 32-bits of MSR value.
1772 @param EDX Upper 32-bits of MSR value.
1774 <b>Example usage</b>
1778 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);
1779 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);
1781 @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
1783 #define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1
1787 Package. Uncore Arb unit, counter 0 event select MSR.
1789 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
1790 @param EAX Lower 32-bits of MSR value.
1791 @param EDX Upper 32-bits of MSR value.
1793 <b>Example usage</b>
1797 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);
1798 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);
1800 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
1802 #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2
1806 Package. Uncore Arb unit, counter 1 event select MSR.
1808 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
1809 @param EAX Lower 32-bits of MSR value.
1810 @param EDX Upper 32-bits of MSR value.
1812 <b>Example usage</b>
1816 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);
1817 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);
1819 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.
1821 #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3
1825 Package. Uncore C-Box 0, counter 0 event select MSR.
1827 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
1828 @param EAX Lower 32-bits of MSR value.
1829 @param EDX Upper 32-bits of MSR value.
1831 <b>Example usage</b>
1835 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);
1836 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);
1838 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
1840 #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700
1844 Package. Uncore C-Box 0, counter 1 event select MSR.
1846 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
1847 @param EAX Lower 32-bits of MSR value.
1848 @param EDX Upper 32-bits of MSR value.
1850 <b>Example usage</b>
1854 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);
1855 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);
1857 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
1859 #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701
1863 Package. Uncore C-Box 0, performance counter 0.
1865 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)
1866 @param EAX Lower 32-bits of MSR value.
1867 @param EDX Upper 32-bits of MSR value.
1869 <b>Example usage</b>
1873 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);
1874 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);
1876 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
1878 #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706
1882 Package. Uncore C-Box 0, performance counter 1.
1884 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)
1885 @param EAX Lower 32-bits of MSR value.
1886 @param EDX Upper 32-bits of MSR value.
1888 <b>Example usage</b>
1892 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);
1893 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);
1895 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
1897 #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707
1901 Package. Uncore C-Box 1, counter 0 event select MSR.
1903 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
1904 @param EAX Lower 32-bits of MSR value.
1905 @param EDX Upper 32-bits of MSR value.
1907 <b>Example usage</b>
1911 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);
1912 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);
1914 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
1916 #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710
1920 Package. Uncore C-Box 1, counter 1 event select MSR.
1922 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
1923 @param EAX Lower 32-bits of MSR value.
1924 @param EDX Upper 32-bits of MSR value.
1926 <b>Example usage</b>
1930 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);
1931 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);
1933 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
1935 #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711
1939 Package. Uncore C-Box 1, performance counter 0.
1941 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)
1942 @param EAX Lower 32-bits of MSR value.
1943 @param EDX Upper 32-bits of MSR value.
1945 <b>Example usage</b>
1949 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);
1950 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);
1952 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
1954 #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716
1958 Package. Uncore C-Box 1, performance counter 1.
1960 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)
1961 @param EAX Lower 32-bits of MSR value.
1962 @param EDX Upper 32-bits of MSR value.
1964 <b>Example usage</b>
1968 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);
1969 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);
1971 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
1973 #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717
1977 Package. Uncore C-Box 2, counter 0 event select MSR.
1979 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
1980 @param EAX Lower 32-bits of MSR value.
1981 @param EDX Upper 32-bits of MSR value.
1983 <b>Example usage</b>
1987 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);
1988 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);
1990 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
1992 #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720
1996 Package. Uncore C-Box 2, counter 1 event select MSR.
1998 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
1999 @param EAX Lower 32-bits of MSR value.
2000 @param EDX Upper 32-bits of MSR value.
2002 <b>Example usage</b>
2006 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);
2007 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);
2009 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2011 #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2015 Package. Uncore C-Box 2, performance counter 0.
2017 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)
2018 @param EAX Lower 32-bits of MSR value.
2019 @param EDX Upper 32-bits of MSR value.
2021 <b>Example usage</b>
2025 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);
2026 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);
2028 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2030 #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726
2034 Package. Uncore C-Box 2, performance counter 1.
2036 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)
2037 @param EAX Lower 32-bits of MSR value.
2038 @param EDX Upper 32-bits of MSR value.
2040 <b>Example usage</b>
2044 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);
2045 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);
2047 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2049 #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727
2053 Package. Uncore C-Box 3, counter 0 event select MSR.
2055 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2056 @param EAX Lower 32-bits of MSR value.
2057 @param EDX Upper 32-bits of MSR value.
2059 <b>Example usage</b>
2063 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);
2064 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);
2066 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2068 #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2072 Package. Uncore C-Box 3, counter 1 event select MSR.
2074 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2075 @param EAX Lower 32-bits of MSR value.
2076 @param EDX Upper 32-bits of MSR value.
2078 <b>Example usage</b>
2082 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);
2083 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);
2085 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2087 #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2091 Package. Uncore C-Box 3, performance counter 0.
2093 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)
2094 @param EAX Lower 32-bits of MSR value.
2095 @param EDX Upper 32-bits of MSR value.
2097 <b>Example usage</b>
2101 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);
2102 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);
2104 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2106 #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736
2110 Package. Uncore C-Box 3, performance counter 1.
2112 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)
2113 @param EAX Lower 32-bits of MSR value.
2114 @param EDX Upper 32-bits of MSR value.
2116 <b>Example usage</b>
2120 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);
2121 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);
2123 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2125 #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737
2129 Package. Uncore PMU global control.
2131 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)
2132 @param EAX Lower 32-bits of MSR value.
2133 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
2134 @param EDX Upper 32-bits of MSR value.
2135 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
2137 <b>Example usage</b>
2139 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
2141 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);
2142 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
2144 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
2146 #define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01
2149 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL
2153 /// Individual bit fields
2157 /// [Bit 0] Slice 0 select.
2159 UINT32 PMI_Sel_Slice0
:1;
2161 /// [Bit 1] Slice 1 select.
2163 UINT32 PMI_Sel_Slice1
:1;
2165 /// [Bit 2] Slice 2 select.
2167 UINT32 PMI_Sel_Slice2
:1;
2169 /// [Bit 3] Slice 3 select.
2171 UINT32 PMI_Sel_Slice3
:1;
2173 /// [Bit 4] Slice 4select.
2175 UINT32 PMI_Sel_Slice4
:1;
2176 UINT32 Reserved1
:14;
2177 UINT32 Reserved2
:10;
2179 /// [Bit 29] Enable all uncore counters.
2183 /// [Bit 30] Enable wake on PMI.
2187 /// [Bit 31] Enable Freezing counter when overflow.
2190 UINT32 Reserved3
:32;
2193 /// All bit fields as a 32-bit value
2197 /// All bit fields as a 64-bit value
2200 } MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
2204 Package. Uncore PMU main status.
2206 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)
2207 @param EAX Lower 32-bits of MSR value.
2208 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2209 @param EDX Upper 32-bits of MSR value.
2210 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2212 <b>Example usage</b>
2214 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
2216 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);
2217 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
2219 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
2221 #define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02
2224 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS
2228 /// Individual bit fields
2232 /// [Bit 0] Fixed counter overflowed.
2236 /// [Bit 1] An ARB counter overflowed.
2241 /// [Bit 3] A CBox counter overflowed (on any slice).
2244 UINT32 Reserved2
:28;
2245 UINT32 Reserved3
:32;
2248 /// All bit fields as a 32-bit value
2252 /// All bit fields as a 64-bit value
2255 } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
;