CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limit

The current PCI resource limit calculation in CorebootPayloadPkg
PciHostBridgeLib is wrong. Adjusted it to match the PciHostBridge
driver's expectation.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by : Prince Agyeman <prince.agyeman@intel.com>

diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 0f1c8cb1a2105835a3e4d6df2ec6d413406f7149..6d94ff72c95695cf9c0bee7b57738baec5b7b32e 100644 (file)
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -91,7 +91,7 @@ AdjustRootBridgeResource (
   // Align IO  resource at 4K  boundary\r
   //\r
   Mask        = 0xFFFULL;\r
   // Align IO  resource at 4K  boundary\r
   //\r
   Mask        = 0xFFFULL;\r

-  Io->Limit   = (Io->Limit + Mask) & ~Mask;\r
+  Io->Limit   = ((Io->Limit + Mask) & ~Mask) - 1;\r

   if (Io->Base != MAX_UINT64) {\r
     Io->Base &= ~Mask;\r
   }\r
   if (Io->Base != MAX_UINT64) {\r
     Io->Base &= ~Mask;\r
   }\r


@@ -100,7 +100,7 @@ AdjustRootBridgeResource (
   // Align MEM resource at 1MB boundary\r
   //\r
   Mask        = 0xFFFFFULL;\r
   // Align MEM resource at 1MB boundary\r
   //\r
   Mask        = 0xFFFFFULL;\r

-  Mem->Limit  = (Mem->Limit + Mask) & ~Mask;\r
+  Mem->Limit  = ((Mem->Limit + Mask) & ~Mask) - 1;\r

   if (Mem->Base != MAX_UINT64) {\r
     Mem->Base &= ~Mask;\r
   }\r
   if (Mem->Base != MAX_UINT64) {\r
     Mem->Base &= ~Mask;\r
   }\r