OvmfPkg/PlatformInitLib: Add hob functions

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863

In this patch of PlatformInitLib, below hob functions are introduced:
 - PlatformAddIoMemoryBaseSizeHob
 - PlatformAddIoMemoryRangeHob
 - PlatformAddMemoryBaseSizeHob
 - PlatformAddMemoryRangeHob
 - PlatformAddReservedMemoryBaseSizeHob

They correspond the below functions in OvmfPkg/PlatformPei:
 - AddIoMemoryBaseSizeHob
 - AddIoMemoryRangeHob
 - AddMemoryBaseSizeHob
 - AddMemoryRangeHob
 - AddReservedMemoryBaseSizeHob

After above hob functions are introduced in PlatformInitLib,
OvmfPkg/PlatformPei is refactored with this library.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>

diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Library/PlatformInitLib.h
index 2ebac5ccb01312fda6f1557f38bf1bc08203aed8..9b99d4c1f514eff218dcfb2a2e99449d3e86cf35 100644 (file)
--- a/OvmfPkg/Include/Library/PlatformInitLib.h
+++ b/OvmfPkg/Include/Library/PlatformInitLib.h
@@ -96,4 +96,40 @@ PlatformDebugDumpCmos (
   VOID\r
   );\r
 \r
+VOID\r
+EFIAPI\r
+PlatformAddIoMemoryBaseSizeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN UINT64                MemorySize\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddIoMemoryRangeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryLimit\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddMemoryBaseSizeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN UINT64                MemorySize\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddMemoryRangeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryLimit\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddReservedMemoryBaseSizeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN UINT64                MemorySize,\r
+  IN BOOLEAN               Cacheable\r
+  );\r
+\r
 #endif // PLATFORM_INIT_LIB_H_\r

diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c
new file mode 100644 (file)
index 0000000..e41f230
--- /dev/null
+++ b/OvmfPkg/Library/PlatformInitLib/Platform.c
@@ -0,0 +1,106 @@
+/**@file\r
+\r
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <PiPei.h>\r
+\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PlatformInitLib.h>\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddIoMemoryBaseSizeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN UINT64                MemorySize\r
+  )\r
+{\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+    MemoryBase,\r
+    MemorySize\r
+    );\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddReservedMemoryBaseSizeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN UINT64                MemorySize,\r
+  IN BOOLEAN               Cacheable\r
+  )\r
+{\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_RESERVED,\r
+    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+    (Cacheable ?\r
+     EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+     EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
+     0\r
+    ) |\r
+    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+    MemoryBase,\r
+    MemorySize\r
+    );\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddIoMemoryRangeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryLimit\r
+  )\r
+{\r
+  PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddMemoryBaseSizeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN UINT64                MemorySize\r
+  )\r
+{\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_SYSTEM_MEMORY,\r
+    EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
+    MemoryBase,\r
+    MemorySize\r
+    );\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformAddMemoryRangeHob (\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
+  IN EFI_PHYSICAL_ADDRESS  MemoryLimit\r
+  )\r
+{\r
+  PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
+}\r

diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
index 4ea2da86274ffaa4c371672fa4e36116e5ac3d78..21813458cb59dc6d74e03ae66cf055e15e9f4dc5 100644 (file)
--- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
+++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf
@@ -24,6 +24,7 @@
 \r
 [Sources]\r
   Cmos.c\r
+  Platform.c\r
 \r
 [Packages]\r
   MdeModulePkg/MdeModulePkg.dec\r
@@ -34,3 +35,4 @@
   BaseLib\r
   DebugLib\r
   IoLib\r
+  HobLib\r

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 9c5bf240e3baf34db374c4daa484bf6ad96ee8fa..e5e105f377dd24b00df86270a5a9e0cb7675652e 100644 (file)
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -275,10 +275,10 @@ ScanOrAdd64BitE820Ram (
         End  = (E820Entry.BaseAddr + E820Entry.Length) &\r
                ~(UINT64)EFI_PAGE_MASK;\r
         if (Base < End) {\r
-          AddMemoryRangeHob (Base, End);\r
+          PlatformAddMemoryRangeHob (Base, End);\r
           DEBUG ((\r
             DEBUG_VERBOSE,\r
-            "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",\r
+            "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n",\r
             __FUNCTION__,\r
             Base,\r
             End\r
@@ -816,8 +816,8 @@ QemuInitializeRamBelow1gb (
   )\r
 {\r
   if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {\r
-    AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);\r
-    AddReservedMemoryBaseSizeHob (\r
+    PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);\r
+    PlatformAddReservedMemoryBaseSizeHob (\r
       SMM_DEFAULT_SMBASE,\r
       MCH_DEFAULT_SMBASE_SIZE,\r
       TRUE /* Cacheable */\r
@@ -826,12 +826,12 @@ QemuInitializeRamBelow1gb (
       SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,\r
       "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"\r
       );\r
-    AddMemoryRangeHob (\r
+    PlatformAddMemoryRangeHob (\r
       SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,\r
       BASE_512KB + BASE_128KB\r
       );\r
   } else {\r
-    AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
+    PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
   }\r
 }\r
 \r
@@ -889,14 +889,14 @@ QemuInitializeRam (
       UINT32  TsegSize;\r
 \r
       TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
-      AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r
-      AddReservedMemoryBaseSizeHob (\r
+      PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r
+      PlatformAddReservedMemoryBaseSizeHob (\r
         LowerMemorySize - TsegSize,\r
         TsegSize,\r
         TRUE\r
         );\r
     } else {\r
-      AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
+      PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
     }\r
 \r
     //\r
@@ -908,7 +908,7 @@ QemuInitializeRam (
     if (EFI_ERROR (Status)) {\r
       UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r
       if (UpperMemorySize != 0) {\r
-        AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
+        PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
       }\r
     }\r
   }\r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 59489178644072886223c8b9a5cc2c9dd4fb8083..62480c3c40e5dec7edf1098803a8ad33b85949c4 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -57,85 +57,6 @@ BOOLEAN  mS3Supported = FALSE;
 \r
 UINT32  mMaxCpuCount;\r
 \r
-VOID\r
-AddIoMemoryBaseSizeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  UINT64                MemorySize\r
-  )\r
-{\r
-  BuildResourceDescriptorHob (\r
-    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
-    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
-    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
-    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
-    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
-    MemoryBase,\r
-    MemorySize\r
-    );\r
-}\r
-\r
-VOID\r
-AddReservedMemoryBaseSizeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  UINT64                MemorySize,\r
-  BOOLEAN               Cacheable\r
-  )\r
-{\r
-  BuildResourceDescriptorHob (\r
-    EFI_RESOURCE_MEMORY_RESERVED,\r
-    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
-    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
-    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
-    (Cacheable ?\r
-     EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
-     EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
-     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
-     0\r
-    ) |\r
-    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
-    MemoryBase,\r
-    MemorySize\r
-    );\r
-}\r
-\r
-VOID\r
-AddIoMemoryRangeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  EFI_PHYSICAL_ADDRESS  MemoryLimit\r
-  )\r
-{\r
-  AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
-VOID\r
-AddMemoryBaseSizeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  UINT64                MemorySize\r
-  )\r
-{\r
-  BuildResourceDescriptorHob (\r
-    EFI_RESOURCE_SYSTEM_MEMORY,\r
-    EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
-    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
-    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
-    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
-    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
-    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
-    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
-    MemoryBase,\r
-    MemorySize\r
-    );\r
-}\r
-\r
-VOID\r
-AddMemoryRangeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  EFI_PHYSICAL_ADDRESS  MemoryLimit\r
-  )\r
-{\r
-  AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
-}\r
-\r
 VOID\r
 MemMapInitialization (\r
   VOID\r
@@ -155,12 +76,12 @@ MemMapInitialization (
   //\r
   // Video memory + Legacy BIOS region\r
   //\r
-  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
+  PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
 \r
   if (mHostBridgeDevId == 0xffff /* microvm */) {\r
-    AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);\r
-    AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */\r
-    AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */\r
+    PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);\r
+    PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */\r
+    PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */\r
     return;\r
   }\r
 \r
@@ -194,20 +115,20 @@ MemMapInitialization (
   // 0xFEE00000    LAPIC                          1 MB\r
   //\r
   PciSize = 0xFC000000 - PciBase;\r
-  AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
+  PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);\r
   PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
   ASSERT_RETURN_ERROR (PcdStatus);\r
   PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);\r
   ASSERT_RETURN_ERROR (PcdStatus);\r
 \r
-  AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
-  AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
+  PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
+  PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
-    AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
+    PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
     //\r
     // Note: there should be an\r
     //\r
-    //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
+    //   PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
     //\r
     // call below, just like the one above for RCBA. However, Linux insists\r
     // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
@@ -225,7 +146,7 @@ MemMapInitialization (
     // is most definitely not RAM; so, as an exception, cover it with\r
     // uncacheable reserved memory right here.\r
     //\r
-    AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
+    PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
     BuildMemoryAllocationHob (\r
       PciExBarBase,\r
       SIZE_256MB,\r
@@ -233,7 +154,7 @@ MemMapInitialization (
       );\r
   }\r
 \r
-  AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
+  PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
 \r
   //\r
   // On Q35, the IO Port space is available for PCI resource allocations from\r

diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h
index 24e4da4e1d93ebb481546165e39ebc0cacb952a4..f193ff7365494ec3f6be57a7e0f43c3035c97f8b 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.h
+++ b/OvmfPkg/PlatformPei/Platform.h
@@ -11,37 +11,6 @@
 \r
 #include <IndustryStandard/E820.h>\r
 \r
-VOID\r
-AddIoMemoryBaseSizeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  UINT64                MemorySize\r
-  );\r
-\r
-VOID\r
-AddIoMemoryRangeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  EFI_PHYSICAL_ADDRESS  MemoryLimit\r
-  );\r
-\r
-VOID\r
-AddMemoryBaseSizeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  UINT64                MemorySize\r
-  );\r
-\r
-VOID\r
-AddMemoryRangeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  EFI_PHYSICAL_ADDRESS  MemoryLimit\r
-  );\r
-\r
-VOID\r
-AddReservedMemoryBaseSizeHob (\r
-  EFI_PHYSICAL_ADDRESS  MemoryBase,\r
-  UINT64                MemorySize,\r
-  BOOLEAN               Cacheable\r
-  );\r
-\r
 VOID\r
 AddressWidthInitialization (\r
   VOID\r