MdeModulePkg: PciHostBridgeDxe: insert horizontal whitespace

... in preparation for the next patch.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 332860eb3819a8fbd1f83975cce8efc74c7c0ee1..932aefd5d621fe8593f2981240b3589a4a8e5b6c 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -78,18 +78,18 @@ CreateRootBridge (
 \r
   DEBUG ((EFI_D_INFO, "RootBridge: "));\r
   DEBUG ((EFI_D_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));\r
-  DEBUG ((EFI_D_INFO, "Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));\r
-  DEBUG ((EFI_D_INFO, "  DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));\r
-  DEBUG ((EFI_D_INFO, "   AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,\r
+  DEBUG ((EFI_D_INFO, "  Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));\r
+  DEBUG ((EFI_D_INFO, "    DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));\r
+  DEBUG ((EFI_D_INFO, "     AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,\r
           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",\r
           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""\r
           ));\r
-  DEBUG ((EFI_D_INFO, "         Bus: %lx - %lx\n", Bridge->Bus.Base, Bridge->Bus.Limit));\r
-  DEBUG ((EFI_D_INFO, "          Io: %lx - %lx\n", Bridge->Io.Base, Bridge->Io.Limit));\r
-  DEBUG ((EFI_D_INFO, "         Mem: %lx - %lx\n", Bridge->Mem.Base, Bridge->Mem.Limit));\r
-  DEBUG ((EFI_D_INFO, "  MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit));\r
-  DEBUG ((EFI_D_INFO, "        PMem: %lx - %lx\n", Bridge->PMem.Base, Bridge->PMem.Limit));\r
-  DEBUG ((EFI_D_INFO, " PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit));\r
+  DEBUG ((EFI_D_INFO, "           Bus: %lx - %lx\n", Bridge->Bus.Base, Bridge->Bus.Limit));\r
+  DEBUG ((EFI_D_INFO, "            Io: %lx - %lx\n", Bridge->Io.Base, Bridge->Io.Limit));\r
+  DEBUG ((EFI_D_INFO, "           Mem: %lx - %lx\n", Bridge->Mem.Base, Bridge->Mem.Limit));\r
+  DEBUG ((EFI_D_INFO, "    MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit));\r
+  DEBUG ((EFI_D_INFO, "          PMem: %lx - %lx\n", Bridge->PMem.Base, Bridge->PMem.Limit));\r
+  DEBUG ((EFI_D_INFO, "   PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit));\r
 \r
   //\r
   // Make sure Mem and MemAbove4G apertures are valid\r

diff --git a/MdeModulePkg/Include/Library/PciHostBridgeLib.h b/MdeModulePkg/Include/Library/PciHostBridgeLib.h
index b1dba0f754d7940a8362cfd7c9a027adc1a6f8ef..16ad104a9368a7511e03cf7be2603437165be085 100644 (file)
--- a/MdeModulePkg/Include/Library/PciHostBridgeLib.h
+++ b/MdeModulePkg/Include/Library/PciHostBridgeLib.h
@@ -25,26 +25,26 @@ typedef struct {
 } PCI_ROOT_BRIDGE_APERTURE;\r
 \r
 typedef struct {\r
-  UINT32                   Segment;              ///< Segment number.\r
-  UINT64                   Supports;             ///< Supported attributes.\r
-                                                 ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
-                                                 ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-  UINT64                   Attributes;           ///< Initial attributes.\r
-                                                 ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
-                                                 ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-  BOOLEAN                  DmaAbove4G;           ///< DMA above 4GB memory.\r
-                                                 ///< Set to TRUE when root bridge supports DMA above 4GB memory.\r
-  UINT64                   AllocationAttributes; ///< Allocation attributes.\r
-                                                 ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r
-                                                 ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r
-                                                 ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
-  PCI_ROOT_BRIDGE_APERTURE Bus;                  ///< Bus aperture which can be used by the root bridge.\r
-  PCI_ROOT_BRIDGE_APERTURE Io;                   ///< IO aperture which can be used by the root bridge.\r
-  PCI_ROOT_BRIDGE_APERTURE Mem;                  ///< MMIO aperture below 4GB which can be used by the root bridge.\r
-  PCI_ROOT_BRIDGE_APERTURE MemAbove4G;           ///< MMIO aperture above 4GB which can be used by the root bridge.\r
-  PCI_ROOT_BRIDGE_APERTURE PMem;                 ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.\r
-  PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;          ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.\r
-  EFI_DEVICE_PATH_PROTOCOL *DevicePath;          ///< Device path.\r
+  UINT32                   Segment;               ///< Segment number.\r
+  UINT64                   Supports;              ///< Supported attributes.\r
+                                                  ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
+                                                  ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+  UINT64                   Attributes;            ///< Initial attributes.\r
+                                                  ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r
+                                                  ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+  BOOLEAN                  DmaAbove4G;            ///< DMA above 4GB memory.\r
+                                                  ///< Set to TRUE when root bridge supports DMA above 4GB memory.\r
+  UINT64                   AllocationAttributes;  ///< Allocation attributes.\r
+                                                  ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r
+                                                  ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r
+                                                  ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
+  PCI_ROOT_BRIDGE_APERTURE Bus;                   ///< Bus aperture which can be used by the root bridge.\r
+  PCI_ROOT_BRIDGE_APERTURE Io;                    ///< IO aperture which can be used by the root bridge.\r
+  PCI_ROOT_BRIDGE_APERTURE Mem;                   ///< MMIO aperture below 4GB which can be used by the root bridge.\r
+  PCI_ROOT_BRIDGE_APERTURE MemAbove4G;            ///< MMIO aperture above 4GB which can be used by the root bridge.\r
+  PCI_ROOT_BRIDGE_APERTURE PMem;                  ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.\r
+  PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;           ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.\r
+  EFI_DEVICE_PATH_PROTOCOL *DevicePath;           ///< Device path.\r
 } PCI_ROOT_BRIDGE;\r
 \r
 /**\r