ArmPkg/ArmV7Lib: fix definition of TTBR_NON_INNER_CACHEABLE

The definition of TTBR_NON_INNER_CACHEABLE should be bit 0 cleared, not
bit 0 set. Furthermore, the name is inconsistent with the other definitions
so rename it to TTBR_INNER_NON_CACHEABLE.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18898 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h
index f612154badc10a2d9e2e70a223da32f982108a94..7fafc888fe94195ef2bbd97528de2e8c815400ec 100644 (file)
--- a/ArmPkg/Include/Chipset/ArmV7Mmu.h
+++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h
@@ -23,7 +23,7 @@
 #define TTBR_SHAREABLE                       BIT1\r
 #define TTBR_NON_SHAREABLE                   0\r
 #define TTBR_INNER_CACHEABLE                 BIT0\r
-#define TTBR_NON_INNER_CACHEABLE             BIT0\r
+#define TTBR_INNER_NON_CACHEABLE             0\r
 #define TTBR_RGN_INNER_NON_CACHEABLE         0\r
 #define TTBR_RGN_INNER_WRITE_BACK_ALLOC      BIT6\r
 #define TTBR_RGN_INNER_WRITE_THROUGH         BIT0\r