It is introduced by
9e9ca2100f22be29f1a53129d741f4305ff34a71.
Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
// will be built based on them in PEI phase.\r
//\r
SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
- SecCoreData->PeiTemporaryRamSize &= ~0x07;\r
+ SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;\r
} else {\r
//\r
// No addition PPI, PpiList directly point to the common PPI list.\r