/** @file\r
UEFI Application to display CPUID leaf information.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
UINT32 SubLeaf;\r
- \r
+\r
SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;\r
do {\r
AsmCpuidEx (\r
//\r
return;\r
}\r
- \r
+\r
CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();\r
CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();\r
CpuidEnumerationOfIntelSgxResourcesSubLeaf ();\r
/** @file\r
CPU DXE Module to produce CPU ARCH Protocol.\r
\r
- Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
}\r
\r
/**\r
- Add and allocate CPU local APIC memory mapped space. \r
+ Add and allocate CPU local APIC memory mapped space.\r
\r
@param[in]ImageHandle Image handle this driver.\r
\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
- // Try to allocate APIC memory mapped space, does not check return \r
+ // Try to allocate APIC memory mapped space, does not check return\r
// status because it may be allocated by other driver, or DXE Core if\r
// this range is built into Memory Allocation HOB.\r
//\r
{\r
EFI_STATUS Status;\r
EFI_EVENT IdleLoopEvent;\r
- \r
+\r
InitializePageTableLib();\r
\r
InitializeFloatingPointUnits ();\r
//\r
// CPU driver installs CPU Architecture Protocol and CPU MP Protocol.\r
//\r
-// Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
// /** @file\r
// CpuDxe Localized Strings and Content\r
//\r
-// Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_MODULE_NAME \r
-#language en-US \r
+#string STR_PROPERTIES_MODULE_NAME\r
+#language en-US\r
"CPU Architectural and CPU Multi-processor DXE Driver"\r
\r
\r
/** @file\r
CPU Features DXE driver to initialize CPU features.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
if (GetFirstGuidHob (&gEdkiiCpuFeaturesInitDoneGuid) != NULL) {\r
//\r
- // Try to find HOB first. This HOB exist means CPU features have \r
- // been initialized by CpuFeaturesPei driver, just install \r
+ // Try to find HOB first. This HOB exist means CPU features have\r
+ // been initialized by CpuFeaturesPei driver, just install\r
// gEdkiiCpuFeaturesInitDoneGuid.\r
//\r
Handle = NULL;\r
/** @file\r
Produces the CPU I/O 2 Protocol.\r
\r
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
/**\r
Check parameters to a CPU I/O 2 Protocol service request.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
+\r
@param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[in] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
// Check to see if Address is aligned\r
//\r
}\r
\r
//\r
- // Check to see if any address associated with this transfer exceeds the maximum \r
+ // Check to see if any address associated with this transfer exceeds the maximum\r
// allowed address. The maximum address implied by the parameters passed in is\r
// Address + Size * Count. If the following condition is met, then the transfer\r
// is not supported.\r
//\r
// Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1\r
//\r
- // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count \r
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count\r
// can also be the maximum integer value supported by the CPU, this range\r
// check must be adjusted to avoid all oveflow conditions.\r
- // \r
- // The following form of the range check is equivalent but assumes that \r
+ //\r
+ // The following form of the range check is equivalent but assumes that\r
// MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
//\r
Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);\r
if (Address > Limit) {\r
return EFI_UNSUPPORTED;\r
}\r
- } else { \r
+ } else {\r
MaxCount = RShiftU64 (Limit, Width);\r
if (MaxCount < (Count - 1)) {\r
return EFI_UNSUPPORTED;\r
/**\r
Reads memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[out] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
/**\r
Writes memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[in] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
/**\r
Reads I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[out] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
/**\r
Write I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[in] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
}\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
The user Entry Point for module CpuIo2Dxe. The user code starts with this function.\r
\r
- @param[in] ImageHandle The firmware allocated handle for the EFI image. \r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
@param[in] SystemTable A pointer to the EFI System Table.\r
- \r
+\r
@retval EFI_SUCCESS The entry point is executed successfully.\r
@retval other Some error occurs when executing this entry point.\r
\r
/** @file\r
Internal include file for the CPU I/O 2 Protocol.\r
\r
-Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
/**\r
Reads memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[out] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
/**\r
Writes memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[in] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
/**\r
Reads I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[out] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
\r
**/\r
/**\r
Write I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is responsible \r
- for satisfying any alignment and I/O width restrictions that a PI System on a \r
- platform might require. For example on some platforms, width requests of \r
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+ The I/O operations are carried out exactly as requested. The caller is responsible\r
+ for satisfying any alignment and I/O width restrictions that a PI System on a\r
+ platform might require. For example on some platforms, width requests of\r
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
be handled by the driver.\r
- \r
- If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
- or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r
each of the Count operations that is performed.\r
- \r
- If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
- EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times on the same Address.\r
- \r
- If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
- EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
- incremented for each of the Count operations that is performed. The read or \r
+\r
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+ incremented for each of the Count operations that is performed. The read or\r
write operation is performed Count times from the first element of Buffer.\r
- \r
+\r
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O or Memory operation.\r
- @param[in] Address The base address of the I/O operation. \r
- @param[in] Count The number of I/O operations to perform. The number of \r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Count The number of I/O operations to perform. The number of\r
bytes moved is Width size * Count, starting at Address.\r
@param[in] Buffer For read operations, the destination buffer to store the results.\r
For write operations, the source buffer from which to write data.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this PI system.\r
- \r
+\r
**/\r
EFI_STATUS\r
EFIAPI\r
## @file\r
# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.\r
#\r
-# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
MODULE_UNI_FILE = CpuIo2Dxe.uni\r
FILE_GUID = A19B1FE7-C1BC-49F8-875F-54A5D542443F\r
MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0 \r
+ VERSION_STRING = 1.0\r
ENTRY_POINT = CpuIo2Initialize\r
\r
#\r
//\r
// Produces the CPU I/O 2 Protocol by using the services of the I/O Library.\r
//\r
-// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
// /** @file\r
// CpuIo2Dxe Localized Strings and Content\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_MODULE_NAME \r
-#language en-US \r
+#string STR_PROPERTIES_MODULE_NAME\r
+#language en-US\r
"CPU I/O v2 DXE Driver"\r
\r
\r
/** @file\r
Produces the SMM CPU I/O Protocol.\r
\r
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
@param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[in] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[in] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- \r
+\r
**/\r
EFI_STATUS\r
CpuIoCheckParameter (\r
if (!MmioOperation && (Width == SMM_IO_UINT64)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
- // Check to see if any address associated with this transfer exceeds the maximum \r
+ // Check to see if any address associated with this transfer exceeds the maximum\r
// allowed address. The maximum address implied by the parameters passed in is\r
// Address + Size * Count. If the following condition is met, then the transfer\r
// is not supported.\r
//\r
// Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1\r
//\r
- // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count \r
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count\r
// can also be the maximum integer value supported by the CPU, this range\r
// check must be adjusted to avoid all overflow conditions.\r
- // \r
- // The following form of the range check is equivalent but assumes that \r
+ //\r
+ // The following form of the range check is equivalent but assumes that\r
// MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
//\r
Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);\r
if (Address > Limit) {\r
return EFI_UNSUPPORTED;\r
}\r
- } else { \r
+ } else {\r
MaxCount = RShiftU64 (Limit, Width);\r
if (MaxCount < (Count - 1)) {\r
return EFI_UNSUPPORTED;\r
return EFI_UNSUPPORTED;\r
}\r
}\r
- \r
+\r
//\r
// Check to see if Address is aligned\r
//\r
/**\r
Reads memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is \r
- responsible for any alignment and I/O width issues that the bus, device, \r
+ The I/O operations are carried out exactly as requested. The caller is\r
+ responsible for any alignment and I/O width issues that the bus, device,\r
platform, or type of I/O might require.\r
\r
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[out] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[out] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
lack of resources\r
\r
**/\r
/**\r
Writes memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is \r
- responsible for any alignment and I/O width issues that the bus, device, \r
+ The I/O operations are carried out exactly as requested. The caller is\r
+ responsible for any alignment and I/O width issues that the bus, device,\r
platform, or type of I/O might require.\r
\r
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[in] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[in] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
lack of resources\r
\r
**/\r
/**\r
Reads I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is \r
- responsible for any alignment and I/O width issues that the bus, device, \r
+ The I/O operations are carried out exactly as requested. The caller is\r
+ responsible for any alignment and I/O width issues that the bus, device,\r
platform, or type of I/O might require.\r
\r
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[out] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[out] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
lack of resources\r
\r
**/\r
/**\r
Write I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is \r
- responsible for any alignment and I/O width issues that the bus, device, \r
+ The I/O operations are carried out exactly as requested. The caller is\r
+ responsible for any alignment and I/O width issues that the bus, device,\r
platform, or type of I/O might require.\r
\r
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[in] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[in] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
lack of resources\r
\r
**/\r
IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
}\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
&mSmmCpuIo2\r
);\r
ASSERT_EFI_ERROR (Status);\r
- \r
+\r
return Status;\r
}\r
/** @file\r
Internal include file for the SMM CPU I/O Protocol.\r
\r
-Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
/**\r
Reads memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is \r
- responsible for any alignment and I/O width issues that the bus, device, \r
+ The I/O operations are carried out exactly as requested. The caller is\r
+ responsible for any alignment and I/O width issues that the bus, device,\r
platform, or type of I/O might require.\r
\r
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[out] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[out] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
lack of resources\r
\r
**/\r
/**\r
Writes memory-mapped registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is \r
- responsible for any alignment and I/O width issues that the bus, device, \r
+ The I/O operations are carried out exactly as requested. The caller is\r
+ responsible for any alignment and I/O width issues that the bus, device,\r
platform, or type of I/O might require.\r
\r
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[in] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[in] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
lack of resources\r
\r
**/\r
/**\r
Reads I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is \r
- responsible for any alignment and I/O width issues that the bus, device, \r
+ The I/O operations are carried out exactly as requested. The caller is\r
+ responsible for any alignment and I/O width issues that the bus, device,\r
platform, or type of I/O might require.\r
\r
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[out] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[out] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
lack of resources\r
\r
**/\r
/**\r
Write I/O registers.\r
\r
- The I/O operations are carried out exactly as requested. The caller is \r
- responsible for any alignment and I/O width issues that the bus, device, \r
+ The I/O operations are carried out exactly as requested. The caller is\r
+ responsible for any alignment and I/O width issues that the bus, device,\r
platform, or type of I/O might require.\r
\r
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.\r
@param[in] Width Signifies the width of the I/O operations.\r
- @param[in] Address The base address of the I/O operations. The caller is \r
- responsible for aligning the Address if required. \r
+ @param[in] Address The base address of the I/O operations. The caller is\r
+ responsible for aligning the Address if required.\r
@param[in] Count The number of I/O operations to perform.\r
- @param[in] Buffer For read operations, the destination buffer to store \r
- the results. For write operations, the source buffer \r
+ @param[in] Buffer For read operations, the destination buffer to store\r
+ the results. For write operations, the source buffer\r
from which to write data.\r
\r
@retval EFI_SUCCESS The data was read from or written to the device.\r
@retval EFI_UNSUPPORTED The Address is not valid for this system.\r
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a \r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a\r
lack of resources\r
\r
**/\r
## @file\r
-# Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library. \r
+# Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library.\r
#\r
-# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
#\r
# The following information is for reference only and not required by the build tools.\r
#\r
-# VALID_ARCHITECTURES = IA32 X64 \r
+# VALID_ARCHITECTURES = IA32 X64\r
#\r
\r
[Sources]\r
CpuIo2Smm.c\r
CpuIo2Smm.h\r
- \r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
IoLib\r
SmmServicesTableLib\r
BaseMemoryLib\r
- \r
+\r
[Protocols]\r
gEfiSmmCpuIo2ProtocolGuid ## PRODUCES\r
\r
// /** @file\r
// CpuIo2Smm Localized Strings and Content\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_MODULE_NAME \r
+#string STR_PROPERTIES_MODULE_NAME\r
#language en-US\r
"CPU I/O v2 SMM Driver"\r
\r
/** @file\r
Produces the CPU I/O PPI.\r
\r
-Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
&gEfiPeiCpuIoPpiInstalledGuid,\r
NULL\r
};\r
- \r
+\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
@retval EFI_SUCCESS The parameters for this request pass the checks.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
- \r
+\r
**/\r
EFI_STATUS\r
CpuIoCheckParameter (\r
if (!MmioOperation && (Width == EfiPeiCpuIoWidthUint64)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- \r
+\r
//\r
- // Check to see if any address associated with this transfer exceeds the maximum \r
+ // Check to see if any address associated with this transfer exceeds the maximum\r
// allowed address. The maximum address implied by the parameters passed in is\r
// Address + Size * Count. If the following condition is met, then the transfer\r
// is not supported.\r
//\r
// Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1\r
//\r
- // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count \r
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count\r
// can also be the maximum integer value supported by the CPU, this range\r
// check must be adjusted to avoid all overflow conditions.\r
- // \r
- // The following form of the range check is equivalent but assumes that \r
+ //\r
+ // The following form of the range check is equivalent but assumes that\r
// MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
//\r
Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);\r
if (Address > Limit) {\r
return EFI_UNSUPPORTED;\r
}\r
- } else { \r
+ } else {\r
MaxCount = RShiftU64 (Limit, Width);\r
if (MaxCount < (Count - 1)) {\r
return EFI_UNSUPPORTED;\r
return EFI_UNSUPPORTED;\r
}\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
@retval EFI_SUCCESS The function completed successfully.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
\r
**/\r
@retval EFI_SUCCESS The function completed successfully.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
\r
**/\r
@retval EFI_SUCCESS The function completed successfully.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
\r
**/\r
@retval EFI_SUCCESS The function completed successfully.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
\r
**/\r
}\r
}\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
\r
/**\r
8-bit I/O read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
16-bit I/O read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
32-bit I/O read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
64-bit I/O read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
8-bit I/O write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
16-bit I/O write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
32-bit I/O write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
64-bit I/O write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
8-bit memory read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
16-bit memory read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
32-bit memory read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
64-bit memory read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
8-bit memory write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
16-bit memory write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
32-bit memory write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
64-bit memory write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
This function is the Entry point of the CPU I/O PEIM which installs CpuIoPpi.\r
\r
@param[in] FileHandle Pointer to image file handle.\r
- @param[in] PeiServices Pointer to PEI Services Table \r
+ @param[in] PeiServices Pointer to PEI Services Table\r
\r
@retval EFI_SUCCESS CPU I/O PPI successfully installed\r
\r
// Register so it will be automatically shadowed to memory\r
//\r
Status = PeiServicesRegisterForShadow (FileHandle);\r
- \r
+\r
//\r
// Make CpuIo pointer in PeiService table point to gCpuIoPpi\r
//\r
(*((EFI_PEI_SERVICES **)PeiServices))->CpuIo = &gCpuIoPpi;\r
- \r
+\r
if (Status == EFI_ALREADY_STARTED) {\r
//\r
// Shadow completed and running from memory\r
Status = PeiServicesInstallPpi (&gPpiList);\r
ASSERT_EFI_ERROR (Status);\r
}\r
- \r
+\r
return EFI_SUCCESS;\r
}\r
/** @file\r
Internal include file for the CPU I/O PPI.\r
\r
-Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
@retval EFI_SUCCESS The function completed successfully.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
\r
**/\r
@retval EFI_SUCCESS The function completed successfully.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
\r
**/\r
@retval EFI_SUCCESS The function completed successfully.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
\r
**/\r
@retval EFI_SUCCESS The function completed successfully.\r
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.\r
@retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r
and Count is not valid for this EFI system.\r
\r
**/\r
/**\r
8-bit I/O read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
16-bit I/O read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
32-bit I/O read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
64-bit I/O read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
8-bit I/O write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
16-bit I/O write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
32-bit I/O write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
64-bit I/O write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
8-bit memory read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
16-bit memory read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
32-bit memory read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
64-bit memory read operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
8-bit memory write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
16-bit memory write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
32-bit memory write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
/**\r
64-bit memory write operations.\r
\r
- @param[in] PeiServices An indirect pointer to the PEI Services Table published \r
+ @param[in] PeiServices An indirect pointer to the PEI Services Table published\r
by the PEI Foundation.\r
@param[in] This Pointer to local data for the interface.\r
@param[in] Address The physical address of the access.\r
IN UINT64 Address,\r
IN UINT64 Data\r
);\r
- \r
+\r
#endif\r
## @file\r
# Produces the CPU I/O PPI by using the services of the I/O Library.\r
#\r
-# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
MODULE_UNI_FILE = CpuIoPei.uni\r
FILE_GUID = AE265864-CF5D-41a8-913D-71C155E76442\r
MODULE_TYPE = PEIM\r
- VERSION_STRING = 1.0 \r
+ VERSION_STRING = 1.0\r
ENTRY_POINT = CpuIoInitialize\r
\r
#\r
[Sources]\r
CpuIoPei.c\r
CpuIoPei.h\r
- \r
+\r
[Packages]\r
MdePkg/MdePkg.dec\r
\r
//\r
// Produces the CPU I/O PPI by using the services of the I/O Library.\r
//\r
-// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
// /** @file\r
// CpuIoPei Localized Strings and Content\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_MODULE_NAME \r
-#language en-US \r
+#string STR_PROPERTIES_MODULE_NAME\r
+#language en-US\r
"CPU I/O PEI Module"\r
\r
\r
/** @file\r
Update and publish processors' BIST information.\r
\r
- Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINTN BistInformationSize;\r
EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2;\r
EFI_SEC_PLATFORM_INFORMATION_CPU *CpuInstanceInHob;\r
- \r
+\r
\r
MpInitLibGetNumberOfProcessors(&NumberOfProcessors, &NumberOfEnabledProcessors);\r
\r
CpuInstanceInHob[ProcessorNumber].CpuLocation = (UINT32) ProcessorInfo.ProcessorId;\r
CpuInstanceInHob[ProcessorNumber].InfoRecord.IA32HealthFlags = BistData;\r
}\r
- \r
+\r
//\r
// Build SecPlatformInformation2 PPI GUIDed HOB that also could be consumed\r
// by CPU MP driver to get CPU BIST data\r
/** @file\r
CPU PEI Module installs CPU Multiple Processor PPI.\r
\r
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
}\r
Status = InitializeCpuExceptionHandlers (VectorInfo);\r
ASSERT_EFI_ERROR (Status);\r
- \r
+\r
//\r
// Wakeup APs to do initialization\r
//\r
Local APIC library assumes local APIC is enabled. It does not\r
handles cases where local APIC is disabled.\r
\r
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
- In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
+ In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r
the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
@return 32-bit initial local APIC ID of the executing processor.\r
/**\r
Send a Fixed IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId The local APIC ID of the target processor.\r
@param Vector The vector number of the interrupt being sent.\r
/**\r
Send a Fixed IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
@param Vector The vector number of the interrupt being sent.\r
**/\r
/**\r
Send a SMI IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send a SMI IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send an INIT IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
);\r
\r
/**\r
- Get the 32-bit address that a device should use to send a Message Signaled \r
+ Get the 32-bit address that a device should use to send a Message Signaled\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
@return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
-EFIAPI \r
+EFIAPI\r
GetApicMsiAddress (\r
VOID\r
);\r
- \r
+\r
/**\r
- Get the 64-bit data value that a device should use to send a Message Signaled \r
+ Get the 64-bit data value that a device should use to send a Message Signaled\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
If Vector is not in range 0x10..0xFE, then ASSERT().\r
If DeliveryMode is not supported, then ASSERT().\r
- \r
- @param Vector The 8-bit interrupt vector associated with the MSI. \r
+\r
+ @param Vector The 8-bit interrupt vector associated with the MSI.\r
Must be in the range 0x10..0xFE\r
- @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
+ @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r
is handled. The only supported values are:\r
0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
4: LOCAL_APIC_DELIVERY_MODE_NMI\r
5: LOCAL_APIC_DELIVERY_MODE_INIT\r
7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
- \r
- @param LevelTriggered TRUE specifies a level triggered interrupt. \r
+\r
+ @param LevelTriggered TRUE specifies a level triggered interrupt.\r
FALSE specifies an edge triggered interrupt.\r
@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
- TRUE specifies a level triggered interrupt that active \r
+ TRUE specifies a level triggered interrupt that active\r
when the interrupt line is asserted.\r
- FALSE specifies a level triggered interrupt that active \r
+ FALSE specifies a level triggered interrupt that active\r
when the interrupt line is deasserted.\r
\r
@return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
-EFIAPI \r
+EFIAPI\r
GetApicMsiValue (\r
IN UINT8 Vector,\r
IN UINTN DeliveryMode,\r
OUT UINT32 *Core OPTIONAL,\r
OUT UINT32 *Thread OPTIONAL\r
);\r
- \r
+\r
#endif\r
\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
-# \r
+#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-# \r
+#\r
##\r
\r
[Defines]\r
FILE_GUID = 34C24FD7-7A90-45c2-89FD-946473D9CE98\r
MODULE_TYPE = BASE\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = UefiCpuLib \r
+ LIBRARY_CLASS = UefiCpuLib\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
//\r
// The library routines are UEFI specification compliant.\r
//\r
-// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
#------------------------------------------------------------------------------\r
#*\r
-#* Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
+#* Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
#* This program and the accompanying materials\r
#* are licensed and made available under the terms and conditions of the BSD License\r
#* which accompanies this distribution. The full text of the license may be found at\r
#------------------------------------------------------------------------------\r
\r
#\r
-# Float control word initial value: \r
+# Float control word initial value:\r
# all exceptions masked, double-precision, round-to-nearest\r
#\r
ASM_PFX(mFpuControlWord): .word 0x027F\r
#\r
finit\r
fldcw ASM_PFX(mFpuControlWord)\r
- \r
+\r
#\r
# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
# whether the processor supports SSE instruction.\r
cpuid\r
btl $25, %edx\r
jnc Done\r
- \r
+\r
#\r
# Set OSFXSR bit 9 in CR4\r
#\r
- movl %cr4, %eax \r
+ movl %cr4, %eax\r
or $0x200, %eax\r
movl %eax, %cr4\r
- \r
+\r
#\r
# The processor should support SSE instruction and we can use\r
# ldmxcsr instruction\r
#------------------------------------------------------------------------------\r
#*\r
-#* Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>\r
+#* Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
#* This program and the accompanying materials\r
#* are licensed and made available under the terms and conditions of the BSD License\r
#* which accompanies this distribution. The full text of the license may be found at\r
# Initialize floating point units\r
#\r
finit\r
- \r
+\r
#\r
- # Float control word initial value: \r
+ # Float control word initial value:\r
# all exceptions masked, double-precision, round-to-nearest\r
#\r
pushq $0x037F\r
- lea (%rsp), %rax \r
+ lea (%rsp), %rax\r
fldcw (%rax)\r
popq %rax\r
- \r
+\r
#\r
# Set OSFXSR bit 9 in CR4\r
#\r
- movq %cr4, %rax \r
+ movq %cr4, %rax\r
or $0x200, %rax\r
movq %rax, %cr4\r
\r
#\r
# Multimedia-extensions control word:\r
# all exceptions masked, round-to-nearest, flush to zero for masked underflow\r
- # \r
+ #\r
pushq $0x01F80\r
lea (%rsp), %rax\r
ldmxcsr (%rax)\r
popq %rax\r
- \r
+\r
ret\r
\r
\r
This local APIC library instance supports xAPIC mode only.\r
\r
- Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
{\r
UINT32 RegEax;\r
UINTN FamilyId;\r
- \r
+\r
AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
if (FamilyId == 0x04 || FamilyId == 0x05) {\r
//\r
- // CPUs with a FamilyId of 0x04 or 0x05 do not support the \r
+ // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r
// Local APIC Base Address MSR\r
//\r
return FALSE;\r
}\r
\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
- \r
+\r
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
}\r
/**\r
Send an IPI by writing to ICR.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param IcrLow 32-bit value to be written to the low half of ICR.\r
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;\r
\r
//\r
- // Check to see if the CPU supports the APIC Base Address MSR \r
+ // Check to see if the CPU supports the APIC Base Address MSR\r
//\r
if (LocalApicBaseAddressMsrSupported ()) {\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
- In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
+ In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r
the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
@return 32-bit initial local APIC ID of the executing processor.\r
AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
\r
//\r
- // If CPUID Leaf B is supported, \r
+ // If CPUID Leaf B is supported,\r
// And CPUID.0BH:EBX[15:0] reports a non-zero value,\r
// Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
// Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
UINT32 ApicId;\r
\r
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
- \r
+\r
if ((ApicId = GetInitialApicId ()) < 0x100) {\r
//\r
// If the initial local APIC ID is less 0x100, read APIC ID from\r
/**\r
Send a Fixed IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId The local APIC ID of the target processor.\r
@param Vector The vector number of the interrupt being sent.\r
/**\r
Send a Fixed IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
@param Vector The vector number of the interrupt being sent.\r
**/\r
/**\r
Send a SMI IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send a SMI IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send an INIT IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
- WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r
+ WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r
}\r
\r
//\r
}\r
\r
/**\r
- Get the 32-bit address that a device should use to send a Message Signaled \r
+ Get the 32-bit address that a device should use to send a Message Signaled\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
@return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
-EFIAPI \r
+EFIAPI\r
GetApicMsiAddress (\r
VOID\r
)\r
LOCAL_APIC_MSI_ADDRESS MsiAddress;\r
\r
//\r
- // Return address for an MSI interrupt to be delivered only to the APIC ID \r
+ // Return address for an MSI interrupt to be delivered only to the APIC ID\r
// of the currently executing processor.\r
//\r
MsiAddress.Uint32 = 0;\r
MsiAddress.Bits.DestinationId = GetApicId ();\r
return MsiAddress.Uint32;\r
}\r
- \r
+\r
/**\r
- Get the 64-bit data value that a device should use to send a Message Signaled \r
+ Get the 64-bit data value that a device should use to send a Message Signaled\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
If Vector is not in range 0x10..0xFE, then ASSERT().\r
If DeliveryMode is not supported, then ASSERT().\r
- \r
- @param Vector The 8-bit interrupt vector associated with the MSI. \r
+\r
+ @param Vector The 8-bit interrupt vector associated with the MSI.\r
Must be in the range 0x10..0xFE\r
- @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
+ @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r
is handled. The only supported values are:\r
0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
4: LOCAL_APIC_DELIVERY_MODE_NMI\r
5: LOCAL_APIC_DELIVERY_MODE_INIT\r
7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
- \r
- @param LevelTriggered TRUE specifies a level triggered interrupt. \r
+\r
+ @param LevelTriggered TRUE specifies a level triggered interrupt.\r
FALSE specifies an edge triggered interrupt.\r
@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
- TRUE specifies a level triggered interrupt that active \r
+ TRUE specifies a level triggered interrupt that active\r
when the interrupt line is asserted.\r
- FALSE specifies a level triggered interrupt that active \r
+ FALSE specifies a level triggered interrupt that active\r
when the interrupt line is deasserted.\r
\r
@return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
-EFIAPI \r
+EFIAPI\r
GetApicMsiValue (\r
IN UINT8 Vector,\r
IN UINTN DeliveryMode,\r
\r
ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
- \r
+\r
MsiData.Uint64 = 0;\r
MsiData.Bits.Vector = Vector;\r
MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
# Note: Local APIC library assumes local APIC is enabled. It does not handle cases\r
# where local APIC is disabled.\r
#\r
-# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
-# \r
+#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-# \r
+#\r
##\r
\r
[Defines]\r
FILE_GUID = D87CA0A8-1AC2-439b-90F8-EF4A2AC88DAF\r
MODULE_TYPE = BASE\r
VERSION_STRING = 1.1\r
- LIBRARY_CLASS = LocalApicLib \r
+ LIBRARY_CLASS = LocalApicLib\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
// Note: Local APIC library assumes local APIC is enabled. It does not handle cases\r
// where local APIC is disabled.\r
//\r
-// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
This local APIC library instance supports x2APIC capable processors\r
which have xAPIC and x2APIC modes.\r
\r
- Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
{\r
UINT32 RegEax;\r
UINTN FamilyId;\r
- \r
+\r
AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
if (FamilyId == 0x04 || FamilyId == 0x05) {\r
//\r
- // CPUs with a FamilyId of 0x04 or 0x05 do not support the \r
+ // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r
// Local APIC Base Address MSR\r
//\r
return FALSE;\r
}\r
\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
- \r
+\r
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
}\r
/**\r
Send an IPI by writing to ICR.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param IcrLow 32-bit value to be written to the low half of ICR.\r
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
\r
} else {\r
//\r
- // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an \r
+ // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an\r
// interrupt in x2APIC mode.\r
//\r
MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
- In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
+ In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r
the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
@return 32-bit initial local APIC ID of the executing processor.\r
//\r
AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
//\r
- // If CPUID Leaf B is supported, \r
+ // If CPUID Leaf B is supported,\r
// And CPUID.0BH:EBX[15:0] reports a non-zero value,\r
// Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
// Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
/**\r
Send a Fixed IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId The local APIC ID of the target processor.\r
@param Vector The vector number of the interrupt being sent.\r
/**\r
Send a Fixed IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
@param Vector The vector number of the interrupt being sent.\r
**/\r
/**\r
Send a SMI IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send a SMI IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send an INIT IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
- WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r
+ WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r
}\r
\r
//\r
}\r
\r
/**\r
- Get the 32-bit address that a device should use to send a Message Signaled \r
+ Get the 32-bit address that a device should use to send a Message Signaled\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
@return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
-EFIAPI \r
+EFIAPI\r
GetApicMsiAddress (\r
VOID\r
)\r
LOCAL_APIC_MSI_ADDRESS MsiAddress;\r
\r
//\r
- // Return address for an MSI interrupt to be delivered only to the APIC ID \r
+ // Return address for an MSI interrupt to be delivered only to the APIC ID\r
// of the currently executing processor.\r
//\r
MsiAddress.Uint32 = 0;\r
MsiAddress.Bits.DestinationId = GetApicId ();\r
return MsiAddress.Uint32;\r
}\r
- \r
+\r
/**\r
- Get the 64-bit data value that a device should use to send a Message Signaled \r
+ Get the 64-bit data value that a device should use to send a Message Signaled\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
If Vector is not in range 0x10..0xFE, then ASSERT().\r
If DeliveryMode is not supported, then ASSERT().\r
- \r
- @param Vector The 8-bit interrupt vector associated with the MSI. \r
+\r
+ @param Vector The 8-bit interrupt vector associated with the MSI.\r
Must be in the range 0x10..0xFE\r
- @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
+ @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r
is handled. The only supported values are:\r
0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
4: LOCAL_APIC_DELIVERY_MODE_NMI\r
5: LOCAL_APIC_DELIVERY_MODE_INIT\r
7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
- \r
- @param LevelTriggered TRUE specifies a level triggered interrupt. \r
+\r
+ @param LevelTriggered TRUE specifies a level triggered interrupt.\r
FALSE specifies an edge triggered interrupt.\r
@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
- TRUE specifies a level triggered interrupt that active \r
+ TRUE specifies a level triggered interrupt that active\r
when the interrupt line is asserted.\r
- FALSE specifies a level triggered interrupt that active \r
+ FALSE specifies a level triggered interrupt that active\r
when the interrupt line is deasserted.\r
\r
@return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
-EFIAPI \r
+EFIAPI\r
GetApicMsiValue (\r
IN UINT8 Vector,\r
IN UINTN DeliveryMode,\r
\r
ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
- \r
+\r
MsiData.Uint64 = 0;\r
MsiData.Bits.Vector = Vector;\r
MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
# Note: Local APIC library assumes local APIC is enabled. It does not handle cases\r
# where local APIC is disabled.\r
#\r
-# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
-# \r
+#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-# \r
+#\r
##\r
\r
[Defines]\r
FILE_GUID = 967B6E05-F10D-4c10-8BF7-365291CA143F\r
MODULE_TYPE = BASE\r
VERSION_STRING = 1.1\r
- LIBRARY_CLASS = LocalApicLib \r
+ LIBRARY_CLASS = LocalApicLib\r
\r
#\r
# The following information is for reference only and not required by the build tools.\r
// Note: Local APIC library assumes local APIC is enabled. It does not handle cases\r
// where local APIC is disabled.\r
//\r
-// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
/** @file\r
CPU Common features library header file.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
);\r
\r
/**\r
- Detects if Protected Processor Inventory Number feature supported on current \r
+ Detects if Protected Processor Inventory Number feature supported on current\r
processor.\r
\r
@param[in] ProcessorNumber The index of the CPU executing this function.\r
by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r
CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
RegisterCpuFeature().\r
- @param[in] State If TRUE, then the Protected Processor Inventory \r
+ @param[in] State If TRUE, then the Protected Processor Inventory\r
Number feature must be enabled.\r
- If FALSE, then the Protected Processor Inventory \r
+ If FALSE, then the Protected Processor Inventory\r
Number feature must be disabled.\r
\r
- @retval RETURN_SUCCESS Protected Processor Inventory Number feature is \r
+ @retval RETURN_SUCCESS Protected Processor Inventory Number feature is\r
initialized.\r
- @retval RETURN_DEVICE_ERROR Device can't change state because it has been \r
+ @retval RETURN_DEVICE_ERROR Device can't change state because it has been\r
locked.\r
\r
**/\r
);\r
\r
/**\r
- Detects if Local machine check exception feature supported on current \r
+ Detects if Local machine check exception feature supported on current\r
processor.\r
\r
@param[in] ProcessorNumber The index of the CPU executing this function.\r
# This library registers CPU features defined in Intel(R) 64 and IA-32\r
# Architectures Software Developer's Manual.\r
#\r
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle ## SOMETIMES_CONSUMES\r
gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset ## SOMETIMES_CONSUMES\r
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## SOMETIMES_CONSUMES\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES
\ No newline at end of file
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES\r
}\r
\r
/**\r
- Detects if Local machine check exception feature supported on current \r
+ Detects if Local machine check exception feature supported on current\r
processor.\r
\r
@param[in] ProcessorNumber The index of the CPU executing this function.\r
/** @file\r
Protected Processor Inventory Number(PPIN) feature.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include "CpuCommonFeatures.h"\r
\r
/**\r
- Detects if Protected Processor Inventory Number feature supported on current \r
+ Detects if Protected Processor Inventory Number feature supported on current\r
processor.\r
\r
@param[in] ProcessorNumber The index of the CPU executing this function.\r
{\r
MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;\r
\r
- if ((CpuInfo->DisplayFamily == 0x06) && \r
+ if ((CpuInfo->DisplayFamily == 0x06) &&\r
((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2\r
(CpuInfo->DisplayModel == 0x56) || // Xeon Processor D Product\r
(CpuInfo->DisplayModel == 0x4F) || // Xeon E5 v4, E7 v4\r
(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable\r
(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.\r
- (CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor \r
+ (CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor\r
)) {\r
//\r
// Check whether platform support this feature.\r
by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r
CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
RegisterCpuFeature().\r
- @param[in] State If TRUE, then the Protected Processor Inventory \r
+ @param[in] State If TRUE, then the Protected Processor Inventory\r
Number feature must be enabled.\r
- If FALSE, then the Protected Processor Inventory \r
+ If FALSE, then the Protected Processor Inventory\r
Number feature must be disabled.\r
\r
- @retval RETURN_SUCCESS Protected Processor Inventory Number feature is \r
+ @retval RETURN_SUCCESS Protected Processor Inventory Number feature is\r
initialized.\r
- @retval RETURN_DEVICE_ERROR Device can't change state because it has been \r
+ @retval RETURN_DEVICE_ERROR Device can't change state because it has been\r
locked.\r
\r
**/\r
/** @file\r
Intel Processor Trace feature.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
///\r
/// This macro define the max entries in the Topa table.\r
-/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region. \r
-/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the \r
-/// current table (for circular array) or to the base of another table. \r
-/// At least 2 entries are needed because the list of entries must \r
-/// be terminated by an entry with the END bit set to 1, so 2 \r
+/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.\r
+/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the\r
+/// current table (for circular array) or to the base of another table.\r
+/// At least 2 entries are needed because the list of entries must\r
+/// be terminated by an entry with the END bit set to 1, so 2\r
/// entries are required to use a single valid entry.\r
///\r
#define MAX_TOPA_ENTRY_COUNT 2\r
typedef struct {\r
UINT32 NumberOfProcessors;\r
\r
- UINT8 ProcTraceOutputScheme; \r
+ UINT8 ProcTraceOutputScheme;\r
UINT32 ProcTraceMemSize;\r
\r
UINTN *ThreadMemRegionTable;\r
}\r
\r
/**\r
- Detects if Intel Processor Trace feature supported on current \r
+ Detects if Intel Processor Trace feature supported on current\r
processor.\r
\r
@param[in] ProcessorNumber The index of the CPU executing this function.\r
//\r
// Single Range output scheme\r
//\r
- if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && \r
+ if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&\r
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {\r
if (FirstIn) {\r
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));\r
//\r
// ToPA(Table of physical address) scheme\r
//\r
- if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && \r
+ if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&\r
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {\r
//\r
// Create ToPA structure aligned at 4KB for each logical thread\r
/** @file\r
CPU Exception Handler Library common functions.\r
\r
- Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
VectorInfo ++;\r
}\r
return EFI_SUCCESS;\r
-}
\ No newline at end of file
+}\r
/** @file\r
MP initialize support functions for DXE phase.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc;\r
UINTN ProcessorNumber;\r
\r
- MpInitLibWhoAmI (&ProcessorNumber); \r
+ MpInitLibWhoAmI (&ProcessorNumber);\r
CpuMpData = GetCpuMpData ();\r
MwaitSupport = IsMwaitSupport ();\r
AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoopFunc;\r
//\r
// Make sure that the buffer memory is executable if NX protection is enabled\r
// for EfiReservedMemoryType.\r
- // \r
+ //\r
// TODO: Check EFI_MEMORY_XP bit set or not once it's available in DXE GCD\r
// service.\r
//\r
jz ProgramStack\r
add edi, 20\r
inc ebx\r
- jmp GetNextProcNumber \r
+ jmp GetNextProcNumber\r
\r
ProgramStack:\r
mov esp, [edi + 12]\r
- \r
+\r
CProcedureInvoke:\r
push ebp ; push BIST data at top of AP stack\r
xor ebp, ebp ; clear ebp for call stack trace\r
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateBusy);\r
//\r
// Enable source debugging on AP function\r
- // \r
+ //\r
EnableDebugAgent ();\r
//\r
// Invoke AP function here\r
\r
//\r
// GetPerformanceCounterProperties () returns the timestamp counter's frequency\r
- // in Hz. \r
+ // in Hz.\r
//\r
TimestampCounterFreq = GetPerformanceCounterProperties (NULL, NULL);\r
\r
enabled AP. Otherwise, it will be disabled.\r
\r
@retval EFI_SUCCESS BSP successfully switched.\r
- @retval others Failed to switch BSP. \r
+ @retval others Failed to switch BSP.\r
\r
**/\r
EFI_STATUS\r
/** @file\r
Common header file for MP Initialize Library.\r
\r
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
enabled AP. Otherwise, it will be disabled.\r
\r
@retval EFI_SUCCESS BSP successfully switched.\r
- @retval others Failed to switch BSP. \r
+ @retval others Failed to switch BSP.\r
\r
**/\r
EFI_STATUS\r
jz ProgramStack\r
add edi, 20\r
inc ebx\r
- jmp GetNextProcNumber \r
+ jmp GetNextProcNumber\r
\r
ProgramStack:\r
mov rsp, qword [edi + 12]\r
## @file\r
# MTRR library provides APIs for MTRR operation.\r
#\r
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
-# \r
+#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-# \r
+#\r
##\r
\r
[Defines]\r
FILE_GUID = 6826b408-f4f3-47ee-917f-af7047f9d937\r
MODULE_TYPE = BASE\r
VERSION_STRING = 1.0\r
- LIBRARY_CLASS = MtrrLib \r
+ LIBRARY_CLASS = MtrrLib\r
\r
\r
#\r
//\r
// MTRR library provides APIs for MTRR operation.\r
//\r
-// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
/** @file\r
CPU Features Initialize functions.\r
\r
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINT8 *SupportBitMask;\r
\r
SupportBitMask = AllocateCopyPool (\r
- PcdGetSize (PcdCpuFeaturesSupport), \r
+ PcdGetSize (PcdCpuFeaturesSupport),\r
PcdGetPtr (PcdCpuFeaturesSupport)\r
);\r
ASSERT (SupportBitMask != NULL);\r
UINT8 *SupportBitMask;\r
\r
SupportBitMask = AllocateCopyPool (\r
- PcdGetSize (PcdCpuFeaturesUserConfiguration), \r
+ PcdGetSize (PcdCpuFeaturesUserConfiguration),\r
PcdGetPtr (PcdCpuFeaturesUserConfiguration)\r
);\r
ASSERT (SupportBitMask != NULL);\r
#\r
# Timer Library that only uses CPU resources to provide calibrated delays\r
# on IA-32, x64, and IPF.\r
-# Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib \r
-# in their initialization without any issues. They only have to be careful in \r
-# the implementation of runtime services and SMI handlers. \r
+# Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib\r
+# in their initialization without any issues. They only have to be careful in\r
+# the implementation of runtime services and SMI handlers.\r
# Because CPU Local APIC and ITC could be programmed by OS, it cannot be\r
# used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM\r
# drivers and runtime drivers.\r
# This library differs with the SecPeiDxeTimerLibCpu library in the MdePkg in\r
# that it uses the local APIC library so that it supports x2APIC mode.\r
#\r
-# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
// Because CPU Local APIC and ITC could be programmed by OS, it cannot be\r
// used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM\r
// drivers and runtime drivers.\r
-// \r
+//\r
// This library differs with the SecPeiDxeTimerLibCpu library in the MdePkg in\r
// that it uses the local APIC library so that it supports x2APIC mode.\r
//\r
-// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
Timer Library functions built upon local APIC on IA32/x64.\r
\r
This library uses the local APIC library so that it supports x2APIC mode.\r
- \r
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r
+\r
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
/** @file\r
SMM CPU misc functions for Ia32 arch specific.\r
- \r
+\r
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
/**\r
Initialize Gdt for all processors.\r
- \r
+\r
@param[in] Cr3 CR3 value.\r
@param[out] GdtStepSize The step size for GDT table.\r
\r
//\r
// IA32 Stack Guard need use task switch to switch stack that need\r
// write GDT and TSS, so AllocateCodePages() could not be used here\r
- // as code pages will be set to RO. \r
+ // as code pages will be set to RO.\r
//\r
GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r
ASSERT (GdtTssTables != NULL);\r
/** @file\r
SMM MP service implementation\r
\r
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
\r
/**\r
Has OS enabled Lmce in the MSR_IA32_MCG_EXT_CTL\r
- \r
+\r
@retval TRUE Os enable lmce.\r
@retval FALSE Os not enable lmce.\r
\r
}\r
\r
/**\r
- Return if Local machine check exception signaled. \r
+ Return if Local machine check exception signaled.\r
\r
- Indicates (when set) that a local machine check exception was generated. This indicates that the current machine-check event was \r
+ Indicates (when set) that a local machine check exception was generated. This indicates that the current machine-check event was\r
delivered to only the logical processor.\r
\r
@retval TRUE LMCE was signaled.\r
)\r
{\r
SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
- \r
+\r
if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
ASSERT(CpuIndex < mMaxNumberOfCpus);\r
CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];\r
/** @file\r
SMM CPU misc functions for x64 arch specific.\r
- \r
+\r
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
/**\r
Initialize Gdt for all processors.\r
- \r
+\r
@param[in] Cr3 CR3 value.\r
@param[out] GdtStepSize The step size for GDT table.\r
\r
## @file\r
# Reset Vector\r
-# \r
+#\r
# This VTF requires build time fixups in order to find the SEC entry point.\r
#\r
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
; @file\r
; Transition from 32 bit flat protected mode into 64 bit flat protected mode\r
;\r
-; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
\r
mov eax, cr4\r
bts eax, 5 ; enable PAE\r
- mov cr4, eax \r
+ mov cr4, eax\r
\r
mov ecx, 0xc0000080\r
rdmsr\r
; @file\r
; Serial port debug support macros\r
;\r
-; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
BITS 16\r
\r
%macro debugInitialize 0\r
- jmp real16InitDebug\r
+ jmp real16InitDebug\r
real16InitDebugReturn:\r
%endmacro\r
\r
// /** @file\r
// UefiCpu Package Localized Strings and Content.\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials are licensed and made available under\r
// the terms and conditions of the BSD License which accompanies this distribution.\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_PACKAGE_NAME \r
-#language en-US \r
+#string STR_PROPERTIES_PACKAGE_NAME\r
+#language en-US\r
"UefiCpu package"\r
\r
\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 MustBe1:1; // Must be 1\r
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
- UINT64 MustBe1:1; // Must be 1 \r
+ UINT64 MustBe1:1; // Must be 1\r
UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
UINT64 Available:3; // Available for use by system software\r
UINT64 PAT:1; //\r
//\r
/**\r
a ASM function to transfer control to OS.\r
- \r
+\r
@param S3WakingVector The S3 waking up vector saved in ACPI Facs table\r
- @param AcpiLowMemoryBase a buffer under 1M which could be used during the transfer \r
+ @param AcpiLowMemoryBase a buffer under 1M which could be used during the transfer\r
**/\r
typedef\r
VOID\r
}\r
\r
//\r
- // NOTE: Because Debug Timer interrupt and system interrupts will be disabled \r
+ // NOTE: Because Debug Timer interrupt and system interrupts will be disabled\r
// in BootScriptExecuteDxe, the rest code in S3ResumeBootOs() cannot be halted\r
// by soft debugger.\r
//\r
\r
/**\r
Restore S3 page table because we do not trust ACPINvs content.\r
- If BootScriptExector driver will not run in 64-bit mode, this function will do nothing. \r
+ If BootScriptExector driver will not run in 64-bit mode, this function will do nothing.\r
\r
@param S3NvsPageTableAddress PageTableAddress in ACPINvs\r
@param Build4GPageTableOnly If BIOS just build 4G page table only\r
//\r
PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
S3NvsPageTableAddress += SIZE_4KB;\r
- \r
+\r
Page1GSupport = FALSE;\r
if (PcdGetBool(PcdUse1GPageTable)) {\r
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
}\r
}\r
}\r
- \r
+\r
//\r
// Get physical address bits supported.\r
//\r
PhysicalAddressBits = 36;\r
}\r
}\r
- \r
+\r
//\r
// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
//\r
NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
NumberOfPdpEntriesNeeded = 512;\r
}\r
- \r
+\r
PageMapLevel4Entry = PageMap;\r
PageAddress = 0;\r
for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
//\r
PageDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
S3NvsPageTableAddress += SIZE_4KB;\r
- \r
+\r
//\r
// Make a PML4 Entry\r
//\r
\r
if (Page1GSupport) {\r
PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;\r
- \r
+\r
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
//\r
// Fill in the Page Directory entries\r
//\r
// Each Directory Pointer entries points to a page of Page Directory entires.\r
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
- // \r
+ //\r
PageDirectoryEntry = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress;\r
S3NvsPageTableAddress += SIZE_4KB;\r
- \r
+\r
//\r
// Fill in a Page Directory Pointer Entries\r
//\r
PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;\r
PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
PageDirectoryPointerEntry->Bits.Present = 1;\r
- \r
+\r
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {\r
//\r
// Fill in the Page Directory entries\r
}\r
return ;\r
} else {\r
- //\r
- // If DXE is running 32-bit mode, no need to establish page table.\r
- //\r
+ //\r
+ // If DXE is running 32-bit mode, no need to establish page table.\r
+ //\r
return ;\r
}\r
}\r
\r
//\r
// Send SMI to APs\r
- // \r
+ //\r
SendSmiIpiAllExcludingSelf ();\r
//\r
// Send SMI to BSP\r
);\r
if (!EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_INFO, "Close all SMRAM regions before executing boot script\n"));\r
- \r
+\r
for (Index = 0, Status = EFI_SUCCESS; !EFI_ERROR (Status); Index++) {\r
Status = SmmAccess->Close ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index);\r
}\r
\r
DEBUG ((DEBUG_INFO, "Lock all SMRAM regions before executing boot script\n"));\r
- \r
+\r
for (Index = 0, Status = EFI_SUCCESS; !EFI_ERROR (Status); Index++) {\r
Status = SmmAccess->Lock ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index);\r
}\r
if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {\r
//\r
// On some platform, such as ECP, a dispatch node in boot script table may execute a 32-bit PEIM which may need PeiServices\r
- // pointer. So PeiServices need preserve in (IDTBase- sizeof (UINTN)). \r
+ // pointer. So PeiServices need preserve in (IDTBase- sizeof (UINTN)).\r
//\r
IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
//\r
// Make sure the newly allocated IDT align with 16-bytes\r
- // \r
+ //\r
IdtBuffer = AllocatePages (EFI_SIZE_TO_PAGES((IdtDescriptor->Limit + 1) + 16));\r
if (IdtBuffer == NULL) {\r
REPORT_STATUS_CODE (\r
//\r
// Additional 16 bytes allocated to save IA32 IDT descriptor and Pei Service Table Pointer\r
// IA32 IDT descriptor will be used to setup IA32 IDT table for 32-bit Framework Boot Script code\r
- // \r
+ //\r
ZeroMem (IdtBuffer, 16);\r
AsmReadIdtr ((IA32_DESCRIPTOR *)IdtBuffer);\r
CopyMem ((VOID*)((UINT8*)IdtBuffer + 16),(VOID*)(IdtDescriptor->Base), (IdtDescriptor->Limit + 1));\r
// Save IDT\r
//\r
AsmReadIdtr (&PeiS3ResumeState->Idtr);\r
- \r
+\r
//\r
// Report Status Code to indicate S3 boot script execution\r
//\r
DEBUG (( DEBUG_INFO, "AcpiS3Context = %x\n", AcpiS3Context));\r
DEBUG (( DEBUG_INFO, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector));\r
DEBUG (( DEBUG_INFO, "AcpiS3Context->AcpiFacsTable = %x\n", AcpiS3Context->AcpiFacsTable));\r
- DEBUG (( DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile)); \r
+ DEBUG (( DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile));\r
DEBUG (( DEBUG_INFO, "AcpiS3Context->S3NvsPageTableAddress = %x\n", AcpiS3Context->S3NvsPageTableAddress));\r
DEBUG (( DEBUG_INFO, "AcpiS3Context->S3DebugBufferAddress = %x\n", AcpiS3Context->S3DebugBufferAddress));\r
DEBUG (( DEBUG_INFO, "AcpiS3Context->BootScriptStackBase = %x\n", AcpiS3Context->BootScriptStackBase));\r
AsmWriteGdtr (&mGdt);\r
//\r
// update segment selectors per the new GDT.\r
- // \r
+ //\r
AsmSetDataSelectors (DATA_SEGEMENT_SELECTOR);\r
//\r
// Restore interrupt state.\r
Main entry for S3 Resume PEIM.\r
\r
This routine is to install EFI_PEI_S3_RESUME2_PPI.\r
- \r
+\r
@param FileHandle Handle of the file being invoked.\r
@param PeiServices Pointer to PEI Services table.\r
\r
// This module will excute the boot script saved during last boot and after that,\r
// control is passed to OS waking up handler.\r
//\r
-// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials are\r
// licensed and made available under the terms and conditions of the BSD License\r
// which accompanies this distribution. The full text of the license may be found at\r
// http://opensource.org/licenses/bsd-license.php\r
-// \r
+//\r
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
// /** @file\r
// S3Resume2Pei Localized Strings and Content\r
//\r
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+// Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
//\r
// This program and the accompanying materials are\r
// licensed and made available under the terms and conditions of the BSD License\r
//\r
// **/\r
\r
-#string STR_PROPERTIES_MODULE_NAME \r
-#language en-US \r
+#string STR_PROPERTIES_MODULE_NAME\r
+#language en-US\r
"S3 Resume v2 PEI Module"\r
\r
\r
projects / mirror_edk2.git / commitdiff