Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17034
6f19259b-4bc3-4df7-8a09-
765794883524
#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27)\r
#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17)\r
#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_E 0x10 // D0 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_F 0x11 // D0 Stepping (25 x 27)\r
\r
#define R_PCH_LPC_MLT 0x0D // Master Latency Timer\r
#define B_PCH_LPC_MLT_MLC 0xF8 // Master Latency Count\r
case V_PCH_LPC_RID_D:\r
return PchC0;\r
break;\r
-\r
+ \r
+ case V_PCH_LPC_RID_E:\r
+ case V_PCH_LPC_RID_F:\r
+ return PchD0;\r
+ break;\r
+ \r
default:\r
return PchSteppingMax;\r
break;\r