}\r
\r
/**\r
- Wait for memory set to the test value.\r
+ Wait for the value of the specified MMIO register set to the test value.\r
\r
@param PciIo The PCI IO protocol instance.\r
- @param Offset The memory address to test.\r
+ @param Offset The MMIO address to test.\r
@param MaskValue The mask value of memory.\r
@param TestValue The test value of memory.\r
- @param Timeout The time out value for wait memory set.\r
+ @param Timeout The time out value for wait memory set, uses 100ns as a unit.\r
\r
- @retval EFI_DEVICE_ERROR The memory is not set.\r
- @retval EFI_TIMEOUT The memory setting is time out.\r
- @retval EFI_SUCCESS The memory is correct set.\r
+ @retval EFI_TIMEOUT The MMIO setting is time out.\r
+ @retval EFI_SUCCESS The MMIO is correct set.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-AhciWaitMemSet (\r
+AhciWaitMmioSet (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset,\r
+ IN UINTN Offset,\r
IN UINT32 MaskValue,\r
IN UINT32 TestValue,\r
IN UINT64 Timeout\r
UINT32 Value; \r
UINT32 Delay;\r
\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
+ Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
\r
do {\r
- Value = AhciReadReg (PciIo, Offset) & MaskValue;\r
+ //\r
+ // Access PCI MMIO space to see if the value is the tested one.\r
+ //\r
+ Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;\r
\r
if (Value == TestValue) {\r
return EFI_SUCCESS;\r
\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
+ return EFI_TIMEOUT;\r
+}\r
+\r
+/**\r
+ Wait for the value of the specified system memory set to the test value.\r
+ \r
+ @param Address The system memory address to test.\r
+ @param MaskValue The mask value of memory.\r
+ @param TestValue The test value of memory.\r
+ @param Timeout The time out value for wait memory set, uses 100ns as a unit.\r
+\r
+ @retval EFI_TIMEOUT The system memory setting is time out.\r
+ @retval EFI_SUCCESS The system memory is correct set.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+AhciWaitMemSet (\r
+ IN EFI_PHYSICAL_ADDRESS Address,\r
+ IN UINT32 MaskValue,\r
+ IN UINT32 TestValue,\r
+ IN UINT64 Timeout\r
+ )\r
+{\r
+ UINT32 Value; \r
+ UINT32 Delay;\r
+\r
+ Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
+\r
+ do {\r
+ //\r
+ // Access sytem memory to see if the value is the tested one.\r
+ //\r
+ // The system memory pointed by Address will be updated by the\r
+ // SATA Host Controller, "volatile" is introduced to prevent\r
+ // compiler from optimizing the access to the memory address\r
+ // to only read once.\r
+ //\r
+ Value = *(volatile UINT32 *) (UINTN) Address;\r
+ Value &= MaskValue;\r
+\r
+ if (Value == TestValue) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Stall for 100 microseconds.\r
+ //\r
+ MicroSecondDelay (100);\r
+\r
+ Delay--;\r
\r
- return EFI_DEVICE_ERROR;\r
+ } while (Delay > 0);\r
+\r
+ return EFI_TIMEOUT;\r
}\r
\r
/**\r
Check the memory status to the test value.\r
\r
- @param[in] PciIo The PCI IO protocol instance.\r
- @param[in] Offset The memory address to test.\r
+ @param[in] Address The memory address to test.\r
@param[in] MaskValue The mask value of memory.\r
@param[in] TestValue The test value of memory.\r
- @param[in, out] RetryTimes The retry times value for waitting memory set.\r
+ @param[in, out] RetryTimes The retry times value for waitting memory set. If 0, then just try once.\r
\r
@retval EFI_NOTREADY The memory is not set.\r
@retval EFI_TIMEOUT The memory setting retry times out.\r
EFI_STATUS\r
EFIAPI\r
AhciCheckMemSet (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT32 Offset,\r
+ IN UINTN Address,\r
IN UINT32 MaskValue,\r
IN UINT32 TestValue,\r
- IN OUT UINTN *RetryTimes\r
+ IN OUT UINTN *RetryTimes OPTIONAL\r
)\r
{\r
UINT32 Value;\r
\r
- (*RetryTimes) --;\r
- \r
- Value = AhciReadReg (PciIo, Offset) & MaskValue;\r
+ if (RetryTimes != NULL) {\r
+ (*RetryTimes)--;\r
+ }\r
+ \r
+ Value = *(volatile UINT32 *) Address;\r
+ Value &= MaskValue;\r
\r
if (Value == TestValue) {\r
return EFI_SUCCESS;\r
}\r
\r
- if ((*RetryTimes) == 0) {\r
+ if ((RetryTimes != NULL) && (*RetryTimes == 0)) {\r
return EFI_TIMEOUT;\r
} else {\r
return EFI_NOT_READY;\r
\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
- @param Timeout The timeout value of enabling FIS.\r
+ @param Timeout The timeout value of enabling FIS, uses 100ns as a unit.\r
\r
@retval EFI_DEVICE_ERROR The FIS enable setting fails.\r
@retval EFI_TIMEOUT The FIS enable setting is time out.\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);\r
\r
- return AhciWaitMemSet (\r
+ return AhciWaitMmioSet (\r
PciIo, \r
Offset,\r
EFI_AHCI_PORT_CMD_FR,\r
\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
- @param Timeout The timeout value of disabling FIS.\r
+ @param Timeout The timeout value of disabling FIS, uses 100ns as a unit.\r
\r
@retval EFI_DEVICE_ERROR The FIS disable setting fails.\r
@retval EFI_TIMEOUT The FIS disable setting is time out.\r
\r
AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));\r
\r
- return AhciWaitMemSet (\r
+ return AhciWaitMmioSet (\r
PciIo,\r
Offset,\r
EFI_AHCI_PORT_CMD_FR,\r
@param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
@param[in, out] MemoryAddr The pointer to the data buffer.\r
@param[in] DataCount The data count to be transferred.\r
- @param[in] Timeout The timeout value of non data transfer.\r
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
\r
{\r
EFI_STATUS Status;\r
UINTN FisBaseAddr;\r
- UINT32 Offset;\r
- UINT32 Value;\r
+ UINTN Offset;\r
EFI_PHYSICAL_ADDRESS PhyAddr;\r
VOID *Map;\r
UINTN MapLength;\r
EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
UINT32 Delay;\r
EFI_AHCI_COMMAND_FIS CFis;\r
- EFI_AHCI_COMMAND_LIST CmdList;\r
+ EFI_AHCI_COMMAND_LIST CmdList; \r
+ UINT32 PortTfd;\r
+ UINT32 PrdCount;\r
\r
if (Read) {\r
Flag = EfiPciIoOperationBusMasterWrite;\r
// Check the status and wait the driver sending data\r
//\r
FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
- //\r
- // Wait device sends the PIO setup fis before data transfer\r
- //\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
- do {\r
- Value = *(volatile UINT32 *) (FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET);\r
-\r
- if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_PIO_SETUP) {\r
- break;\r
- }\r
\r
+ if (Read && (AtapiCommand == 0)) {\r
//\r
- // Stall for 100 microseconds.\r
+ // Wait device sends the PIO setup fis before data transfer\r
//\r
- MicroSecondDelay(100);\r
+ Status = EFI_TIMEOUT;\r
+ Delay = (UINT32) (DivU64x32 (Timeout, 1000) + 1);\r
+ do {\r
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
+ PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
+\r
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ break;\r
+ }\r
+ Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;\r
\r
- Delay--;\r
- } while (Delay > 0);\r
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, 0);\r
+ if (!EFI_ERROR (Status)) {\r
+ PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));\r
+ if (PrdCount == DataCount) {\r
+ break;\r
+ }\r
+ }\r
\r
- if (Delay == 0) {\r
- Status = EFI_TIMEOUT;\r
- goto Exit;\r
- }\r
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, 0);\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ break;\r
+ }\r
\r
- //\r
- // Wait for command compelte\r
- //\r
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;\r
- Status = AhciWaitMemSet (\r
- PciIo,\r
- Offset,\r
- 0xFFFFFFFF,\r
- 0,\r
- Timeout\r
- );\r
+ //\r
+ // Stall for 100 microseconds.\r
+ //\r
+ MicroSecondDelay(100);\r
\r
- if (EFI_ERROR (Status)) {\r
- goto Exit;\r
- }\r
+ Delay--;\r
+ } while (Delay > 0);\r
+ } else {\r
+ //\r
+ // Wait for D2H Fis is received\r
+ //\r
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
+ Status = AhciWaitMemSet (\r
+ Offset,\r
+ EFI_AHCI_FIS_TYPE_MASK,\r
+ EFI_AHCI_FIS_REGISTER_D2H,\r
+ Timeout\r
+ );\r
\r
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;\r
- Status = AhciWaitMemSet (\r
- PciIo,\r
- Offset,\r
- EFI_AHCI_PORT_IS_PSS,\r
- EFI_AHCI_PORT_IS_PSS,\r
- Timeout\r
- );\r
- if (EFI_ERROR (Status)) {\r
- goto Exit;\r
+ if (EFI_ERROR (Status)) {\r
+ goto Exit;\r
+ }\r
+\r
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
+ PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ }\r
}\r
\r
Exit:\r
@param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
@param[in, out] MemoryAddr The pointer to the data buffer.\r
@param[in] DataCount The data count to be transferred.\r
- @param[in] Timeout The timeout value of non data transfer.\r
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
\r
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,\r
IN OUT VOID *MemoryAddr,\r
- IN UINTN DataCount,\r
+ IN UINT32 DataCount,\r
IN UINT64 Timeout,\r
IN ATA_NONBLOCK_TASK *Task\r
)\r
{\r
EFI_STATUS Status;\r
- UINT32 Offset;\r
+ UINTN Offset;\r
EFI_PHYSICAL_ADDRESS PhyAddr;\r
VOID *Map;\r
UINTN MapLength;\r
EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
EFI_AHCI_COMMAND_FIS CFis;\r
EFI_AHCI_COMMAND_LIST CmdList;\r
+ UINTN FisBaseAddr;\r
+ UINT32 PortTfd;\r
\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- EFI_TPL OldTpl;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_TPL OldTpl;\r
\r
Map = NULL;\r
PciIo = Instance->PciIo;\r
if (EFI_ERROR (Status)) {\r
goto Exit;\r
}\r
-\r
- //\r
- // Wait device PRD processed\r
- //\r
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;\r
- Status = AhciWaitMemSet (\r
- PciIo,\r
- Offset,\r
- EFI_AHCI_PORT_IS_DPS,\r
- EFI_AHCI_PORT_IS_DPS,\r
- Timeout\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- goto Exit;\r
- }\r
}\r
\r
//\r
// Wait for command compelte\r
//\r
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;\r
+ FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
if (Task != NULL) {\r
//\r
// For Non-blocking\r
//\r
Status = AhciCheckMemSet (\r
- PciIo,\r
Offset,\r
- 0xFFFFFFFF,\r
- 0,\r
+ EFI_AHCI_FIS_TYPE_MASK,\r
+ EFI_AHCI_FIS_REGISTER_D2H,\r
(UINTN *) (&Task->RetryTimes)\r
);\r
} else {\r
Status = AhciWaitMemSet (\r
- PciIo,\r
Offset,\r
- 0xFFFFFFFF,\r
- 0,\r
+ EFI_AHCI_FIS_TYPE_MASK,\r
+ EFI_AHCI_FIS_REGISTER_D2H,\r
Timeout\r
);\r
}\r
goto Exit;\r
}\r
\r
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;\r
-\r
- if (Task != NULL) {\r
- //\r
- // For Non-blocking\r
- //\r
- Status = AhciCheckMemSet (\r
- PciIo,\r
- Offset,\r
- EFI_AHCI_PORT_IS_DHRS,\r
- EFI_AHCI_PORT_IS_DHRS,\r
- (UINTN *) (&Task->RetryTimes)\r
- );\r
- } else {\r
- Status = AhciWaitMemSet (\r
- PciIo,\r
- Offset,\r
- EFI_AHCI_PORT_IS_DHRS,\r
- EFI_AHCI_PORT_IS_DHRS,\r
- Timeout\r
- );\r
- }\r
-\r
- if (EFI_ERROR (Status)) {\r
- goto Exit;\r
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
+ PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {\r
+ Status = EFI_DEVICE_ERROR;\r
}\r
\r
Exit:\r
@param[in] AtapiCommandLength The length of the atapi command.\r
@param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.\r
@param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.\r
- @param[in] Timeout The timeout value of non data transfer.\r
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
\r
{\r
EFI_STATUS Status;\r
UINTN FisBaseAddr;\r
- UINT32 Offset;\r
- UINT32 Value;\r
- UINT32 Delay;\r
-\r
+ UINTN Offset;\r
+ UINT32 PortTfd;\r
EFI_AHCI_COMMAND_FIS CFis;\r
EFI_AHCI_COMMAND_LIST CmdList;\r
\r
// Wait device sends the Response Fis\r
//\r
FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);\r
- //\r
- // Wait device sends the PIO setup fis before data transfer\r
- //\r
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
- do {\r
- Value = *(volatile UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);\r
-\r
- if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {\r
- break;\r
- }\r
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;\r
+ Status = AhciWaitMemSet (\r
+ Offset,\r
+ EFI_AHCI_FIS_TYPE_MASK,\r
+ EFI_AHCI_FIS_REGISTER_D2H,\r
+ Timeout\r
+ );\r
\r
- //\r
- // Stall for 100 microseconds.\r
- //\r
- MicroSecondDelay(100);\r
-\r
- Delay --;\r
- } while (Delay > 0);\r
-\r
- if (Delay == 0) {\r
- Status = EFI_TIMEOUT;\r
+ if (EFI_ERROR (Status)) {\r
goto Exit;\r
}\r
\r
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;\r
-\r
- Status = AhciWaitMemSet (\r
- PciIo,\r
- Offset,\r
- 0xFFFFFFFF,\r
- 0,\r
- Timeout\r
- );\r
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;\r
+ PortTfd = AhciReadReg (PciIo, (UINT32) Offset);\r
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ }\r
\r
Exit:\r
AhciStopCommand (\r
\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
- @param Timeout The timeout value of stop.\r
+ @param Timeout The timeout value of stop, uses 100ns as a unit.\r
\r
@retval EFI_DEVICE_ERROR The command stop unsuccessfully.\r
@retval EFI_TIMEOUT The operation is time out.\r
AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));\r
}\r
\r
- return AhciWaitMemSet (\r
+ return AhciWaitMmioSet (\r
PciIo,\r
Offset,\r
EFI_AHCI_PORT_CMD_CR,\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
@param CommandSlot The number of Command Slot.\r
- @param Timeout The timeout value of start.\r
+ @param Timeout The timeout value of start, uses 100ns as a unit.\r
\r
@retval EFI_DEVICE_ERROR The command start unsuccessfully.\r
@retval EFI_TIMEOUT The operation is time out.\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_CLO);\r
\r
- AhciWaitMemSet (\r
+ AhciWaitMmioSet (\r
PciIo,\r
Offset,\r
EFI_AHCI_PORT_CMD_CLO,\r
\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
- @param Timeout The timeout value of reset.\r
+ @param Timeout The timeout value of reset, uses 100ns as a unit.\r
\r
@retval EFI_DEVICE_ERROR The port reset unsuccessfully\r
@retval EFI_TIMEOUT The reset operation is time out.\r
// Wait for communication to be re-established\r
//\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;\r
- Status = AhciWaitMemSet (\r
+ Status = AhciWaitMmioSet (\r
PciIo,\r
Offset,\r
EFI_AHCI_PORT_SSTS_DET_MASK,\r
Do AHCI HBA reset.\r
\r
@param PciIo The PCI IO protocol instance.\r
- @param Timeout The timeout value of reset.\r
+ @param Timeout The timeout value of reset, uses 100ns as a unit.\r
\r
@retval EFI_DEVICE_ERROR AHCI controller is failed to complete hardware reset.\r
@retval EFI_TIMEOUT The reset operation is time out.\r
//\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;\r
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);\r
- Status = AhciWaitMemSet (\r
+ Status = AhciWaitMmioSet (\r
PciIo, \r
Offset,\r
EFI_AHCI_PORT_CMD_FR,\r
// When the first D2H register FIS is received, the content of PxSIG register is updated.\r
//\r
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;\r
- Status = AhciWaitMemSet (\r
+ Status = AhciWaitMmioSet (\r
PciIo, \r
Offset,\r
0x0000FFFF,\r
/**\r
read a one-byte data from a IDE port.\r
\r
- @param PciIo The PCI IO protocol instance\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
@param Port The IDE Port number \r
\r
@return the one-byte data read from IDE port\r
/**\r
write a 1-byte data to a specific IDE port.\r
\r
- @param PciIo The PCI IO protocol instance\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
@param Port The IDE port to be writen\r
@param Data The data to write to the port\r
**/\r
/**\r
write a 1-word data to a specific IDE port.\r
\r
- @param PciIo PCI IO protocol instance\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
@param Port The IDE port to be writen\r
@param Data The data to write to the port\r
**/\r
/**\r
write a 2-word data to a specific IDE port.\r
\r
- @param PciIo PCI IO protocol instance\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
@param Port The IDE port to be writen\r
@param Data The data to write to the port\r
**/\r
Call the IO abstraction once to do the complete read,\r
not one word at a time\r
\r
- @param PciIo Pointer to the EFI_PCI_IO instance\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
@param Port IO port to read\r
@param Count No. of UINT16's to read\r
@param Buffer Pointer to the data buffer for read\r
Call the IO abstraction once to do the complete read,\r
not one word at a time\r
\r
- @param PciIo Pointer to the EFI_PCI_IO instance\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure\r
@param Port IO port to read\r
@param Count Number of UINT16's to read\r
@param Buffer Pointer to the data buffer for read\r
some debug information and if there is ERR bit set in the Status\r
Register, the Error Register's value is also be parsed and print out.\r
\r
- @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
\r
}\r
\r
/**\r
- This function is used to analyze the Status Register and print out\r
- some debug information and if there is ERR bit set in the Status\r
- Register, the Error Register's value is also be parsed and print out.\r
+ This function is used to analyze the Status Register at the condition that BSY is zero.\r
+ if there is ERR bit set in the Status Register, then return error.\r
\r
- @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
\r
@retval EFI_SUCCESS No err information in the Status Register.\r
IN EFI_IDE_REGISTERS *IdeRegisters\r
)\r
{\r
- EFI_STATUS Status;\r
UINT8 StatusRegister;\r
\r
ASSERT (PciIo != NULL);\r
\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
- if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {\r
- Status = EFI_SUCCESS;\r
- } else {\r
- Status = EFI_DEVICE_ERROR;\r
+ if ((StatusRegister & ATA_STSREG_BSY) == 0) {\r
+ if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
}\r
-\r
- return Status;\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
Register. DRQ is cleared when the device is finished transferring data.\r
So this function is called after data transfer is finished.\r
\r
- @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS DRQ bit clear within the time out.\r
\r
{\r
UINT32 Delay;\r
UINT8 StatusRegister;\r
- UINT8 ErrorRegister;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
//\r
- // wait for BSY == 0 and DRQ == 0\r
+ // Wait for BSY == 0, then judge if DRQ is clear\r
//\r
- if ((StatusRegister & (ATA_STSREG_DRQ | ATA_STSREG_BSY)) == 0) {\r
- break;\r
- }\r
-\r
- if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {\r
- ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
-\r
- if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
- return EFI_ABORTED;\r
+ if ((StatusRegister & ATA_STSREG_BSY) == 0) {\r
+ if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {\r
+ return EFI_DEVICE_ERROR;\r
+ } else {\r
+ return EFI_SUCCESS;\r
}\r
}\r
\r
//\r
- // Stall for 100 microseconds.\r
+ // Stall for 100 microseconds.\r
//\r
MicroSecondDelay (100);\r
\r
\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ return EFI_TIMEOUT;\r
}\r
/**\r
This function is used to poll for the DRQ bit clear in the Alternate\r
transferring data. So this function is called after data transfer\r
is finished.\r
\r
- @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS DRQ bit clear within the time out.\r
\r
{\r
UINT32 Delay;\r
UINT8 AltRegister;\r
- UINT8 ErrorRegister;\r
\r
ASSERT (PciIo != NULL);\r
ASSERT (IdeRegisters != NULL);\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
\r
//\r
- // wait for BSY == 0 and DRQ == 0\r
+ // Wait for BSY == 0, then judge if DRQ is clear\r
//\r
- if ((AltRegister & (ATA_STSREG_DRQ | ATA_STSREG_BSY)) == 0) {\r
- break;\r
- }\r
-\r
- if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {\r
- ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
-\r
- if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
- return EFI_ABORTED;\r
+ if ((AltRegister & ATA_STSREG_BSY) == 0) {\r
+ if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {\r
+ return EFI_DEVICE_ERROR;\r
+ } else {\r
+ return EFI_SUCCESS;\r
}\r
}\r
\r
\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ return EFI_TIMEOUT;\r
}\r
\r
/**\r
is called after the command is sent to the device and before required\r
data is transferred.\r
\r
- @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS DRQ bit set within the time out.\r
@retval EFI_TIMEOUT DRQ bit not set within the time out.\r
Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);\r
do {\r
//\r
- // read Status Register will clear interrupt\r
+ // Read Status Register will clear interrupt\r
//\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
//\r
- // BSY==0,DRQ==1\r
+ // Wait for BSY == 0, then judge if DRQ is clear or ERR is set\r
//\r
- if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {\r
- break;\r
- }\r
+ if ((StatusRegister & ATA_STSREG_BSY) == 0) {\r
+ if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {\r
+ ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
\r
- if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {\r
- ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
+ if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
+ return EFI_ABORTED;\r
+ }\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
\r
- if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
- return EFI_ABORTED;\r
+ if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_NOT_READY;\r
}\r
}\r
\r
Delay--;\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ return EFI_TIMEOUT;\r
}\r
/**\r
This function is used to poll for the DRQ bit set in the Alternate Status Register.\r
DRQ is set when the device is ready to transfer data. So this function is called after \r
the command is sent to the device and before required data is transferred.\r
\r
- @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS DRQ bit set within the time out.\r
@retval EFI_TIMEOUT DRQ bit not set within the time out.\r
\r
do {\r
//\r
- // Read Alternate Status Register will not clear interrupt status\r
+ // Read Alternate Status Register will not clear interrupt status\r
//\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
//\r
- // BSY == 0 , DRQ == 1\r
+ // Wait for BSY == 0, then judge if DRQ is clear or ERR is set\r
//\r
- if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {\r
- break;\r
- }\r
+ if ((AltRegister & ATA_STSREG_BSY) == 0) {\r
+ if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {\r
+ ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
\r
- if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {\r
- ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
+ if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
+ return EFI_ABORTED;\r
+ }\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
\r
- if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
- return EFI_ABORTED;\r
+ if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_NOT_READY;\r
}\r
}\r
\r
Delay--;\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ return EFI_TIMEOUT;\r
}\r
\r
/**\r
bit is set when the device is ready to accept command. Most ATA commands must be \r
sent after DRDY set except the ATAPI Packet Command.\r
\r
- @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS DRDY bit set within the time out.\r
@retval EFI_TIMEOUT DRDY bit not set within the time out.\r
do {\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
//\r
- // BSY == 0 , DRDY == 1\r
+ // Wait for BSY == 0, then judge if DRDY is set or ERR is set\r
//\r
- if ((StatusRegister & (ATA_STSREG_DRDY | ATA_STSREG_BSY)) == ATA_STSREG_DRDY) {\r
- break;\r
- }\r
+ if ((StatusRegister & ATA_STSREG_BSY) == 0) {\r
+ if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {\r
+ ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
\r
- if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {\r
- ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
+ if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
+ return EFI_ABORTED;\r
+ }\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
\r
- if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
- return EFI_ABORTED;\r
+ if ((StatusRegister & ATA_STSREG_DRDY) == ATA_STSREG_DRDY) {\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_DEVICE_ERROR;\r
}\r
}\r
\r
Delay--;\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ return EFI_TIMEOUT;\r
}\r
\r
/**\r
DRDY bit is set when the device is ready to accept command. Most ATA commands must \r
be sent after DRDY set except the ATAPI Packet Command.\r
\r
- @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
+ @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS DRDY bit set within the time out.\r
@retval EFI_TIMEOUT DRDY bit not set within the time out.\r
do {\r
AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
//\r
- // BSY == 0 , DRDY == 1\r
+ // Wait for BSY == 0, then judge if DRDY is set or ERR is set\r
//\r
- if ((AltRegister & (ATA_STSREG_DRDY | ATA_STSREG_BSY)) == ATA_STSREG_DRDY) {\r
- break;\r
- }\r
+ if ((AltRegister & ATA_STSREG_BSY) == 0) {\r
+ if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {\r
+ ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
\r
- if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {\r
- ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);\r
+ if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
+ return EFI_ABORTED;\r
+ }\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
\r
- if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {\r
- return EFI_ABORTED;\r
+ if ((AltRegister & ATA_STSREG_DRDY) == ATA_STSREG_DRDY) {\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_DEVICE_ERROR;\r
}\r
}\r
\r
Delay--;\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ return EFI_TIMEOUT;\r
}\r
\r
/**\r
\r
@param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS BSY bit clear within the time out.\r
@retval EFI_TIMEOUT BSY bit not clear within the time out.\r
StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);\r
\r
if ((StatusRegister & ATA_STSREG_BSY) == 0x00) {\r
- break;\r
+ return EFI_SUCCESS;\r
}\r
\r
//\r
\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ return EFI_TIMEOUT;\r
}\r
\r
/**\r
\r
@param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS BSY bit clear within the time out.\r
@retval EFI_TIMEOUT BSY bit not clear within the time out.\r
AltStatusRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);\r
\r
if ((AltStatusRegister & ATA_STSREG_BSY) == 0x00) {\r
- break;\r
+ return EFI_SUCCESS;\r
}\r
\r
//\r
\r
} while (Delay > 0);\r
\r
- if (Delay == 0) {\r
- return EFI_TIMEOUT;\r
- }\r
-\r
- return EFI_SUCCESS;\r
+ return EFI_TIMEOUT;\r
}\r
\r
/**\r
\r
@param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS Soft reset completes successfully.\r
@retval EFI_DEVICE_ERROR Any step during the reset process is failed.\r
@param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.\r
@param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
@param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.\r
- @param Timeout The time to complete the command.\r
+ @param Timeout The time to complete the command, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS Reading succeed\r
@retval EFI_DEVICE_ERROR Error executing commands on this device.\r
from host to device.\r
@param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.\r
@param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
- @param[in] Timeout The time to complete the command.\r
+ @param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
\r
@param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data\r
structure.\r
@param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
- @param[in] Timeout The time to complete the command.\r
+ @param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
\r
Wait for memory to be set.\r
\r
@param[in] PciIo The PCI IO protocol instance.\r
- @param[in] PortNum The IDE Port number.\r
+ @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
\r
@retval EFI_DEVICE_ERROR The memory is not set.\r
@retval EFI_TIMEOUT The memory setting is time out.\r
EFI_STATUS\r
AtaUdmStatusWait (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN UINT16 PortNum\r
+ IN EFI_IDE_REGISTERS *IdeRegisters\r
) \r
{\r
UINT8 RegisterValue;\r
EFI_STATUS Status;\r
+ UINT16 IoPortForBmis;\r
UINT64 Timeout;\r
\r
Timeout = 2000;\r
\r
while (TRUE) {\r
- RegisterValue = IdeReadPortB (PciIo, PortNum);\r
+ Status = CheckStatusRegister (PciIo, IdeRegisters);\r
+ if (EFI_ERROR (Status)) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ break;\r
+ }\r
\r
+ IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
+ RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);\r
if (((RegisterValue & BMIS_ERROR) != 0) || (Timeout == 0)) {\r
DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));\r
Status = EFI_DEVICE_ERROR;\r
@param[in] PciIo The PCI IO protocol instance.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
- @param[in] PortForBit The bit to be checked.\r
+ @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.\r
\r
@retval EFI_DEVICE_ERROR The memory setting met a issue.\r
@retval EFI_NOT_READY The memory is not set.\r
AtaUdmStatusCheck (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN ATA_NONBLOCK_TASK *Task,\r
- IN UINT16 PortForBit\r
+ IN EFI_IDE_REGISTERS *IdeRegisters\r
)\r
{\r
- UINT8 RegisterValue;\r
+ UINT8 RegisterValue;\r
+ UINT16 IoPortForBmis;\r
+ EFI_STATUS Status;\r
\r
Task->RetryTimes--;\r
- RegisterValue = IdeReadPortB(PciIo, PortForBit);\r
+\r
+ Status = CheckStatusRegister (PciIo, IdeRegisters);\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);\r
+ RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);\r
\r
if ((RegisterValue & BMIS_ERROR) != 0) {\r
DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));\r
@param[in] DataLength The length of the data.\r
@param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.\r
@param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.\r
- @param[in] Timeout The time to complete the command.\r
+ @param[in] Timeout The time to complete the command, uses 100ns as a unit.\r
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK\r
used by non-blocking mode.\r
\r
//\r
RegisterValue = IdeReadPortB(PciIo, IoPortForBmis);\r
RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);\r
- IdeWritePortB(PciIo, IoPortForBmis, RegisterValue);\r
+ IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);\r
\r
//\r
// Set the base address to BMID register\r
goto Exit;\r
}\r
\r
+ Status = CheckStatusRegister (PciIo, IdeRegisters);\r
+ if (EFI_ERROR (Status)) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ goto Exit;\r
+ }\r
//\r
// Set START bit of BMIC register\r
//\r
// So set the variable Count to 2000, for about 2 second Timeout time.\r
//\r
if (Task != NULL) {\r
- Status = AtaUdmStatusCheck (PciIo, Task, IoPortForBmis);\r
+ Status = AtaUdmStatusCheck (PciIo, Task, IdeRegisters);\r
} else {\r
- Status = AtaUdmStatusWait (PciIo, IoPortForBmis);\r
+ Status = AtaUdmStatusWait (PciIo, IdeRegisters);\r
}\r
\r
//\r
@param Read Flag used to determine the data transfer direction.\r
Read equals 1, means data transferred from device to host;\r
Read equals 0, means data transferred from host to device.\r
- @param Timeout Timeout value for wait DRQ ready before each data stream's transfer.\r
+ @param Timeout Timeout value for wait DRQ ready before each data stream's transfer\r
+ , uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS data is transferred successfully.\r
@retval EFI_DEVICE_ERROR the device failed to transfer data.\r
//\r
// After data transfer is completed, normally, DRQ bit should clear.\r
//\r
- Status = DRQClear2 (PciIo, IdeRegisters, Timeout);\r
+ Status = DRQClear (PciIo, IdeRegisters, Timeout);\r
if (EFI_ERROR (Status)) {\r
return EFI_DEVICE_ERROR;\r
}\r
@param[in] Device The device number of device.\r
@param[in] SenseData A pointer to store sense data.\r
@param[in] SenseDataLength The sense data length.\r
- @param[in] Timeout The timeout value to execute this cmd.\r
+ @param[in] Timeout The timeout value to execute this cmd, uses 100ns as a unit.\r
\r
@retval EFI_SUCCESS Send out the ATAPI packet command successfully.\r
@retval EFI_DEVICE_ERROR The device failed to send data.\r
IN UINT8 Device,\r
IN EFI_ATA_DRIVE_PARMS *DriveParameters,\r
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock\r
- \r
)\r
{\r
EFI_STATUS Status;\r
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